CLKMGR Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.480s 234.055us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.830s 52.883us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.200s 264.568us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.440s 328.269us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.790s 234.619us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
clkmgr_csr_aliasing 2.440s 328.269us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.010s 102.340us 50 50 100.00
V2 trans_enables clkmgr_trans 1.560s 281.934us 50 50 100.00
V2 extclk clkmgr_extclk 1.540s 241.490us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.140s 146.996us 50 50 100.00
V2 jitter clkmgr_smoke 1.480s 234.055us 50 50 100.00
V2 frequency clkmgr_frequency 16.470s 2.242ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.100s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.470s 2.242ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.479m 13.148ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.900s 118.859us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.300s 189.756us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.320s 503.970us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.320s 503.970us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.830s 52.883us 5 5 100.00
clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
clkmgr_csr_aliasing 2.440s 328.269us 5 5 100.00
clkmgr_same_csr_outstanding 2.140s 440.167us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.830s 52.883us 5 5 100.00
clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
clkmgr_csr_aliasing 2.440s 328.269us 5 5 100.00
clkmgr_same_csr_outstanding 2.140s 440.167us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.690s 620.355us 5 5 100.00
clkmgr_tl_intg_err 6.290s 1.577ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.270s 796.217us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.270s 796.217us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.270s 796.217us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.270s 796.217us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.790s 799.416us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.290s 1.577ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.470s 2.242ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.100s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.270s 796.217us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.920s 375.414us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.800s 341.777us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.240s 172.485us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.940s 396.430us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.950s 376.069us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.690s 620.355us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.960s 89.655us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.690s 620.355us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.150s 1.257ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 30.713m 414.298ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results