CLKMGR Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.690s 300.602us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.010s 58.745us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.600s 526.794us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.820s 67.638us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.110s 429.640us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
clkmgr_csr_aliasing 1.820s 67.638us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.140s 172.123us 50 50 100.00
V2 trans_enables clkmgr_trans 1.650s 307.498us 50 50 100.00
V2 extclk clkmgr_extclk 1.160s 115.351us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.170s 190.594us 50 50 100.00
V2 jitter clkmgr_smoke 1.690s 300.602us 50 50 100.00
V2 frequency clkmgr_frequency 18.300s 2.361ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.310s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.300s 2.361ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.503m 12.438ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.970s 163.169us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.090s 112.495us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.880s 255.278us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.880s 255.278us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.010s 58.745us 5 5 100.00
clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
clkmgr_csr_aliasing 1.820s 67.638us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 223.648us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.010s 58.745us 5 5 100.00
clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
clkmgr_csr_aliasing 1.820s 67.638us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 223.648us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.670s 539.857us 5 5 100.00
clkmgr_tl_intg_err 5.180s 1.059ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.710s 935.096us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.710s 935.096us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.710s 935.096us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.710s 935.096us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.500s 485.008us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.180s 1.059ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.300s 2.361ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.310s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.710s 935.096us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.440s 205.287us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.670s 325.799us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.500s 267.869us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.740s 342.065us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.830s 348.152us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.670s 539.857us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.160s 161.262us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.670s 539.857us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.860s 2.591ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 30.253m 554.238ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80

Past Results