CLKMGR Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.720s 324.753us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.240s 193.978us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.610s 1.358ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.940s 115.640us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.800s 195.417us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
clkmgr_csr_aliasing 1.940s 115.640us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.030s 113.508us 50 50 100.00
V2 trans_enables clkmgr_trans 1.470s 229.463us 50 50 100.00
V2 extclk clkmgr_extclk 1.240s 133.722us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.130s 150.356us 50 50 100.00
V2 jitter clkmgr_smoke 1.720s 324.753us 50 50 100.00
V2 frequency clkmgr_frequency 17.530s 2.359ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.770s 2.419ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.530s 2.359ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.646m 14.765ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.890s 116.407us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.010s 103.692us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.580s 549.209us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.580s 549.209us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.240s 193.978us 5 5 100.00
clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
clkmgr_csr_aliasing 1.940s 115.640us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 175.248us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.240s 193.978us 5 5 100.00
clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
clkmgr_csr_aliasing 1.940s 115.640us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 175.248us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.790s 1.259ms 5 5 100.00
clkmgr_tl_intg_err 3.820s 412.906us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.680s 374.627us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.680s 374.627us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.680s 374.627us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.680s 374.627us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.900s 1.015ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.820s 412.906us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.530s 2.359ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.770s 2.419ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.680s 374.627us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.860s 351.823us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.650s 302.659us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.420s 243.602us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.220s 127.397us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.940s 369.681us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.790s 1.259ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.430s 252.051us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.790s 1.259ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.160s 1.261ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 45.739m 777.676ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results