CLKMGR Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.100s 126.976us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.960s 68.339us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.600s 1.857ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 3.600s 809.581us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.910s 115.039us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
clkmgr_csr_aliasing 3.600s 809.581us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.930s 59.537us 50 50 100.00
V2 trans_enables clkmgr_trans 2.770s 613.667us 50 50 100.00
V2 extclk clkmgr_extclk 1.470s 236.595us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.860s 93.544us 50 50 100.00
V2 jitter clkmgr_smoke 1.100s 126.976us 50 50 100.00
V2 frequency clkmgr_frequency 19.040s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.770s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.040s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.230m 10.396ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 83.786us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.140s 146.861us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 7.070s 1.823ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 7.070s 1.823ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.960s 68.339us 5 5 100.00
clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
clkmgr_csr_aliasing 3.600s 809.581us 5 5 100.00
clkmgr_same_csr_outstanding 1.500s 115.184us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.960s 68.339us 5 5 100.00
clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
clkmgr_csr_aliasing 3.600s 809.581us 5 5 100.00
clkmgr_same_csr_outstanding 1.500s 115.184us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 7.440s 1.905ms 5 5 100.00
clkmgr_tl_intg_err 4.730s 942.022us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.780s 364.888us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.780s 364.888us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.780s 364.888us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.780s 364.888us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.860s 882.186us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.730s 942.022us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.040s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.770s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.780s 364.888us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.610s 224.363us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.300s 162.062us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.590s 237.514us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.880s 336.522us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.250s 151.321us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 7.440s 1.905ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.200s 166.605us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 7.440s 1.905ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.930s 1.368ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 27.484m 424.933ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results