CLKMGR Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.340s 136.091us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.850s 29.623us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.630s 562.767us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.550s 92.087us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.960s 129.140us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
clkmgr_csr_aliasing 1.550s 92.087us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.030s 133.129us 50 50 100.00
V2 trans_enables clkmgr_trans 1.740s 301.286us 50 50 100.00
V2 extclk clkmgr_extclk 1.600s 273.714us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.990s 125.706us 50 50 100.00
V2 jitter clkmgr_smoke 1.340s 136.091us 50 50 100.00
V2 frequency clkmgr_frequency 19.620s 2.483ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.300s 2.414ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.620s 2.483ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.677m 14.387ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.920s 135.524us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.360s 194.584us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.360s 650.831us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.360s 650.831us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.850s 29.623us 5 5 100.00
clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
clkmgr_csr_aliasing 1.550s 92.087us 5 5 100.00
clkmgr_same_csr_outstanding 1.820s 216.421us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.850s 29.623us 5 5 100.00
clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
clkmgr_csr_aliasing 1.550s 92.087us 5 5 100.00
clkmgr_same_csr_outstanding 1.820s 216.421us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.350s 1.249ms 5 5 100.00
clkmgr_tl_intg_err 3.500s 459.502us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.830s 567.716us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.830s 567.716us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.830s 567.716us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.830s 567.716us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.790s 525.971us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.500s 459.502us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.620s 2.483ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.300s 2.414ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.830s 567.716us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.610s 299.511us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.830s 376.842us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.290s 170.818us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.590s 286.064us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.270s 177.594us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.350s 1.249ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.420s 280.486us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.350s 1.249ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.730s 1.292ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 44.494m 705.224ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results