CLKMGR Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.700s 311.668us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.250s 208.751us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.730s 538.438us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.830s 77.836us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.920s 36.899us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
clkmgr_csr_aliasing 1.830s 77.836us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.320s 218.527us 50 50 100.00
V2 trans_enables clkmgr_trans 2.130s 404.701us 50 50 100.00
V2 extclk clkmgr_extclk 1.880s 343.787us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.010s 150.569us 50 50 100.00
V2 jitter clkmgr_smoke 1.700s 311.668us 50 50 100.00
V2 frequency clkmgr_frequency 16.740s 2.237ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.950s 2.416ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.740s 2.237ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.647m 14.117ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.000s 156.504us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.140s 145.225us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.190s 903.189us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.190s 903.189us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.250s 208.751us 5 5 100.00
clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
clkmgr_csr_aliasing 1.830s 77.836us 5 5 100.00
clkmgr_same_csr_outstanding 1.590s 89.077us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.250s 208.751us 5 5 100.00
clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
clkmgr_csr_aliasing 1.830s 77.836us 5 5 100.00
clkmgr_same_csr_outstanding 1.590s 89.077us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 2.940s 582.738us 5 5 100.00
clkmgr_tl_intg_err 6.540s 1.653ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.720s 530.526us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.720s 530.526us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.720s 530.526us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.720s 530.526us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.800s 464.672us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.540s 1.653ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.740s 2.237ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.950s 2.416ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.720s 530.526us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.180s 438.341us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.190s 123.091us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.190s 103.656us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.470s 197.691us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.480s 254.812us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 2.940s 582.738us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.170s 157.893us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 2.940s 582.738us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.110s 1.227ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 38.873m 666.547ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80

Past Results