CLKMGR Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.490s 217.803us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.950s 44.649us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 14.070s 2.972ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.100s 211.587us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.820s 362.478us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
clkmgr_csr_aliasing 2.100s 211.587us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.970s 106.743us 50 50 100.00
V2 trans_enables clkmgr_trans 1.530s 243.136us 50 50 100.00
V2 extclk clkmgr_extclk 1.810s 311.600us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.080s 157.257us 50 50 100.00
V2 jitter clkmgr_smoke 1.490s 217.803us 50 50 100.00
V2 frequency clkmgr_frequency 17.690s 2.241ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.260s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.690s 2.241ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.587m 12.323ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.880s 101.205us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.080s 123.011us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.130s 1.058ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.130s 1.058ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.950s 44.649us 5 5 100.00
clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
clkmgr_csr_aliasing 2.100s 211.587us 5 5 100.00
clkmgr_same_csr_outstanding 2.430s 388.642us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.950s 44.649us 5 5 100.00
clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
clkmgr_csr_aliasing 2.100s 211.587us 5 5 100.00
clkmgr_same_csr_outstanding 2.430s 388.642us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.810s 622.249us 5 5 100.00
clkmgr_tl_intg_err 5.500s 1.319ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.400s 235.480us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.400s 235.480us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.400s 235.480us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.400s 235.480us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.530s 550.752us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.500s 1.319ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.690s 2.241ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.260s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.400s 235.480us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.100s 381.290us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.820s 303.972us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.530s 244.113us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.420s 224.949us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.290s 154.311us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.810s 622.249us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.200s 201.430us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.810s 622.249us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 8.050s 1.267ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 44.182m 563.190ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results