CLKMGR Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.240s 114.148us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.050s 131.135us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.890s 1.455ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.950s 71.599us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.230s 251.194us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
clkmgr_csr_aliasing 1.950s 71.599us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.040s 118.287us 50 50 100.00
V2 trans_enables clkmgr_trans 2.030s 385.408us 50 50 100.00
V2 extclk clkmgr_extclk 1.440s 208.224us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.030s 135.900us 50 50 100.00
V2 jitter clkmgr_smoke 1.240s 114.148us 50 50 100.00
V2 frequency clkmgr_frequency 19.570s 2.478ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.480s 2.298ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.570s 2.478ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.159m 9.297ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.930s 131.777us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.150s 165.649us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.410s 468.469us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.410s 468.469us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.050s 131.135us 5 5 100.00
clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
clkmgr_csr_aliasing 1.950s 71.599us 5 5 100.00
clkmgr_same_csr_outstanding 2.380s 465.820us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.050s 131.135us 5 5 100.00
clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
clkmgr_csr_aliasing 1.950s 71.599us 5 5 100.00
clkmgr_same_csr_outstanding 2.380s 465.820us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.980s 1.481ms 5 5 100.00
clkmgr_tl_intg_err 4.080s 848.458us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.610s 852.845us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.610s 852.845us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.610s 852.845us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.610s 852.845us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.050s 721.400us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.080s 848.458us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.570s 2.478ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.480s 2.298ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.610s 852.845us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.920s 338.920us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.620s 228.135us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.310s 150.598us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.700s 277.712us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.450s 208.591us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.980s 1.481ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.990s 130.250us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.980s 1.481ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.670s 1.339ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 50.193m 849.257ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results