CLKMGR Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.610s 271.478us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.980s 80.053us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 15.880s 4.805ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.490s 452.414us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.340s 388.397us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
clkmgr_csr_aliasing 2.490s 452.414us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.030s 115.917us 50 50 100.00
V2 trans_enables clkmgr_trans 1.460s 152.938us 50 50 100.00
V2 extclk clkmgr_extclk 1.420s 203.576us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.170s 193.204us 50 50 100.00
V2 jitter clkmgr_smoke 1.610s 271.478us 50 50 100.00
V2 frequency clkmgr_frequency 19.150s 2.476ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.150s 2.423ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.150s 2.476ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.445m 12.094ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.890s 96.390us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.320s 214.452us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 8.370s 2.074ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 8.370s 2.074ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.980s 80.053us 5 5 100.00
clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
clkmgr_csr_aliasing 2.490s 452.414us 5 5 100.00
clkmgr_same_csr_outstanding 2.230s 366.680us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.980s 80.053us 5 5 100.00
clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
clkmgr_csr_aliasing 2.490s 452.414us 5 5 100.00
clkmgr_same_csr_outstanding 2.230s 366.680us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.800s 578.356us 5 5 100.00
clkmgr_tl_intg_err 5.580s 1.242ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.580s 157.717us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.580s 157.717us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.580s 157.717us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.580s 157.717us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.350s 1.478ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.580s 1.242ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.150s 2.476ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.150s 2.423ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.580s 157.717us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.120s 387.184us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.180s 145.106us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.570s 227.729us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.650s 263.091us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.400s 244.608us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.800s 578.356us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.030s 91.698us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.800s 578.356us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.500s 1.333ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 25.909m 275.256ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results