CLKMGR Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 3.000s 355.676us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.970s 44.267us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 22.299s 19 20 95.00
V1 csr_bit_bash clkmgr_csr_bit_bash 25.216s 3 5 60.00
V1 csr_aliasing clkmgr_csr_aliasing 25.202s 3 5 60.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 25.150s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 22.299s 19 20 95.00
clkmgr_csr_aliasing 25.202s 3 5 60.00
V1 TOTAL 99 105 94.29
V2 peri_enables clkmgr_peri 32.716s 49 50 98.00
V2 trans_enables clkmgr_trans 31.667s 49 50 98.00
V2 extclk clkmgr_extclk 1.820s 122.587us 50 50 100.00
V2 clk_status clkmgr_clk_status 31.642s 49 50 98.00
V2 jitter clkmgr_smoke 3.000s 355.676us 50 50 100.00
V2 frequency clkmgr_frequency 29.825s 49 50 98.00
V2 frequency_timeout clkmgr_frequency_timeout 23.284s 49 50 98.00
V2 frequency_overflow clkmgr_frequency 29.825s 49 50 98.00
V2 stress_all clkmgr_stress_all 1.602m 10.049ms 50 50 100.00
V2 intr_test clkmgr_intr_test 23.467s 49 50 98.00
V2 alert_test clkmgr_alert_test 29.925s 49 50 98.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 23.486s 19 20 95.00
V2 tl_d_illegal_access clkmgr_tl_errors 23.486s 19 20 95.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.970s 44.267us 5 5 100.00
clkmgr_csr_rw 22.299s 19 20 95.00
clkmgr_csr_aliasing 25.202s 3 5 60.00
clkmgr_same_csr_outstanding 25.175s 18 20 90.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.970s 44.267us 5 5 100.00
clkmgr_csr_rw 22.299s 19 20 95.00
clkmgr_csr_aliasing 25.202s 3 5 60.00
clkmgr_same_csr_outstanding 25.175s 18 20 90.00
V2 TOTAL 480 490 97.96
V2S tl_intg_err clkmgr_sec_cm 4.010s 653.553us 5 5 100.00
clkmgr_tl_intg_err 29.980s 18 20 90.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 45.530s 18 20 90.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 45.530s 18 20 90.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 45.530s 18 20 90.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 45.530s 18 20 90.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.110s 1.168ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 29.980s 18 20 90.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 29.825s 49 50 98.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 23.284s 49 50 98.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 45.530s 18 20 90.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.830s 130.555us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.750s 91.183us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 26.114s 49 50 98.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.840s 300.084us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.790s 96.602us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 22.299s 19 20 95.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.010s 653.553us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 22.299s 19 20 95.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 22.299s 19 20 95.00
V2S prim_count_check clkmgr_sec_cm 4.010s 653.553us 5 5 100.00
V2S TOTAL 310 315 98.41
V3 regwen clkmgr_regwen 8.120s 1.304ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 4.547m 72.027ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 989 1010 97.92

Testplan Progress

Items Total Written Passing Progress
V1 6 6 2 33.33
V2 11 11 2 18.18
V2S 9 9 6 66.67
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Failure Buckets

Past Results