CLKMGR Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.810s 197.861us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.490s 18.984us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.470s 1.035ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.540s 107.248us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.550s 454.566us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
clkmgr_csr_aliasing 2.540s 107.248us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.480s 54.161us 50 50 100.00
V2 trans_enables clkmgr_trans 23.621s 49 50 98.00
V2 extclk clkmgr_extclk 2.240s 276.801us 50 50 100.00
V2 clk_status clkmgr_clk_status 23.586s 49 50 98.00
V2 jitter clkmgr_smoke 1.810s 197.861us 50 50 100.00
V2 frequency clkmgr_frequency 23.670s 2.003ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 19.250s 2.415ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 23.670s 2.003ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.752m 13.579ms 49 50 98.00
V2 intr_test clkmgr_intr_test 0.970s 18.436us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.710s 197.258us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 25.158s 19 20 95.00
V2 tl_d_illegal_access clkmgr_tl_errors 25.158s 19 20 95.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.490s 18.984us 5 5 100.00
clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
clkmgr_csr_aliasing 2.540s 107.248us 5 5 100.00
clkmgr_same_csr_outstanding 2.540s 438.720us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.490s 18.984us 5 5 100.00
clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
clkmgr_csr_aliasing 2.540s 107.248us 5 5 100.00
clkmgr_same_csr_outstanding 2.540s 438.720us 20 20 100.00
V2 TOTAL 486 490 99.18
V2S tl_intg_err clkmgr_sec_cm 9.120s 1.700ms 5 5 100.00
clkmgr_tl_intg_err 25.114s 19 20 95.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 25.233s 19 20 95.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 25.233s 19 20 95.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 25.233s 19 20 95.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 25.233s 19 20 95.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 25.196s 19 20 95.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 25.114s 19 20 95.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 23.670s 2.003ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 19.250s 2.415ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 25.233s 19 20 95.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 23.547s 49 50 98.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 23.517s 49 50 98.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 3.040s 333.623us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.860s 99.016us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.560s 282.792us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 9.120s 1.700ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.410s 202.900us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 9.120s 1.700ms 5 5 100.00
V2S TOTAL 310 315 98.41
V3 regwen clkmgr_regwen 7.870s 986.557us 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 4.315m 64.847ms 49 50 98.00
V3 TOTAL 99 100 99.00
TOTAL 1000 1010 99.01

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 9 9 4 44.44
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.76 100.00 100.00 98.81 97.02 98.80

Failure Buckets

Past Results