CLKMGR Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.560s	73.281us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.430s	35.304us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	16.960s	3.229ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	5.460s	624.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	3.200s	69.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
		clkmgr_csr_aliasing	5.460s	624.253us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.390s	69.808us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.810s	236.092us	50	50	100.00
V2	extclk	clkmgr_extclk	1.580s	201.917us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.190s	143.870us	50	50	100.00
V2	jitter	clkmgr_smoke	1.560s	73.281us	50	50	100.00
V2	frequency	clkmgr_frequency	17.040s	2.238ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.070s	2.177ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.040s	2.238ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.382m	21.208ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.330s	97.268us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.480s	112.204us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.060s	420.108us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.060s	420.108us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.430s	35.304us	5	5	100.00
		clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
		clkmgr_csr_aliasing	5.460s	624.253us	5	5	100.00
		clkmgr_same_csr_outstanding	3.230s	358.803us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.430s	35.304us	5	5	100.00
		clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
		clkmgr_csr_aliasing	5.460s	624.253us	5	5	100.00
		clkmgr_same_csr_outstanding	3.230s	358.803us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.370s	1.073ms	5	5	100.00
		clkmgr_tl_intg_err	7.230s	978.582us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	5.390s	419.564us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	5.390s	419.564us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	5.390s	419.564us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	5.390s	419.564us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	7.930s	674.119us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	7.230s	978.582us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.040s	2.238ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.070s	2.177ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	5.390s	419.564us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.050s	402.552us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.360s	40.779us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.760s	145.655us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.410s	440.971us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	29.253s		49	50	98.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.370s	1.073ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.450s	104.024us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.370s	1.073ms	5	5	100.00
V2S		TOTAL			314	315	99.68
V3	regwen	clkmgr_regwen	6.930s	1.231ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	2.559m	26.686ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test clkmgr_div_intersig_mubi has 1 failures.

    • 23.clkmgr_div_intersig_mubi.62535556213210893303672512378570555217068006177908958884812384926737493522564
      Log /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest/run.log

        Chronologic VCS simulator copyright 1991-2022
        Contains Synopsys proprietary information.
        Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 12 00:54 2024
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
        
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
        
        make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
      

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