CLKMGR Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 32.787s 49 50 98.00
V1 csr_hw_reset clkmgr_csr_hw_reset 43.973s 3 5 60.00
V1 csr_rw clkmgr_csr_rw 43.986s 18 20 90.00
V1 csr_bit_bash clkmgr_csr_bit_bash 12.250s 1.996ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.320s 257.499us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 47.832s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 43.986s 18 20 90.00
clkmgr_csr_aliasing 2.320s 257.499us 5 5 100.00
V1 TOTAL 99 105 94.29
V2 peri_enables clkmgr_peri 1.590s 99.424us 50 50 100.00
V2 trans_enables clkmgr_trans 2.750s 480.039us 50 50 100.00
V2 extclk clkmgr_extclk 1.940s 288.701us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.450s 116.266us 50 50 100.00
V2 jitter clkmgr_smoke 32.787s 49 50 98.00
V2 frequency clkmgr_frequency 22.720s 2.361ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 21.870s 2.294ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 22.720s 2.361ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.260m 9.452ms 49 50 98.00
V2 intr_test clkmgr_intr_test 1.020s 29.535us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.660s 126.796us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 22.498s 19 20 95.00
V2 tl_d_illegal_access clkmgr_tl_errors 22.498s 19 20 95.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 43.973s 3 5 60.00
clkmgr_csr_rw 43.986s 18 20 90.00
clkmgr_csr_aliasing 2.320s 257.499us 5 5 100.00
clkmgr_same_csr_outstanding 2.080s 53.460us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 43.973s 3 5 60.00
clkmgr_csr_rw 43.986s 18 20 90.00
clkmgr_csr_aliasing 2.320s 257.499us 5 5 100.00
clkmgr_same_csr_outstanding 2.080s 53.460us 20 20 100.00
V2 TOTAL 488 490 99.59
V2S tl_intg_err clkmgr_sec_cm 4.720s 719.171us 5 5 100.00
clkmgr_tl_intg_err 4.050s 1.004ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.270s 1.094ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.270s 1.094ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.270s 1.094ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.270s 1.094ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 47.761s 18 20 90.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.050s 1.004ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 22.720s 2.361ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 21.870s 2.294ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.270s 1.094ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.900s 105.182us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.870s 130.238us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 24.908s 49 50 98.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 33.081s 49 50 98.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 24.813s 49 50 98.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 43.986s 18 20 90.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.720s 719.171us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 43.986s 18 20 90.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 43.986s 18 20 90.00
V2S prim_count_check clkmgr_sec_cm 4.720s 719.171us 5 5 100.00
V2S TOTAL 310 315 98.41
V3 regwen clkmgr_regwen 32.999s 49 50 98.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.052m 20.545ms 49 50 98.00
V3 TOTAL 98 100 98.00
TOTAL 995 1010 98.51

Testplan Progress

Items Total Written Passing Progress
V1 6 6 2 33.33
V2 11 11 9 81.82
V2S 9 9 5 55.56
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.10 95.68 100.00 100.00 98.70 97.02 98.80

Failure Buckets

Past Results