FLASH_CTRL Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.645m	1.388ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.040s	55.337us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.800s	163.980us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.210m	2.918ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.080m	16.035ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.380s	108.971us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
		flash_ctrl_csr_aliasing	1.080m	16.035ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.340s	23.111us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.620s	33.164us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.360s	87.856us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.060m	531.411us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	51.730m	1.153s	3	3	100.00
		flash_ctrl_hw_rma_reset	16.769m	230.198ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.410s	15.322us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.588m	247.332ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	11.307m	18.619ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.394m	14.029ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.260h	157.490ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.420m	720.447us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.790s	34.804us	29	40	72.50
		flash_ctrl_rw_evict_all_en	33.320s	39.411us	35	40	87.50
		flash_ctrl_re_evict	40.090s	245.090us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.823m	53.770ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.823m	53.770ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.684m	119.309ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.150s	6.464ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.768m	386.925us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.968m	12.877ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	19.178m	3.492ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.742m	783.479us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.190s	26.333us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.261m	1.732ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.960s	47.395us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.440s	53.900us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	20.498m	263.075us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.929m	5.958ms	50	50	100.00
		flash_ctrl_otp_reset	2.304m	44.060us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	51.730m	1.153s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.389m	2.221ms	40	40	100.00
		flash_ctrl_intr_wr	1.544m	20.569ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.188m	23.969ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.770m	99.458ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.885m	8.912ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.206m	2.673ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.300s	19.310us	5	5	100.00
		flash_ctrl_ro_derr	2.971m	487.797us	10	10	100.00
		flash_ctrl_rw_derr	14.360m	9.111ms	8	10	80.00
		flash_ctrl_derr_detect	1.815m	358.079us	5	5	100.00
		flash_ctrl_integrity	12.036m	19.969ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.250s	5.344us	3	5	60.00
		flash_ctrl_ro_serr	2.765m	1.312ms	10	10	100.00
		flash_ctrl_rw_serr	12.262m	8.508ms	5	10	50.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	2.093m	1.173ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.701m	928.669us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.869m	13.738ms	18	20	90.00
		flash_ctrl_write_word_sweep	15.550s	77.971us	1	1	100.00
		flash_ctrl_read_word_sweep	13.910s	23.764us	1	1	100.00
		flash_ctrl_ro	2.565m	1.974ms	19	20	95.00
		flash_ctrl_rw	11.705m	7.717ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	45.890s	694.189us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.166m	157.538ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.098m	10.014ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.350s	65.168us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.790s	55.814us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.070s	853.781us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.070s	853.781us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.800s	163.980us	5	5	100.00
		flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
		flash_ctrl_csr_aliasing	1.080m	16.035ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.430s	851.241us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.800s	163.980us	5	5	100.00
		flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
		flash_ctrl_csr_aliasing	1.080m	16.035ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.430s	851.241us	20	20	100.00
V2		TOTAL			982	1013	96.94
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.720s	19.786us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.278m	6.075ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.278m	6.075ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.278m	6.075ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.500s	115.881us	3	3	100.00
		flash_ctrl_wr_intg	16.080s	189.153us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.645m	1.388ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.304m	44.060us	80	80	100.00
		flash_ctrl_disable	22.960s	47.395us	50	50	100.00
		flash_ctrl_sec_info_access	1.424m	10.145ms	50	50	100.00
		flash_ctrl_connect	16.440s	53.900us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.070s	4.927us	4	5	80.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.570s	271.787us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	13.130us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.960s	47.395us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.500s	115.881us	3	3	100.00
		flash_ctrl_access_after_disable	13.770s	13.907us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.960s	47.395us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.150s	6.464ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.705m	7.717ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.262m	8.508ms	5	10	50.00
		flash_ctrl_rw_derr	14.360m	9.111ms	8	10	80.00
		flash_ctrl_integrity	12.036m	19.969ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	51.730m	1.153s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.770s	835.951us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.210s	17.072us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.160s	53.941us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.378h	1.546ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	49.490s	243.612us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1246	1278	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.41	95.79	94.12	98.85	91.84	98.09	98.10	98.06

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 16 failures:

Test flash_ctrl_rw_evict has 11 failures.

1.flash_ctrl_rw_evict.70991665357716240113655325856810584069153173501677526649106954405990690925497
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 33813.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004658
  UVM_INFO @ 33813.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_rw_evict.72863603908341634117503995937008218693029959955572665416230961543026831503071
Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 13847.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003b38
  UVM_INFO @ 13847.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test flash_ctrl_rw_evict_all_en has 5 failures.

4.flash_ctrl_rw_evict_all_en.98511432234728083452453342149809924801133094031525514671882987485453583760072
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 21395.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0002a1e8
  UVM_INFO @ 21395.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_rw_evict_all_en.46530559786173074372164259898482587509683402696101910422728205761628330342882
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 109328.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0004ff28
  UVM_INFO @ 109328.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_wo has 2 failures.
  - 0.flash_ctrl_wo.84887751132136139542311279717783969522831521210557145067342642559692497084200
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:f9282032-e9b6-4850-a5d4-7a15d586d929
```
  - 3.flash_ctrl_wo.24367000634797869257583974292187004535641018896384204118714757046125626447394
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:127f3b51-1516-4b09-9be1-551fe14af654
```
- Test flash_ctrl_rw_serr has 2 failures.
  - 2.flash_ctrl_rw_serr.26419384190845790603030740286800845121080967839988076886735855894866262378688
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:2949f5fc-77ff-48b6-b07b-3daffe55fd33
```
  - 7.flash_ctrl_rw_serr.22934870577650475800301261511697582121768997139893567494704904744640080888354
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:be01006e-c008-443c-9106-88c7a2bf900e
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 4 failures:

Test flash_ctrl_rw_serr has 3 failures.

0.flash_ctrl_rw_serr.4920565262429174143630915475140485679673098545815978341583175643130335287016
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1960210.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (19264212708291637073257 [0x41450a8000498ced569] vs 19264210456491823388009 [0x41450a0000498ced569])
  UVM_INFO @ 1960210.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.2348024461213848264753652905884049621859296798223947032895775051710254592108
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 175954.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (30696968145006215397985 [0x6801602a06021298261] vs 21252235179266924970593 [0x4801602a06021298261])
  UVM_INFO @ 175954.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test flash_ctrl_rw_derr has 1 failures.

3.flash_ctrl_rw_derr.38659361664410898719528909017677447951809850414362353683760762261462578933289
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 9216936.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (121707674502905219096 [0x69908852020884818] vs 47920698208067012632 [0x29908852020884818])
  UVM_INFO @ 9216936.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 3 failures:
- Test flash_ctrl_read_word_sweep_serr has 2 failures.
  - 0.flash_ctrl_read_word_sweep_serr.61725406912951604846498097902755144275432264473246143090550894457293350956715
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5344.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 5344.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_read_word_sweep_serr.87108729936945192548703956114454202450693720967658703229735271790776297132669
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5475.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 5475.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 14.flash_ctrl_ro.47047032525913363935350934818029033162143350310068415489344765490652856037161
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 129213.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 129213.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 2 failures.

0.flash_ctrl_integrity.112540525832608155063815661703668413937342765158424723154021321649470080384669
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 3691065.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (21622754975693093775040 [0x4942c0160208900a6c0] vs 13764748284545063757028 [0x2ea304184082000a4e4])
  UVM_INFO @ 3691065.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_integrity.113308329437454729780041280046212268157594678165144053842342887640605870506313
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 3672536.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (1983892071602754488327 [0x6b8c08800314010807] vs 1678942015884003199158 [0x5b04004407cc4148b6])
  UVM_INFO @ 3672536.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test flash_ctrl_config_regwen has 1 failures.
  - 0.flash_ctrl_config_regwen.77462006897976401117997597013872779942167766032997377175471619347832966373635
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][*]] addr * is out of bounds: size = * has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 2.flash_ctrl_fs_sup.27803694316515390527436211506593291393906553820228409241742033921972359105653
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 254337.8 ns: (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][0]] addr 5000 is out of bounds: size = 5000
  UVM_INFO @ 254337.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 7.flash_ctrl_rw_derr.97075164971582026237593903005013183505748502686425845130376784662047481912883
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 4070988.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004a00
  UVM_INFO @ 4070988.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```