FLASH_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.652m	86.264us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.470s	37.963us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.110s	25.610us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.323m	3.163ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.046m	5.003ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.740s	355.814us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
		flash_ctrl_csr_aliasing	1.046m	5.003ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.990s	14.798us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.330s	19.823us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.130s	45.153us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.065m	136.349us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	52.778m	1.590s	3	3	100.00
		flash_ctrl_hw_rma_reset	17.820m	420.298ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.050s	15.837us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.206m	1.363s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.130m	5.512ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.815m	13.167ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	48.355m	312.976ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.973m	786.469us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.810s	67.427us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.550s	40.953us	39	40	97.50
		flash_ctrl_re_evict	36.140s	85.754us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.531m	4.451ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.531m	4.451ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.232m	40.443ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.160s	1.594ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.963m	8.033ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.968m	3.784ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.181m	4.271ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.032m	3.770ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.860s	92.436us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.136m	6.188ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.380s	22.498us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.130s	35.559us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.467m	6.395ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.272m	11.592ms	50	50	100.00
		flash_ctrl_otp_reset	2.252m	73.981us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	52.778m	1.590s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.603m	1.646ms	38	40	95.00
		flash_ctrl_intr_wr	1.526m	39.748ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	7.675m	12.551ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.488m	85.849ms	7	10	70.00
V2	invalid_op	flash_ctrl_invalid_op	1.528m	975.333us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.193m	1.678ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.680s	33.532us	5	5	100.00
		flash_ctrl_ro_derr	2.448m	1.093ms	10	10	100.00
		flash_ctrl_rw_derr	11.946m	76.125ms	9	10	90.00
		flash_ctrl_derr_detect	1.024m	49.672us	0	5	0.00
		flash_ctrl_integrity	14.058m	6.611ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.020s	24.847us	5	5	100.00
		flash_ctrl_ro_serr	2.461m	1.387ms	10	10	100.00
		flash_ctrl_rw_serr	12.231m	14.753ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.486m	3.401ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.517m	1.017ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.836m	3.102ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.750s	148.005us	1	1	100.00
		flash_ctrl_read_word_sweep	14.560s	167.053us	1	1	100.00
		flash_ctrl_ro	2.102m	4.797ms	20	20	100.00
		flash_ctrl_rw	11.348m	23.221ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	39.270s	321.698us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	21.618m	86.749ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.641m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.790s	1.307ms	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.940s	15.255us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.320s	113.100us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.320s	113.100us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.110s	25.610us	5	5	100.00
		flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
		flash_ctrl_csr_aliasing	1.046m	5.003ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.370s	157.206us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.110s	25.610us	5	5	100.00
		flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
		flash_ctrl_csr_aliasing	1.046m	5.003ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.370s	157.206us	20	20	100.00
V2		TOTAL			997	1013	98.42
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.650s	22.117us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.227m	3.920ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.227m	3.920ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.227m	3.920ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.650s	112.895us	3	3	100.00
		flash_ctrl_wr_intg	15.410s	163.257us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.652m	86.264us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.252m	73.981us	80	80	100.00
		flash_ctrl_disable	22.380s	22.498us	50	50	100.00
		flash_ctrl_sec_info_access	1.571m	13.699ms	50	50	100.00
		flash_ctrl_connect	17.130s	35.559us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.890s	36.395us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.880s	112.706us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.310s	30.647us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.380s	22.498us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.650s	112.895us	3	3	100.00
		flash_ctrl_access_after_disable	13.670s	14.606us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.110s	29.280us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.380s	22.498us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.160s	1.594ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.348m	23.221ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.231m	14.753ms	9	10	90.00
		flash_ctrl_rw_derr	11.946m	76.125ms	9	10	90.00
		flash_ctrl_integrity	14.058m	6.611ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	52.778m	1.590s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.390s	825.946us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.320s	15.110us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.280s	74.158us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.383h	3.965ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.640s	83.061us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1265	1281	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.71	94.00	98.31	92.52	98.23	96.89	98.12

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_intr_wr_slow_flash has 3 failures.
  - 5.flash_ctrl_intr_wr_slow_flash.115239715039562060581603081040465462095323879015189099287322274674068015234836
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:192e637a-6d6c-4b3d-8e73-1b176874ec36
```
  - 6.flash_ctrl_intr_wr_slow_flash.16113140354578417239436531298665135990733520426125972417824772007255178115360
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:05742001-5cc8-44db-96fa-267c3d2c60f4
```
  - ... and 1 more failures.
- Test flash_ctrl_intr_wr has 1 failures.
  - 8.flash_ctrl_intr_wr.1149792709558641432080587680092699178966410900892770122061086133553627800234
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:2e9d73ba-e792-4868-850e-4c4a6e51688e
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_derr_detect has 2 failures.
  - 0.flash_ctrl_derr_detect.27014627600375935310165240784002449846879512406770702310912656808840114063410
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 30205.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 30205.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_derr_detect.87332299218519608172652145477255887474911807350023184857620494860997817232432
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 80480.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 80480.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 12.flash_ctrl_rw_evict_all_en.68530222270353833451232482473827850838768310601414219964882296098115055218436
    Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 9725.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 9725.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154637) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.114457569691506597465213134065870583705166254243042461292314788213802884836336
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 301792.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154637) { a_addr: 'h9423c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hff  a_opcode: 'h4  a_user: 'h272aa  d_param: 'h0  d_source: 'hff  d_data: 'h59d6ab76  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd44  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 301792.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 1.flash_ctrl_integrity.34838531746124652334769612779402120231033085289001622631599785128558265235286
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 4072493.2 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (42734228181638600213520 [0x90ca08d038e40004410] vs 230623781687757269272 [0xc808c438c40026918])
  UVM_INFO @ 4072493.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@228444) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.109040445333384196642286360191029952744971019080859751723271602646767600041469
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 49671.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@228444) { a_addr: 'h769cc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdc  a_opcode: 'h4  a_user: 'h245aa  d_param: 'h0  d_source: 'hdc  d_data: 'h8d1a9d8a  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd05  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 49671.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 2.flash_ctrl_lcmgr_intg.7928289598666754363640893265053532010895698088831089660750927745957330778722
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 27214.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 27214.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 4.flash_ctrl_rw_serr.112202601822990405370272529957441987690006065695090796771416264879925824647494
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 17647275.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 17647275.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153227) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.99547952768282591203362306726213464306544549842147592591587997902429240226144
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 215653.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153227) { a_addr: 'hbb4a8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7f  a_opcode: 'h4  a_user: 'h2672a  d_param: 'h0  d_source: 'h7f  d_data: 'h121b92f1  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 215653.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 7.flash_ctrl_rw_derr.2076657028362845750061813976923548740426591557324834229763490852961218253246
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 3873171.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004008
  UVM_INFO @ 3873171.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp d06abffa_43b03006:ffffffff_43b* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 21.flash_ctrl_intr_rd.1658471142956805632717785789008635597975085143033444283039364254269996639536
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1109631.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    d06abffa_43b03006:ffffffff_43b03006  mismatch!!
  UVM_INFO @ 1109631.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *faef_a37e7191:ffffffff_a37e* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 33.flash_ctrl_intr_rd.37595527859513906914891927029879794365015871151675475875871874297553702284588
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1580953.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    3603faef_a37e7191:ffffffff_a37e7191  mismatch!!
  UVM_INFO @ 1580953.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

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Past Results

GitHub Revision: `2e5d86c9b5`