3e678c112b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.647m | 174.738us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 27.140s | 14.844us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 47.740s | 25.640us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.202m | 2.430ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.212m | 3.381ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.780s | 65.132us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.212m | 3.381ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 14.320s | 37.794us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 14.040s | 22.053us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 27.000s | 27.776us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.915m | 555.773us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 37.450m | 138.740ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 20.252m | 420.294ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.990s | 15.511us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 43.491m | 246.076ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.515m | 16.009ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.651m | 5.149ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.254h | 195.640ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.277m | 2.764ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.320s | 135.722us | 40 | 40 | 100.00 |
| flash_ctrl_rw_evict_all_en | 32.640s | 30.069us | 38 | 40 | 95.00 | ||
| flash_ctrl_re_evict | 36.090s | 147.282us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 9.515m | 6.599ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 9.515m | 6.599ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 19.069m | 57.901ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 29.760s | 2.299ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 21.478m | 2.738ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 40.801m | 5.899ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 18.159m | 1.749ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 48.959m | 884.160us | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 13.910s | 18.886us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.482m | 1.645ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.860s | 78.811us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 17.360s | 17.307us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 19.825m | 991.557us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.266m | 3.268ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.281m | 38.912us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 37.450m | 138.740ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.756m | 5.588ms | 37 | 40 | 92.50 |
| flash_ctrl_intr_wr | 1.594m | 3.137ms | 9 | 10 | 90.00 | ||
| flash_ctrl_intr_rd_slow_flash | 7.419m | 23.365ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 3.889m | 107.424ms | 9 | 10 | 90.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.941m | 35.076ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.247m | 919.770us | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.230s | 132.085us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 2.539m | 2.781ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 12.491m | 23.718ms | 9 | 10 | 90.00 | ||
| flash_ctrl_derr_detect | 1.072m | 77.541us | 0 | 5 | 0.00 | ||
| flash_ctrl_integrity | 11.868m | 3.779ms | 3 | 5 | 60.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 23.410s | 26.928us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 2.664m | 617.696us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 12.273m | 16.486ms | 8 | 10 | 80.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.417m | 3.735ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.344m | 5.325ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 3.701m | 2.846ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.440s | 79.733us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.190s | 25.954us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.459m | 1.223ms | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 11.438m | 24.147ms | 18 | 20 | 90.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 41.300s | 2.636ms | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 17.181m | 83.020ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 4.815m | 10.014ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 16.210s | 496.391us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.320s | 15.446us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.290s | 212.212us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.290s | 212.212us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 47.740s | 25.640us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.212m | 3.381ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.930s | 222.705us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 47.740s | 25.640us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.212m | 3.381ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.930s | 222.705us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 994 | 1013 | 98.12 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.790s | 13.813us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.444m | 670.396us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.444m | 670.396us | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.444m | 670.396us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.450s | 118.713us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.340s | 226.583us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.647m | 174.738us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.281m | 38.912us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 22.860s | 78.811us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.384m | 4.702ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 17.360s | 17.307us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.130s | 201.138us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 18.880s | 112.996us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.550s | 171.481us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.860s | 78.811us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.450s | 118.713us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.830s | 22.868us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.860s | 78.811us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 29.760s | 2.299ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 11.438m | 24.147ms | 18 | 20 | 90.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 12.273m | 16.486ms | 8 | 10 | 80.00 |
| flash_ctrl_rw_derr | 12.491m | 23.718ms | 9 | 10 | 90.00 | ||
| flash_ctrl_integrity | 11.868m | 3.779ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 37.450m | 138.740ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 22.600s | 725.923us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.330s | 28.562us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.450s | 81.954us | 4 | 5 | 80.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.350h | 1.056ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 143 | 144 | 99.31 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 43.470s | 395.311us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1258 | 1278 | 98.44 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 46 | 83.64 |
| V2S | 12 | 12 | 11 | 91.67 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.27 | 95.67 | 94.09 | 98.31 | 92.52 | 98.17 | 96.89 | 98.21 |
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
Test flash_ctrl_intr_wr has 1 failures.
2.flash_ctrl_intr_wr.51038355574331538474539679919920951773673902493152894670175327764122713559093
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest/run.log
Job ID: smart:b495f5ec-68cc-4dd5-8ebb-ca392627db90
Test flash_ctrl_integrity has 2 failures.
3.flash_ctrl_integrity.71832484914414593445242240116383470064994967865688904221743711454679987689286
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
Job ID: smart:3c6195d9-990f-4b95-8d47-f8d47a39d540
4.flash_ctrl_integrity.9238285969832513306922225164796802387110462857202905252003986104813859036784
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
Job ID: smart:b9253bec-f29d-450a-b482-e43cd00d18dd
Test flash_ctrl_rw_derr has 1 failures.
6.flash_ctrl_rw_derr.103964552469284388383786168270613033986549735333857490554962972765679728105603
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
Job ID: smart:8ba42786-d1f1-4e0c-8111-3f0709135283
Test flash_ctrl_rw has 1 failures.
7.flash_ctrl_rw.36629958343928758798990127642087181996379810512982608250749014159803344019490
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log
Job ID: smart:14187d43-d1c2-4c5a-bf66-e5413ececca1
Test flash_ctrl_intr_wr_slow_flash has 1 failures.
8.flash_ctrl_intr_wr_slow_flash.76014410754324377065185504528503823664466552641463267401525083967097034671979
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest/run.log
Job ID: smart:4f3276b9-7042-4326-ab33-19b8cbcbab90
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
0.flash_ctrl_rw_serr.87307223640345889138005111250913544193850155497954921567598999949007228171006
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 12983869.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 12983869.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.flash_ctrl_rw_serr.45504605986125961606622228146158460961790773498819826932330678524669635737279
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 5820652.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 5820652.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
19.flash_ctrl_rw_evict_all_en.112513491424976283795185624046379550219329561191805317638454998161987531501629
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 39531.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 39531.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.flash_ctrl_rw_evict_all_en.59349058737290958520290433131830864129008725449754463496335460140947858797255
Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 8602.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 8602.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154455) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.flash_ctrl_derr_detect.68060612002195591319356967274792363462089681477620861585252777290878062948559
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 38893.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154455) { a_addr: 'ha8a4 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h24c2a d_param: 'h0 d_source: 'h5 d_data: 'h29e6002b d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd43 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 38893.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157685) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.flash_ctrl_derr_detect.91602761203347540917373008196015060364773093298086226032414699732368487595382
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 80116.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157685) { a_addr: 'hcc780 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h24c2a d_param: 'h0 d_source: 'h1f d_data: 'h6e2513c5 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd42 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 80116.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154325) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.flash_ctrl_derr_detect.43157643625557087420336783075062748383513339707473619086135965195010908941804
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 24261.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154325) { a_addr: 'hf21e0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h2552a d_param: 'h0 d_source: 'h1f d_data: 'h553df8ed d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd13 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 24261.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
2.flash_ctrl_phy_ack_consistency.18682559327354520019165313045055402888036527298474210452062184690054029078649
Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 13696.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x79)
UVM_INFO @ 13696.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154115) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.flash_ctrl_derr_detect.15741112864519350152782355131686218709269285840361890911331741878730510270119
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 182198.6 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154115) { a_addr: 'h199b8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf3 a_opcode: 'h4 a_user: 'h246aa d_param: 'h0 d_source: 'hf3 d_data: 'ha29c1b10 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd0e a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 182198.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@229506) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.flash_ctrl_derr_detect.43432362753740210738806076291829211951666519616682790969594200850975674882734
Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 77540.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@229506) { a_addr: 'h2452c a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb3 a_opcode: 'h4 a_user: 'h2472a d_param: 'h0 d_source: 'hb3 d_data: 'h342a0129 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd34 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 77540.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp de8b2ba9_14eb3e73:ffffffff_ffffffff mismatch!! has 1 failures:
9.flash_ctrl_intr_rd.73497058225353377914848783198031619651390975773223643843674926359088948380918
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 479546.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp de8b2ba9_14eb3e73:ffffffff_ffffffff mismatch!!
UVM_INFO @ 479546.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
14.flash_ctrl_rw.6411443205893833227227233176574496535155957052824649665256525455286902319211
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 7585149.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 7585149.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e89fe19_f6f8ead7:ffffffff_ffffffff mismatch!! has 1 failures:
19.flash_ctrl_intr_rd.60919931113372264749346424289460103547725873315149435151812253553241300315284
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1574087.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp 8e89fe19_f6f8ead7:ffffffff_ffffffff mismatch!!
UVM_INFO @ 1574087.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *eeda5_cddae47a:ffffffff_cddae47a mismatch!! has 1 failures:
34.flash_ctrl_intr_rd.3468570095453594062827395085167203888120861516601695424749073127937927319928
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 2914768.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 0: obs:exp 262eeda5_cddae47a:ffffffff_cddae47a mismatch!!
UVM_INFO @ 2914768.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---