FLASH_CTRL Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.788m	1.414ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.870s	57.532us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.280s	47.546us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.403m	12.819ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.161m	3.315ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.210s	508.664us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
		flash_ctrl_csr_aliasing	1.161m	3.315ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.080s	34.621us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.390s	17.772us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	29.060s	39.054us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.069m	259.441us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.539m	122.178ms	3	3	100.00
		flash_ctrl_hw_rma_reset	21.320m	760.478ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.270s	16.169us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.663m	260.623ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.433m	3.353ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.927m	5.765ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.387h	814.845ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.910m	8.029ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.380s	78.365us	38	40	95.00
		flash_ctrl_rw_evict_all_en	32.880s	120.872us	40	40	100.00
		flash_ctrl_re_evict	36.470s	240.106us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.955m	3.497ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.955m	3.497ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.814m	30.689ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	35.920s	6.809ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.411m	1.800ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.150m	16.651ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.126m	820.765us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.079m	528.246us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.650s	16.494us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.571m	29.988ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.170s	17.962us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.960s	14.527us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.111m	1.262ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.805m	7.376ms	50	50	100.00
		flash_ctrl_otp_reset	2.275m	72.139us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.539m	122.178ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.245m	3.927ms	37	40	92.50
		flash_ctrl_intr_wr	1.399m	9.531ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.025m	49.917ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.273m	254.056ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.725m	3.906ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.296m	10.306ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	28.350s	163.184us	5	5	100.00
		flash_ctrl_ro_derr	3.011m	2.707ms	10	10	100.00
		flash_ctrl_rw_derr	12.461m	8.098ms	9	10	90.00
		flash_ctrl_derr_detect	1.826m	119.453us	5	5	100.00
		flash_ctrl_integrity	12.106m	34.651ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	28.070s	201.727us	4	5	80.00
		flash_ctrl_ro_serr	3.159m	822.480us	10	10	100.00
		flash_ctrl_rw_serr	12.729m	47.172ms	6	10	60.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.354m	1.468ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.786m	1.183ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.720m	5.094ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.590s	78.212us	1	1	100.00
		flash_ctrl_read_word_sweep	19.280s	81.843us	1	1	100.00
		flash_ctrl_ro	2.497m	5.251ms	19	20	95.00
		flash_ctrl_rw	13.506m	46.744ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	43.160s	616.829us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.357m	163.840ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.804m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	17.840s	640.833us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.890s	16.769us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.540s	68.916us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.540s	68.916us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.280s	47.546us	5	5	100.00
		flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
		flash_ctrl_csr_aliasing	1.161m	3.315ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.560s	813.704us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.280s	47.546us	5	5	100.00
		flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
		flash_ctrl_csr_aliasing	1.161m	3.315ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.560s	813.704us	20	20	100.00
V2		TOTAL			998	1013	98.52
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.670s	13.471us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.379m	9.421ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.379m	9.421ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.379m	9.421ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.410s	817.964us	3	3	100.00
		flash_ctrl_wr_intg	15.520s	172.496us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.788m	1.414ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.275m	72.139us	80	80	100.00
		flash_ctrl_disable	23.170s	17.962us	50	50	100.00
		flash_ctrl_sec_info_access	1.517m	12.308ms	50	50	100.00
		flash_ctrl_connect	16.960s	14.527us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.350s	64.832us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.310s	87.293us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.390s	12.124us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.170s	17.962us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.410s	817.964us	3	3	100.00
		flash_ctrl_access_after_disable	14.290s	16.606us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.170s	17.962us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	35.920s	6.809ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	13.506m	46.744ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.729m	47.172ms	6	10	60.00
		flash_ctrl_rw_derr	12.461m	8.098ms	9	10	90.00
		flash_ctrl_integrity	12.106m	34.651ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.539m	122.178ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.170s	655.307us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.480s	14.972us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.950s	32.949us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.343h	1.944ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	49.210s	374.261us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1263	1278	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.67	94.03	98.31	91.84	98.17	96.89	98.12

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_derr has 1 failures.

0.flash_ctrl_rw_derr.35618269550927631773754525922078692477713111624600057713173167916707572656598
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 3517860.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (38535322752151376183304 [0x8290108423103014008] vs 38535322752082656706568 [0x8290108422103014008])
  UVM_INFO @ 3517860.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 1 failures.

3.flash_ctrl_rw_serr.43560936814394635284694825175678154172989475185071296118757431159782863459808
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 4650186.6 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (54308241391935414339585 [0xb800e4010920c140801] vs 54308241391935414339589 [0xb800e4010920c140805])
  UVM_INFO @ 4650186.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 1.flash_ctrl_read_word_sweep_serr.92917517263219134000772008811538255663790700785952731236676453420392484193283
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 15140.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 15140.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 17.flash_ctrl_ro.34961588844812868341633223498249596515870533919376825462845173567672174867119
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 104532.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 104532.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 1.flash_ctrl_rw_serr.48491851925341423633820358498227993057253080754943268111711257548718929983760
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 835932.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 835932.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_serr.82590294722714137407809883434930636156955918593589836914593456528591754647201
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 4946535.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 4946535.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
- Test flash_ctrl_wo has 1 failures.
  - 4.flash_ctrl_wo.84808588011106723372212344432524487891557612461209741513311640715169363197376
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:1720ee32-018c-45a1-9cf6-6837c14eddf9
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 9.flash_ctrl_intr_wr_slow_flash.62653416524415879633778963601165649234071056469803890540399803572629062477944
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:8a72f0db-3bc5-4c5d-b5db-440166005e75
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.16361423747788051937947246030497937619677939504289115379433349482412017799640
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 6075786.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a10
  UVM_INFO @ 6075786.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 7.flash_ctrl_rw_serr.78458146416698992689244665091979358734347831998820832194882451191386686149709
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 6980628.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9551871754182928899 [0x848f10c0a0292a03] vs 9551871754182928898 [0x848f10c0a0292a02])
  UVM_INFO @ 6980628.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *eb9ba52_4417c70c:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 10.flash_ctrl_intr_rd.81517589828442271102299835200969444750441477606309320659418167974440290617734
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4818110.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    1eb9ba52_4417c70c:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 4818110.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 14.flash_ctrl_rw_evict.103219105188253441895575032925162222692165421982794749293605574988358792950850
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 144541.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 144541.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 15.flash_ctrl_rw_evict.79953879384899078113619840297014700325773839708502921743436446031361953568773
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 23417.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 23417.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c2454a5_294f4f70:ffffffff_294f4f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 34.flash_ctrl_intr_rd.91091937401954424063128314366864136178217320254820311621093078036943844484570
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2524695.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    0c2454a5_294f4f70:ffffffff_294f4f70  mismatch!!
  UVM_INFO @ 2524695.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp c229a5e9_bba6a8b9:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 38.flash_ctrl_intr_rd.98871617241972181203182332034895938959859062947463112420648205458232242776408
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3452550.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    c229a5e9_bba6a8b9:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3452550.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```