FLASH_CTRL Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.713m	1.134ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.860s	65.431us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	39.380s	776.543us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.477m	5.050ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.159m	7.058ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.110s	112.771us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
		flash_ctrl_csr_aliasing	1.159m	7.058ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.060s	17.951us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.480s	44.104us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.530s	43.426us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.713m	110.665us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	38.864m	397.589ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.237m	240.256ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.000s	47.017us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.548m	245.163ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.297m	2.757ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.982m	8.821ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.144h	101.737ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.499m	7.809ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.040s	239.257us	37	40	92.50
		flash_ctrl_rw_evict_all_en	31.980s	137.910us	40	40	100.00
		flash_ctrl_re_evict	36.740s	1.063ms	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.849m	9.219ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.849m	9.219ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.198m	42.615ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.490s	5.076ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.584m	314.491us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.294m	41.829ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.798m	413.583us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.424m	2.604ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.830s	27.148us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.380m	6.578ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.660s	25.291us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.810s	57.806us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.382m	3.505ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.974m	11.444ms	50	50	100.00
		flash_ctrl_otp_reset	2.293m	40.031us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	38.864m	397.589ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.525m	6.062ms	37	40	92.50
		flash_ctrl_intr_wr	1.328m	12.544ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.971m	47.713ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.941m	126.922ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.535m	3.582ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.255m	2.907ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.090s	19.593us	5	5	100.00
		flash_ctrl_ro_derr	2.815m	6.765ms	10	10	100.00
		flash_ctrl_rw_derr	11.362m	4.598ms	9	10	90.00
		flash_ctrl_derr_detect	42.910s	28.627us	0	5	0.00
		flash_ctrl_integrity	11.131m	3.818ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.030s	23.387us	5	5	100.00
		flash_ctrl_ro_serr	2.470m	2.893ms	10	10	100.00
		flash_ctrl_rw_serr	11.132m	36.105ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.390m	1.279ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.555m	1.700ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.596m	13.157ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.470s	152.229us	1	1	100.00
		flash_ctrl_read_word_sweep	14.290s	45.184us	1	1	100.00
		flash_ctrl_ro	2.118m	5.679ms	20	20	100.00
		flash_ctrl_rw	10.379m	4.041ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	43.580s	703.827us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.775m	80.589ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.766m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.690s	291.749us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.320s	34.500us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.340s	60.311us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.340s	60.311us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	39.380s	776.543us	5	5	100.00
		flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
		flash_ctrl_csr_aliasing	1.159m	7.058ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.360s	858.409us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	39.380s	776.543us	5	5	100.00
		flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
		flash_ctrl_csr_aliasing	1.159m	7.058ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.360s	858.409us	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.510s	25.458us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.308m	343.629us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.308m	343.629us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.308m	343.629us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.820s	70.831us	3	3	100.00
		flash_ctrl_wr_intg	15.520s	46.075us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.713m	1.134ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.293m	40.031us	80	80	100.00
		flash_ctrl_disable	22.660s	25.291us	50	50	100.00
		flash_ctrl_sec_info_access	1.454m	17.019ms	50	50	100.00
		flash_ctrl_connect	16.810s	57.806us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.280s	81.526us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.110s	29.844us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.480s	10.858us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.660s	25.291us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.820s	70.831us	3	3	100.00
		flash_ctrl_access_after_disable	13.820s	47.624us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.660s	25.291us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.490s	5.076ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.379m	4.041ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.132m	36.105ms	7	10	70.00
		flash_ctrl_rw_derr	11.362m	4.598ms	9	10	90.00
		flash_ctrl_integrity	11.131m	3.818ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	38.864m	397.589ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.870s	649.118us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.230s	15.676us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.070s	15.992us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.351h	1.108ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.790s	56.547us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1254	1278	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.74	94.03	98.31	91.84	98.31	96.89	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 0.flash_ctrl_rw_serr.77797686070546552792997092405930609009775505061648661069526573964686868101254
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:32438397-d1ec-43a4-94f0-677926f5743c
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 5.flash_ctrl_prog_reset.42558263925524963923226826593794953734034351650550064498386963972571845842872
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:f8028714-8397-42cd-a074-541b897bae92
```
- Test flash_ctrl_rw has 3 failures.
  - 9.flash_ctrl_rw.68283322879902976257847786016864717874642841614341862680376182639711745897738
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:d75b28e6-98bf-4638-b1b5-cea2e7ae1927
```
  - 18.flash_ctrl_rw.104451352774855073563369844487501539103184766892231504516698827424177345814194
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:9aea49f8-c22f-450a-8008-dd20e2923ca9
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 1.flash_ctrl_rw_serr.107054744457887428248065316907855003933188145063630930998086914681126950104370
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 12474167.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 12474167.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_serr.112650225825242130074444438108541056242672447562522472628747249425232271589982
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 3588564.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3588564.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 2 failures.

2.flash_ctrl_integrity.67953950506137077181867502728581208756608493784837870507739895818214202892943
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 5318725.8 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (2522593976116698960160 [0x88c0062000a0105120] vs 9470674825494496591880 [0x201680400006210c008])
  UVM_INFO @ 5318725.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_integrity.84517825248820003359314626967441815870400009561501356949208407749229662733388
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 4747733.3 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (57887927546349256640034 [0xc421c60080511430622] vs 18305786308788996 [0x41090402450304])
  UVM_INFO @ 4747733.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.22331674707550254789416021656592836027291341759387623679742380507613503869157
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 5273252.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004610
  UVM_INFO @ 5273252.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 5.flash_ctrl_rw_derr.82644555292249341168658886486762967827805813033734888832386308503756504164672
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2567975.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002200
  UVM_INFO @ 2567975.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 11.flash_ctrl_rw_evict.101399239800040767188560462282198917931097914138548327174927223362240569556074
    Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 40372.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 40372.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.flash_ctrl_rw_evict.5496843342128652348508417770464045471346906710478905327115280119995153340065
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 23449.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 23449.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153471) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.1115372748889871880964585754207034731145528540201455994529168323526936713493
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 216734.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153471) { a_addr: 'ha5884  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'haa  a_opcode: 'h4  a_user: 'h257aa  d_param: 'h0  d_source: 'haa  d_data: 'hc62c2727  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 216734.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.92040849932114394812835155566293787705876765084460567384865417356966873673235
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 9909.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x50)
  UVM_INFO @ 9909.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154312) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.39522958695924579511222202048330651364411773660159472936002732573589760714998
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 42510.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154312) { a_addr: 'hdb788  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h24caa  d_param: 'h0  d_source: 'h21  d_data: 'h875803ae  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd51  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 42510.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154352) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.23842862394982939418736493899482247503898981061717452997437938669954408919371
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 49738.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154352) { a_addr: 'h33f3c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'heb  a_opcode: 'h4  a_user: 'h25faa  d_param: 'h0  d_source: 'heb  d_data: 'h605b2af  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd3d  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 49738.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154256) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.46777554135848703555521153522638980939446760728939754897137875101959919894995
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 28626.6 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154256) { a_addr: 'h3b994  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdb  a_opcode: 'h4  a_user: 'h2622a  d_param: 'h0  d_source: 'hdb  d_data: 'heca5d85f  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd18  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 28626.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 3.flash_ctrl_oversize_error.47561599365928372024205263402188892584991214136477899818670260594926662268999
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 4275952.5 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 4275952.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154624) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.50375274589754387109447443228982295028662862767041082891299139227732375544385
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25264.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154624) { a_addr: 'h545b8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h249aa  d_param: 'h0  d_source: 'h1e  d_data: 'hed8aacf9  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd03  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25264.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c14cab5_b6b42ae4:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 7.flash_ctrl_intr_rd.20736369376982463307756602894910702179961808994969685843940099816863874434750
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 68546.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    9c14cab5_b6b42ae4:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 68546.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ce7ffb0_a62126be:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 23.flash_ctrl_intr_rd.23459600466177845885720843899035552615587866913223637579062768212685590019476
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4635696.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    6ce7ffb0_a62126be:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 4635696.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d0043_598ec443:ffffffff_598ec* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 27.flash_ctrl_intr_rd.99571996997400615128319521286378073987886849859648813568075588163544418344954
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3705939.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    341d0043_598ec443:ffffffff_598ec443  mismatch!!
  UVM_INFO @ 3705939.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 38.flash_ctrl_rw_evict.29721883979336654264660598682468538176800762049385089677332214224917478501708
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 94976.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000820
  UVM_INFO @ 94976.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```