FLASH_CTRL Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.615m	31.241us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.730s	168.963us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.050s	158.556us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.241m	6.606ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.177m	7.271ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.400s	499.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.177m	7.271ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.500s	16.249us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.320s	18.241us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.190s	23.587us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.853m	64.640us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.998m	334.677ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.590m	160.172ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.320s	15.615us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.666m	274.464ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.266m	11.990ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	2.675m	4.448ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	58.434m	70.436ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.145m	4.097ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.230s	52.238us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.140s	74.886us	39	40	97.50
		flash_ctrl_re_evict	36.560s	293.879us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.620m	2.878ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.620m	2.878ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.419m	14.460ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.390s	2.363ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.618m	3.218ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	46.120m	40.212ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.962m	1.497ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.465m	839.666us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.740s	26.373us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.329m	8.052ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.240s	31.744us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.940s	14.148us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.248m	513.694us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.499m	6.323ms	50	50	100.00
		flash_ctrl_otp_reset	2.257m	76.457us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.998m	334.677ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.023m	1.936ms	39	40	97.50
		flash_ctrl_intr_wr	1.286m	2.939ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.486m	69.816ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.553m	95.321ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.491m	23.333ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.230m	1.640ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.550s	49.514us	5	5	100.00
		flash_ctrl_ro_derr	2.771m	8.827ms	10	10	100.00
		flash_ctrl_rw_derr	12.355m	8.203ms	8	10	80.00
		flash_ctrl_derr_detect	43.820s	28.064us	0	5	0.00
		flash_ctrl_integrity	11.000m	4.469ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.330s	388.549us	5	5	100.00
		flash_ctrl_ro_serr	2.451m	613.915us	10	10	100.00
		flash_ctrl_rw_serr	13.071m	4.616ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.748m	2.231ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.808m	1.060ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.993m	5.821ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.040s	156.228us	1	1	100.00
		flash_ctrl_read_word_sweep	14.490s	46.788us	1	1	100.00
		flash_ctrl_ro	2.240m	2.955ms	19	20	95.00
		flash_ctrl_rw	11.288m	18.629ms	15	20	75.00
V2	filesystem_support	flash_ctrl_fs_sup	43.190s	387.422us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.809m	165.705ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.391m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.810s	272.506us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.590s	15.613us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.200s	58.733us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.200s	58.733us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.050s	158.556us	5	5	100.00
		flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.177m	7.271ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.890s	215.203us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.050s	158.556us	5	5	100.00
		flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.177m	7.271ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.890s	215.203us	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.360s	19.390us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.172m	2.415ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.172m	2.415ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.172m	2.415ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.950s	232.275us	3	3	100.00
		flash_ctrl_wr_intg	15.840s	83.822us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.615m	31.241us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.257m	76.457us	80	80	100.00
		flash_ctrl_disable	22.240s	31.744us	50	50	100.00
		flash_ctrl_sec_info_access	1.475m	2.753ms	50	50	100.00
		flash_ctrl_connect	16.940s	14.148us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.160s	35.483us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.990s	25.995us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	13.433us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.240s	31.744us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.950s	232.275us	3	3	100.00
		flash_ctrl_access_after_disable	13.730s	38.696us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.120s	100.749us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.240s	31.744us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.390s	2.363ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.288m	18.629ms	15	20	75.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.071m	4.616ms	7	10	70.00
		flash_ctrl_rw_derr	12.355m	8.203ms	8	10	80.00
		flash_ctrl_integrity	11.000m	4.469ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.998m	334.677ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.310s	685.980us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.030s	35.528us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.050s	16.281us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.403h	9.561ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.780s	73.065us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1257	1281	98.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.73	94.07	98.31	91.84	98.29	96.89	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.54901990463691411807014094817895830417595352347857186603236349188426791983707
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:a49190d6-ba70-4c56-9e98-dcb1f1768260
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.26884266604726351152790319373583980506641856137120666729209711517791685367247
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:91903b45-4546-49b2-bbf8-af21024ef22e
```
- Test flash_ctrl_rw has 4 failures.
  - 3.flash_ctrl_rw.32027654889581391082527376417066373956991276781616007063849963146842680885683
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:239bedfd-bc28-4d02-a3f2-f98338e13052
```
  - 11.flash_ctrl_rw.4747113179314092412147970795817456373731612162965178289708412431354015496873
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:9b07c76d-29e9-42d9-abd4-df9bb845794e
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_ro has 1 failures.

1.flash_ctrl_ro.96318632196631918739826882962437057736707527447316944430574368911287954811146
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 275557.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 275557.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_serr has 2 failures.

5.flash_ctrl_rw_serr.12582606010072224278874615345882640448501347995152962772848446217435529459031
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1945080.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1945080.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_serr.90149463404197790827863259367667806571173274927678643647752471500925463052736
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2619054.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2619054.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_integrity has 2 failures.
  - 1.flash_ctrl_integrity.78715885662393867588353862537973468167210281319846109270629627105391746135102
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1580245.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004800
  UVM_INFO @ 1580245.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_integrity.100430786213035789494958993135452220852417460549247537091834988190728007271157
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 4469465.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004e00
  UVM_INFO @ 4469465.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.3016994542700234986133086273345478406754933308383808289865322549942290818799
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1827721.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004800
  UVM_INFO @ 1827721.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154061) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.43338346390561971911784991042316733039779000040346239662101510853092970427834
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 28063.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154061) { a_addr: 'hfea40  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6f  a_opcode: 'h4  a_user: 'h26e2a  d_param: 'h0  d_source: 'h6f  d_data: 'hcc85c4fa  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 28063.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.89657114496157357695489507745025979000879998061077346514810599755070576572585
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 4011905.3 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (56668690884964676534328 [0xc000411444880240038] vs 9804336700173197488 [0x88100048802620b0])
  UVM_INFO @ 4011905.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.7920080476346637264546053877878850167948607710510729454231811725269968705289
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20282.9 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x36)
  UVM_INFO @ 20282.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152991) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.34125932978845116371181573358054156301332787405716165784145254699922550340390
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26215.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152991) { a_addr: 'h1cd7c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h2692a  d_param: 'h0  d_source: 'h30  d_data: 'hc68bcaf  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd51  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26215.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153659) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.51187966835608359309887185546485333487220597561178302304516974857736831316576
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26123.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153659) { a_addr: 'hf631c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6a  a_opcode: 'h4  a_user: 'h2472a  d_param: 'h0  d_source: 'h6a  d_data: 'hdbc0ee01  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd00  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26123.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@304653) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_oversize_error has 1 failures.

2.flash_ctrl_oversize_error.72696886628625505603769880556716521981459301562751445078623205638162208883251
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 139247.1 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@304653) { a_addr: 'ha005c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8b  a_opcode: 'h4  a_user: 'h274aa  d_param: 'h0  d_source: 'h8b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 139247.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153642) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.55055831474936378059917987795768154429548597167763987538523696213406465865628
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25166.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153642) { a_addr: 'h2a750  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h269aa  d_param: 'h0  d_source: 'h15  d_data: 'h505e005e  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd79  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25166.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79962) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_derr_detect has 1 failures.

4.flash_ctrl_derr_detect.75047278557245874908870437018259348820840869271716398590751996961967323438108
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 4686.7 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79962) { a_addr: 'h19b0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h98  a_opcode: 'h4  a_user: 'h2622a  d_param: 'h0  d_source: 'h98  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4686.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw has 1 failures.
  - 9.flash_ctrl_rw.40810475725447727593456077663645538382839207854985847642155702059525890397756
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 454098.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 454098.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *b6b839_471d90a2:ffffffff_471d90a* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 13.flash_ctrl_intr_rd.54495958738314451701528018975033123357805563855741375560456119061700429882947
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1422299.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    12b6b839_471d90a2:ffffffff_471d90a2  mismatch!!
  UVM_INFO @ 1422299.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 29.flash_ctrl_rw_evict.16820151504130481807805269478988066213051092623618329211422471926381334257413
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 23605.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 23605.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 31.flash_ctrl_rw_evict_all_en.79885534931723337782841212998545615989080582213638944661832362411952635530649
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 32900.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 32900.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```