FLASH_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.614m	131.343us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.850s	74.297us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.110s	83.827us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.445m	9.373ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.164m	1.786ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.960s	39.154us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.164m	1.786ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.940s	15.663us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.670s	16.544us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.380s	77.109us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.061m	243.566us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	40.883m	746.207ms	3	3	100.00
		flash_ctrl_hw_rma_reset	26.330m	630.315ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.210s	33.014us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	37.959m	284.135ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.266m	5.612ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.100m	8.723ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	49.419m	1.304s	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.601m	3.197ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.180s	47.033us	37	40	92.50
		flash_ctrl_rw_evict_all_en	32.070s	27.409us	39	40	97.50
		flash_ctrl_re_evict	35.760s	75.173us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.345m	8.468ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.345m	8.468ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.610m	53.862ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.310s	408.741us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.030m	2.181ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.332m	11.290ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.944m	888.220us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.809m	1.428ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.220s	18.753us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.778m	6.114ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.960s	10.950us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.920s	28.957us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.368m	1.046ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.340m	17.514ms	50	50	100.00
		flash_ctrl_otp_reset	2.275m	75.712us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	40.883m	746.207ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.079m	19.316ms	39	40	97.50
		flash_ctrl_intr_wr	1.451m	6.465ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.950m	134.817ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.176m	150.285ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.571m	1.957ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.176m	856.916us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.770s	63.415us	5	5	100.00
		flash_ctrl_ro_derr	3.036m	8.187ms	10	10	100.00
		flash_ctrl_rw_derr	13.607m	57.648ms	7	10	70.00
		flash_ctrl_derr_detect	43.450s	24.895us	0	5	0.00
		flash_ctrl_integrity	12.211m	3.815ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.720s	23.886us	5	5	100.00
		flash_ctrl_ro_serr	2.864m	761.730us	10	10	100.00
		flash_ctrl_rw_serr	10.101m	20.092ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.453m	9.109ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.524m	1.511ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.175m	5.994ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.270s	41.891us	1	1	100.00
		flash_ctrl_read_word_sweep	14.540s	42.606us	1	1	100.00
		flash_ctrl_ro	2.456m	5.552ms	20	20	100.00
		flash_ctrl_rw	11.794m	5.064ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	44.670s	7.156ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.222m	142.945ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.708m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.580s	104.515us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.980s	35.045us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	22.170s	279.612us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	22.170s	279.612us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.110s	83.827us	5	5	100.00
		flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.164m	1.786ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.280s	250.662us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.110s	83.827us	5	5	100.00
		flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
		flash_ctrl_csr_aliasing	1.164m	1.786ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.280s	250.662us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.600s	12.545us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.352m	3.653ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.352m	3.653ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.352m	3.653ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.010s	114.127us	3	3	100.00
		flash_ctrl_wr_intg	15.050s	45.648us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.614m	131.343us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.275m	75.712us	80	80	100.00
		flash_ctrl_disable	22.960s	10.950us	50	50	100.00
		flash_ctrl_sec_info_access	1.612m	9.813ms	50	50	100.00
		flash_ctrl_connect	16.920s	28.957us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.150s	35.653us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.610s	660.709us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	55.553us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.960s	10.950us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.010s	114.127us	3	3	100.00
		flash_ctrl_access_after_disable	14.070s	40.525us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.150s	33.893us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.960s	10.950us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.310s	408.741us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.794m	5.064ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.101m	20.092ms	7	10	70.00
		flash_ctrl_rw_derr	13.607m	57.648ms	7	10	70.00
		flash_ctrl_integrity	12.211m	3.815ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	40.883m	746.207ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.950s	726.222us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.320s	25.248us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.890s	84.633us	3	5	60.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	13.616ms	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.830s	264.011us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1260	1281	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.67	93.97	98.31	92.52	98.19	96.89	98.24

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 3.flash_ctrl_rw_serr.55422732079711735509255392187654978027709237518253159043269049382828524838010
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:55474f12-7311-41c2-91a0-64d4da1f5fa2
```
- Test flash_ctrl_rw has 1 failures.
  - 8.flash_ctrl_rw.38410842600223000537831937099282538614289884599097405010303962319340318095274
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:996af8a2-9a51-4f22-9976-a8fdf81a09c1
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 9.flash_ctrl_rw_derr.65950410893557555479998205292341916576048715255715331401037296687244540458977
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:44621561-6e71-417b-a168-0c9b2ee1fb25
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 3.flash_ctrl_rw_evict_all_en.100218659997951154736220015604570218161032797694137956626814077596703774342712
    Line 305, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 19443.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 19443.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 2 failures.
  - 19.flash_ctrl_rw_evict.110417738277985502366398856308102803462965121913056733196786548781637954482259
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 33800.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 33800.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.flash_ctrl_rw_evict.31434391100343396571483459505675187924655746148355654764629884697122445981457
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 33464.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 33464.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 2 failures:
- Test flash_ctrl_phy_ack_consistency has 2 failures.
  - 0.flash_ctrl_phy_ack_consistency.49950323030674143933389733632483567293960712006079311808866990741093692572605
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 25669.3 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x79)
  UVM_INFO @ 25669.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_phy_ack_consistency.72640356418926980340239778652834525631849719055801311186599084707522814463414
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 9022.3 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x4b)
  UVM_INFO @ 9022.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.21490578681439419957445487038881099242653053413236611547261877259309560710089
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 4133666.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 4133666.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw has 1 failures.
  - 4.flash_ctrl_rw.108916826571758234008894115089697475534050983563756768029314425504183656981659
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 295599.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 295599.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 4.flash_ctrl_rw_derr.36543589529292905661754087333619887036648556456334971850781162315826444179921
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1945378.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002c08
  UVM_INFO @ 1945378.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.flash_ctrl_rw_derr.37022053675680664341891733535041455565379149637904673601756707886766874719782
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 11434465.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004200
  UVM_INFO @ 11434465.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154689) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.21424701268240042780211297483460711930109551211815864606745220577007938124209
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 28237.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154689) { a_addr: 'he95ec  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf5  a_opcode: 'h4  a_user: 'h2762a  d_param: 'h0  d_source: 'hf5  d_data: 'h93506061  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd44  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 28237.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153939) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.74067013009391719128519828650229344583423724626584248013921166924477785307994
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 24894.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153939) { a_addr: 'ha6c4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he4  a_opcode: 'h4  a_user: 'h2472a  d_param: 'h0  d_source: 'he4  d_data: 'h5252556b  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 24894.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154911) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.47280019074620013371058967481887159418114827881480550102553470642056785244297
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 24776.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154911) { a_addr: 'h44c14  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h274aa  d_param: 'h0  d_source: 'h17  d_data: 'h54bb0612  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd21  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 24776.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.28294752121381623954078316042246998356220414143201790030537302790687743194889
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1113136.5 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (627782314057936674816 [0x22083ad080a0082000] vs 2999992671408016851010 [0xa2a1430000d2040042])
  UVM_INFO @ 1113136.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155694) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.73694255536926158400997644080961185449823830027882455103596702897424533943277
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 59688.4 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155694) { a_addr: 'h12344  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h89  a_opcode: 'h4  a_user: 'h253aa  d_param: 'h0  d_source: 'h89  d_data: 'h954e75d2  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd69  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 59688.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153889) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.68677707296510860721193372847516019280287599268093958321324518780420985719362
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78004.1 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153889) { a_addr: 'hb3b64  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6f  a_opcode: 'h4  a_user: 'h2422a  d_param: 'h0  d_source: 'h6f  d_data: 'h578425e1  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 78004.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp ebbedfff_5895a9ac:ffffffff_5895a9ac mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 5.flash_ctrl_intr_rd.46570004293584693453126587735396474643358446127600660302402077042244691392132
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 284478.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    ebbedfff_5895a9ac:ffffffff_5895a9ac  mismatch!!
  UVM_INFO @ 284478.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@2880850) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_serr has 1 failures.

6.flash_ctrl_rw_serr.70498206664458811980735189150446942361733946609536823444329122695500713079305
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3635571.8 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@2880850) { a_addr: 'h6007c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9c  a_opcode: 'h4  a_user: 'h2742a  d_param: 'h0  d_source: 'h9c  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3635571.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 12.flash_ctrl_rw_evict.65982541985038143014440192155657401576212769225347444608534247819324129301419
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 10302.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 10302.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```