39211701b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.930m | 3.980ms | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 26.950s | 27.159us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 37.940s | 447.502us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 49.840s | 2.084ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 40.110s | 9.905ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.870s | 48.934us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 40.110s | 9.905ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 14.120s | 16.188us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.930s | 17.414us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.670s | 30.898us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 2.092m | 577.389us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 35.479m | 167.295ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 19.607m | 480.307ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.750s | 104.667us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 42.667m | 280.918ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 8.344m | 10.792ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 4.052m | 4.744ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.269h | 180.974ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.494m | 2.812ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.640s | 31.378us | 38 | 40 | 95.00 |
| flash_ctrl_rw_evict_all_en | 33.300s | 627.630us | 38 | 40 | 95.00 | ||
| flash_ctrl_re_evict | 36.660s | 436.783us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 9.255m | 1.397ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 9.255m | 1.397ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 19.816m | 15.103ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 27.100s | 710.261us | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 20.389m | 202.545us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 44.128m | 6.495ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 17.403m | 790.160us | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 54.528m | 4.640ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.180s | 52.725us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 4.036m | 17.170ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.960s | 30.185us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.690s | 18.703us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 24.012m | 3.956ms | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.364m | 3.426ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.242m | 147.928us | 79 | 80 | 98.75 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 35.479m | 167.295ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.060m | 6.603ms | 38 | 40 | 95.00 |
| flash_ctrl_intr_wr | 1.478m | 5.521ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 7.370m | 156.062ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 4.681m | 114.025ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.837m | 10.698ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.252m | 2.661ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.700s | 63.776us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 2.819m | 1.164ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 12.808m | 9.663ms | 9 | 10 | 90.00 | ||
| flash_ctrl_derr_detect | 43.290s | 25.881us | 0 | 5 | 0.00 | ||
| flash_ctrl_integrity | 12.444m | 4.134ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.870s | 47.639us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 2.897m | 3.038ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 14.181m | 4.806ms | 7 | 10 | 70.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.516m | 4.503ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.791m | 1.524ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.144m | 11.954ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.100s | 141.555us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.450s | 24.971us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.397m | 1.152ms | 18 | 20 | 90.00 | ||
| flash_ctrl_rw | 11.225m | 8.615ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 43.260s | 2.642ms | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 17.612m | 159.329ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 2.903m | 10.020ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.620s | 421.236us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.390s | 21.540us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.060s | 61.095us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.060s | 61.095us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 37.940s | 447.502us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 40.110s | 9.905ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.380s | 183.625us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 37.940s | 447.502us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 40.110s | 9.905ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.380s | 183.625us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 994 | 1013 | 98.12 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.890s | 14.621us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.236m | 9.341ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.236m | 9.341ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.236m | 9.341ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 31.880s | 72.041us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.020s | 88.237us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.930m | 3.980ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.242m | 147.928us | 79 | 80 | 98.75 |
| flash_ctrl_disable | 22.960s | 30.185us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.620m | 21.738ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.690s | 18.703us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.030s | 76.519us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 18.000s | 61.601us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.140s | 16.194us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.960s | 30.185us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 31.880s | 72.041us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.810s | 39.526us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_addr_infection | flash_ctrl_host_addr_infection | 30.220s | 39.464us | 3 | 3 | 100.00 |
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.960s | 30.185us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 27.100s | 710.261us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 11.225m | 8.615ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 14.181m | 4.806ms | 7 | 10 | 70.00 |
| flash_ctrl_rw_derr | 12.808m | 9.663ms | 9 | 10 | 90.00 | ||
| flash_ctrl_integrity | 12.444m | 4.134ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 35.479m | 167.295ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 21.120s | 780.194us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.490s | 53.429us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.210s | 15.528us | 4 | 5 | 80.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.401h | 1.045ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 146 | 147 | 99.32 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 47.930s | 1.093ms | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1261 | 1281 | 98.44 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 46 | 83.64 |
| V2S | 13 | 13 | 12 | 92.31 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.06 | 95.71 | 93.94 | 98.31 | 91.16 | 98.21 | 96.89 | 98.21 |
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
Test flash_ctrl_rw_serr has 1 failures.
0.flash_ctrl_rw_serr.14389286894146197738801432464465052528570550545698879839628028725678796230094
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 1071737.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 1071737.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_ro has 2 failures.
9.flash_ctrl_ro.102850961963082831708384426473518445550966678458081402970002142475323156003121
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 18657.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 18657.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.flash_ctrl_ro.104316265225326543307028844032343644374452594330212439154564017614594791380572
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 1037961.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 1037961.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
Test flash_ctrl_rw_serr has 2 failures.
5.flash_ctrl_rw_serr.896651706491302273825554993871110441137314958421389670621048101497534781834
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
Job ID: smart:a65bcd1c-b749-4e79-a067-b1fc3ba78637
7.flash_ctrl_rw_serr.25441153508255006201464512709477404568763434907158305991973309436884808300593
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log
Job ID: smart:5d828f90-aec1-4026-b52b-b352d0e051ca
Test flash_ctrl_rw has 1 failures.
8.flash_ctrl_rw.75244425308370274706760571109241252158861795631601993479269142044792314504834
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
Job ID: smart:19246f84-5f0d-44bd-a2ee-6ea299368e22
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
Test flash_ctrl_rw_evict_all_en has 2 failures.
18.flash_ctrl_rw_evict_all_en.86382374231369635770780250881819699634688706167200950250606916441569756943945
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 21965.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 21965.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.flash_ctrl_rw_evict_all_en.36637378537687258488852637052747491020357777342774917738984502297616217324299
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 9811.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 9811.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_evict has 1 failures.
33.flash_ctrl_rw_evict.83773001607217021880813845752646604205976824896988388009035954258546581399415
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 22679.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 22679.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154052) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.flash_ctrl_derr_detect.98834119194952341968220897815203585926622938677195564852884660281897682642834
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 28028.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154052) { a_addr: 'h935bc a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd8 a_opcode: 'h4 a_user: 'h2602a d_param: 'h0 d_source: 'hd8 d_data: 'h1ca6a749 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd36 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 28028.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
0.flash_ctrl_phy_ack_consistency.93009736037207315032451585992392488729028090047160531077686175593169270625557
Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 19678.0 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x2c)
UVM_INFO @ 19678.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154809) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.flash_ctrl_derr_detect.31066557280363776650937782931846293406355429719435844463988964891888832989651
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 25881.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154809) { a_addr: 'hf7e3c a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf0 a_opcode: 'h4 a_user: 'h265aa d_param: 'h0 d_source: 'hf0 d_data: 'h81733f06 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd17 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 25881.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153078) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.flash_ctrl_derr_detect.30088187413902369673438682339336456912210552885314001291313222913902091525604
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 77936.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153078) { a_addr: 'h230dc a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h42 a_opcode: 'h4 a_user: 'h24a2a d_param: 'h0 d_source: 'h42 d_data: 'h3a7d6786 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd0b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 77936.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155308) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.flash_ctrl_derr_detect.12125586203580016295934106156299596927428405650307642230967953634503576665633
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 26097.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155308) { a_addr: 'h10b88 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf3 a_opcode: 'h4 a_user: 'h265aa d_param: 'h0 d_source: 'hf3 d_data: 'hc884de9c d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd5a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 26097.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' has 1 failures:
4.flash_ctrl_otp_reset.107199792532791032217577952008201597938162304926315995599917392701369616899297
Line 387, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest/run.log
Offending 'dst_req_o'
UVM_ERROR @ 89768.0 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 89768.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
4.flash_ctrl_rw_derr.65784605627904846814398996486885957479552775015060781070340805222336820887428
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 991259.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003600
UVM_INFO @ 991259.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154030) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.flash_ctrl_derr_detect.110607979123263527375855653420642215305177206290133137469735663998613211219073
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
UVM_ERROR @ 26166.6 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154030) { a_addr: 'h2d164 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h64 a_opcode: 'h4 a_user: 'h27c2a d_param: 'h0 d_source: 'h64 d_data: 'h7d33d37f d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd13 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 26166.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f3a_8d629e4b:ffffffff_8d629e4b mismatch!! has 1 failures:
18.flash_ctrl_intr_rd.49686748858856048943801411946011479401077052457610303607808376281651468085552
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 14201822.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp 07321f3a_8d629e4b:ffffffff_8d629e4b mismatch!!
UVM_INFO @ 14201822.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fe_*:ffffffff_* mismatch!! has 1 failures:
29.flash_ctrl_intr_rd.58786479256864024173549389530526183209384962809262023170239954823947686499770
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 992744.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 2: obs:exp 620461fe_79746727:ffffffff_79746727 mismatch!!
UVM_INFO @ 992744.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
31.flash_ctrl_rw_evict.46462242834689006095280137950962554825211070153465564987530136965563510100986
Line 301, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 13342.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
UVM_INFO @ 13342.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---