FLASH_CTRL Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.693m	159.453us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.350s	48.822us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.160s	44.555us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.163m	2.981ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.129m	17.605ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.890s	44.377us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	17.605ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.330s	31.548us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.040s	58.790us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.180s	28.597us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.708m	235.937us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.454m	89.745ms	3	3	100.00
		flash_ctrl_hw_rma_reset	23.878m	760.509ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.760s	29.741us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.130m	294.002ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.236m	15.857ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.326m	41.433ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.125h	48.913ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.666m	11.688ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.470s	71.510us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.780s	65.299us	37	40	92.50
		flash_ctrl_re_evict	35.490s	149.035us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.827m	7.719ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.827m	7.719ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.192m	28.105ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.200s	804.720us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.765m	818.563us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.322m	12.843ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.575m	880.940us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.308m	1.843ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	15.383us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.700m	30.956ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.640s	13.423us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.350s	51.311us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.566m	9.070ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.268m	3.218ms	50	50	100.00
		flash_ctrl_otp_reset	2.252m	62.092us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.454m	89.745ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.259m	6.620ms	38	40	95.00
		flash_ctrl_intr_wr	1.394m	6.206ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.562m	24.200ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.480m	481.622ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.653m	19.374ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.353m	9.176ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.990s	19.684us	5	5	100.00
		flash_ctrl_ro_derr	2.881m	5.678ms	10	10	100.00
		flash_ctrl_rw_derr	11.884m	4.855ms	9	10	90.00
		flash_ctrl_derr_detect	43.060s	155.890us	0	5	0.00
		flash_ctrl_integrity	11.059m	3.576ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.850s	297.440us	5	5	100.00
		flash_ctrl_ro_serr	2.817m	12.092ms	10	10	100.00
		flash_ctrl_rw_serr	12.757m	24.638ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.651m	1.980ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.653m	3.620ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.195m	25.257ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.840s	74.479us	1	1	100.00
		flash_ctrl_read_word_sweep	14.040s	24.962us	1	1	100.00
		flash_ctrl_ro	2.427m	2.175ms	20	20	100.00
		flash_ctrl_rw	11.540m	4.600ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	41.440s	4.597ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.399m	250.824ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.160m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.730s	193.606us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.470s	15.439us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.910s	109.266us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.910s	109.266us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.160s	44.555us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	17.605ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.170s	503.774us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.160s	44.555us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
		flash_ctrl_csr_aliasing	1.129m	17.605ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.170s	503.774us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.270s	18.645us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.507m	6.826ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.507m	6.826ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.507m	6.826ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.940s	258.468us	3	3	100.00
		flash_ctrl_wr_intg	15.610s	550.489us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.693m	159.453us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.252m	62.092us	80	80	100.00
		flash_ctrl_disable	22.640s	13.423us	50	50	100.00
		flash_ctrl_sec_info_access	1.363m	2.361ms	50	50	100.00
		flash_ctrl_connect	17.350s	51.311us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.220s	20.827us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.790s	203.744us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	91.687us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.640s	13.423us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.940s	258.468us	3	3	100.00
		flash_ctrl_access_after_disable	14.200s	14.207us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.720s	27.935us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.640s	13.423us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.200s	804.720us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.540m	4.600ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.757m	24.638ms	7	10	70.00
		flash_ctrl_rw_derr	11.884m	4.855ms	9	10	90.00
		flash_ctrl_integrity	11.059m	3.576ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.454m	89.745ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.800s	796.060us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.360s	15.719us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.260s	15.867us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.351h	2.178ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.100s	113.901us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1281	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	95.74	94.06	98.31	92.52	98.31	96.89	98.18

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 6 failures:

Test flash_ctrl_rw_serr has 3 failures.

1.flash_ctrl_rw_serr.21581412342066059661259839868690473312139283210145378464347481386288036501219
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 5713430.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5713430.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_serr.26383227724120758590091188075064505799699379105797440088516203482621413387328
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1557653.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1557653.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test flash_ctrl_rw has 3 failures.

4.flash_ctrl_rw.106102233954676403071524365740187803376835325634190467370789882341921747591821
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 4080571.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 4080571.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.flash_ctrl_rw.26441687074567695622234921840505691310548038505053267789420862581174134610157
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 355952.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 355952.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.6690999386930269825893924659134238773331808312693082868735332842705045995883
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3935945.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004430
  UVM_INFO @ 3935945.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.75604852580611989796086221960474540489835554454467584761406496693901143509817
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 669436.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003730
  UVM_INFO @ 669436.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 6.flash_ctrl_rw_evict_all_en.91766459761778975732420160614018750880832263598730959891807845280137262682195
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 22821.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 22821.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.flash_ctrl_rw_evict_all_en.90240873144627468412692040582316901549000525812516190209478057809026433800330
    Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 25206.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 25206.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154416) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.95545985831866779372906607481507580457826307841112640306831787884173786384204
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 202351.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154416) { a_addr: 'hea44  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc9  a_opcode: 'h4  a_user: 'h262aa  d_param: 'h0  d_source: 'hc9  d_data: 'h64ace6a9  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd52  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 202351.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155322) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.21053160306023656092947725335556777695877391848387111402135132253155968945186
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 87170.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155322) { a_addr: 'hde99c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5a  a_opcode: 'h4  a_user: 'h277aa  d_param: 'h0  d_source: 'h5a  d_data: 'h1529fd2  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 87170.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *edd518_a3a9e3b3:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 1.flash_ctrl_intr_rd.104577356434245258941326202556871873059538614176441947943502973025317968524517
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2640150.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    05edd518_a3a9e3b3:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 2640150.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153710) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.10058796389100949847173748699542871812628973382383413646512616451432037462810
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 155889.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153710) { a_addr: 'hcfadc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h2772a  d_param: 'h0  d_source: 'h1f  d_data: 'hdfe9e88a  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd53  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 155889.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153579) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.103230077036695078481472678103493473286777875639906871403949300430079897351198
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 43692.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153579) { a_addr: 'hccf58  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb3  a_opcode: 'h4  a_user: 'h2472a  d_param: 'h0  d_source: 'hb3  d_data: 'hac16f353  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd77  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 43692.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153194) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.104071447296347332233104686618725321438795534068485687874201889110605959350289
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 72358.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153194) { a_addr: 'he4a84  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hba  a_opcode: 'h4  a_user: 'h25faa  d_param: 'h0  d_source: 'hba  d_data: 'h7da405e0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd54  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 72358.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.15415870133420065821497891785748951204091052649085047974733592245721474267706
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1667605.0 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (29328080242529943588 [0x19702459800264024] vs 313672074423827695648 [0x11011311c858240820])
  UVM_INFO @ 1667605.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.65577665093454963635280205678795348731067451387848798749142056269459603003199
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 20141.5 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x10)
  UVM_INFO @ 20141.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 12.flash_ctrl_rw_evict_all_en.102621969350739435090116228910343942162705419637115455694779713799269765750747
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 40879.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000011f8
  UVM_INFO @ 40879.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e47e1_137e02c6:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 25.flash_ctrl_intr_rd.24764426188899091061608113572966381259920557583207627624241429656641767769121
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1144291.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    436e47e1_137e02c6:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1144291.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```