FLASH_CTRL Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.640m	63.436us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.290s	52.071us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.710s	164.481us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.254m	2.366ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.099m	8.983ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.420s	63.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	8.983ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.740s	14.260us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.180s	25.682us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.230s	39.929us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.649m	240.648us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.529m	120.747ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.858m	100.148ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.920s	46.538us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.666m	288.336ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.368m	13.407ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.933m	19.055ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.289h	163.369ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.957m	1.472ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.210s	72.656us	38	40	95.00
		flash_ctrl_rw_evict_all_en	32.610s	68.490us	39	40	97.50
		flash_ctrl_re_evict	36.400s	86.902us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.716m	2.344ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.716m	2.344ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.940m	50.162ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	34.010s	2.430ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.564m	164.839us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.016m	10.524ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.191m	790.443us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.830m	1.930ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.650s	15.294us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.767m	6.291ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.220s	13.808us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.770s	15.876us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	14.554m	1.652ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.260m	37.860ms	50	50	100.00
		flash_ctrl_otp_reset	2.268m	141.079us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	36.529m	120.747ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.357m	4.928ms	39	40	97.50
		flash_ctrl_intr_wr	1.461m	5.849ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.207m	50.145ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.482m	265.406ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.674m	12.143ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.260m	3.966ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.370s	18.682us	5	5	100.00
		flash_ctrl_ro_derr	2.872m	3.119ms	10	10	100.00
		flash_ctrl_rw_derr	12.659m	11.026ms	6	10	60.00
		flash_ctrl_derr_detect	1.029m	83.360us	0	5	0.00
		flash_ctrl_integrity	11.630m	13.946ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.280s	92.355us	5	5	100.00
		flash_ctrl_ro_serr	2.825m	3.634ms	10	10	100.00
		flash_ctrl_rw_serr	13.316m	20.556ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.455m	4.407ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.751m	920.929us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.438m	3.959ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.390s	39.628us	1	1	100.00
		flash_ctrl_read_word_sweep	14.220s	106.751us	1	1	100.00
		flash_ctrl_ro	2.429m	2.268ms	20	20	100.00
		flash_ctrl_rw	12.542m	4.578ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	45.200s	1.656ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.504m	562.427ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.438m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.380s	179.221us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.360s	15.428us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.790s	130.825us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.790s	130.825us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.710s	164.481us	5	5	100.00
		flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	8.983ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.420s	178.238us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.710s	164.481us	5	5	100.00
		flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	8.983ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.420s	178.238us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.420s	17.847us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.489m	3.993ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.489m	3.993ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.489m	3.993ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.980s	218.739us	3	3	100.00
		flash_ctrl_wr_intg	16.300s	167.286us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.640m	63.436us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.268m	141.079us	79	80	98.75
		flash_ctrl_disable	23.220s	13.808us	50	50	100.00
		flash_ctrl_sec_info_access	1.523m	8.367ms	50	50	100.00
		flash_ctrl_connect	16.770s	15.876us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.140s	35.529us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.630s	74.894us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.470s	14.500us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.220s	13.808us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.980s	218.739us	3	3	100.00
		flash_ctrl_access_after_disable	13.720s	12.312us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.380s	63.744us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.220s	13.808us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	34.010s	2.430ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.542m	4.578ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.316m	20.556ms	7	10	70.00
		flash_ctrl_rw_derr	12.659m	11.026ms	6	10	60.00
		flash_ctrl_integrity	11.630m	13.946ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.529m	120.747ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.340s	656.375us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.430s	15.542us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.040s	48.917us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.366h	4.101ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.820s	59.887us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1261	1281	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.73	93.98	98.31	92.52	98.25	96.80	98.24

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.18566870178791204831980835216701149769531540396263887064592864306280016178990
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:5e3d759f-af5f-4896-9f20-630e79bbb5d4
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.97701428424503165492037897110726052466052459091367084436595763949253970496850
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:665dd0bb-96e2-44eb-a6c0-98ec88ef8987
```
- Test flash_ctrl_wo has 1 failures.
  - 2.flash_ctrl_wo.3753633198362011349578687134800838416051871182084340567045062752636351103516
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:cb68a01d-8cb3-4f3a-91e9-b5300fb04bb9
```
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.82806048285503165457112383160588491596253737460833525234329307170002322219283
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  Job ID: smart:71991ee7-d4e5-4b64-928f-a354fc645eb4
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 0.flash_ctrl_rw_serr.78805732103393795431743789370660245560945112027820405724834633957749908808088
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 3146370.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3146370.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_rw_serr.30239854146372054043630842758924214629296979541998119850674142168426325159550
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 10885933.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 10885933.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 3.flash_ctrl_rw_derr.106334034640377347382009649986587796766926721009172400516682037313051338655365
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1032788.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004000
  UVM_INFO @ 1032788.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.flash_ctrl_rw_derr.101497763252581981990045921059691436223277869952372846801082352368819614000537
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 16619730.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004630
  UVM_INFO @ 16619730.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@229384) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.11946288269154113110284463846890913845951640520520412228256810445462582487427
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 83360.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@229384) { a_addr: 'hb4f00  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb7  a_opcode: 'h4  a_user: 'h250aa  d_param: 'h0  d_source: 'hb7  d_data: 'h2bc16f2b  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 83360.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'dst_req_o' has 1 failures:
- Test flash_ctrl_otp_reset has 1 failures.
  - 1.flash_ctrl_otp_reset.94939065722549871322571781937912752416509267302057279845163694773109288466467
    Line 387, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest/run.log
```
      Offending 'dst_req_o'
  UVM_ERROR @ 22876.6 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 22876.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154135) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.74199148701703027993153197783179702783364850778543454833712030866704587308946
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 245753.6 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154135) { a_addr: 'hf3534  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4f  a_opcode: 'h4  a_user: 'h27b2a  d_param: 'h0  d_source: 'h4f  d_data: 'h59c9b5ae  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd73  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 245753.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0] *: obs:exp ff_*_ca06ae2b_be6c78b4:*_*_ca06ae2b_be6c78b* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 1.flash_ctrl_wr_intg.41349243488719709896744060543278963622984916296087445594182459665944861445654
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 26602.4 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0]    0: obs:exp    ff_8_ca06ae2b_be6c78b4:47_8_ca06ae2b_be6c78b4  mismatch!!
  UVM_INFO @ 26602.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154195) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.531817250664384521268544812371023340833033482466603474266753507456031489169
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 27553.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154195) { a_addr: 'h40dc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6d  a_opcode: 'h4  a_user: 'h2462a  d_param: 'h0  d_source: 'h6d  d_data: 'h47163a0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd50  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 27553.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155324) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.36352402182801662903640348514715404753410197679849063595638131899201915055102
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 25362.3 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155324) { a_addr: 'he9f04  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hcc  a_opcode: 'h4  a_user: 'h24a2a  d_param: 'h0  d_source: 'hcc  d_data: 'hb493dc7d  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd48  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 25362.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 3.flash_ctrl_rw_evict.1920856408189959246726530173291855096415462819373651590697713060245269738537
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 12432.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 12432.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153638) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.94032633351517943706352496611756046055142030141217470412137310521587258784876
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 53968.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153638) { a_addr: 'ha5ab4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hde  a_opcode: 'h4  a_user: 'h260aa  d_param: 'h0  d_source: 'hde  d_data: 'hc49cb590  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd07  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 53968.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@489173) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_derr has 1 failures.

6.flash_ctrl_rw_derr.20606567498422067578749830441208723453439669046990042051986556446199496582493
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 206912.9 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@489173) { a_addr: 'h6001c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hcf  a_opcode: 'h4  a_user: 'h2442a  d_param: 'h0  d_source: 'hcf  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 206912.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 6.flash_ctrl_rw_evict.22709802881574942315103272002301129563509080942697357214850368820172283233470
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 23967.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 23967.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp af784ee4_eec4aa05:ffffffff_eec4aa* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 22.flash_ctrl_intr_rd.72993309035945082555755432229180714849138540708374289547600176468056194260310
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2161557.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    af784ee4_eec4aa05:ffffffff_eec4aa05  mismatch!!
  UVM_INFO @ 2161557.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 26.flash_ctrl_rw_evict_all_en.33400357338103307784168447141688817058337167316320430989362131939955714754971
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 8617.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000d90
  UVM_INFO @ 8617.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```