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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 95.71 93.88 98.31 92.52 98.23 96.99 98.18


Total test records in report: 1257
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T474 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.1657675949 Aug 23 11:04:37 AM UTC 24 Aug 23 11:07:34 AM UTC 24 783189700 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.225178074 Aug 23 11:06:28 AM UTC 24 Aug 23 11:07:35 AM UTC 24 13383860500 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.1147792167 Aug 23 11:07:36 AM UTC 24 Aug 23 11:08:01 AM UTC 24 41560700 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3132355666 Aug 23 11:07:32 AM UTC 24 Aug 23 11:08:07 AM UTC 24 78663100 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.1759847255 Aug 23 10:35:58 AM UTC 24 Aug 23 11:08:08 AM UTC 24 3775927100 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2174738055 Aug 23 11:07:35 AM UTC 24 Aug 23 11:08:09 AM UTC 24 42530300 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2510817369 Aug 23 11:07:35 AM UTC 24 Aug 23 11:08:13 AM UTC 24 78453700 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3220922759 Aug 23 11:08:09 AM UTC 24 Aug 23 11:08:24 AM UTC 24 12929800 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1466215520 Aug 23 10:57:11 AM UTC 24 Aug 23 11:08:37 AM UTC 24 556145700 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.605712719 Aug 23 11:08:25 AM UTC 24 Aug 23 11:08:41 AM UTC 24 24826200 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2428291700 Aug 23 11:08:30 AM UTC 24 Aug 23 11:08:46 AM UTC 24 25283700 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.800884560 Aug 23 11:08:10 AM UTC 24 Aug 23 11:08:47 AM UTC 24 307608300 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3658129553 Aug 23 11:08:38 AM UTC 24 Aug 23 11:08:54 AM UTC 24 36795200 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3077855240 Aug 23 11:08:42 AM UTC 24 Aug 23 11:08:58 AM UTC 24 26626600 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1603063373 Aug 23 11:08:47 AM UTC 24 Aug 23 11:09:03 AM UTC 24 18838000 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2591136564 Aug 23 11:08:01 AM UTC 24 Aug 23 11:09:05 AM UTC 24 1517216200 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.3790157112 Aug 23 11:08:54 AM UTC 24 Aug 23 11:09:10 AM UTC 24 115454500 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1127887491 Aug 23 11:06:57 AM UTC 24 Aug 23 11:09:33 AM UTC 24 2276903000 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2545103521 Aug 23 11:06:48 AM UTC 24 Aug 23 11:09:50 AM UTC 24 48018363000 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2489215479 Aug 23 10:58:49 AM UTC 24 Aug 23 11:09:50 AM UTC 24 12400085800 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2361780536 Aug 23 11:09:03 AM UTC 24 Aug 23 11:09:58 AM UTC 24 36732900 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3007607033 Aug 23 11:02:33 AM UTC 24 Aug 23 11:10:09 AM UTC 24 13281909000 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2318521331 Aug 23 11:09:06 AM UTC 24 Aug 23 11:10:19 AM UTC 24 34208900 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.312151477 Aug 23 11:08:58 AM UTC 24 Aug 23 11:10:21 AM UTC 24 75982200 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.3793430977 Aug 23 11:09:59 AM UTC 24 Aug 23 11:10:24 AM UTC 24 687184300 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3092637374 Aug 23 11:08:47 AM UTC 24 Aug 23 11:10:24 AM UTC 24 10012710700 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2108578002 Aug 23 10:27:30 AM UTC 24 Aug 23 11:10:25 AM UTC 24 4491632100 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1188134022 Aug 23 11:08:09 AM UTC 24 Aug 23 11:10:33 AM UTC 24 114986400 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2215355880 Aug 23 11:09:11 AM UTC 24 Aug 23 11:10:56 AM UTC 24 14907095300 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.976671636 Aug 23 11:06:33 AM UTC 24 Aug 23 11:11:09 AM UTC 24 50215399600 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1111804245 Aug 23 11:10:21 AM UTC 24 Aug 23 11:11:27 AM UTC 24 1008791500 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.707457083 Aug 23 10:59:07 AM UTC 24 Aug 23 11:11:33 AM UTC 24 60130388400 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.823013431 Aug 23 10:35:53 AM UTC 24 Aug 23 11:11:46 AM UTC 24 489694087500 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.3302820920 Aug 23 11:04:56 AM UTC 24 Aug 23 11:12:06 AM UTC 24 27434038200 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.986574822 Aug 23 11:09:51 AM UTC 24 Aug 23 11:12:18 AM UTC 24 131498300 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.2254678547 Aug 23 11:10:33 AM UTC 24 Aug 23 11:12:20 AM UTC 24 10229215900 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1995389169 Aug 23 11:10:25 AM UTC 24 Aug 23 11:12:23 AM UTC 24 609352800 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.864288247 Aug 23 11:12:21 AM UTC 24 Aug 23 11:12:36 AM UTC 24 72958000 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2628144308 Aug 23 11:10:24 AM UTC 24 Aug 23 11:12:41 AM UTC 24 2444259300 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.848670003 Aug 23 11:11:50 AM UTC 24 Aug 23 11:12:52 AM UTC 24 9024576800 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.489280723 Aug 23 11:12:24 AM UTC 24 Aug 23 11:12:58 AM UTC 24 66503000 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.429653221 Aug 23 11:10:57 AM UTC 24 Aug 23 11:13:11 AM UTC 24 2222389400 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.2298119120 Aug 23 11:12:53 AM UTC 24 Aug 23 11:13:17 AM UTC 24 35043500 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1264505682 Aug 23 11:12:42 AM UTC 24 Aug 23 11:13:19 AM UTC 24 65504700 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.2452650092 Aug 23 11:13:12 AM UTC 24 Aug 23 11:13:28 AM UTC 24 15398500 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.2369025305 Aug 23 11:13:11 AM UTC 24 Aug 23 11:13:30 AM UTC 24 74199600 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2317795482 Aug 23 11:11:11 AM UTC 24 Aug 23 11:13:34 AM UTC 24 4771450900 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.2895464515 Aug 23 11:13:18 AM UTC 24 Aug 23 11:13:34 AM UTC 24 48237800 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2775157748 Aug 23 11:13:29 AM UTC 24 Aug 23 11:13:45 AM UTC 24 48228700 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.1406638285 Aug 23 11:12:59 AM UTC 24 Aug 23 11:13:54 AM UTC 24 1805730200 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.687003165 Aug 23 11:11:28 AM UTC 24 Aug 23 11:14:05 AM UTC 24 3396217100 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1443475766 Aug 23 11:12:07 AM UTC 24 Aug 23 11:14:09 AM UTC 24 9043596300 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.4157459373 Aug 23 11:11:34 AM UTC 24 Aug 23 11:14:12 AM UTC 24 1696274700 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.633628917 Aug 23 11:14:13 AM UTC 24 Aug 23 11:14:38 AM UTC 24 275334400 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3561942848 Aug 23 11:13:20 AM UTC 24 Aug 23 11:14:38 AM UTC 24 10019186100 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3919439695 Aug 23 10:34:46 AM UTC 24 Aug 23 11:14:39 AM UTC 24 243512810700 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.1837943690 Aug 23 11:13:31 AM UTC 24 Aug 23 11:14:54 AM UTC 24 73396900 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.330687041 Aug 23 11:13:35 AM UTC 24 Aug 23 11:15:28 AM UTC 24 39128000 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1976583776 Aug 23 11:13:46 AM UTC 24 Aug 23 11:15:35 AM UTC 24 15263589200 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.4240642831 Aug 23 11:14:39 AM UTC 24 Aug 23 11:15:38 AM UTC 24 3415772700 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.559358656 Aug 23 11:00:33 AM UTC 24 Aug 23 11:15:57 AM UTC 24 656431500 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.1208747907 Aug 23 11:14:05 AM UTC 24 Aug 23 11:16:32 AM UTC 24 150888600 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3066543608 Aug 23 11:12:19 AM UTC 24 Aug 23 11:16:38 AM UTC 24 103863740500 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1093626655 Aug 23 11:13:35 AM UTC 24 Aug 23 11:16:48 AM UTC 24 415161100 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3532282517 Aug 23 11:10:25 AM UTC 24 Aug 23 11:16:49 AM UTC 24 3809441400 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.137457232 Aug 23 11:15:39 AM UTC 24 Aug 23 11:17:18 AM UTC 24 2407021900 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.480210625 Aug 23 11:15:29 AM UTC 24 Aug 23 11:17:18 AM UTC 24 597468200 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1906892518 Aug 23 11:14:56 AM UTC 24 Aug 23 11:17:30 AM UTC 24 9246221100 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.250765662 Aug 23 11:17:31 AM UTC 24 Aug 23 11:17:46 AM UTC 24 34974400 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.4158082520 Aug 23 11:16:50 AM UTC 24 Aug 23 11:17:54 AM UTC 24 8669235100 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.4066163165 Aug 23 11:16:32 AM UTC 24 Aug 23 11:18:06 AM UTC 24 490173300 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1059718429 Aug 23 10:36:55 AM UTC 24 Aug 23 11:18:07 AM UTC 24 4632890700 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3510771562 Aug 23 11:17:47 AM UTC 24 Aug 23 11:18:21 AM UTC 24 28492600 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.3591971276 Aug 23 11:15:57 AM UTC 24 Aug 23 11:18:26 AM UTC 24 2985721200 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.938982132 Aug 23 11:17:55 AM UTC 24 Aug 23 11:18:29 AM UTC 24 32365500 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1964392962 Aug 23 11:18:07 AM UTC 24 Aug 23 11:18:32 AM UTC 24 11103300 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.840320841 Aug 23 10:26:51 AM UTC 24 Aug 23 11:18:34 AM UTC 24 1006141000 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2794513669 Aug 23 11:18:07 AM UTC 24 Aug 23 11:18:44 AM UTC 24 205100600 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3404589049 Aug 23 11:18:29 AM UTC 24 Aug 23 11:18:45 AM UTC 24 15504700 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1829771194 Aug 23 11:18:27 AM UTC 24 Aug 23 11:18:46 AM UTC 24 25399100 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1265255512 Aug 23 11:18:32 AM UTC 24 Aug 23 11:18:48 AM UTC 24 15839200 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3941288323 Aug 23 11:18:45 AM UTC 24 Aug 23 11:19:00 AM UTC 24 87512200 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2428215911 Aug 23 11:16:39 AM UTC 24 Aug 23 11:19:09 AM UTC 24 2618958600 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.1230208821 Aug 23 11:14:09 AM UTC 24 Aug 23 11:19:10 AM UTC 24 64850234700 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2274659732 Aug 23 11:17:19 AM UTC 24 Aug 23 11:19:17 AM UTC 24 22992237500 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.918333651 Aug 23 11:18:21 AM UTC 24 Aug 23 11:19:25 AM UTC 24 5952498500 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.4233056563 Aug 23 11:19:25 AM UTC 24 Aug 23 11:19:49 AM UTC 24 158050100 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.778296381 Aug 23 11:18:35 AM UTC 24 Aug 23 11:19:52 AM UTC 24 10019485400 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.3176245957 Aug 23 11:16:48 AM UTC 24 Aug 23 11:19:56 AM UTC 24 1428632600 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1123011759 Aug 23 11:18:46 AM UTC 24 Aug 23 11:20:07 AM UTC 24 86068700 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2317405433 Aug 23 10:47:08 AM UTC 24 Aug 23 11:20:46 AM UTC 24 573837676100 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.3702949336 Aug 23 10:48:14 AM UTC 24 Aug 23 11:20:51 AM UTC 24 652156700 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2405768964 Aug 23 10:48:13 AM UTC 24 Aug 23 11:20:57 AM UTC 24 93112961600 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.411625560 Aug 23 11:19:57 AM UTC 24 Aug 23 11:21:02 AM UTC 24 8387936700 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3017753813 Aug 23 11:19:11 AM UTC 24 Aug 23 11:21:12 AM UTC 24 82159100 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.140229072 Aug 23 11:17:19 AM UTC 24 Aug 23 11:21:14 AM UTC 24 80485222800 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3681448275 Aug 23 11:19:18 AM UTC 24 Aug 23 11:21:19 AM UTC 24 5152812300 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3486596699 Aug 23 11:20:47 AM UTC 24 Aug 23 11:22:12 AM UTC 24 1006677400 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.1985328004 Aug 23 11:09:34 AM UTC 24 Aug 23 11:22:12 AM UTC 24 80139660100 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3278892586 Aug 23 11:19:01 AM UTC 24 Aug 23 11:22:29 AM UTC 24 22552587400 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1455112756 Aug 23 11:20:08 AM UTC 24 Aug 23 11:22:37 AM UTC 24 2551211200 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1863383076 Aug 23 11:21:01 AM UTC 24 Aug 23 11:22:39 AM UTC 24 1384034500 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3025249201 Aug 23 11:21:13 AM UTC 24 Aug 23 11:23:00 AM UTC 24 703705500 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1414182918 Aug 23 11:18:49 AM UTC 24 Aug 23 11:23:06 AM UTC 24 58245200 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3654141224 Aug 23 11:22:40 AM UTC 24 Aug 23 11:23:13 AM UTC 24 27032600 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.894562151 Aug 23 11:22:12 AM UTC 24 Aug 23 11:23:14 AM UTC 24 2325059000 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1724357990 Aug 23 11:21:03 AM UTC 24 Aug 23 11:23:17 AM UTC 24 5130454700 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.3577654284 Aug 23 11:15:36 AM UTC 24 Aug 23 11:23:20 AM UTC 24 4857602100 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.4082167226 Aug 23 11:23:18 AM UTC 24 Aug 23 11:23:33 AM UTC 24 27402600 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2851924403 Aug 23 11:23:21 AM UTC 24 Aug 23 11:23:38 AM UTC 24 103138300 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1627805845 Aug 23 11:23:14 AM UTC 24 Aug 23 11:23:38 AM UTC 24 14319400 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3108941508 Aug 23 11:23:07 AM UTC 24 Aug 23 11:23:43 AM UTC 24 207445000 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2952744442 Aug 23 11:23:34 AM UTC 24 Aug 23 11:23:50 AM UTC 24 46263100 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.2310808854 Aug 23 11:23:38 AM UTC 24 Aug 23 11:23:54 AM UTC 24 27796300 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.4179962022 Aug 23 11:23:15 AM UTC 24 Aug 23 11:24:08 AM UTC 24 738029700 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3459288888 Aug 23 11:21:15 AM UTC 24 Aug 23 11:24:11 AM UTC 24 5916941400 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.4002401590 Aug 23 11:21:20 AM UTC 24 Aug 23 11:24:11 AM UTC 24 16857068600 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3349884588 Aug 23 11:23:35 AM UTC 24 Aug 23 11:24:32 AM UTC 24 10030186700 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.56890864 Aug 23 11:09:51 AM UTC 24 Aug 23 11:24:48 AM UTC 24 26578055900 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.2735479986 Aug 23 11:24:33 AM UTC 24 Aug 23 11:24:59 AM UTC 24 1106241900 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.3910637707 Aug 23 11:22:38 AM UTC 24 Aug 23 11:25:03 AM UTC 24 8395967700 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.313326137 Aug 23 11:22:30 AM UTC 24 Aug 23 11:25:11 AM UTC 24 39976900600 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3484477509 Aug 23 11:13:55 AM UTC 24 Aug 23 11:25:11 AM UTC 24 40122670200 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.3270509842 Aug 23 11:23:55 AM UTC 24 Aug 23 11:25:21 AM UTC 24 2769522600 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3641118062 Aug 23 11:22:12 AM UTC 24 Aug 23 11:26:12 AM UTC 24 12526151600 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1295482260 Aug 23 11:23:40 AM UTC 24 Aug 23 11:26:19 AM UTC 24 18229400 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3674754661 Aug 23 11:25:04 AM UTC 24 Aug 23 11:26:21 AM UTC 24 3923869000 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.3943940377 Aug 23 11:25:13 AM UTC 24 Aug 23 11:26:27 AM UTC 24 392511300 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3618190259 Aug 23 11:24:11 AM UTC 24 Aug 23 11:26:39 AM UTC 24 39969500 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2141742478 Aug 23 11:10:10 AM UTC 24 Aug 23 11:26:45 AM UTC 24 3073051000 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1346431714 Aug 23 11:25:12 AM UTC 24 Aug 23 11:27:26 AM UTC 24 4736154000 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1831894276 Aug 23 11:20:52 AM UTC 24 Aug 23 11:27:39 AM UTC 24 8007015000 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2669947372 Aug 23 11:26:45 AM UTC 24 Aug 23 11:27:48 AM UTC 24 4718528100 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3637761526 Aug 23 11:26:13 AM UTC 24 Aug 23 11:27:51 AM UTC 24 1263398400 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2668252020 Aug 23 11:26:21 AM UTC 24 Aug 23 11:28:15 AM UTC 24 2579855400 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3999523146 Aug 23 11:27:52 AM UTC 24 Aug 23 11:28:25 AM UTC 24 28350500 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3426679021 Aug 23 11:26:39 AM UTC 24 Aug 23 11:28:29 AM UTC 24 544657000 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.2191429977 Aug 23 11:26:20 AM UTC 24 Aug 23 11:28:33 AM UTC 24 2174818400 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1804057850 Aug 23 11:28:30 AM UTC 24 Aug 23 11:28:53 AM UTC 24 35591200 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1771934416 Aug 23 10:48:29 AM UTC 24 Aug 23 11:28:58 AM UTC 24 4661948900 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.911182681 Aug 23 11:28:26 AM UTC 24 Aug 23 11:29:02 AM UTC 24 55136200 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3884455924 Aug 23 11:28:50 AM UTC 24 Aug 23 11:29:06 AM UTC 24 25262000 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1703753683 Aug 23 11:28:54 AM UTC 24 Aug 23 11:29:10 AM UTC 24 35214400 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3314889176 Aug 23 11:28:58 AM UTC 24 Aug 23 11:29:14 AM UTC 24 15935600 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.1073721830 Aug 23 11:29:06 AM UTC 24 Aug 23 11:29:22 AM UTC 24 157320300 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4273189535 Aug 23 11:27:26 AM UTC 24 Aug 23 11:29:30 AM UTC 24 15113075300 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.278159164 Aug 23 11:28:33 AM UTC 24 Aug 23 11:29:41 AM UTC 24 2104772100 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3689205688 Aug 23 11:26:27 AM UTC 24 Aug 23 11:29:43 AM UTC 24 2045213300 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3764037929 Aug 23 11:29:10 AM UTC 24 Aug 23 11:30:04 AM UTC 24 23690400 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.575375628 Aug 23 11:27:49 AM UTC 24 Aug 23 11:30:12 AM UTC 24 16906808300 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3124569635 Aug 23 11:29:31 AM UTC 24 Aug 23 11:30:16 AM UTC 24 1778635700 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.274413971 Aug 23 11:27:39 AM UTC 24 Aug 23 11:30:30 AM UTC 24 21432776800 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.3279031623 Aug 23 10:59:54 AM UTC 24 Aug 23 11:30:30 AM UTC 24 1817528700 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.1080194721 Aug 23 11:14:38 AM UTC 24 Aug 23 11:30:37 AM UTC 24 3142092800 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2507387872 Aug 23 11:30:12 AM UTC 24 Aug 23 11:30:40 AM UTC 24 4976452300 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.989519219 Aug 23 11:29:02 AM UTC 24 Aug 23 11:31:00 AM UTC 24 10012773500 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3013995036 Aug 23 11:30:31 AM UTC 24 Aug 23 11:31:31 AM UTC 24 4617317900 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.3163535378 Aug 23 11:25:22 AM UTC 24 Aug 23 11:31:34 AM UTC 24 6778748000 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3834287157 Aug 23 11:24:12 AM UTC 24 Aug 23 11:31:49 AM UTC 24 7324667100 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3213448058 Aug 23 11:18:47 AM UTC 24 Aug 23 11:31:58 AM UTC 24 4385457300 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1286232004 Aug 23 11:30:40 AM UTC 24 Aug 23 11:32:03 AM UTC 24 6839683900 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.1880680649 Aug 23 11:29:44 AM UTC 24 Aug 23 11:32:12 AM UTC 24 69061200 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3000855989 Aug 23 11:30:37 AM UTC 24 Aug 23 11:32:49 AM UTC 24 3862432200 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2244633366 Aug 23 11:32:12 AM UTC 24 Aug 23 11:33:13 AM UTC 24 9155901900 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.371110509 Aug 23 11:31:32 AM UTC 24 Aug 23 11:33:17 AM UTC 24 2836752700 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2043853080 Aug 23 11:33:18 AM UTC 24 Aug 23 11:33:33 AM UTC 24 227016300 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.783749935 Aug 23 11:31:50 AM UTC 24 Aug 23 11:33:36 AM UTC 24 1201403100 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3989667716 Aug 23 11:31:35 AM UTC 24 Aug 23 11:33:41 AM UTC 24 7440728400 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.4238363505 Aug 23 11:32:04 AM UTC 24 Aug 23 11:33:45 AM UTC 24 2212518000 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3981968696 Aug 23 11:33:36 AM UTC 24 Aug 23 11:34:07 AM UTC 24 41824800 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1371214659 Aug 23 11:33:34 AM UTC 24 Aug 23 11:34:08 AM UTC 24 74107900 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.945296474 Aug 23 11:33:45 AM UTC 24 Aug 23 11:34:08 AM UTC 24 10721100 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.2169759263 Aug 23 11:33:41 AM UTC 24 Aug 23 11:34:18 AM UTC 24 219144200 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.3475765556 Aug 23 11:23:51 AM UTC 24 Aug 23 11:34:20 AM UTC 24 2693818600 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.3837028610 Aug 23 11:34:09 AM UTC 24 Aug 23 11:34:25 AM UTC 24 15746900 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2481577520 Aug 23 11:34:08 AM UTC 24 Aug 23 11:34:27 AM UTC 24 28931400 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3500034672 Aug 23 11:34:18 AM UTC 24 Aug 23 11:34:34 AM UTC 24 213421100 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1555065628 Aug 23 11:34:26 AM UTC 24 Aug 23 11:34:41 AM UTC 24 169704100 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2064501584 Aug 23 11:32:51 AM UTC 24 Aug 23 11:34:57 AM UTC 24 5889448600 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3383460639 Aug 23 11:34:08 AM UTC 24 Aug 23 11:35:13 AM UTC 24 1333671700 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.1915249997 Aug 23 11:31:59 AM UTC 24 Aug 23 11:35:39 AM UTC 24 4563140800 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1479259855 Aug 23 11:34:21 AM UTC 24 Aug 23 11:35:46 AM UTC 24 10033956500 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3336631344 Aug 23 10:59:20 AM UTC 24 Aug 23 11:35:58 AM UTC 24 465679384300 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.4092124683 Aug 23 10:59:49 AM UTC 24 Aug 23 11:36:42 AM UTC 24 330658988900 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2375934400 Aug 23 11:29:22 AM UTC 24 Aug 23 11:36:56 AM UTC 24 2900060100 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.2294580153 Aug 23 11:31:00 AM UTC 24 Aug 23 11:37:02 AM UTC 24 21581343300 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.449056916 Aug 23 11:30:05 AM UTC 24 Aug 23 11:37:03 AM UTC 24 12643736000 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1572587308 Aug 23 11:34:28 AM UTC 24 Aug 23 11:37:05 AM UTC 24 49585600 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.486237210 Aug 23 11:35:59 AM UTC 24 Aug 23 11:37:12 AM UTC 24 1009715500 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3342997876 Aug 23 11:34:58 AM UTC 24 Aug 23 11:37:20 AM UTC 24 2595052200 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.748537090 Aug 23 11:37:13 AM UTC 24 Aug 23 11:37:29 AM UTC 24 21033900 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3425575373 Aug 23 11:19:50 AM UTC 24 Aug 23 11:37:41 AM UTC 24 1403686700 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.906690998 Aug 23 11:35:40 AM UTC 24 Aug 23 11:38:09 AM UTC 24 71101000 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.168199545 Aug 23 11:36:57 AM UTC 24 Aug 23 11:38:15 AM UTC 24 1074256200 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2926315417 Aug 23 11:37:42 AM UTC 24 Aug 23 11:38:19 AM UTC 24 86761100 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.580394285 Aug 23 11:37:56 AM UTC 24 Aug 23 11:38:21 AM UTC 24 15153700 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1807819395 Aug 23 11:24:48 AM UTC 24 Aug 23 11:38:21 AM UTC 24 1068662900 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2858799890 Aug 23 11:38:10 AM UTC 24 Aug 23 11:38:29 AM UTC 24 14421000 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.2500220931 Aug 23 11:38:15 AM UTC 24 Aug 23 11:38:31 AM UTC 24 33350300 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.4047410511 Aug 23 11:38:19 AM UTC 24 Aug 23 11:38:35 AM UTC 24 25756300 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.1069403026 Aug 23 11:38:22 AM UTC 24 Aug 23 11:38:37 AM UTC 24 162871600 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.1517047645 Aug 23 11:24:09 AM UTC 24 Aug 23 11:38:50 AM UTC 24 630371831500 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2243182291 Aug 23 11:23:44 AM UTC 24 Aug 23 11:39:03 AM UTC 24 834366100 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.168500779 Aug 23 11:38:04 AM UTC 24 Aug 23 11:39:04 AM UTC 24 2065753500 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1400296671 Aug 23 11:37:05 AM UTC 24 Aug 23 11:39:08 AM UTC 24 11848331200 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1620702230 Aug 23 11:36:46 AM UTC 24 Aug 23 11:39:19 AM UTC 24 3548544300 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3805343564 Aug 23 11:19:10 AM UTC 24 Aug 23 11:39:35 AM UTC 24 760532972700 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3796313606 Aug 23 11:34:42 AM UTC 24 Aug 23 11:39:40 AM UTC 24 1443226800 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1315406077 Aug 23 11:33:14 AM UTC 24 Aug 23 11:39:45 AM UTC 24 409839249600 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.116053432 Aug 23 11:37:04 AM UTC 24 Aug 23 11:39:46 AM UTC 24 3972103300 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.452282647 Aug 23 11:38:30 AM UTC 24 Aug 23 11:39:51 AM UTC 24 91253000 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1322891523 Aug 23 11:39:09 AM UTC 24 Aug 23 11:40:07 AM UTC 24 8743186300 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.1772924983 Aug 23 11:35:47 AM UTC 24 Aug 23 11:40:07 AM UTC 24 40479271500 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.785616140 Aug 23 11:38:21 AM UTC 24 Aug 23 11:40:07 AM UTC 24 10012638900 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.1952045457 Aug 23 11:39:53 AM UTC 24 Aug 23 11:40:14 AM UTC 24 453265000 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1127787793 Aug 23 11:38:38 AM UTC 24 Aug 23 11:40:16 AM UTC 24 13265119800 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.3970906406 Aug 23 11:40:15 AM UTC 24 Aug 23 11:40:38 AM UTC 24 21859700 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3657345721 Aug 23 11:40:08 AM UTC 24 Aug 23 11:40:40 AM UTC 24 72938800 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3653552441 Aug 23 11:40:08 AM UTC 24 Aug 23 11:40:41 AM UTC 24 200835300 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2573599807 Aug 23 11:40:08 AM UTC 24 Aug 23 11:40:42 AM UTC 24 41634000 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.808864240 Aug 23 11:40:41 AM UTC 24 Aug 23 11:40:57 AM UTC 24 120561400 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1256186004 Aug 23 11:40:39 AM UTC 24 Aug 23 11:40:58 AM UTC 24 34271500 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3165406721 Aug 23 11:40:42 AM UTC 24 Aug 23 11:40:58 AM UTC 24 26577000 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.2757630067 Aug 23 11:29:42 AM UTC 24 Aug 23 11:41:00 AM UTC 24 80135710500 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.824892169 Aug 23 11:39:36 AM UTC 24 Aug 23 11:41:00 AM UTC 24 516956700 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2161670330 Aug 23 11:40:17 AM UTC 24 Aug 23 11:41:12 AM UTC 24 417626500 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1539192519 Aug 23 11:40:57 AM UTC 24 Aug 23 11:41:13 AM UTC 24 89060700 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.2702232516 Aug 23 11:39:04 AM UTC 24 Aug 23 11:41:34 AM UTC 24 41355500 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.344632146 Aug 23 11:39:46 AM UTC 24 Aug 23 11:41:44 AM UTC 24 16634380600 ps
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T633 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.221434141 Aug 23 11:00:36 AM UTC 24 Aug 23 11:42:07 AM UTC 24 4486315200 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.899023586 Aug 23 11:40:42 AM UTC 24 Aug 23 11:42:08 AM UTC 24 10012463500 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3279229415 Aug 23 11:39:46 AM UTC 24 Aug 23 11:42:30 AM UTC 24 1787238700 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.1227010506 Aug 23 11:41:45 AM UTC 24 Aug 23 11:42:48 AM UTC 24 4181569100 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2904318858 Aug 23 11:42:07 AM UTC 24 Aug 23 11:43:28 AM UTC 24 1068217100 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3640682490 Aug 23 11:41:01 AM UTC 24 Aug 23 11:43:15 AM UTC 24 2491118800 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2654849227 Aug 23 11:43:16 AM UTC 24 Aug 23 11:43:31 AM UTC 24 19948200 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3662271231 Aug 23 11:40:59 AM UTC 24 Aug 23 11:43:33 AM UTC 24 39439600 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1881636011 Aug 23 11:41:14 AM UTC 24 Aug 23 11:43:43 AM UTC 24 42867500 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.2083613676 Aug 23 11:43:29 AM UTC 24 Aug 23 11:44:01 AM UTC 24 31278300 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2598939895 Aug 23 11:43:32 AM UTC 24 Aug 23 11:44:04 AM UTC 24 43290700 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2833678395 Aug 23 11:43:43 AM UTC 24 Aug 23 11:44:07 AM UTC 24 60014100 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2339503105 Aug 23 11:43:33 AM UTC 24 Aug 23 11:44:10 AM UTC 24 338883200 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.379457151 Aug 23 11:44:04 AM UTC 24 Aug 23 11:44:23 AM UTC 24 50438100 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.2296242660 Aug 23 11:44:07 AM UTC 24 Aug 23 11:44:23 AM UTC 24 24866400 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.797495744 Aug 23 11:42:04 AM UTC 24 Aug 23 11:44:23 AM UTC 24 2030973300 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1949165490 Aug 23 11:44:10 AM UTC 24 Aug 23 11:44:26 AM UTC 24 209035500 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.3698721975 Aug 23 11:37:03 AM UTC 24 Aug 23 11:44:31 AM UTC 24 17153262100 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3478386241 Aug 23 11:42:32 AM UTC 24 Aug 23 11:44:34 AM UTC 24 2037051300 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.91786100 Aug 23 11:44:24 AM UTC 24 Aug 23 11:44:39 AM UTC 24 100030500 ps
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