| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.895246186 |
|
|
Aug 23 12:15:26 PM UTC 24 |
Aug 23 12:17:55 PM UTC 24 |
43250300 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1327150659 |
|
|
Aug 23 12:17:41 PM UTC 24 |
Aug 23 12:17:57 PM UTC 24 |
14008300 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.1441355970 |
|
|
Aug 23 12:17:44 PM UTC 24 |
Aug 23 12:18:00 PM UTC 24 |
52536400 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.2005372106 |
|
|
Aug 23 12:17:53 PM UTC 24 |
Aug 23 12:18:11 PM UTC 24 |
65910200 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1615217142 |
|
|
Aug 23 12:14:45 PM UTC 24 |
Aug 23 12:18:12 PM UTC 24 |
2852457400 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.708941656 |
|
|
Aug 23 12:17:58 PM UTC 24 |
Aug 23 12:18:14 PM UTC 24 |
20272700 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.3478152552 |
|
|
Aug 23 12:15:50 PM UTC 24 |
Aug 23 12:18:20 PM UTC 24 |
40281500 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.3825592027 |
|
|
Aug 23 12:14:26 PM UTC 24 |
Aug 23 12:18:25 PM UTC 24 |
44976400 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1609576702 |
|
|
Aug 23 12:16:00 PM UTC 24 |
Aug 23 12:18:29 PM UTC 24 |
38662100 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1311781264 |
|
|
Aug 23 12:16:02 PM UTC 24 |
Aug 23 12:18:31 PM UTC 24 |
43141700 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3009668703 |
|
|
Aug 23 12:18:12 PM UTC 24 |
Aug 23 12:18:31 PM UTC 24 |
27496600 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3833279577 |
|
|
Aug 23 12:16:05 PM UTC 24 |
Aug 23 12:18:34 PM UTC 24 |
96147700 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.2486659467 |
|
|
Aug 23 12:16:05 PM UTC 24 |
Aug 23 12:18:34 PM UTC 24 |
441002500 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3363654033 |
|
|
Aug 23 12:18:16 PM UTC 24 |
Aug 23 12:18:35 PM UTC 24 |
15235900 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.2568465959 |
|
|
Aug 23 12:16:10 PM UTC 24 |
Aug 23 12:18:40 PM UTC 24 |
169880300 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.565909879 |
|
|
Aug 23 12:16:39 PM UTC 24 |
Aug 23 12:18:40 PM UTC 24 |
178654500 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1579999482 |
|
|
Aug 23 12:16:11 PM UTC 24 |
Aug 23 12:18:44 PM UTC 24 |
141144900 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.203892898 |
|
|
Aug 23 12:18:26 PM UTC 24 |
Aug 23 12:18:45 PM UTC 24 |
28864600 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.962830344 |
|
|
Aug 23 12:16:47 PM UTC 24 |
Aug 23 12:18:48 PM UTC 24 |
41065200 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3139895208 |
|
|
Aug 23 12:16:21 PM UTC 24 |
Aug 23 12:18:49 PM UTC 24 |
40824700 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2274282793 |
|
|
Aug 23 12:18:31 PM UTC 24 |
Aug 23 12:18:50 PM UTC 24 |
24937400 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1542241219 |
|
|
Aug 23 12:16:25 PM UTC 24 |
Aug 23 12:18:52 PM UTC 24 |
50495900 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3209542549 |
|
|
Aug 23 12:16:27 PM UTC 24 |
Aug 23 12:18:55 PM UTC 24 |
40847700 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3696003125 |
|
|
Aug 23 12:16:30 PM UTC 24 |
Aug 23 12:18:59 PM UTC 24 |
75949600 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.39075109 |
|
|
Aug 23 12:17:01 PM UTC 24 |
Aug 23 12:19:02 PM UTC 24 |
139707800 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.873536804 |
|
|
Aug 23 12:17:02 PM UTC 24 |
Aug 23 12:19:04 PM UTC 24 |
211555600 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3990590906 |
|
|
Aug 23 12:16:42 PM UTC 24 |
Aug 23 12:19:12 PM UTC 24 |
128306200 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3970354788 |
|
|
Aug 23 12:17:00 PM UTC 24 |
Aug 23 12:19:27 PM UTC 24 |
76763000 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1189401271 |
|
|
Aug 23 12:17:07 PM UTC 24 |
Aug 23 12:19:35 PM UTC 24 |
69929500 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.4163920687 |
|
|
Aug 23 12:17:19 PM UTC 24 |
Aug 23 12:19:47 PM UTC 24 |
139198600 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.3797111887 |
|
|
Aug 23 12:17:20 PM UTC 24 |
Aug 23 12:19:52 PM UTC 24 |
42717500 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1686502920 |
|
|
Aug 23 12:17:56 PM UTC 24 |
Aug 23 12:19:58 PM UTC 24 |
39236700 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1934592559 |
|
|
Aug 23 12:17:34 PM UTC 24 |
Aug 23 12:20:01 PM UTC 24 |
71587100 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2407981012 |
|
|
Aug 23 12:17:35 PM UTC 24 |
Aug 23 12:20:03 PM UTC 24 |
331534700 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.908122291 |
|
|
Aug 23 12:17:42 PM UTC 24 |
Aug 23 12:20:09 PM UTC 24 |
40712100 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.2503213752 |
|
|
Aug 23 12:17:51 PM UTC 24 |
Aug 23 12:20:18 PM UTC 24 |
40026600 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2640812263 |
|
|
Aug 23 12:18:01 PM UTC 24 |
Aug 23 12:20:30 PM UTC 24 |
42461000 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2939482644 |
|
|
Aug 23 12:18:12 PM UTC 24 |
Aug 23 12:20:42 PM UTC 24 |
254611100 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1514484788 |
|
|
Aug 23 12:18:21 PM UTC 24 |
Aug 23 12:20:48 PM UTC 24 |
69997100 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.840914418 |
|
|
Aug 23 12:18:30 PM UTC 24 |
Aug 23 12:20:59 PM UTC 24 |
139139000 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.3301137375 |
|
|
Aug 23 10:57:01 AM UTC 24 |
Aug 23 12:28:58 PM UTC 24 |
6106062900 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.964631884 |
|
|
Aug 23 11:07:51 AM UTC 24 |
Aug 23 12:39:42 PM UTC 24 |
5777333700 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3707413181 |
|
|
Aug 23 10:14:10 AM UTC 24 |
Aug 23 10:14:25 AM UTC 24 |
40892600 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3768774381 |
|
|
Aug 23 10:14:10 AM UTC 24 |
Aug 23 10:14:26 AM UTC 24 |
17473700 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3616131436 |
|
|
Aug 23 10:14:10 AM UTC 24 |
Aug 23 10:14:26 AM UTC 24 |
15053400 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.856256532 |
|
|
Aug 23 10:14:08 AM UTC 24 |
Aug 23 10:14:27 AM UTC 24 |
342558900 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.972727606 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:29 AM UTC 24 |
32052700 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2833910008 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:29 AM UTC 24 |
28263000 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.635460381 |
|
|
Aug 23 10:14:10 AM UTC 24 |
Aug 23 10:14:29 AM UTC 24 |
23734200 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.811011565 |
|
|
Aug 23 10:14:13 AM UTC 24 |
Aug 23 10:14:30 AM UTC 24 |
23959300 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2779433414 |
|
|
Aug 23 10:14:13 AM UTC 24 |
Aug 23 10:14:30 AM UTC 24 |
45182000 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2154292524 |
|
|
Aug 23 10:14:13 AM UTC 24 |
Aug 23 10:14:30 AM UTC 24 |
43276300 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3800306320 |
|
|
Aug 23 10:14:13 AM UTC 24 |
Aug 23 10:14:30 AM UTC 24 |
18362600 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3021202074 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:14:32 AM UTC 24 |
360949500 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2902080723 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:33 AM UTC 24 |
83681700 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.992865004 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:33 AM UTC 24 |
105295300 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1435646885 |
|
|
Aug 23 10:14:17 AM UTC 24 |
Aug 23 10:14:33 AM UTC 24 |
14829800 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.582129870 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:14:33 AM UTC 24 |
31981700 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3902512476 |
|
|
Aug 23 10:14:15 AM UTC 24 |
Aug 23 10:14:34 AM UTC 24 |
81257600 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1940713397 |
|
|
Aug 23 10:14:13 AM UTC 24 |
Aug 23 10:14:34 AM UTC 24 |
21217100 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3926675611 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:14:36 AM UTC 24 |
317780700 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1819618244 |
|
|
Aug 23 10:14:28 AM UTC 24 |
Aug 23 10:14:44 AM UTC 24 |
60653600 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1310171030 |
|
|
Aug 23 10:14:28 AM UTC 24 |
Aug 23 10:14:44 AM UTC 24 |
26525000 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2284361318 |
|
|
Aug 23 10:14:28 AM UTC 24 |
Aug 23 10:14:44 AM UTC 24 |
17481700 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.657696063 |
|
|
Aug 23 10:14:26 AM UTC 24 |
Aug 23 10:14:45 AM UTC 24 |
21110600 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.228291329 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:46 AM UTC 24 |
233816500 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2856331086 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:49 AM UTC 24 |
209962100 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1728819246 |
|
|
Aug 23 10:14:30 AM UTC 24 |
Aug 23 10:14:50 AM UTC 24 |
40746400 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3583630606 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:14:50 AM UTC 24 |
345631800 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1298373961 |
|
|
Aug 23 10:14:35 AM UTC 24 |
Aug 23 10:14:51 AM UTC 24 |
13959000 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3207824478 |
|
|
Aug 23 10:14:34 AM UTC 24 |
Aug 23 10:14:51 AM UTC 24 |
38865500 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4219972420 |
|
|
Aug 23 10:14:35 AM UTC 24 |
Aug 23 10:14:51 AM UTC 24 |
17217500 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.731570006 |
|
|
Aug 23 10:14:35 AM UTC 24 |
Aug 23 10:14:51 AM UTC 24 |
23706700 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1473735574 |
|
|
Aug 23 10:14:32 AM UTC 24 |
Aug 23 10:14:51 AM UTC 24 |
684232800 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1026295771 |
|
|
Aug 23 10:14:35 AM UTC 24 |
Aug 23 10:14:52 AM UTC 24 |
16927500 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1933522914 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:14:53 AM UTC 24 |
876876800 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3917946053 |
|
|
Aug 23 10:14:32 AM UTC 24 |
Aug 23 10:14:55 AM UTC 24 |
469806300 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2239662731 |
|
|
Aug 23 10:14:32 AM UTC 24 |
Aug 23 10:14:55 AM UTC 24 |
77962200 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.709212991 |
|
|
Aug 23 10:14:38 AM UTC 24 |
Aug 23 10:14:58 AM UTC 24 |
146433100 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3643482461 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:15:01 AM UTC 24 |
859407700 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1974628987 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:15:02 AM UTC 24 |
1710794900 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3904109090 |
|
|
Aug 23 10:14:48 AM UTC 24 |
Aug 23 10:15:06 AM UTC 24 |
46471700 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2713069105 |
|
|
Aug 23 10:14:35 AM UTC 24 |
Aug 23 10:15:07 AM UTC 24 |
97069300 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4060371107 |
|
|
Aug 23 10:14:51 AM UTC 24 |
Aug 23 10:15:07 AM UTC 24 |
68451100 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.357389538 |
|
|
Aug 23 10:14:51 AM UTC 24 |
Aug 23 10:15:08 AM UTC 24 |
207538500 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.652252562 |
|
|
Aug 23 10:14:14 AM UTC 24 |
Aug 23 10:15:08 AM UTC 24 |
42556900 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2114027250 |
|
|
Aug 23 10:14:51 AM UTC 24 |
Aug 23 10:15:08 AM UTC 24 |
69749000 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.568422587 |
|
|
Aug 23 10:14:46 AM UTC 24 |
Aug 23 10:15:09 AM UTC 24 |
136566000 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.373417375 |
|
|
Aug 23 10:14:52 AM UTC 24 |
Aug 23 10:15:10 AM UTC 24 |
78616600 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2276600927 |
|
|
Aug 23 10:14:51 AM UTC 24 |
Aug 23 10:15:10 AM UTC 24 |
23664200 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2115695153 |
|
|
Aug 23 10:14:51 AM UTC 24 |
Aug 23 10:15:11 AM UTC 24 |
14699300 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3304659359 |
|
|
Aug 23 10:14:54 AM UTC 24 |
Aug 23 10:15:13 AM UTC 24 |
189373800 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4192609187 |
|
|
Aug 23 10:14:56 AM UTC 24 |
Aug 23 10:15:14 AM UTC 24 |
70902400 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.55486351 |
|
|
Aug 23 10:14:56 AM UTC 24 |
Aug 23 10:15:16 AM UTC 24 |
103991700 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.316638710 |
|
|
Aug 23 10:15:09 AM UTC 24 |
Aug 23 10:15:30 AM UTC 24 |
280526200 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.689332840 |
|
|
Aug 23 10:14:30 AM UTC 24 |
Aug 23 10:15:17 AM UTC 24 |
124812900 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1148348548 |
|
|
Aug 23 10:14:30 AM UTC 24 |
Aug 23 10:15:17 AM UTC 24 |
1401465600 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3791404369 |
|
|
Aug 23 10:15:02 AM UTC 24 |
Aug 23 10:15:21 AM UTC 24 |
29535900 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3872479690 |
|
|
Aug 23 10:14:46 AM UTC 24 |
Aug 23 10:15:21 AM UTC 24 |
1208966500 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.90429825 |
|
|
Aug 23 10:15:03 AM UTC 24 |
Aug 23 10:15:23 AM UTC 24 |
26148900 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.1051817455 |
|
|
Aug 23 10:15:08 AM UTC 24 |
Aug 23 10:15:24 AM UTC 24 |
54978800 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3914595603 |
|
|
Aug 23 10:15:10 AM UTC 24 |
Aug 23 10:15:26 AM UTC 24 |
37492600 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.68019041 |
|
|
Aug 23 10:15:11 AM UTC 24 |
Aug 23 10:15:28 AM UTC 24 |
36544700 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2485646124 |
|
|
Aug 23 10:15:11 AM UTC 24 |
Aug 23 10:15:28 AM UTC 24 |
169345900 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3449376187 |
|
|
Aug 23 10:15:08 AM UTC 24 |
Aug 23 10:15:28 AM UTC 24 |
389777300 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.553418807 |
|
|
Aug 23 10:15:10 AM UTC 24 |
Aug 23 10:15:29 AM UTC 24 |
20590400 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.557540390 |
|
|
Aug 23 10:15:09 AM UTC 24 |
Aug 23 10:15:31 AM UTC 24 |
106244700 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.732926667 |
|
|
Aug 23 10:15:08 AM UTC 24 |
Aug 23 10:15:32 AM UTC 24 |
742395100 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1329195475 |
|
|
Aug 23 10:14:30 AM UTC 24 |
Aug 23 10:15:32 AM UTC 24 |
2241141500 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2533171621 |
|
|
Aug 23 10:15:17 AM UTC 24 |
Aug 23 10:15:36 AM UTC 24 |
121451800 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2565754716 |
|
|
Aug 23 10:15:15 AM UTC 24 |
Aug 23 10:15:36 AM UTC 24 |
45161700 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1192596630 |
|
|
Aug 23 10:15:17 AM UTC 24 |
Aug 23 10:15:37 AM UTC 24 |
34006100 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.96449447 |
|
|
Aug 23 10:15:22 AM UTC 24 |
Aug 23 10:15:39 AM UTC 24 |
16525300 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4141000204 |
|
|
Aug 23 10:15:21 AM UTC 24 |
Aug 23 10:15:41 AM UTC 24 |
14454100 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.202129094 |
|
|
Aug 23 10:15:25 AM UTC 24 |
Aug 23 10:15:43 AM UTC 24 |
102289400 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1178526283 |
|
|
Aug 23 10:15:23 AM UTC 24 |
Aug 23 10:15:44 AM UTC 24 |
93229200 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3631129815 |
|
|
Aug 23 10:14:46 AM UTC 24 |
Aug 23 10:15:44 AM UTC 24 |
6315872100 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4060223408 |
|
|
Aug 23 10:14:52 AM UTC 24 |
Aug 23 10:15:46 AM UTC 24 |
26351400 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.759303853 |
|
|
Aug 23 10:14:46 AM UTC 24 |
Aug 23 10:15:46 AM UTC 24 |
3002742900 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1158151215 |
|
|
Aug 23 10:15:29 AM UTC 24 |
Aug 23 10:15:47 AM UTC 24 |
249226600 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1294133472 |
|
|
Aug 23 10:15:31 AM UTC 24 |
Aug 23 10:15:48 AM UTC 24 |
53607700 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2731254099 |
|
|
Aug 23 10:15:30 AM UTC 24 |
Aug 23 10:15:49 AM UTC 24 |
33233700 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.14301638 |
|
|
Aug 23 10:15:30 AM UTC 24 |
Aug 23 10:15:49 AM UTC 24 |
13058300 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.558699718 |
|
|
Aug 23 10:15:28 AM UTC 24 |
Aug 23 10:15:50 AM UTC 24 |
129303500 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3597889465 |
|
|
Aug 23 10:15:32 AM UTC 24 |
Aug 23 10:15:52 AM UTC 24 |
22272800 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2080960982 |
|
|
Aug 23 10:15:33 AM UTC 24 |
Aug 23 10:15:52 AM UTC 24 |
120892500 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.294411585 |
|
|
Aug 23 10:14:52 AM UTC 24 |
Aug 23 10:15:53 AM UTC 24 |
2415504200 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.966298866 |
|
|
Aug 23 10:15:13 AM UTC 24 |
Aug 23 10:15:54 AM UTC 24 |
449639100 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.953978025 |
|
|
Aug 23 10:15:37 AM UTC 24 |
Aug 23 10:15:56 AM UTC 24 |
67709400 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3077126340 |
|
|
Aug 23 10:15:33 AM UTC 24 |
Aug 23 10:15:56 AM UTC 24 |
276902500 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3757836074 |
|
|
Aug 23 10:15:38 AM UTC 24 |
Aug 23 10:15:57 AM UTC 24 |
32746700 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1373094129 |
|
|
Aug 23 10:15:41 AM UTC 24 |
Aug 23 10:15:58 AM UTC 24 |
127282800 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.479088471 |
|
|
Aug 23 10:15:40 AM UTC 24 |
Aug 23 10:15:59 AM UTC 24 |
36735800 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2000935935 |
|
|
Aug 23 10:15:48 AM UTC 24 |
Aug 23 10:16:04 AM UTC 24 |
24486500 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2363122894 |
|
|
Aug 23 10:15:43 AM UTC 24 |
Aug 23 10:16:04 AM UTC 24 |
91430000 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.535576033 |
|
|
Aug 23 10:15:44 AM UTC 24 |
Aug 23 10:16:05 AM UTC 24 |
35476300 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3617054220 |
|
|
Aug 23 10:15:50 AM UTC 24 |
Aug 23 10:16:06 AM UTC 24 |
28986100 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1211638070 |
|
|
Aug 23 10:14:52 AM UTC 24 |
Aug 23 10:16:06 AM UTC 24 |
4812823100 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.984749510 |
|
|
Aug 23 10:15:45 AM UTC 24 |
Aug 23 10:16:07 AM UTC 24 |
44109200 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.898215459 |
|
|
Aug 23 10:15:49 AM UTC 24 |
Aug 23 10:16:08 AM UTC 24 |
13388900 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2693540257 |
|
|
Aug 23 10:15:47 AM UTC 24 |
Aug 23 10:16:08 AM UTC 24 |
58722900 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.653861993 |
|
|
Aug 23 10:15:50 AM UTC 24 |
Aug 23 10:16:10 AM UTC 24 |
19874700 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3231346461 |
|
|
Aug 23 10:15:53 AM UTC 24 |
Aug 23 10:16:11 AM UTC 24 |
152559000 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3795927901 |
|
|
Aug 23 10:15:56 AM UTC 24 |
Aug 23 10:16:12 AM UTC 24 |
13237500 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4284579021 |
|
|
Aug 23 10:15:53 AM UTC 24 |
Aug 23 10:16:12 AM UTC 24 |
138458900 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4292872667 |
|
|
Aug 23 10:15:51 AM UTC 24 |
Aug 23 10:16:12 AM UTC 24 |
411919800 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3476169646 |
|
|
Aug 23 10:15:54 AM UTC 24 |
Aug 23 10:16:13 AM UTC 24 |
18954800 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.279818913 |
|
|
Aug 23 10:15:57 AM UTC 24 |
Aug 23 10:16:13 AM UTC 24 |
17581900 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1247271079 |
|
|
Aug 23 10:15:58 AM UTC 24 |
Aug 23 10:16:18 AM UTC 24 |
122106000 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3619350085 |
|
|
Aug 23 10:15:58 AM UTC 24 |
Aug 23 10:16:20 AM UTC 24 |
86734400 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2563270536 |
|
|
Aug 23 10:16:00 AM UTC 24 |
Aug 23 10:16:22 AM UTC 24 |
80969100 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3859900312 |
|
|
Aug 23 10:16:06 AM UTC 24 |
Aug 23 10:16:23 AM UTC 24 |
34932500 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3233299361 |
|
|
Aug 23 10:16:07 AM UTC 24 |
Aug 23 10:16:24 AM UTC 24 |
24967400 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3032106728 |
|
|
Aug 23 10:16:06 AM UTC 24 |
Aug 23 10:16:25 AM UTC 24 |
105542700 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3216227308 |
|
|
Aug 23 10:16:08 AM UTC 24 |
Aug 23 10:16:26 AM UTC 24 |
38658100 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3728836902 |
|
|
Aug 23 10:16:04 AM UTC 24 |
Aug 23 10:16:26 AM UTC 24 |
72120400 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1977554860 |
|
|
Aug 23 10:16:08 AM UTC 24 |
Aug 23 10:16:26 AM UTC 24 |
70855400 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2538627683 |
|
|
Aug 23 10:16:13 AM UTC 24 |
Aug 23 10:16:29 AM UTC 24 |
12680200 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1846758580 |
|
|
Aug 23 10:16:13 AM UTC 24 |
Aug 23 10:16:29 AM UTC 24 |
15169400 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2237627242 |
|
|
Aug 23 10:16:13 AM UTC 24 |
Aug 23 10:16:31 AM UTC 24 |
23516400 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3783288380 |
|
|
Aug 23 10:16:11 AM UTC 24 |
Aug 23 10:16:32 AM UTC 24 |
59527000 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2273144754 |
|
|
Aug 23 10:16:14 AM UTC 24 |
Aug 23 10:16:33 AM UTC 24 |
19236800 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.305688028 |
|
|
Aug 23 10:16:14 AM UTC 24 |
Aug 23 10:16:35 AM UTC 24 |
97303500 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.112411347 |
|
|
Aug 23 10:16:19 AM UTC 24 |
Aug 23 10:16:38 AM UTC 24 |
267380200 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1523835564 |
|
|
Aug 23 10:16:23 AM UTC 24 |
Aug 23 10:16:40 AM UTC 24 |
42703300 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4124114682 |
|
|
Aug 23 10:16:21 AM UTC 24 |
Aug 23 10:16:41 AM UTC 24 |
126240000 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3329226059 |
|
|
Aug 23 10:16:26 AM UTC 24 |
Aug 23 10:16:42 AM UTC 24 |
92079200 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4236627108 |
|
|
Aug 23 10:16:24 AM UTC 24 |
Aug 23 10:16:44 AM UTC 24 |
12284500 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1119784847 |
|
|
Aug 23 10:16:27 AM UTC 24 |
Aug 23 10:16:46 AM UTC 24 |
88701100 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2224270264 |
|
|
Aug 23 10:16:26 AM UTC 24 |
Aug 23 10:16:46 AM UTC 24 |
61042800 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.755696956 |
|
|
Aug 23 10:16:32 AM UTC 24 |
Aug 23 10:16:48 AM UTC 24 |
24349100 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.344784902 |
|
|
Aug 23 10:16:08 AM UTC 24 |
Aug 23 10:16:48 AM UTC 24 |
312799000 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3417311805 |
|
|
Aug 23 10:16:27 AM UTC 24 |
Aug 23 10:16:50 AM UTC 24 |
43536700 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2912264027 |
|
|
Aug 23 10:16:29 AM UTC 24 |
Aug 23 10:16:50 AM UTC 24 |
352511400 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1841144161 |
|
|
Aug 23 10:16:32 AM UTC 24 |
Aug 23 10:16:52 AM UTC 24 |
41659800 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1658454163 |
|
|
Aug 23 10:16:34 AM UTC 24 |
Aug 23 10:16:52 AM UTC 24 |
44535400 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.410840208 |
|
|
Aug 23 10:16:36 AM UTC 24 |
Aug 23 10:16:57 AM UTC 24 |
41319500 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2865636512 |
|
|
Aug 23 10:16:39 AM UTC 24 |
Aug 23 10:16:58 AM UTC 24 |
115156500 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2427099480 |
|
|
Aug 23 10:16:42 AM UTC 24 |
Aug 23 10:17:02 AM UTC 24 |
206856100 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.370498080 |
|
|
Aug 23 10:16:41 AM UTC 24 |
Aug 23 10:17:02 AM UTC 24 |
41223300 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2510476798 |
|
|
Aug 23 10:16:47 AM UTC 24 |
Aug 23 10:17:03 AM UTC 24 |
15249200 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2252862254 |
|
|
Aug 23 10:16:45 AM UTC 24 |
Aug 23 10:17:04 AM UTC 24 |
36836400 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1199489846 |
|
|
Aug 23 10:16:47 AM UTC 24 |
Aug 23 10:17:06 AM UTC 24 |
11821000 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3175509179 |
|
|
Aug 23 10:16:49 AM UTC 24 |
Aug 23 10:17:09 AM UTC 24 |
79644300 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3875231397 |
|
|
Aug 23 10:16:50 AM UTC 24 |
Aug 23 10:17:10 AM UTC 24 |
430773100 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3972240781 |
|
|
Aug 23 10:16:53 AM UTC 24 |
Aug 23 10:17:12 AM UTC 24 |
36617100 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.832685771 |
|
|
Aug 23 10:16:51 AM UTC 24 |
Aug 23 10:17:13 AM UTC 24 |
478617200 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1875218147 |
|
|
Aug 23 10:16:59 AM UTC 24 |
Aug 23 10:17:16 AM UTC 24 |
43855400 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2495584651 |
|
|
Aug 23 10:16:57 AM UTC 24 |
Aug 23 10:17:16 AM UTC 24 |
43166100 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2991695175 |
|
|
Aug 23 10:16:49 AM UTC 24 |
Aug 23 10:17:23 AM UTC 24 |
169971500 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.252117632 |
|
|
Aug 23 10:17:03 AM UTC 24 |
Aug 23 10:17:24 AM UTC 24 |
880034900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1893250200 |
|
|
Aug 23 10:17:03 AM UTC 24 |
Aug 23 10:17:25 AM UTC 24 |
108166600 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.588151209 |
|
|
Aug 23 10:17:04 AM UTC 24 |
Aug 23 10:17:26 AM UTC 24 |
137318900 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3786772585 |
|
|
Aug 23 10:17:04 AM UTC 24 |
Aug 23 10:17:26 AM UTC 24 |
111003400 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.471373652 |
|
|
Aug 23 10:17:09 AM UTC 24 |
Aug 23 10:17:29 AM UTC 24 |
27507400 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.4091604962 |
|
|
Aug 23 10:17:13 AM UTC 24 |
Aug 23 10:17:29 AM UTC 24 |
16103200 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1332557626 |
|
|
Aug 23 10:17:11 AM UTC 24 |
Aug 23 10:17:31 AM UTC 24 |
49370200 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2059583016 |
|
|
Aug 23 10:17:14 AM UTC 24 |
Aug 23 10:17:35 AM UTC 24 |
415314300 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2562950339 |
|
|
Aug 23 10:17:17 AM UTC 24 |
Aug 23 10:17:35 AM UTC 24 |
434959900 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1024169803 |
|
|
Aug 23 10:17:18 AM UTC 24 |
Aug 23 10:17:35 AM UTC 24 |
29828100 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3958260772 |
|
|
Aug 23 10:17:27 AM UTC 24 |
Aug 23 10:17:43 AM UTC 24 |
48054300 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1497269343 |
|
|
Aug 23 10:17:26 AM UTC 24 |
Aug 23 10:17:45 AM UTC 24 |
13106800 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.416968173 |
|
|
Aug 23 10:17:24 AM UTC 24 |
Aug 23 10:17:45 AM UTC 24 |
301285000 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3890205770 |
|
|
Aug 23 10:17:29 AM UTC 24 |
Aug 23 10:17:46 AM UTC 24 |
19241600 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1736369597 |
|
|
Aug 23 10:17:27 AM UTC 24 |
Aug 23 10:17:46 AM UTC 24 |
18509300 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.913600276 |
|
|
Aug 23 10:17:30 AM UTC 24 |
Aug 23 10:17:50 AM UTC 24 |
66988300 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.4284745963 |
|
|
Aug 23 10:17:35 AM UTC 24 |
Aug 23 10:17:52 AM UTC 24 |
20760100 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3917228741 |
|
|
Aug 23 10:17:36 AM UTC 24 |
Aug 23 10:17:52 AM UTC 24 |
51965900 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1888396223 |
|
|
Aug 23 10:17:36 AM UTC 24 |
Aug 23 10:17:52 AM UTC 24 |
23959600 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2806665157 |
|
|
Aug 23 10:17:31 AM UTC 24 |
Aug 23 10:17:53 AM UTC 24 |
151048400 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.1007364564 |
|
|
Aug 23 10:17:44 AM UTC 24 |
Aug 23 10:18:01 AM UTC 24 |
17531200 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2742446075 |
|
|
Aug 23 10:17:45 AM UTC 24 |
Aug 23 10:18:02 AM UTC 24 |
14901600 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1383305291 |
|
|
Aug 23 10:17:46 AM UTC 24 |
Aug 23 10:18:02 AM UTC 24 |
26463300 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3230227530 |
|
|
Aug 23 10:17:46 AM UTC 24 |
Aug 23 10:18:03 AM UTC 24 |
17049100 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.976379528 |
|
|
Aug 23 10:17:46 AM UTC 24 |
Aug 23 10:18:03 AM UTC 24 |
52585500 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1470409549 |
|
|
Aug 23 10:17:51 AM UTC 24 |
Aug 23 10:18:08 AM UTC 24 |
28983300 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.3274115055 |
|
|
Aug 23 10:17:53 AM UTC 24 |
Aug 23 10:18:09 AM UTC 24 |
72029700 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.10024480 |
|
|
Aug 23 10:17:54 AM UTC 24 |
Aug 23 10:18:10 AM UTC 24 |
18210900 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1036885816 |
|
|
Aug 23 10:17:54 AM UTC 24 |
Aug 23 10:18:10 AM UTC 24 |
14673200 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1840024590 |
|
|
Aug 23 10:17:55 AM UTC 24 |
Aug 23 10:18:11 AM UTC 24 |
24987500 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2644265688 |
|
|
Aug 23 10:18:02 AM UTC 24 |
Aug 23 10:18:18 AM UTC 24 |
186852200 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2556894432 |
|
|
Aug 23 10:18:03 AM UTC 24 |
Aug 23 10:18:19 AM UTC 24 |
27400400 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2474261053 |
|
|
Aug 23 10:18:03 AM UTC 24 |
Aug 23 10:18:19 AM UTC 24 |
16187500 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.629268682 |
|
|
Aug 23 10:18:04 AM UTC 24 |
Aug 23 10:18:20 AM UTC 24 |
52130400 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.1801150540 |
|
|
Aug 23 10:18:04 AM UTC 24 |
Aug 23 10:18:21 AM UTC 24 |
40682600 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3083637280 |
|
|
Aug 23 10:18:09 AM UTC 24 |
Aug 23 10:18:26 AM UTC 24 |
111100900 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.570649918 |
|
|
Aug 23 10:18:10 AM UTC 24 |
Aug 23 10:18:26 AM UTC 24 |
15835300 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1449198155 |
|
|
Aug 23 10:18:11 AM UTC 24 |
Aug 23 10:18:27 AM UTC 24 |
45752300 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1775668715 |
|
|
Aug 23 10:18:11 AM UTC 24 |
Aug 23 10:18:28 AM UTC 24 |
17941400 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.552899353 |
|
|
Aug 23 10:18:12 AM UTC 24 |
Aug 23 10:18:29 AM UTC 24 |
17929500 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.1081148503 |
|
|
Aug 23 10:18:17 AM UTC 24 |
Aug 23 10:18:33 AM UTC 24 |
25999900 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2094652536 |
|
|
Aug 23 10:18:18 AM UTC 24 |
Aug 23 10:18:34 AM UTC 24 |
112592900 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3217989269 |
|
|
Aug 23 10:18:19 AM UTC 24 |
Aug 23 10:18:37 AM UTC 24 |
53674000 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.4105674103 |
|
|
Aug 23 10:18:21 AM UTC 24 |
Aug 23 10:18:37 AM UTC 24 |
27563000 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2287537095 |
|
|
Aug 23 10:18:21 AM UTC 24 |
Aug 23 10:18:37 AM UTC 24 |
57851900 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.59569284 |
|
|
Aug 23 10:18:23 AM UTC 24 |
Aug 23 10:18:39 AM UTC 24 |
17975100 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.728323864 |
|
|
Aug 23 10:18:27 AM UTC 24 |
Aug 23 10:18:43 AM UTC 24 |
26882000 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3570768313 |
|
|
Aug 23 10:14:15 AM UTC 24 |
Aug 23 10:21:37 AM UTC 24 |
741397300 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3843240712 |
|
|
Aug 23 10:14:34 AM UTC 24 |
Aug 23 10:21:56 AM UTC 24 |
388534200 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3686848931 |
|
|
Aug 23 10:14:12 AM UTC 24 |
Aug 23 10:23:01 AM UTC 24 |
956847700 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1169691074 |
|
|
Aug 23 10:14:50 AM UTC 24 |
Aug 23 10:23:41 AM UTC 24 |
228599500 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1142560330 |
|
|
Aug 23 10:15:09 AM UTC 24 |
Aug 23 10:24:02 AM UTC 24 |
346955800 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.983562759 |
|
|
Aug 23 10:16:52 AM UTC 24 |
Aug 23 10:24:16 AM UTC 24 |
694922600 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2740965351 |
|
|
Aug 23 10:15:17 AM UTC 24 |
Aug 23 10:24:24 AM UTC 24 |
661704000 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3234053295 |
|
|
Aug 23 10:15:29 AM UTC 24 |
Aug 23 10:24:24 AM UTC 24 |
282997800 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3585630774 |
|
|
Aug 23 10:15:47 AM UTC 24 |
Aug 23 10:24:42 AM UTC 24 |
943084400 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1851030246 |
|
|
Aug 23 10:15:54 AM UTC 24 |
Aug 23 10:24:49 AM UTC 24 |
1017927900 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2650425494 |
|
|
Aug 23 10:16:04 AM UTC 24 |
Aug 23 10:24:56 AM UTC 24 |
716924100 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2633856716 |
|
|
Aug 23 10:16:23 AM UTC 24 |
Aug 23 10:25:16 AM UTC 24 |
688665800 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4199929771 |
|
|
Aug 23 10:16:29 AM UTC 24 |
Aug 23 10:25:21 AM UTC 24 |
191124900 ps |