| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.26 | 95.71 | 93.88 | 98.31 | 92.52 | 98.23 | 96.99 | 98.18 |
| T1257 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3492464306 | Aug 23 10:16:43 AM UTC 24 | Aug 23 10:25:37 AM UTC 24 | 704695800 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1452230073 | Aug 23 10:17:06 AM UTC 24 | Aug 23 10:26:08 AM UTC 24 | 1431238900 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1784387600 | Aug 23 10:17:25 AM UTC 24 | Aug 23 10:26:19 AM UTC 24 | 1793283500 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3583475138 | Aug 23 10:15:00 AM UTC 24 | Aug 23 10:29:27 AM UTC 24 | 362763200 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1096731733 | Aug 23 10:15:37 AM UTC 24 | Aug 23 10:29:58 AM UTC 24 | 486063100 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3455280245 | Aug 23 10:14:08 AM UTC 24 | Aug 23 10:31:43 AM UTC 24 | 469300000 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1806486178 | Aug 23 10:16:12 AM UTC 24 | Aug 23 10:33:47 AM UTC 24 | 5366599100 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1612559986 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 136690500 ps |
| CPU time | 167.71 seconds |
| Started | Aug 23 10:18:37 AM UTC 24 |
| Finished | Aug 23 10:21:27 AM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612559986 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1612559986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3528660536 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 82920112300 ps |
| CPU time | 241.81 seconds |
| Started | Aug 23 10:19:31 AM UTC 24 |
| Finished | Aug 23 10:23:36 AM UTC 24 |
| Peak memory | 283416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3528660536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3528660536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3926675611 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 317780700 ps |
| CPU time | 20.74 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:14:36 AM UTC 24 |
| Peak memory | 284544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3926675611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3926675611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.1605897277 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 42485200 ps |
| CPU time | 144.84 seconds |
| Started | Aug 23 10:18:58 AM UTC 24 |
| Finished | Aug 23 10:21:25 AM UTC 24 |
| Peak memory | 271424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605897277 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.1605897277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3021526 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4376120200 ps |
| CPU time | 57.15 seconds |
| Started | Aug 23 10:24:15 AM UTC 24 |
| Finished | Aug 23 10:25:14 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021526 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.3021526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2254039376 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 593370000 ps |
| CPU time | 94.23 seconds |
| Started | Aug 23 10:22:36 AM UTC 24 |
| Finished | Aug 23 10:24:12 AM UTC 24 |
| Peak memory | 306084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2254039376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_ro_serr.2254039376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1974628987 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1710794900 ps |
| CPU time | 48.66 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:15:02 AM UTC 24 |
| Peak memory | 272388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974628987 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.1974628987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.357124265 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2743530800 ps |
| CPU time | 5312.5 seconds |
| Started | Aug 23 10:32:20 AM UTC 24 |
| Finished | Aug 23 12:01:42 PM UTC 24 |
| Peak memory | 316468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357124265 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.357124265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.13610981 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 125143478700 ps |
| CPU time | 1564.51 seconds |
| Started | Aug 23 10:18:40 AM UTC 24 |
| Finished | Aug 23 10:45:00 AM UTC 24 |
| Peak memory | 277776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13610981 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.13610981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.473225181 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 44484100 ps |
| CPU time | 15.82 seconds |
| Started | Aug 23 10:25:17 AM UTC 24 |
| Finished | Aug 23 10:25:34 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473225181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_wr_intg.473225181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.1134585009 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8876131400 ps |
| CPU time | 427.71 seconds |
| Started | Aug 23 10:18:38 AM UTC 24 |
| Finished | Aug 23 10:25:51 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134585009 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.1134585009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.2205373744 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2901357000 ps |
| CPU time | 153.38 seconds |
| Started | Aug 23 10:23:43 AM UTC 24 |
| Finished | Aug 23 10:26:18 AM UTC 24 |
| Peak memory | 291744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2205373744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rw_derr.2205373744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1752541163 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 855097000 ps |
| CPU time | 66.74 seconds |
| Started | Aug 23 10:21:26 AM UTC 24 |
| Finished | Aug 23 10:22:35 AM UTC 24 |
| Peak memory | 270884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752541163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1752541163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1329195475 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2241141500 ps |
| CPU time | 60.3 seconds |
| Started | Aug 23 10:14:30 AM UTC 24 |
| Finished | Aug 23 10:15:32 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329195475 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.1329195475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3746254650 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 378538100 ps |
| CPU time | 145.23 seconds |
| Started | Aug 23 10:34:28 AM UTC 24 |
| Finished | Aug 23 10:36:55 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746254650 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.3746254650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3350352011 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 43108200 ps |
| CPU time | 14.57 seconds |
| Started | Aug 23 10:57:32 AM UTC 24 |
| Finished | Aug 23 10:57:48 AM UTC 24 |
| Peak memory | 273504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3350352011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3350352011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1508337175 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 74362700 ps |
| CPU time | 150.54 seconds |
| Started | Aug 23 10:59:12 AM UTC 24 |
| Finished | Aug 23 11:01:45 AM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508337175 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1508337175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1832930507 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 6014642700 ps |
| CPU time | 88.33 seconds |
| Started | Aug 23 10:26:14 AM UTC 24 |
| Finished | Aug 23 10:27:44 AM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832930507 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.1832930507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2154292524 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 43276300 ps |
| CPU time | 15.62 seconds |
| Started | Aug 23 10:14:13 AM UTC 24 |
| Finished | Aug 23 10:14:30 AM UTC 24 |
| Peak memory | 272332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154292524 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2154292524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.1880680649 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 69061200 ps |
| CPU time | 146.01 seconds |
| Started | Aug 23 11:29:44 AM UTC 24 |
| Finished | Aug 23 11:32:12 AM UTC 24 |
| Peak memory | 275236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880680649 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.1880680649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1169691074 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 228599500 ps |
| CPU time | 525.68 seconds |
| Started | Aug 23 10:14:50 AM UTC 24 |
| Finished | Aug 23 10:23:41 AM UTC 24 |
| Peak memory | 276404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169691074 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.1169691074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2239662731 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 77962200 ps |
| CPU time | 21.41 seconds |
| Started | Aug 23 10:14:32 AM UTC 24 |
| Finished | Aug 23 10:14:55 AM UTC 24 |
| Peak memory | 290624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2239662731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2239662731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3191564678 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 10035192700 ps |
| CPU time | 96.35 seconds |
| Started | Aug 23 10:25:51 AM UTC 24 |
| Finished | Aug 23 10:27:30 AM UTC 24 |
| Peak memory | 283396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3191564678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3191564678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4267884201 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3652135000 ps |
| CPU time | 63.77 seconds |
| Started | Aug 23 10:24:58 AM UTC 24 |
| Finished | Aug 23 10:26:03 AM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267884201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4267884201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.212408297 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 39232100 ps |
| CPU time | 14.38 seconds |
| Started | Aug 23 10:57:48 AM UTC 24 |
| Finished | Aug 23 10:58:04 AM UTC 24 |
| Peak memory | 275512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=212408297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_lcmgr_intg.212408297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.4067499614 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 986407500 ps |
| CPU time | 23.81 seconds |
| Started | Aug 23 10:20:00 AM UTC 24 |
| Finished | Aug 23 10:20:25 AM UTC 24 |
| Peak memory | 273352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 67499614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc h_code.4067499614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.610524545 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12188478800 ps |
| CPU time | 219.83 seconds |
| Started | Aug 23 10:30:44 AM UTC 24 |
| Finished | Aug 23 10:34:27 AM UTC 24 |
| Peak memory | 293660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=610524545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_rd_slow_flash.610524545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3917946053 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 469806300 ps |
| CPU time | 21.02 seconds |
| Started | Aug 23 10:14:32 AM UTC 24 |
| Finished | Aug 23 10:14:55 AM UTC 24 |
| Peak memory | 274252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917946053 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3917946053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.1715955169 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 59965600 ps |
| CPU time | 14.6 seconds |
| Started | Aug 23 10:25:51 AM UTC 24 |
| Finished | Aug 23 10:26:07 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715955169 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1715955169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3497927998 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 160782565000 ps |
| CPU time | 885.54 seconds |
| Started | Aug 23 10:25:37 AM UTC 24 |
| Finished | Aug 23 10:40:32 AM UTC 24 |
| Peak memory | 275836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3497927998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. flash_ctrl_rma_err.3497927998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1949165490 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 209035500 ps |
| CPU time | 14.17 seconds |
| Started | Aug 23 11:44:10 AM UTC 24 |
| Finished | Aug 23 11:44:26 AM UTC 24 |
| Peak memory | 275228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1949165490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1949165490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.949156795 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 537427402700 ps |
| CPU time | 2019.86 seconds |
| Started | Aug 23 10:19:02 AM UTC 24 |
| Finished | Aug 23 10:53:02 AM UTC 24 |
| Peak memory | 277984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949156795 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.949156795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2654849227 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 19948200 ps |
| CPU time | 14.58 seconds |
| Started | Aug 23 11:43:16 AM UTC 24 |
| Finished | Aug 23 11:43:31 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654849227 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.2654849227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1008857270 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4714434200 ps |
| CPU time | 69.05 seconds |
| Started | Aug 23 11:01:45 AM UTC 24 |
| Finished | Aug 23 11:02:56 AM UTC 24 |
| Peak memory | 270888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008857270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1008857270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.4017585377 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1904542800 ps |
| CPU time | 137.53 seconds |
| Started | Aug 23 10:23:58 AM UTC 24 |
| Finished | Aug 23 10:26:18 AM UTC 24 |
| Peak memory | 292068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4017585377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.4017585377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.4247874890 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 129180900 ps |
| CPU time | 33.16 seconds |
| Started | Aug 23 10:24:42 AM UTC 24 |
| Finished | Aug 23 10:25:17 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247874890 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.4247874890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2895480604 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 725407000 ps |
| CPU time | 18.41 seconds |
| Started | Aug 23 10:33:14 AM UTC 24 |
| Finished | Aug 23 10:33:34 AM UTC 24 |
| Peak memory | 275768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2895480604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2895480604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.972727606 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 32052700 ps |
| CPU time | 15.54 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:29 AM UTC 24 |
| Peak memory | 274200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972727606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.972727606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.1161127358 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1572957600 ps |
| CPU time | 192.89 seconds |
| Started | Aug 23 10:24:13 AM UTC 24 |
| Finished | Aug 23 10:27:29 AM UTC 24 |
| Peak memory | 293992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161127358 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.1161127358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3349911098 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15206008500 ps |
| CPU time | 391.42 seconds |
| Started | Aug 23 10:26:36 AM UTC 24 |
| Finished | Aug 23 10:33:13 AM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3349911098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3349911098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.980891757 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3940245800 ps |
| CPU time | 78.72 seconds |
| Started | Aug 23 10:21:04 AM UTC 24 |
| Finished | Aug 23 10:22:25 AM UTC 24 |
| Peak memory | 270972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980891757 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.980891757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.1160675972 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 7871814600 ps |
| CPU time | 375.27 seconds |
| Started | Aug 23 10:28:25 AM UTC 24 |
| Finished | Aug 23 10:34:45 AM UTC 24 |
| Peak memory | 324520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160675972 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.1160675972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4060371107 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 68451100 ps |
| CPU time | 15.23 seconds |
| Started | Aug 23 10:14:51 AM UTC 24 |
| Finished | Aug 23 10:15:07 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060371107 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.4060371107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1096929081 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 10015451500 ps |
| CPU time | 92.15 seconds |
| Started | Aug 23 10:33:34 AM UTC 24 |
| Finished | Aug 23 10:35:08 AM UTC 24 |
| Peak memory | 350992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1096929081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1096929081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1933522914 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 876876800 ps |
| CPU time | 39.84 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:53 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933522914 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1933522914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3108941508 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 207445000 ps |
| CPU time | 34.83 seconds |
| Started | Aug 23 11:23:07 AM UTC 24 |
| Finished | Aug 23 11:23:43 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108941508 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.3108941508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1096731733 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 486063100 ps |
| CPU time | 852.25 seconds |
| Started | Aug 23 10:15:37 AM UTC 24 |
| Finished | Aug 23 10:29:58 AM UTC 24 |
| Peak memory | 274360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096731733 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.1096731733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1851030246 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1017927900 ps |
| CPU time | 529.72 seconds |
| Started | Aug 23 10:15:54 AM UTC 24 |
| Finished | Aug 23 10:24:49 AM UTC 24 |
| Peak memory | 274164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851030246 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.1851030246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.3577654284 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4857602100 ps |
| CPU time | 458.97 seconds |
| Started | Aug 23 11:15:36 AM UTC 24 |
| Finished | Aug 23 11:23:20 AM UTC 24 |
| Peak memory | 330944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577654284 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.3577654284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.4143545371 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 45084200 ps |
| CPU time | 14.67 seconds |
| Started | Aug 23 10:25:34 AM UTC 24 |
| Finished | Aug 23 10:25:50 AM UTC 24 |
| Peak memory | 273540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143545371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4143545371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.4238363505 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2212518000 ps |
| CPU time | 98.53 seconds |
| Started | Aug 23 11:32:04 AM UTC 24 |
| Finished | Aug 23 11:33:45 AM UTC 24 |
| Peak memory | 306080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238363505 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.4238363505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1573042214 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 311163200 ps |
| CPU time | 32.58 seconds |
| Started | Aug 23 10:25:22 AM UTC 24 |
| Finished | Aug 23 10:25:56 AM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573042 214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f s_sup.1573042214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.721323699 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 73095400 ps |
| CPU time | 31.46 seconds |
| Started | Aug 23 10:32:42 AM UTC 24 |
| Finished | Aug 23 10:33:15 AM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721323699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.721323699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4124114682 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 126240000 ps |
| CPU time | 18.53 seconds |
| Started | Aug 23 10:16:21 AM UTC 24 |
| Finished | Aug 23 10:16:41 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124114682 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.4124114682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2081937023 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 45392700 ps |
| CPU time | 23.26 seconds |
| Started | Aug 23 12:06:25 PM UTC 24 |
| Finished | Aug 23 12:06:50 PM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2081937023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ ctrl_disable.2081937023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3342997876 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2595052200 ps |
| CPU time | 139.82 seconds |
| Started | Aug 23 11:34:58 AM UTC 24 |
| Finished | Aug 23 11:37:20 AM UTC 24 |
| Peak memory | 273236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342997876 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.3342997876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3431574599 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 149550300 ps |
| CPU time | 31 seconds |
| Started | Aug 23 10:32:02 AM UTC 24 |
| Finished | Aug 23 10:32:34 AM UTC 24 |
| Peak memory | 287804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3431574599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.3431574599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2851924403 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 103138300 ps |
| CPU time | 14.55 seconds |
| Started | Aug 23 11:23:21 AM UTC 24 |
| Finished | Aug 23 11:23:38 AM UTC 24 |
| Peak memory | 275480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2851924403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.2851924403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.168500779 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2065753500 ps |
| CPU time | 57.89 seconds |
| Started | Aug 23 11:38:04 AM UTC 24 |
| Finished | Aug 23 11:39:04 AM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168500779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.168500779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2518445606 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1776189700 ps |
| CPU time | 171.81 seconds |
| Started | Aug 23 10:40:33 AM UTC 24 |
| Finished | Aug 23 10:43:27 AM UTC 24 |
| Peak memory | 291752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2518445606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.2518445606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3318614938 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 27353900 ps |
| CPU time | 17.31 seconds |
| Started | Aug 23 10:25:15 AM UTC 24 |
| Finished | Aug 23 10:25:33 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318614938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3318614938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.1759847255 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3775927100 ps |
| CPU time | 1911.2 seconds |
| Started | Aug 23 10:35:58 AM UTC 24 |
| Finished | Aug 23 11:08:08 AM UTC 24 |
| Peak memory | 275936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 59847255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _error_prog_type.1759847255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1287486244 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1984180700 ps |
| CPU time | 818.94 seconds |
| Started | Aug 23 10:20:39 AM UTC 24 |
| Finished | Aug 23 10:34:26 AM UTC 24 |
| Peak memory | 276256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287486244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1287486244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2838814497 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 110733000 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 10:33:16 AM UTC 24 |
| Finished | Aug 23 10:33:32 AM UTC 24 |
| Peak memory | 273504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2838814497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2838814497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.557540390 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 106244700 ps |
| CPU time | 20.33 seconds |
| Started | Aug 23 10:15:09 AM UTC 24 |
| Finished | Aug 23 10:15:31 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557540390 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.557540390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.817066798 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 22326800 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 10:25:18 AM UTC 24 |
| Finished | Aug 23 10:25:33 AM UTC 24 |
| Peak memory | 273304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=817066798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.817066798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3576080104 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 24464600 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 10:25:50 AM UTC 24 |
| Finished | Aug 23 10:26:06 AM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3576080104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3576080104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3439657031 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10019211400 ps |
| CPU time | 78.75 seconds |
| Started | Aug 23 11:47:44 AM UTC 24 |
| Finished | Aug 23 11:49:04 AM UTC 24 |
| Peak memory | 300292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3439657031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3439657031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2240609280 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 38402700 ps |
| CPU time | 23.28 seconds |
| Started | Aug 23 10:24:50 AM UTC 24 |
| Finished | Aug 23 10:25:15 AM UTC 24 |
| Peak memory | 285476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2240609280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_disable.2240609280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2294561024 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 975160500 ps |
| CPU time | 74.34 seconds |
| Started | Aug 23 10:27:31 AM UTC 24 |
| Finished | Aug 23 10:28:47 AM UTC 24 |
| Peak memory | 275068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294561024 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2294561024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.4243377651 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5742257600 ps |
| CPU time | 63.88 seconds |
| Started | Aug 23 11:44:02 AM UTC 24 |
| Finished | Aug 23 11:45:08 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243377651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.4243377651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.4248871306 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1518376600 ps |
| CPU time | 65.08 seconds |
| Started | Aug 23 11:56:26 AM UTC 24 |
| Finished | Aug 23 11:57:33 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248871306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4248871306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.534048183 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 24935445500 ps |
| CPU time | 227.09 seconds |
| Started | Aug 23 10:41:56 AM UTC 24 |
| Finished | Aug 23 10:45:47 AM UTC 24 |
| Peak memory | 301852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=534048183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_rd_slow_flash.534048183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1739228808 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 6172343800 ps |
| CPU time | 64.9 seconds |
| Started | Aug 23 12:10:15 PM UTC 24 |
| Finished | Aug 23 12:11:22 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739228808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1739228808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1099058125 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 915685100 ps |
| CPU time | 24.65 seconds |
| Started | Aug 23 10:25:32 AM UTC 24 |
| Finished | Aug 23 10:25:58 AM UTC 24 |
| Peak memory | 275800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1099058125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1099058125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.433336542 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 23622100 ps |
| CPU time | 14.88 seconds |
| Started | Aug 23 10:33:16 AM UTC 24 |
| Finished | Aug 23 10:33:32 AM UTC 24 |
| Peak memory | 283212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433336542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.433336542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2926315417 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 86761100 ps |
| CPU time | 35.41 seconds |
| Started | Aug 23 11:37:42 AM UTC 24 |
| Finished | Aug 23 11:38:19 AM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926315417 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.2926315417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2136114441 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 183249700 ps |
| CPU time | 15.72 seconds |
| Started | Aug 23 10:32:56 AM UTC 24 |
| Finished | Aug 23 10:33:13 AM UTC 24 |
| Peak memory | 271432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136114441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.2136114441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3455280245 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 469300000 ps |
| CPU time | 1043.63 seconds |
| Started | Aug 23 10:14:08 AM UTC 24 |
| Finished | Aug 23 10:31:43 AM UTC 24 |
| Peak memory | 276348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455280245 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.3455280245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1806486178 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5366599100 ps |
| CPU time | 1044.14 seconds |
| Started | Aug 23 10:16:12 AM UTC 24 |
| Finished | Aug 23 10:33:47 AM UTC 24 |
| Peak memory | 286876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806486178 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.1806486178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4199929771 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 191124900 ps |
| CPU time | 525.66 seconds |
| Started | Aug 23 10:16:29 AM UTC 24 |
| Finished | Aug 23 10:25:21 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199929771 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.4199929771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.983562759 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 694922600 ps |
| CPU time | 438.66 seconds |
| Started | Aug 23 10:16:52 AM UTC 24 |
| Finished | Aug 23 10:24:16 AM UTC 24 |
| Peak memory | 274260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983562759 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.983562759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1452230073 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1431238900 ps |
| CPU time | 535.55 seconds |
| Started | Aug 23 10:17:06 AM UTC 24 |
| Finished | Aug 23 10:26:08 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452230073 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.1452230073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3843240712 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 388534200 ps |
| CPU time | 436.12 seconds |
| Started | Aug 23 10:14:34 AM UTC 24 |
| Finished | Aug 23 10:21:56 AM UTC 24 |
| Peak memory | 274348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843240712 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.3843240712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2410363030 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 45599000 ps |
| CPU time | 14.68 seconds |
| Started | Aug 23 10:25:35 AM UTC 24 |
| Finished | Aug 23 10:25:51 AM UTC 24 |
| Peak memory | 273104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410363030 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.2410363030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4056144983 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 158302451900 ps |
| CPU time | 2001.87 seconds |
| Started | Aug 23 10:20:26 AM UTC 24 |
| Finished | Aug 23 10:54:07 AM UTC 24 |
| Peak memory | 288064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056144983 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.4056144983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2978302884 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 39038600 ps |
| CPU time | 23.4 seconds |
| Started | Aug 23 10:32:14 AM UTC 24 |
| Finished | Aug 23 10:32:38 AM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2978302884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_disable.2978302884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.580394285 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 15153700 ps |
| CPU time | 23.63 seconds |
| Started | Aug 23 11:37:56 AM UTC 24 |
| Finished | Aug 23 11:38:21 AM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=580394285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_disable.580394285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3165406721 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 26577000 ps |
| CPU time | 14.33 seconds |
| Started | Aug 23 11:40:42 AM UTC 24 |
| Finished | Aug 23 11:40:58 AM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3165406721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3165406721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2833678395 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 60014100 ps |
| CPU time | 22.42 seconds |
| Started | Aug 23 11:43:43 AM UTC 24 |
| Finished | Aug 23 11:44:07 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2833678395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.2833678395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3851233583 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1670754600 ps |
| CPU time | 57.67 seconds |
| Started | Aug 23 11:45:29 AM UTC 24 |
| Finished | Aug 23 11:46:28 AM UTC 24 |
| Peak memory | 275064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851233583 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3851233583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3790342604 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 140165300 ps |
| CPU time | 32.95 seconds |
| Started | Aug 23 11:46:29 AM UTC 24 |
| Finished | Aug 23 11:47:04 AM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790342604 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3790342604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.3180636434 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 42733600 ps |
| CPU time | 23.5 seconds |
| Started | Aug 23 11:51:47 AM UTC 24 |
| Finished | Aug 23 11:52:12 AM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3180636434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ ctrl_disable.3180636434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.1221864102 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 70154800 ps |
| CPU time | 23.62 seconds |
| Started | Aug 23 12:01:42 PM UTC 24 |
| Finished | Aug 23 12:02:11 PM UTC 24 |
| Peak memory | 285484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1221864102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.1221864102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1595240131 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 21469200 ps |
| CPU time | 23.47 seconds |
| Started | Aug 23 12:05:44 PM UTC 24 |
| Finished | Aug 23 12:06:13 PM UTC 24 |
| Peak memory | 285612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1595240131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ ctrl_disable.1595240131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.3617213874 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 20490973500 ps |
| CPU time | 80.1 seconds |
| Started | Aug 23 12:05:45 PM UTC 24 |
| Finished | Aug 23 12:07:11 PM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617213874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3617213874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.1742259949 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2891939900 ps |
| CPU time | 57.8 seconds |
| Started | Aug 23 12:14:37 PM UTC 24 |
| Finished | Aug 23 12:15:37 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742259949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1742259949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1579999482 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 141144900 ps |
| CPU time | 149.71 seconds |
| Started | Aug 23 12:16:11 PM UTC 24 |
| Finished | Aug 23 12:18:44 PM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579999482 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1579999482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.856256532 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 342558900 ps |
| CPU time | 17.4 seconds |
| Started | Aug 23 10:14:08 AM UTC 24 |
| Finished | Aug 23 10:14:27 AM UTC 24 |
| Peak memory | 274180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856256532 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.856256532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.795520771 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 40123178100 ps |
| CPU time | 658.06 seconds |
| Started | Aug 23 10:18:43 AM UTC 24 |
| Finished | Aug 23 10:29:48 AM UTC 24 |
| Peak memory | 276084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795520771 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.795520771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.969180412 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 148156000 ps |
| CPU time | 107.9 seconds |
| Started | Aug 23 10:45:47 AM UTC 24 |
| Finished | Aug 23 10:47:37 AM UTC 24 |
| Peak memory | 273088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969180412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.969180412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3025249201 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 703705500 ps |
| CPU time | 105.09 seconds |
| Started | Aug 23 11:21:13 AM UTC 24 |
| Finished | Aug 23 11:23:00 AM UTC 24 |
| Peak memory | 291756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025249201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3025249201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.228291329 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 233816500 ps |
| CPU time | 33.07 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:46 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 228291329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_s ame_csr_outstanding.228291329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.3926482766 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3160762500 ps |
| CPU time | 340.34 seconds |
| Started | Aug 23 11:46:02 AM UTC 24 |
| Finished | Aug 23 11:51:46 AM UTC 24 |
| Peak memory | 320472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926482766 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.3926482766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2902080723 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 83681700 ps |
| CPU time | 19.34 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:33 AM UTC 24 |
| Peak memory | 274376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902080723 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2902080723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3585630774 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 943084400 ps |
| CPU time | 529.32 seconds |
| Started | Aug 23 10:15:47 AM UTC 24 |
| Finished | Aug 23 10:24:42 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585630774 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.3585630774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3610630375 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 7434116700 ps |
| CPU time | 2482.32 seconds |
| Started | Aug 23 10:20:47 AM UTC 24 |
| Finished | Aug 23 11:02:32 AM UTC 24 |
| Peak memory | 275872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610630375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3610630375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.49674309 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7660527100 ps |
| CPU time | 5424.04 seconds |
| Started | Aug 23 10:24:57 AM UTC 24 |
| Finished | Aug 23 11:56:11 AM UTC 24 |
| Peak memory | 314436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49674309 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.49674309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.1772924983 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 40479271500 ps |
| CPU time | 256.76 seconds |
| Started | Aug 23 11:35:47 AM UTC 24 |
| Finished | Aug 23 11:40:07 AM UTC 24 |
| Peak memory | 283404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1772924983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.1772924983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2130712332 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 677881500 ps |
| CPU time | 17.6 seconds |
| Started | Aug 23 10:44:29 AM UTC 24 |
| Finished | Aug 23 10:44:48 AM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2130712332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2130712332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.234800653 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 585718800 ps |
| CPU time | 24.67 seconds |
| Started | Aug 23 10:47:51 AM UTC 24 |
| Finished | Aug 23 10:48:17 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 4800653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch _code.234800653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2856331086 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 209962100 ps |
| CPU time | 35.91 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:49 AM UTC 24 |
| Peak memory | 272380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856331086 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.2856331086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.992865004 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 105295300 ps |
| CPU time | 19.54 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:33 AM UTC 24 |
| Peak memory | 274304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=992865004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.992865004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2833910008 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28263000 ps |
| CPU time | 15.84 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:14:29 AM UTC 24 |
| Peak memory | 274436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833910008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.2833910008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3616131436 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 15053400 ps |
| CPU time | 15.61 seconds |
| Started | Aug 23 10:14:10 AM UTC 24 |
| Finished | Aug 23 10:14:26 AM UTC 24 |
| Peak memory | 272132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616131436 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3616131436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3768774381 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 17473700 ps |
| CPU time | 15.33 seconds |
| Started | Aug 23 10:14:10 AM UTC 24 |
| Finished | Aug 23 10:14:26 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768774381 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.3768774381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.635460381 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 23734200 ps |
| CPU time | 18.24 seconds |
| Started | Aug 23 10:14:10 AM UTC 24 |
| Finished | Aug 23 10:14:29 AM UTC 24 |
| Peak memory | 261892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635 460381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shad ow_reg_errors.635460381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3707413181 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 40892600 ps |
| CPU time | 14.8 seconds |
| Started | Aug 23 10:14:10 AM UTC 24 |
| Finished | Aug 23 10:14:25 AM UTC 24 |
| Peak memory | 261960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3707413181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3707413181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3643482461 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 859407700 ps |
| CPU time | 46.23 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:15:01 AM UTC 24 |
| Peak memory | 272392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643482461 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.3643482461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3583630606 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 345631800 ps |
| CPU time | 35.35 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:14:50 AM UTC 24 |
| Peak memory | 272260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583630606 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.3583630606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.652252562 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 42556900 ps |
| CPU time | 52.64 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:15:08 AM UTC 24 |
| Peak memory | 272388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652252562 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.652252562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.582129870 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 31981700 ps |
| CPU time | 18.64 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:14:33 AM UTC 24 |
| Peak memory | 274504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582129870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.582129870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3800306320 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 18362600 ps |
| CPU time | 15.74 seconds |
| Started | Aug 23 10:14:13 AM UTC 24 |
| Finished | Aug 23 10:14:30 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800306320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.3800306320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2779433414 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 45182000 ps |
| CPU time | 15.35 seconds |
| Started | Aug 23 10:14:13 AM UTC 24 |
| Finished | Aug 23 10:14:30 AM UTC 24 |
| Peak memory | 272264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779433414 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2779433414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3021202074 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 360949500 ps |
| CPU time | 17.43 seconds |
| Started | Aug 23 10:14:14 AM UTC 24 |
| Finished | Aug 23 10:14:32 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3021202074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ same_csr_outstanding.3021202074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1940713397 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 21217100 ps |
| CPU time | 19.35 seconds |
| Started | Aug 23 10:14:13 AM UTC 24 |
| Finished | Aug 23 10:14:34 AM UTC 24 |
| Peak memory | 261900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194 0713397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha dow_reg_errors.1940713397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.811011565 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 23959300 ps |
| CPU time | 15.22 seconds |
| Started | Aug 23 10:14:13 AM UTC 24 |
| Finished | Aug 23 10:14:30 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=811011565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_shadow_reg_errors_with_csr_rw.811011565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3686848931 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 956847700 ps |
| CPU time | 522.61 seconds |
| Started | Aug 23 10:14:12 AM UTC 24 |
| Finished | Aug 23 10:23:01 AM UTC 24 |
| Peak memory | 276412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686848931 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.3686848931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3231346461 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 152559000 ps |
| CPU time | 16.94 seconds |
| Started | Aug 23 10:15:53 AM UTC 24 |
| Finished | Aug 23 10:16:11 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3231346461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3231346461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.653861993 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 19874700 ps |
| CPU time | 18.76 seconds |
| Started | Aug 23 10:15:50 AM UTC 24 |
| Finished | Aug 23 10:16:10 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653861993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.653861993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3617054220 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 28986100 ps |
| CPU time | 15.15 seconds |
| Started | Aug 23 10:15:50 AM UTC 24 |
| Finished | Aug 23 10:16:06 AM UTC 24 |
| Peak memory | 272200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617054220 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.3617054220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4292872667 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 411919800 ps |
| CPU time | 20.43 seconds |
| Started | Aug 23 10:15:51 AM UTC 24 |
| Finished | Aug 23 10:16:12 AM UTC 24 |
| Peak memory | 272448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4292872667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _same_csr_outstanding.4292872667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2000935935 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 24486500 ps |
| CPU time | 15.02 seconds |
| Started | Aug 23 10:15:48 AM UTC 24 |
| Finished | Aug 23 10:16:04 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200 0935935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.2000935935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.898215459 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 13388900 ps |
| CPU time | 17.9 seconds |
| Started | Aug 23 10:15:49 AM UTC 24 |
| Finished | Aug 23 10:16:08 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=898215459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_shadow_reg_errors_with_csr_rw.898215459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2693540257 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 58722900 ps |
| CPU time | 20.17 seconds |
| Started | Aug 23 10:15:47 AM UTC 24 |
| Finished | Aug 23 10:16:08 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693540257 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.2693540257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2563270536 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 80969100 ps |
| CPU time | 20.45 seconds |
| Started | Aug 23 10:16:00 AM UTC 24 |
| Finished | Aug 23 10:16:22 AM UTC 24 |
| Peak memory | 288832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2563270536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2563270536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1247271079 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 122106000 ps |
| CPU time | 18.81 seconds |
| Started | Aug 23 10:15:58 AM UTC 24 |
| Finished | Aug 23 10:16:18 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247271079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.1247271079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.279818913 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 17581900 ps |
| CPU time | 15.06 seconds |
| Started | Aug 23 10:15:57 AM UTC 24 |
| Finished | Aug 23 10:16:13 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279818913 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.279818913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3619350085 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 86734400 ps |
| CPU time | 20.56 seconds |
| Started | Aug 23 10:15:58 AM UTC 24 |
| Finished | Aug 23 10:16:20 AM UTC 24 |
| Peak memory | 272256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3619350085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.3619350085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3476169646 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 18954800 ps |
| CPU time | 17.96 seconds |
| Started | Aug 23 10:15:54 AM UTC 24 |
| Finished | Aug 23 10:16:13 AM UTC 24 |
| Peak memory | 261692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347 6169646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh adow_reg_errors.3476169646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3795927901 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 13237500 ps |
| CPU time | 14.96 seconds |
| Started | Aug 23 10:15:56 AM UTC 24 |
| Finished | Aug 23 10:16:12 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3795927901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f lash_ctrl_shadow_reg_errors_with_csr_rw.3795927901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4284579021 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 138458900 ps |
| CPU time | 18.23 seconds |
| Started | Aug 23 10:15:53 AM UTC 24 |
| Finished | Aug 23 10:16:12 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284579021 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.4284579021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1977554860 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 70855400 ps |
| CPU time | 16.35 seconds |
| Started | Aug 23 10:16:08 AM UTC 24 |
| Finished | Aug 23 10:16:26 AM UTC 24 |
| Peak memory | 284736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1977554860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1977554860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3216227308 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 38658100 ps |
| CPU time | 15.73 seconds |
| Started | Aug 23 10:16:08 AM UTC 24 |
| Finished | Aug 23 10:16:26 AM UTC 24 |
| Peak memory | 274432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216227308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.3216227308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3233299361 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 24967400 ps |
| CPU time | 15.19 seconds |
| Started | Aug 23 10:16:07 AM UTC 24 |
| Finished | Aug 23 10:16:24 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233299361 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.3233299361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.344784902 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 312799000 ps |
| CPU time | 38.37 seconds |
| Started | Aug 23 10:16:08 AM UTC 24 |
| Finished | Aug 23 10:16:48 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 344784902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ same_csr_outstanding.344784902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3032106728 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 105542700 ps |
| CPU time | 18.03 seconds |
| Started | Aug 23 10:16:06 AM UTC 24 |
| Finished | Aug 23 10:16:25 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303 2106728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh adow_reg_errors.3032106728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3859900312 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 34932500 ps |
| CPU time | 15.22 seconds |
| Started | Aug 23 10:16:06 AM UTC 24 |
| Finished | Aug 23 10:16:23 AM UTC 24 |
| Peak memory | 261948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3859900312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.3859900312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3728836902 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 72120400 ps |
| CPU time | 20.74 seconds |
| Started | Aug 23 10:16:04 AM UTC 24 |
| Finished | Aug 23 10:16:26 AM UTC 24 |
| Peak memory | 274076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728836902 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.3728836902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2650425494 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 716924100 ps |
| CPU time | 526.27 seconds |
| Started | Aug 23 10:16:04 AM UTC 24 |
| Finished | Aug 23 10:24:56 AM UTC 24 |
| Peak memory | 274080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650425494 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.2650425494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.112411347 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 267380200 ps |
| CPU time | 18 seconds |
| Started | Aug 23 10:16:19 AM UTC 24 |
| Finished | Aug 23 10:16:38 AM UTC 24 |
| Peak memory | 284484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=112411347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.112411347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2273144754 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 19236800 ps |
| CPU time | 18.56 seconds |
| Started | Aug 23 10:16:14 AM UTC 24 |
| Finished | Aug 23 10:16:33 AM UTC 24 |
| Peak memory | 272388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273144754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.2273144754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1846758580 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 15169400 ps |
| CPU time | 15.12 seconds |
| Started | Aug 23 10:16:13 AM UTC 24 |
| Finished | Aug 23 10:16:29 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846758580 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1846758580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.305688028 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 97303500 ps |
| CPU time | 20.43 seconds |
| Started | Aug 23 10:16:14 AM UTC 24 |
| Finished | Aug 23 10:16:35 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 305688028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ same_csr_outstanding.305688028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2237627242 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 23516400 ps |
| CPU time | 17.76 seconds |
| Started | Aug 23 10:16:13 AM UTC 24 |
| Finished | Aug 23 10:16:31 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223 7627242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh adow_reg_errors.2237627242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2538627683 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 12680200 ps |
| CPU time | 15.05 seconds |
| Started | Aug 23 10:16:13 AM UTC 24 |
| Finished | Aug 23 10:16:29 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2538627683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f lash_ctrl_shadow_reg_errors_with_csr_rw.2538627683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3783288380 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 59527000 ps |
| CPU time | 20.23 seconds |
| Started | Aug 23 10:16:11 AM UTC 24 |
| Finished | Aug 23 10:16:32 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783288380 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.3783288380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3417311805 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 43536700 ps |
| CPU time | 21.15 seconds |
| Started | Aug 23 10:16:27 AM UTC 24 |
| Finished | Aug 23 10:16:50 AM UTC 24 |
| Peak memory | 290620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3417311805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3417311805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2224270264 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 61042800 ps |
| CPU time | 18.57 seconds |
| Started | Aug 23 10:16:26 AM UTC 24 |
| Finished | Aug 23 10:16:46 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224270264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.2224270264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3329226059 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 92079200 ps |
| CPU time | 15.07 seconds |
| Started | Aug 23 10:16:26 AM UTC 24 |
| Finished | Aug 23 10:16:42 AM UTC 24 |
| Peak memory | 272128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329226059 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.3329226059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1119784847 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 88701100 ps |
| CPU time | 17.18 seconds |
| Started | Aug 23 10:16:27 AM UTC 24 |
| Finished | Aug 23 10:16:46 AM UTC 24 |
| Peak memory | 272448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1119784847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _same_csr_outstanding.1119784847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1523835564 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 42703300 ps |
| CPU time | 15.77 seconds |
| Started | Aug 23 10:16:23 AM UTC 24 |
| Finished | Aug 23 10:16:40 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152 3835564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.1523835564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4236627108 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 12284500 ps |
| CPU time | 18.58 seconds |
| Started | Aug 23 10:16:24 AM UTC 24 |
| Finished | Aug 23 10:16:44 AM UTC 24 |
| Peak memory | 262080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4236627108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f lash_ctrl_shadow_reg_errors_with_csr_rw.4236627108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2633856716 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 688665800 ps |
| CPU time | 527.52 seconds |
| Started | Aug 23 10:16:23 AM UTC 24 |
| Finished | Aug 23 10:25:16 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633856716 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2633856716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.370498080 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 41223300 ps |
| CPU time | 20.75 seconds |
| Started | Aug 23 10:16:41 AM UTC 24 |
| Finished | Aug 23 10:17:02 AM UTC 24 |
| Peak memory | 284676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=370498080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.370498080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.410840208 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 41319500 ps |
| CPU time | 18.9 seconds |
| Started | Aug 23 10:16:36 AM UTC 24 |
| Finished | Aug 23 10:16:57 AM UTC 24 |
| Peak memory | 272448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410840208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.410840208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1658454163 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 44535400 ps |
| CPU time | 16.44 seconds |
| Started | Aug 23 10:16:34 AM UTC 24 |
| Finished | Aug 23 10:16:52 AM UTC 24 |
| Peak memory | 272132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658454163 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.1658454163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2865636512 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 115156500 ps |
| CPU time | 18.08 seconds |
| Started | Aug 23 10:16:39 AM UTC 24 |
| Finished | Aug 23 10:16:58 AM UTC 24 |
| Peak memory | 274496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2865636512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl _same_csr_outstanding.2865636512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.755696956 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 24349100 ps |
| CPU time | 14.87 seconds |
| Started | Aug 23 10:16:32 AM UTC 24 |
| Finished | Aug 23 10:16:48 AM UTC 24 |
| Peak memory | 261892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755 696956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sha dow_reg_errors.755696956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1841144161 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 41659800 ps |
| CPU time | 18.08 seconds |
| Started | Aug 23 10:16:32 AM UTC 24 |
| Finished | Aug 23 10:16:52 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1841144161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f lash_ctrl_shadow_reg_errors_with_csr_rw.1841144161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2912264027 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 352511400 ps |
| CPU time | 19.84 seconds |
| Started | Aug 23 10:16:29 AM UTC 24 |
| Finished | Aug 23 10:16:50 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912264027 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.2912264027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3875231397 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 430773100 ps |
| CPU time | 19.07 seconds |
| Started | Aug 23 10:16:50 AM UTC 24 |
| Finished | Aug 23 10:17:10 AM UTC 24 |
| Peak memory | 290880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3875231397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3875231397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3175509179 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 79644300 ps |
| CPU time | 18.81 seconds |
| Started | Aug 23 10:16:49 AM UTC 24 |
| Finished | Aug 23 10:17:09 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175509179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.3175509179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2510476798 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 15249200 ps |
| CPU time | 15.38 seconds |
| Started | Aug 23 10:16:47 AM UTC 24 |
| Finished | Aug 23 10:17:03 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510476798 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.2510476798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2991695175 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 169971500 ps |
| CPU time | 33.03 seconds |
| Started | Aug 23 10:16:49 AM UTC 24 |
| Finished | Aug 23 10:17:23 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2991695175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _same_csr_outstanding.2991695175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2252862254 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 36836400 ps |
| CPU time | 17.69 seconds |
| Started | Aug 23 10:16:45 AM UTC 24 |
| Finished | Aug 23 10:17:04 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225 2862254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh adow_reg_errors.2252862254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1199489846 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 11821000 ps |
| CPU time | 17.69 seconds |
| Started | Aug 23 10:16:47 AM UTC 24 |
| Finished | Aug 23 10:17:06 AM UTC 24 |
| Peak memory | 261880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1199489846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f lash_ctrl_shadow_reg_errors_with_csr_rw.1199489846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2427099480 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 206856100 ps |
| CPU time | 19.41 seconds |
| Started | Aug 23 10:16:42 AM UTC 24 |
| Finished | Aug 23 10:17:02 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427099480 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.2427099480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3492464306 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 704695800 ps |
| CPU time | 528.11 seconds |
| Started | Aug 23 10:16:43 AM UTC 24 |
| Finished | Aug 23 10:25:37 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492464306 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.3492464306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.588151209 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 137318900 ps |
| CPU time | 20.43 seconds |
| Started | Aug 23 10:17:04 AM UTC 24 |
| Finished | Aug 23 10:17:26 AM UTC 24 |
| Peak memory | 284484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=588151209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.588151209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.252117632 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 880034900 ps |
| CPU time | 19.68 seconds |
| Started | Aug 23 10:17:03 AM UTC 24 |
| Finished | Aug 23 10:17:24 AM UTC 24 |
| Peak memory | 274312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252117632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.252117632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1875218147 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 43855400 ps |
| CPU time | 15.28 seconds |
| Started | Aug 23 10:16:59 AM UTC 24 |
| Finished | Aug 23 10:17:16 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875218147 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.1875218147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1893250200 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 108166600 ps |
| CPU time | 19.92 seconds |
| Started | Aug 23 10:17:03 AM UTC 24 |
| Finished | Aug 23 10:17:25 AM UTC 24 |
| Peak memory | 274432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1893250200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl _same_csr_outstanding.1893250200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3972240781 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 36617100 ps |
| CPU time | 17.61 seconds |
| Started | Aug 23 10:16:53 AM UTC 24 |
| Finished | Aug 23 10:17:12 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397 2240781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh adow_reg_errors.3972240781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2495584651 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 43166100 ps |
| CPU time | 17.72 seconds |
| Started | Aug 23 10:16:57 AM UTC 24 |
| Finished | Aug 23 10:17:16 AM UTC 24 |
| Peak memory | 261876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2495584651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f lash_ctrl_shadow_reg_errors_with_csr_rw.2495584651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.832685771 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 478617200 ps |
| CPU time | 20.79 seconds |
| Started | Aug 23 10:16:51 AM UTC 24 |
| Finished | Aug 23 10:17:13 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832685771 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.832685771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1024169803 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 29828100 ps |
| CPU time | 16.29 seconds |
| Started | Aug 23 10:17:18 AM UTC 24 |
| Finished | Aug 23 10:17:35 AM UTC 24 |
| Peak memory | 274232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1024169803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1024169803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2059583016 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 415314300 ps |
| CPU time | 19.65 seconds |
| Started | Aug 23 10:17:14 AM UTC 24 |
| Finished | Aug 23 10:17:35 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059583016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.2059583016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.4091604962 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 16103200 ps |
| CPU time | 15.39 seconds |
| Started | Aug 23 10:17:13 AM UTC 24 |
| Finished | Aug 23 10:17:29 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091604962 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.4091604962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2562950339 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 434959900 ps |
| CPU time | 17.48 seconds |
| Started | Aug 23 10:17:17 AM UTC 24 |
| Finished | Aug 23 10:17:35 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2562950339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl _same_csr_outstanding.2562950339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.471373652 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 27507400 ps |
| CPU time | 18 seconds |
| Started | Aug 23 10:17:09 AM UTC 24 |
| Finished | Aug 23 10:17:29 AM UTC 24 |
| Peak memory | 261892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471 373652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sha dow_reg_errors.471373652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1332557626 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 49370200 ps |
| CPU time | 18 seconds |
| Started | Aug 23 10:17:11 AM UTC 24 |
| Finished | Aug 23 10:17:31 AM UTC 24 |
| Peak memory | 261880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1332557626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f lash_ctrl_shadow_reg_errors_with_csr_rw.1332557626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3786772585 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 111003400 ps |
| CPU time | 20.42 seconds |
| Started | Aug 23 10:17:04 AM UTC 24 |
| Finished | Aug 23 10:17:26 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786772585 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.3786772585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2806665157 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 151048400 ps |
| CPU time | 21.29 seconds |
| Started | Aug 23 10:17:31 AM UTC 24 |
| Finished | Aug 23 10:17:53 AM UTC 24 |
| Peak memory | 290620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2806665157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2806665157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3890205770 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 19241600 ps |
| CPU time | 15.53 seconds |
| Started | Aug 23 10:17:29 AM UTC 24 |
| Finished | Aug 23 10:17:46 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890205770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.3890205770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3958260772 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 48054300 ps |
| CPU time | 15.04 seconds |
| Started | Aug 23 10:17:27 AM UTC 24 |
| Finished | Aug 23 10:17:43 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958260772 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3958260772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.913600276 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 66988300 ps |
| CPU time | 19.31 seconds |
| Started | Aug 23 10:17:30 AM UTC 24 |
| Finished | Aug 23 10:17:50 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 913600276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ same_csr_outstanding.913600276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1497269343 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 13106800 ps |
| CPU time | 17.85 seconds |
| Started | Aug 23 10:17:26 AM UTC 24 |
| Finished | Aug 23 10:17:45 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149 7269343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.1497269343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1736369597 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 18509300 ps |
| CPU time | 17.88 seconds |
| Started | Aug 23 10:17:27 AM UTC 24 |
| Finished | Aug 23 10:17:46 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1736369597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f lash_ctrl_shadow_reg_errors_with_csr_rw.1736369597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.416968173 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 301285000 ps |
| CPU time | 20.6 seconds |
| Started | Aug 23 10:17:24 AM UTC 24 |
| Finished | Aug 23 10:17:45 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416968173 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.416968173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1784387600 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1793283500 ps |
| CPU time | 528 seconds |
| Started | Aug 23 10:17:25 AM UTC 24 |
| Finished | Aug 23 10:26:19 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784387600 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.1784387600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1148348548 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1401465600 ps |
| CPU time | 45.37 seconds |
| Started | Aug 23 10:14:30 AM UTC 24 |
| Finished | Aug 23 10:15:17 AM UTC 24 |
| Peak memory | 272392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148348548 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.1148348548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.689332840 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 124812900 ps |
| CPU time | 45.14 seconds |
| Started | Aug 23 10:14:30 AM UTC 24 |
| Finished | Aug 23 10:15:17 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689332840 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.689332840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1728819246 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 40746400 ps |
| CPU time | 18.57 seconds |
| Started | Aug 23 10:14:30 AM UTC 24 |
| Finished | Aug 23 10:14:50 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728819246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1728819246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2284361318 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 17481700 ps |
| CPU time | 15.29 seconds |
| Started | Aug 23 10:14:28 AM UTC 24 |
| Finished | Aug 23 10:14:44 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284361318 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2284361318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1310171030 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 26525000 ps |
| CPU time | 15.26 seconds |
| Started | Aug 23 10:14:28 AM UTC 24 |
| Finished | Aug 23 10:14:44 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310171030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.1310171030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1819618244 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 60653600 ps |
| CPU time | 15.07 seconds |
| Started | Aug 23 10:14:28 AM UTC 24 |
| Finished | Aug 23 10:14:44 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819618244 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.1819618244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1473735574 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 684232800 ps |
| CPU time | 17.72 seconds |
| Started | Aug 23 10:14:32 AM UTC 24 |
| Finished | Aug 23 10:14:51 AM UTC 24 |
| Peak memory | 272392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1473735574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.1473735574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1435646885 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 14829800 ps |
| CPU time | 15.23 seconds |
| Started | Aug 23 10:14:17 AM UTC 24 |
| Finished | Aug 23 10:14:33 AM UTC 24 |
| Peak memory | 261900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143 5646885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.1435646885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.657696063 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 21110600 ps |
| CPU time | 18.36 seconds |
| Started | Aug 23 10:14:26 AM UTC 24 |
| Finished | Aug 23 10:14:45 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=657696063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_shadow_reg_errors_with_csr_rw.657696063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3902512476 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 81257600 ps |
| CPU time | 17.73 seconds |
| Started | Aug 23 10:14:15 AM UTC 24 |
| Finished | Aug 23 10:14:34 AM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902512476 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3902512476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3570768313 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 741397300 ps |
| CPU time | 437.33 seconds |
| Started | Aug 23 10:14:15 AM UTC 24 |
| Finished | Aug 23 10:21:37 AM UTC 24 |
| Peak memory | 274380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570768313 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.3570768313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.4284745963 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 20760100 ps |
| CPU time | 15.44 seconds |
| Started | Aug 23 10:17:35 AM UTC 24 |
| Finished | Aug 23 10:17:52 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284745963 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.4284745963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1888396223 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 23959600 ps |
| CPU time | 15.21 seconds |
| Started | Aug 23 10:17:36 AM UTC 24 |
| Finished | Aug 23 10:17:52 AM UTC 24 |
| Peak memory | 272132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888396223 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.1888396223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3917228741 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 51965900 ps |
| CPU time | 15.1 seconds |
| Started | Aug 23 10:17:36 AM UTC 24 |
| Finished | Aug 23 10:17:52 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917228741 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.3917228741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.1007364564 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 17531200 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 10:17:44 AM UTC 24 |
| Finished | Aug 23 10:18:01 AM UTC 24 |
| Peak memory | 272200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007364564 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.1007364564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2742446075 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 14901600 ps |
| CPU time | 15.43 seconds |
| Started | Aug 23 10:17:45 AM UTC 24 |
| Finished | Aug 23 10:18:02 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742446075 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.2742446075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3230227530 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 17049100 ps |
| CPU time | 15.11 seconds |
| Started | Aug 23 10:17:46 AM UTC 24 |
| Finished | Aug 23 10:18:03 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230227530 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.3230227530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.976379528 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 52585500 ps |
| CPU time | 15.79 seconds |
| Started | Aug 23 10:17:46 AM UTC 24 |
| Finished | Aug 23 10:18:03 AM UTC 24 |
| Peak memory | 272260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976379528 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.976379528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1383305291 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 26463300 ps |
| CPU time | 14.96 seconds |
| Started | Aug 23 10:17:46 AM UTC 24 |
| Finished | Aug 23 10:18:02 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383305291 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.1383305291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1470409549 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 28983300 ps |
| CPU time | 15.12 seconds |
| Started | Aug 23 10:17:51 AM UTC 24 |
| Finished | Aug 23 10:18:08 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470409549 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.1470409549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.3274115055 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 72029700 ps |
| CPU time | 15.32 seconds |
| Started | Aug 23 10:17:53 AM UTC 24 |
| Finished | Aug 23 10:18:09 AM UTC 24 |
| Peak memory | 272128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274115055 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.3274115055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.759303853 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3002742900 ps |
| CPU time | 58.89 seconds |
| Started | Aug 23 10:14:46 AM UTC 24 |
| Finished | Aug 23 10:15:46 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759303853 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.759303853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3631129815 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6315872100 ps |
| CPU time | 56.84 seconds |
| Started | Aug 23 10:14:46 AM UTC 24 |
| Finished | Aug 23 10:15:44 AM UTC 24 |
| Peak memory | 272192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631129815 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.3631129815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2713069105 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 97069300 ps |
| CPU time | 31.54 seconds |
| Started | Aug 23 10:14:35 AM UTC 24 |
| Finished | Aug 23 10:15:07 AM UTC 24 |
| Peak memory | 272380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713069105 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.2713069105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.568422587 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 136566000 ps |
| CPU time | 21.63 seconds |
| Started | Aug 23 10:14:46 AM UTC 24 |
| Finished | Aug 23 10:15:09 AM UTC 24 |
| Peak memory | 290624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=568422587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.568422587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.709212991 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 146433100 ps |
| CPU time | 19.58 seconds |
| Started | Aug 23 10:14:38 AM UTC 24 |
| Finished | Aug 23 10:14:58 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709212991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.709212991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.731570006 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 23706700 ps |
| CPU time | 15.52 seconds |
| Started | Aug 23 10:14:35 AM UTC 24 |
| Finished | Aug 23 10:14:51 AM UTC 24 |
| Peak memory | 272256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731570006 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.731570006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1026295771 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 16927500 ps |
| CPU time | 15.91 seconds |
| Started | Aug 23 10:14:35 AM UTC 24 |
| Finished | Aug 23 10:14:52 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026295771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.1026295771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4219972420 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 17217500 ps |
| CPU time | 15.38 seconds |
| Started | Aug 23 10:14:35 AM UTC 24 |
| Finished | Aug 23 10:14:51 AM UTC 24 |
| Peak memory | 272264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219972420 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.4219972420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3872479690 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 1208966500 ps |
| CPU time | 34.31 seconds |
| Started | Aug 23 10:14:46 AM UTC 24 |
| Finished | Aug 23 10:15:21 AM UTC 24 |
| Peak memory | 274248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3872479690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ same_csr_outstanding.3872479690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3207824478 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 38865500 ps |
| CPU time | 15.11 seconds |
| Started | Aug 23 10:14:34 AM UTC 24 |
| Finished | Aug 23 10:14:51 AM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320 7824478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha dow_reg_errors.3207824478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1298373961 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 13959000 ps |
| CPU time | 15.04 seconds |
| Started | Aug 23 10:14:35 AM UTC 24 |
| Finished | Aug 23 10:14:51 AM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1298373961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1298373961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.10024480 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 18210900 ps |
| CPU time | 15.27 seconds |
| Started | Aug 23 10:17:54 AM UTC 24 |
| Finished | Aug 23 10:18:10 AM UTC 24 |
| Peak memory | 272320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10024480 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.10024480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1036885816 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 14673200 ps |
| CPU time | 15.57 seconds |
| Started | Aug 23 10:17:54 AM UTC 24 |
| Finished | Aug 23 10:18:10 AM UTC 24 |
| Peak memory | 272320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036885816 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.1036885816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1840024590 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 24987500 ps |
| CPU time | 15.19 seconds |
| Started | Aug 23 10:17:55 AM UTC 24 |
| Finished | Aug 23 10:18:11 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840024590 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.1840024590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2644265688 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 186852200 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 10:18:02 AM UTC 24 |
| Finished | Aug 23 10:18:18 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644265688 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.2644265688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2556894432 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 27400400 ps |
| CPU time | 15.16 seconds |
| Started | Aug 23 10:18:03 AM UTC 24 |
| Finished | Aug 23 10:18:19 AM UTC 24 |
| Peak memory | 272128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556894432 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.2556894432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2474261053 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 16187500 ps |
| CPU time | 15.52 seconds |
| Started | Aug 23 10:18:03 AM UTC 24 |
| Finished | Aug 23 10:18:19 AM UTC 24 |
| Peak memory | 272320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474261053 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2474261053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.1801150540 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 40682600 ps |
| CPU time | 16.49 seconds |
| Started | Aug 23 10:18:04 AM UTC 24 |
| Finished | Aug 23 10:18:21 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801150540 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.1801150540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.629268682 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 52130400 ps |
| CPU time | 15.08 seconds |
| Started | Aug 23 10:18:04 AM UTC 24 |
| Finished | Aug 23 10:18:20 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629268682 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.629268682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3083637280 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 111100900 ps |
| CPU time | 15.57 seconds |
| Started | Aug 23 10:18:09 AM UTC 24 |
| Finished | Aug 23 10:18:26 AM UTC 24 |
| Peak memory | 272264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083637280 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.3083637280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.570649918 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 15835300 ps |
| CPU time | 15.24 seconds |
| Started | Aug 23 10:18:10 AM UTC 24 |
| Finished | Aug 23 10:18:26 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570649918 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.570649918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.294411585 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 2415504200 ps |
| CPU time | 58.72 seconds |
| Started | Aug 23 10:14:52 AM UTC 24 |
| Finished | Aug 23 10:15:53 AM UTC 24 |
| Peak memory | 272452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294411585 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.294411585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1211638070 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4812823100 ps |
| CPU time | 72.17 seconds |
| Started | Aug 23 10:14:52 AM UTC 24 |
| Finished | Aug 23 10:16:06 AM UTC 24 |
| Peak memory | 272280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211638070 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.1211638070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4060223408 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 26351400 ps |
| CPU time | 52.04 seconds |
| Started | Aug 23 10:14:52 AM UTC 24 |
| Finished | Aug 23 10:15:46 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060223408 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.4060223408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.55486351 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 103991700 ps |
| CPU time | 19.5 seconds |
| Started | Aug 23 10:14:56 AM UTC 24 |
| Finished | Aug 23 10:15:16 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=55486351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.55486351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.373417375 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 78616600 ps |
| CPU time | 16.07 seconds |
| Started | Aug 23 10:14:52 AM UTC 24 |
| Finished | Aug 23 10:15:10 AM UTC 24 |
| Peak memory | 274240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373417375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.373417375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.357389538 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 207538500 ps |
| CPU time | 15.21 seconds |
| Started | Aug 23 10:14:51 AM UTC 24 |
| Finished | Aug 23 10:15:08 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357389538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.357389538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2114027250 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 69749000 ps |
| CPU time | 15.41 seconds |
| Started | Aug 23 10:14:51 AM UTC 24 |
| Finished | Aug 23 10:15:08 AM UTC 24 |
| Peak memory | 272264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114027250 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.2114027250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3304659359 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 189373800 ps |
| CPU time | 17.15 seconds |
| Started | Aug 23 10:14:54 AM UTC 24 |
| Finished | Aug 23 10:15:13 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3304659359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ same_csr_outstanding.3304659359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2276600927 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 23664200 ps |
| CPU time | 18.16 seconds |
| Started | Aug 23 10:14:51 AM UTC 24 |
| Finished | Aug 23 10:15:10 AM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227 6600927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha dow_reg_errors.2276600927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2115695153 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 14699300 ps |
| CPU time | 18.26 seconds |
| Started | Aug 23 10:14:51 AM UTC 24 |
| Finished | Aug 23 10:15:11 AM UTC 24 |
| Peak memory | 261892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2115695153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2115695153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3904109090 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 46471700 ps |
| CPU time | 17.33 seconds |
| Started | Aug 23 10:14:48 AM UTC 24 |
| Finished | Aug 23 10:15:06 AM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904109090 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3904109090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1449198155 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 45752300 ps |
| CPU time | 15.27 seconds |
| Started | Aug 23 10:18:11 AM UTC 24 |
| Finished | Aug 23 10:18:27 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449198155 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.1449198155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1775668715 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 17941400 ps |
| CPU time | 15.4 seconds |
| Started | Aug 23 10:18:11 AM UTC 24 |
| Finished | Aug 23 10:18:28 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775668715 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.1775668715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.552899353 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 17929500 ps |
| CPU time | 15.52 seconds |
| Started | Aug 23 10:18:12 AM UTC 24 |
| Finished | Aug 23 10:18:29 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552899353 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.552899353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.1081148503 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 25999900 ps |
| CPU time | 15.05 seconds |
| Started | Aug 23 10:18:17 AM UTC 24 |
| Finished | Aug 23 10:18:33 AM UTC 24 |
| Peak memory | 272128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081148503 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.1081148503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2094652536 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 112592900 ps |
| CPU time | 14.97 seconds |
| Started | Aug 23 10:18:18 AM UTC 24 |
| Finished | Aug 23 10:18:34 AM UTC 24 |
| Peak memory | 272200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094652536 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.2094652536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3217989269 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 53674000 ps |
| CPU time | 16.09 seconds |
| Started | Aug 23 10:18:19 AM UTC 24 |
| Finished | Aug 23 10:18:37 AM UTC 24 |
| Peak memory | 272328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217989269 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.3217989269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.4105674103 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 27563000 ps |
| CPU time | 15.23 seconds |
| Started | Aug 23 10:18:21 AM UTC 24 |
| Finished | Aug 23 10:18:37 AM UTC 24 |
| Peak memory | 272060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105674103 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.4105674103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2287537095 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 57851900 ps |
| CPU time | 15.31 seconds |
| Started | Aug 23 10:18:21 AM UTC 24 |
| Finished | Aug 23 10:18:37 AM UTC 24 |
| Peak memory | 272136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287537095 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.2287537095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.59569284 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 17975100 ps |
| CPU time | 15.28 seconds |
| Started | Aug 23 10:18:23 AM UTC 24 |
| Finished | Aug 23 10:18:39 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59569284 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.59569284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.728323864 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 26882000 ps |
| CPU time | 15.03 seconds |
| Started | Aug 23 10:18:27 AM UTC 24 |
| Finished | Aug 23 10:18:43 AM UTC 24 |
| Peak memory | 272324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728323864 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.728323864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.316638710 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 280526200 ps |
| CPU time | 19.53 seconds |
| Started | Aug 23 10:15:09 AM UTC 24 |
| Finished | Aug 23 10:15:30 AM UTC 24 |
| Peak memory | 287864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=316638710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.316638710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3449376187 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 389777300 ps |
| CPU time | 19.37 seconds |
| Started | Aug 23 10:15:08 AM UTC 24 |
| Finished | Aug 23 10:15:28 AM UTC 24 |
| Peak memory | 272320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449376187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.3449376187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.1051817455 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 54978800 ps |
| CPU time | 15.15 seconds |
| Started | Aug 23 10:15:08 AM UTC 24 |
| Finished | Aug 23 10:15:24 AM UTC 24 |
| Peak memory | 272204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051817455 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.1051817455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.732926667 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 742395100 ps |
| CPU time | 22.99 seconds |
| Started | Aug 23 10:15:08 AM UTC 24 |
| Finished | Aug 23 10:15:32 AM UTC 24 |
| Peak memory | 272196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 732926667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_s ame_csr_outstanding.732926667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3791404369 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 29535900 ps |
| CPU time | 17.7 seconds |
| Started | Aug 23 10:15:02 AM UTC 24 |
| Finished | Aug 23 10:15:21 AM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379 1404369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha dow_reg_errors.3791404369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.90429825 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 26148900 ps |
| CPU time | 18.58 seconds |
| Started | Aug 23 10:15:03 AM UTC 24 |
| Finished | Aug 23 10:15:23 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=90429825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_shadow_reg_errors_with_csr_rw.90429825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4192609187 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 70902400 ps |
| CPU time | 17.6 seconds |
| Started | Aug 23 10:14:56 AM UTC 24 |
| Finished | Aug 23 10:15:14 AM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192609187 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.4192609187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3583475138 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 362763200 ps |
| CPU time | 858.43 seconds |
| Started | Aug 23 10:15:00 AM UTC 24 |
| Finished | Aug 23 10:29:27 AM UTC 24 |
| Peak memory | 276408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583475138 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.3583475138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2565754716 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 45161700 ps |
| CPU time | 19.88 seconds |
| Started | Aug 23 10:15:15 AM UTC 24 |
| Finished | Aug 23 10:15:36 AM UTC 24 |
| Peak memory | 284476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2565754716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2565754716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2485646124 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 169345900 ps |
| CPU time | 15.96 seconds |
| Started | Aug 23 10:15:11 AM UTC 24 |
| Finished | Aug 23 10:15:28 AM UTC 24 |
| Peak memory | 274436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485646124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.2485646124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.68019041 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 36544700 ps |
| CPU time | 15.26 seconds |
| Started | Aug 23 10:15:11 AM UTC 24 |
| Finished | Aug 23 10:15:28 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68019041 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.68019041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.966298866 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 449639100 ps |
| CPU time | 39.12 seconds |
| Started | Aug 23 10:15:13 AM UTC 24 |
| Finished | Aug 23 10:15:54 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 966298866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_s ame_csr_outstanding.966298866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.553418807 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 20590400 ps |
| CPU time | 18 seconds |
| Started | Aug 23 10:15:10 AM UTC 24 |
| Finished | Aug 23 10:15:29 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553 418807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shad ow_reg_errors.553418807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3914595603 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 37492600 ps |
| CPU time | 14.99 seconds |
| Started | Aug 23 10:15:10 AM UTC 24 |
| Finished | Aug 23 10:15:26 AM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3914595603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3914595603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1142560330 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 346955800 ps |
| CPU time | 526.48 seconds |
| Started | Aug 23 10:15:09 AM UTC 24 |
| Finished | Aug 23 10:24:02 AM UTC 24 |
| Peak memory | 273512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142560330 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.1142560330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.558699718 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 129303500 ps |
| CPU time | 20.8 seconds |
| Started | Aug 23 10:15:28 AM UTC 24 |
| Finished | Aug 23 10:15:50 AM UTC 24 |
| Peak memory | 284480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=558699718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.558699718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1178526283 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 93229200 ps |
| CPU time | 18.88 seconds |
| Started | Aug 23 10:15:23 AM UTC 24 |
| Finished | Aug 23 10:15:44 AM UTC 24 |
| Peak memory | 274436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178526283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.1178526283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.96449447 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 16525300 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 10:15:22 AM UTC 24 |
| Finished | Aug 23 10:15:39 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96449447 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.96449447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.202129094 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 102289400 ps |
| CPU time | 16.91 seconds |
| Started | Aug 23 10:15:25 AM UTC 24 |
| Finished | Aug 23 10:15:43 AM UTC 24 |
| Peak memory | 274244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 202129094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_s ame_csr_outstanding.202129094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1192596630 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 34006100 ps |
| CPU time | 18.31 seconds |
| Started | Aug 23 10:15:17 AM UTC 24 |
| Finished | Aug 23 10:15:37 AM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119 2596630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha dow_reg_errors.1192596630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4141000204 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 14454100 ps |
| CPU time | 18.14 seconds |
| Started | Aug 23 10:15:21 AM UTC 24 |
| Finished | Aug 23 10:15:41 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4141000204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fl ash_ctrl_shadow_reg_errors_with_csr_rw.4141000204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2533171621 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 121451800 ps |
| CPU time | 17.7 seconds |
| Started | Aug 23 10:15:17 AM UTC 24 |
| Finished | Aug 23 10:15:36 AM UTC 24 |
| Peak memory | 274252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533171621 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2533171621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2740965351 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 661704000 ps |
| CPU time | 540.14 seconds |
| Started | Aug 23 10:15:17 AM UTC 24 |
| Finished | Aug 23 10:24:24 AM UTC 24 |
| Peak memory | 274316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740965351 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.2740965351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2080960982 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 120892500 ps |
| CPU time | 17.96 seconds |
| Started | Aug 23 10:15:33 AM UTC 24 |
| Finished | Aug 23 10:15:52 AM UTC 24 |
| Peak memory | 284440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2080960982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2080960982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3597889465 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 22272800 ps |
| CPU time | 18.86 seconds |
| Started | Aug 23 10:15:32 AM UTC 24 |
| Finished | Aug 23 10:15:52 AM UTC 24 |
| Peak memory | 272388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597889465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.3597889465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1294133472 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 53607700 ps |
| CPU time | 15.92 seconds |
| Started | Aug 23 10:15:31 AM UTC 24 |
| Finished | Aug 23 10:15:48 AM UTC 24 |
| Peak memory | 272332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294133472 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1294133472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3077126340 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 276902500 ps |
| CPU time | 21.76 seconds |
| Started | Aug 23 10:15:33 AM UTC 24 |
| Finished | Aug 23 10:15:56 AM UTC 24 |
| Peak memory | 272040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3077126340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.3077126340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.14301638 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 13058300 ps |
| CPU time | 18.07 seconds |
| Started | Aug 23 10:15:30 AM UTC 24 |
| Finished | Aug 23 10:15:49 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143 01638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shado w_reg_errors.14301638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2731254099 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 33233700 ps |
| CPU time | 17.83 seconds |
| Started | Aug 23 10:15:30 AM UTC 24 |
| Finished | Aug 23 10:15:49 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2731254099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2731254099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1158151215 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 249226600 ps |
| CPU time | 17.21 seconds |
| Started | Aug 23 10:15:29 AM UTC 24 |
| Finished | Aug 23 10:15:47 AM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158151215 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1158151215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3234053295 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 282997800 ps |
| CPU time | 529.44 seconds |
| Started | Aug 23 10:15:29 AM UTC 24 |
| Finished | Aug 23 10:24:24 AM UTC 24 |
| Peak memory | 274316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234053295 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.3234053295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.984749510 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 44109200 ps |
| CPU time | 20.74 seconds |
| Started | Aug 23 10:15:45 AM UTC 24 |
| Finished | Aug 23 10:16:07 AM UTC 24 |
| Peak memory | 284480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=984749510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.984749510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2363122894 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 91430000 ps |
| CPU time | 19.21 seconds |
| Started | Aug 23 10:15:43 AM UTC 24 |
| Finished | Aug 23 10:16:04 AM UTC 24 |
| Peak memory | 274432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363122894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.2363122894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1373094129 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 127282800 ps |
| CPU time | 15.29 seconds |
| Started | Aug 23 10:15:41 AM UTC 24 |
| Finished | Aug 23 10:15:58 AM UTC 24 |
| Peak memory | 272204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373094129 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1373094129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.535576033 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 35476300 ps |
| CPU time | 19.46 seconds |
| Started | Aug 23 10:15:44 AM UTC 24 |
| Finished | Aug 23 10:16:05 AM UTC 24 |
| Peak memory | 272200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 535576033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_s ame_csr_outstanding.535576033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3757836074 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 32746700 ps |
| CPU time | 18.16 seconds |
| Started | Aug 23 10:15:38 AM UTC 24 |
| Finished | Aug 23 10:15:57 AM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375 7836074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.3757836074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.479088471 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 36735800 ps |
| CPU time | 17.9 seconds |
| Started | Aug 23 10:15:40 AM UTC 24 |
| Finished | Aug 23 10:15:59 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=479088471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_shadow_reg_errors_with_csr_rw.479088471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.953978025 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 67709400 ps |
| CPU time | 17.42 seconds |
| Started | Aug 23 10:15:37 AM UTC 24 |
| Finished | Aug 23 10:15:56 AM UTC 24 |
| Peak memory | 274432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953978025 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.953978025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3994146426 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 736246500 ps |
| CPU time | 173.8 seconds |
| Started | Aug 23 10:23:54 AM UTC 24 |
| Finished | Aug 23 10:26:50 AM UTC 24 |
| Peak memory | 289700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3994146426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3994146426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.1609326865 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 11914748700 ps |
| CPU time | 2752.7 seconds |
| Started | Aug 23 10:20:37 AM UTC 24 |
| Finished | Aug 23 11:06:56 AM UTC 24 |
| Peak memory | 277992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 09326865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _error_prog_type.1609326865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1119335981 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 27900500 ps |
| CPU time | 29.76 seconds |
| Started | Aug 23 10:25:51 AM UTC 24 |
| Finished | Aug 23 10:26:22 AM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111933598 1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.1119335981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.696079173 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 124965500 ps |
| CPU time | 120.21 seconds |
| Started | Aug 23 10:18:34 AM UTC 24 |
| Finished | Aug 23 10:20:36 AM UTC 24 |
| Peak memory | 275132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696079173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.696079173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1030145370 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 19436523600 ps |
| CPU time | 125.85 seconds |
| Started | Aug 23 10:18:38 AM UTC 24 |
| Finished | Aug 23 10:20:46 AM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030145370 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.1030145370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.284773902 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 10253118100 ps |
| CPU time | 367.21 seconds |
| Started | Aug 23 10:24:03 AM UTC 24 |
| Finished | Aug 23 10:30:14 AM UTC 24 |
| Peak memory | 342952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=284773902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integrity.284773902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1286959286 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5714570700 ps |
| CPU time | 113.59 seconds |
| Started | Aug 23 10:24:17 AM UTC 24 |
| Finished | Aug 23 10:26:13 AM UTC 24 |
| Peak memory | 303904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1286959286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.1286959286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.151085138 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 92939938600 ps |
| CPU time | 232.04 seconds |
| Started | Aug 23 10:24:17 AM UTC 24 |
| Finished | Aug 23 10:28:12 AM UTC 24 |
| Peak memory | 271204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151085138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.151085138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1846504488 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 18643800 ps |
| CPU time | 14.66 seconds |
| Started | Aug 23 10:25:41 AM UTC 24 |
| Finished | Aug 23 10:25:57 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1846504488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.1846504488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2194679503 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 24115400 ps |
| CPU time | 14.86 seconds |
| Started | Aug 23 10:25:34 AM UTC 24 |
| Finished | Aug 23 10:25:50 AM UTC 24 |
| Peak memory | 273132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2194679503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2194679503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.3034342963 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 50892100 ps |
| CPU time | 14.38 seconds |
| Started | Aug 23 10:24:24 AM UTC 24 |
| Finished | Aug 23 10:24:40 AM UTC 24 |
| Peak memory | 271120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034342963 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.3034342963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4215812612 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 62938100 ps |
| CPU time | 87.56 seconds |
| Started | Aug 23 10:18:29 AM UTC 24 |
| Finished | Aug 23 10:19:59 AM UTC 24 |
| Peak memory | 279492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215812612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.4215812612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2358496248 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2926914500 ps |
| CPU time | 146.1 seconds |
| Started | Aug 23 10:18:35 AM UTC 24 |
| Finished | Aug 23 10:21:03 AM UTC 24 |
| Peak memory | 273348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358496248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2358496248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3433369264 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 65424600 ps |
| CPU time | 33.63 seconds |
| Started | Aug 23 10:25:16 AM UTC 24 |
| Finished | Aug 23 10:25:51 AM UTC 24 |
| Peak memory | 287548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343336926 4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.3433369264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.4018733912 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 102266200 ps |
| CPU time | 49.56 seconds |
| Started | Aug 23 10:25:51 AM UTC 24 |
| Finished | Aug 23 10:26:42 AM UTC 24 |
| Peak memory | 291772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018733912 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.4018733912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.3050833566 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 193715000 ps |
| CPU time | 15.15 seconds |
| Started | Aug 23 10:21:56 AM UTC 24 |
| Finished | Aug 23 10:22:12 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050833566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.3050833566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2521826066 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 18619900 ps |
| CPU time | 23.99 seconds |
| Started | Aug 23 10:23:32 AM UTC 24 |
| Finished | Aug 23 10:23:57 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2521826066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_read_word_sweep_derr.2521826066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2557558010 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 88734700 ps |
| CPU time | 22.78 seconds |
| Started | Aug 23 10:22:26 AM UTC 24 |
| Finished | Aug 23 10:22:50 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557558010 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.2557558010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.3308247925 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 567366200 ps |
| CPU time | 93.12 seconds |
| Started | Aug 23 10:21:57 AM UTC 24 |
| Finished | Aug 23 10:23:32 AM UTC 24 |
| Peak memory | 291800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3308247925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.3308247925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.2577954996 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2336889800 ps |
| CPU time | 113.03 seconds |
| Started | Aug 23 10:23:37 AM UTC 24 |
| Finished | Aug 23 10:25:32 AM UTC 24 |
| Peak memory | 291756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577954996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2577954996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.540235031 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 64401300 ps |
| CPU time | 30.59 seconds |
| Started | Aug 23 10:24:25 AM UTC 24 |
| Finished | Aug 23 10:24:57 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540235031 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.540235031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1653172123 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3295017800 ps |
| CPU time | 166.52 seconds |
| Started | Aug 23 10:22:51 AM UTC 24 |
| Finished | Aug 23 10:25:40 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1653172123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.1653172123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3980701905 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 952590700 ps |
| CPU time | 69.98 seconds |
| Started | Aug 23 10:23:02 AM UTC 24 |
| Finished | Aug 23 10:24:14 AM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398 0701905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.3980701905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2986761954 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 818344300 ps |
| CPU time | 74.84 seconds |
| Started | Aug 23 10:22:59 AM UTC 24 |
| Finished | Aug 23 10:24:16 AM UTC 24 |
| Peak memory | 285864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 86761954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se rr_counter.2986761954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2418000499 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 245844200 ps |
| CPU time | 129.28 seconds |
| Started | Aug 23 10:18:27 AM UTC 24 |
| Finished | Aug 23 10:20:38 AM UTC 24 |
| Peak memory | 287688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418000499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2418000499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.2486649827 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 16390900 ps |
| CPU time | 28.31 seconds |
| Started | Aug 23 10:18:28 AM UTC 24 |
| Finished | Aug 23 10:18:57 AM UTC 24 |
| Peak memory | 271188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486649827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2486649827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.14201869 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 169675800 ps |
| CPU time | 809.92 seconds |
| Started | Aug 23 10:25:15 AM UTC 24 |
| Finished | Aug 23 10:38:53 AM UTC 24 |
| Peak memory | 294260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14201869 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.14201869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.3350386863 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 78121500 ps |
| CPU time | 28.93 seconds |
| Started | Aug 23 10:18:30 AM UTC 24 |
| Finished | Aug 23 10:19:02 AM UTC 24 |
| Peak memory | 271128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350386863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3350386863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3956393745 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2534125700 ps |
| CPU time | 141.21 seconds |
| Started | Aug 23 10:21:28 AM UTC 24 |
| Finished | Aug 23 10:23:52 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3956393745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.3956393745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2267250074 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 75314800 ps |
| CPU time | 15.89 seconds |
| Started | Aug 23 10:21:37 AM UTC 24 |
| Finished | Aug 23 10:21:55 AM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267250074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2267250074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2976999247 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 22431900 ps |
| CPU time | 14.55 seconds |
| Started | Aug 23 10:32:58 AM UTC 24 |
| Finished | Aug 23 10:33:14 AM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2976999247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2976999247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2550978624 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 49899000 ps |
| CPU time | 14.55 seconds |
| Started | Aug 23 10:33:44 AM UTC 24 |
| Finished | Aug 23 10:34:00 AM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550978624 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2550978624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3932353248 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 37775400 ps |
| CPU time | 15.12 seconds |
| Started | Aug 23 10:33:17 AM UTC 24 |
| Finished | Aug 23 10:33:33 AM UTC 24 |
| Peak memory | 273060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932353248 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.3932353248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2132504039 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 17098100 ps |
| CPU time | 17.62 seconds |
| Started | Aug 23 10:32:39 AM UTC 24 |
| Finished | Aug 23 10:32:58 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132504039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2132504039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.786837920 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 921853300 ps |
| CPU time | 205.12 seconds |
| Started | Aug 23 10:30:15 AM UTC 24 |
| Finished | Aug 23 10:33:43 AM UTC 24 |
| Peak memory | 291744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=786837920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_derr_detect.786837920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2602048397 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3722370500 ps |
| CPU time | 418.71 seconds |
| Started | Aug 23 10:26:18 AM UTC 24 |
| Finished | Aug 23 10:33:21 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602048397 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2602048397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2108578002 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4491632100 ps |
| CPU time | 2550.56 seconds |
| Started | Aug 23 10:27:30 AM UTC 24 |
| Finished | Aug 23 11:10:25 AM UTC 24 |
| Peak memory | 275924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108578002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2108578002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.840320841 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1006141000 ps |
| CPU time | 3074.26 seconds |
| Started | Aug 23 10:26:51 AM UTC 24 |
| Finished | Aug 23 11:18:34 AM UTC 24 |
| Peak memory | 275944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84 0320841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ error_prog_type.840320841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.799775616 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 328472100 ps |
| CPU time | 899.11 seconds |
| Started | Aug 23 10:27:04 AM UTC 24 |
| Finished | Aug 23 10:42:12 AM UTC 24 |
| Peak memory | 285392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799775616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.799775616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1528017704 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 435938500 ps |
| CPU time | 22.89 seconds |
| Started | Aug 23 10:26:38 AM UTC 24 |
| Finished | Aug 23 10:27:02 AM UTC 24 |
| Peak memory | 275136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 28017704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc h_code.1528017704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.356857202 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 342319900 ps |
| CPU time | 36.23 seconds |
| Started | Aug 23 10:33:13 AM UTC 24 |
| Finished | Aug 23 10:33:51 AM UTC 24 |
| Peak memory | 273184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568572 02 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fs _sup.356857202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.345156025 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 350857089800 ps |
| CPU time | 1933.25 seconds |
| Started | Aug 23 10:26:43 AM UTC 24 |
| Finished | Aug 23 10:59:16 AM UTC 24 |
| Peak memory | 277836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345156025 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.345156025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.498083383 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 39980900 ps |
| CPU time | 29.74 seconds |
| Started | Aug 23 10:33:35 AM UTC 24 |
| Finished | Aug 23 10:34:06 AM UTC 24 |
| Peak memory | 277368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498083383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hos t_addr_infection.498083383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.835009042 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 575999686800 ps |
| CPU time | 1794.02 seconds |
| Started | Aug 23 10:26:25 AM UTC 24 |
| Finished | Aug 23 10:56:36 AM UTC 24 |
| Peak memory | 277988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835009042 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.835009042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3067655209 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 65574000 ps |
| CPU time | 29.24 seconds |
| Started | Aug 23 10:26:07 AM UTC 24 |
| Finished | Aug 23 10:26:37 AM UTC 24 |
| Peak memory | 275392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067655209 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3067655209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.876836959 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 151947700 ps |
| CPU time | 14.65 seconds |
| Started | Aug 23 10:33:33 AM UTC 24 |
| Finished | Aug 23 10:33:49 AM UTC 24 |
| Peak memory | 269268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=876836959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_hw_read_seed_err.876836959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2503835369 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 397582814700 ps |
| CPU time | 1695.17 seconds |
| Started | Aug 23 10:26:19 AM UTC 24 |
| Finished | Aug 23 10:54:51 AM UTC 24 |
| Peak memory | 277836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503835369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2503835369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.327815836 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 80144323300 ps |
| CPU time | 662.86 seconds |
| Started | Aug 23 10:26:20 AM UTC 24 |
| Finished | Aug 23 10:37:30 AM UTC 24 |
| Peak memory | 274920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327815836 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.327815836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2592052871 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 13317472200 ps |
| CPU time | 391.3 seconds |
| Started | Aug 23 10:30:19 AM UTC 24 |
| Finished | Aug 23 10:36:55 AM UTC 24 |
| Peak memory | 340952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2592052871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr ity.2592052871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.645602144 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 937781300 ps |
| CPU time | 106.57 seconds |
| Started | Aug 23 10:30:24 AM UTC 24 |
| Finished | Aug 23 10:32:13 AM UTC 24 |
| Peak memory | 306084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645602144 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.645602144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.3441826486 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7983313200 ps |
| CPU time | 57.65 seconds |
| Started | Aug 23 10:30:31 AM UTC 24 |
| Finished | Aug 23 10:31:30 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441826486 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.3441826486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4204320399 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 20216828100 ps |
| CPU time | 166.96 seconds |
| Started | Aug 23 10:31:31 AM UTC 24 |
| Finished | Aug 23 10:34:21 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204320399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.4204320399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2646676047 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 27214400 ps |
| CPU time | 14.36 seconds |
| Started | Aug 23 10:33:33 AM UTC 24 |
| Finished | Aug 23 10:33:48 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2646676047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_lcmgr_intg.2646676047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.4023983006 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1884947300 ps |
| CPU time | 70.01 seconds |
| Started | Aug 23 10:27:44 AM UTC 24 |
| Finished | Aug 23 10:28:55 AM UTC 24 |
| Peak memory | 270892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023983006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.4023983006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1898338599 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 76384800 ps |
| CPU time | 151.6 seconds |
| Started | Aug 23 10:26:23 AM UTC 24 |
| Finished | Aug 23 10:28:57 AM UTC 24 |
| Peak memory | 271208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898338599 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1898338599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1056021626 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 904243400 ps |
| CPU time | 108.84 seconds |
| Started | Aug 23 10:30:15 AM UTC 24 |
| Finished | Aug 23 10:32:06 AM UTC 24 |
| Peak memory | 291744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1056021626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1056021626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2869869472 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3892589100 ps |
| CPU time | 454.19 seconds |
| Started | Aug 23 10:26:09 AM UTC 24 |
| Finished | Aug 23 10:33:48 AM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869869472 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2869869472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.3383639340 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 18112200 ps |
| CPU time | 14.65 seconds |
| Started | Aug 23 10:31:44 AM UTC 24 |
| Finished | Aug 23 10:32:01 AM UTC 24 |
| Peak memory | 268980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383639340 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.3383639340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.51079014 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2844422800 ps |
| CPU time | 1759.66 seconds |
| Started | Aug 23 10:25:59 AM UTC 24 |
| Finished | Aug 23 10:55:36 AM UTC 24 |
| Peak memory | 302500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51079014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.51079014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.2078955406 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2826665200 ps |
| CPU time | 133.62 seconds |
| Started | Aug 23 10:26:08 AM UTC 24 |
| Finished | Aug 23 10:28:24 AM UTC 24 |
| Peak memory | 273408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078955406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2078955406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1846028581 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 127944600 ps |
| CPU time | 32.92 seconds |
| Started | Aug 23 10:32:07 AM UTC 24 |
| Finished | Aug 23 10:32:41 AM UTC 24 |
| Peak memory | 287708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846028581 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.1846028581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3993554288 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 135743900 ps |
| CPU time | 23.18 seconds |
| Started | Aug 23 10:29:50 AM UTC 24 |
| Finished | Aug 23 10:30:14 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3993554288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_read_word_sweep_derr.3993554288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2121647246 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 42275800 ps |
| CPU time | 23.53 seconds |
| Started | Aug 23 10:28:48 AM UTC 24 |
| Finished | Aug 23 10:29:13 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121647246 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.2121647246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1817652686 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 95257399000 ps |
| CPU time | 724.42 seconds |
| Started | Aug 23 10:33:22 AM UTC 24 |
| Finished | Aug 23 10:45:34 AM UTC 24 |
| Peak memory | 273044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1817652686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.1817652686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3832898280 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 602557200 ps |
| CPU time | 104.3 seconds |
| Started | Aug 23 10:28:13 AM UTC 24 |
| Finished | Aug 23 10:29:59 AM UTC 24 |
| Peak memory | 291780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3832898280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.3832898280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3645097304 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2379192900 ps |
| CPU time | 102.77 seconds |
| Started | Aug 23 10:29:59 AM UTC 24 |
| Finished | Aug 23 10:31:44 AM UTC 24 |
| Peak memory | 291772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645097304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3645097304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3240970199 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 715353200 ps |
| CPU time | 92.58 seconds |
| Started | Aug 23 10:28:56 AM UTC 24 |
| Finished | Aug 23 10:30:31 AM UTC 24 |
| Peak memory | 292036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3240970199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_ro_serr.3240970199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.3563145741 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6531064100 ps |
| CPU time | 173.25 seconds |
| Started | Aug 23 10:30:00 AM UTC 24 |
| Finished | Aug 23 10:32:56 AM UTC 24 |
| Peak memory | 299964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3563145741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_rw_derr.3563145741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2830441962 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 71645900 ps |
| CPU time | 32.99 seconds |
| Started | Aug 23 10:31:45 AM UTC 24 |
| Finished | Aug 23 10:32:19 AM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830441962 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2830441962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.403398530 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 12480105600 ps |
| CPU time | 201.32 seconds |
| Started | Aug 23 10:28:57 AM UTC 24 |
| Finished | Aug 23 10:32:21 AM UTC 24 |
| Peak memory | 292008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=403398530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.403398530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.3054986143 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 434112400 ps |
| CPU time | 52.92 seconds |
| Started | Aug 23 10:32:22 AM UTC 24 |
| Finished | Aug 23 10:33:16 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054986143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3054986143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1800809718 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1758054500 ps |
| CPU time | 74.2 seconds |
| Started | Aug 23 10:29:28 AM UTC 24 |
| Finished | Aug 23 10:30:43 AM UTC 24 |
| Peak memory | 275632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180 0809718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser r_address.1800809718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.4055132015 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8650233700 ps |
| CPU time | 62.88 seconds |
| Started | Aug 23 10:29:13 AM UTC 24 |
| Finished | Aug 23 10:30:18 AM UTC 24 |
| Peak memory | 275624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 55132015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.4055132015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1408221572 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 91248900 ps |
| CPU time | 104.99 seconds |
| Started | Aug 23 10:25:57 AM UTC 24 |
| Finished | Aug 23 10:27:43 AM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408221572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1408221572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3006590537 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 21768000 ps |
| CPU time | 25.76 seconds |
| Started | Aug 23 10:25:58 AM UTC 24 |
| Finished | Aug 23 10:26:25 AM UTC 24 |
| Peak memory | 270868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006590537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3006590537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.1400624901 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2714260100 ps |
| CPU time | 1814.67 seconds |
| Started | Aug 23 10:32:35 AM UTC 24 |
| Finished | Aug 23 11:03:07 AM UTC 24 |
| Peak memory | 302448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400624901 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.1400624901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3151900984 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 24937600 ps |
| CPU time | 30.31 seconds |
| Started | Aug 23 10:26:04 AM UTC 24 |
| Finished | Aug 23 10:26:35 AM UTC 24 |
| Peak memory | 272920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151900984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3151900984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.4224493311 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2385303100 ps |
| CPU time | 155.83 seconds |
| Started | Aug 23 10:27:45 AM UTC 24 |
| Finished | Aug 23 10:30:23 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4224493311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.4224493311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.1069403026 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 162871600 ps |
| CPU time | 14.67 seconds |
| Started | Aug 23 11:38:22 AM UTC 24 |
| Finished | Aug 23 11:38:37 AM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069403026 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.1069403026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2858799890 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14421000 ps |
| CPU time | 17.33 seconds |
| Started | Aug 23 11:38:10 AM UTC 24 |
| Finished | Aug 23 11:38:29 AM UTC 24 |
| Peak memory | 285088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858799890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2858799890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.785616140 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 10012638900 ps |
| CPU time | 103.81 seconds |
| Started | Aug 23 11:38:21 AM UTC 24 |
| Finished | Aug 23 11:40:07 AM UTC 24 |
| Peak memory | 340696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=785616140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.785616140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.4047410511 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 25756300 ps |
| CPU time | 14.51 seconds |
| Started | Aug 23 11:38:19 AM UTC 24 |
| Finished | Aug 23 11:38:35 AM UTC 24 |
| Peak memory | 269232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4047410511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.4047410511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.2964337758 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 40126422300 ps |
| CPU time | 699.98 seconds |
| Started | Aug 23 11:35:14 AM UTC 24 |
| Finished | Aug 23 11:47:01 AM UTC 24 |
| Peak memory | 277840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964337758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res et.2964337758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.116053432 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3972103300 ps |
| CPU time | 159 seconds |
| Started | Aug 23 11:37:04 AM UTC 24 |
| Finished | Aug 23 11:39:46 AM UTC 24 |
| Peak memory | 293732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116053432 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.116053432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1400296671 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 11848331200 ps |
| CPU time | 120.36 seconds |
| Started | Aug 23 11:37:05 AM UTC 24 |
| Finished | Aug 23 11:39:08 AM UTC 24 |
| Peak memory | 304252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1400296671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_intr_rd_slow_flash.1400296671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.486237210 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1009715500 ps |
| CPU time | 70.98 seconds |
| Started | Aug 23 11:35:59 AM UTC 24 |
| Finished | Aug 23 11:37:12 AM UTC 24 |
| Peak memory | 270972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486237210 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.486237210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.2500220931 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 33350300 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 11:38:15 AM UTC 24 |
| Finished | Aug 23 11:38:31 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2500220931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_lcmgr_intg.2500220931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.906690998 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 71101000 ps |
| CPU time | 146.85 seconds |
| Started | Aug 23 11:35:40 AM UTC 24 |
| Finished | Aug 23 11:38:09 AM UTC 24 |
| Peak memory | 275520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906690998 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.906690998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3796313606 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1443226800 ps |
| CPU time | 294.54 seconds |
| Started | Aug 23 11:34:42 AM UTC 24 |
| Finished | Aug 23 11:39:40 AM UTC 24 |
| Peak memory | 275132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796313606 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3796313606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.748537090 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 21033900 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 11:37:13 AM UTC 24 |
| Finished | Aug 23 11:37:29 AM UTC 24 |
| Peak memory | 275396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748537090 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.748537090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2704291895 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1474478400 ps |
| CPU time | 993.47 seconds |
| Started | Aug 23 11:34:35 AM UTC 24 |
| Finished | Aug 23 11:51:18 AM UTC 24 |
| Peak memory | 298400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704291895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2704291895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.168199545 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1074256200 ps |
| CPU time | 76.07 seconds |
| Started | Aug 23 11:36:57 AM UTC 24 |
| Finished | Aug 23 11:38:15 AM UTC 24 |
| Peak memory | 308024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=168199545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.168199545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.3698721975 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 17153262100 ps |
| CPU time | 443.16 seconds |
| Started | Aug 23 11:37:03 AM UTC 24 |
| Finished | Aug 23 11:44:31 AM UTC 24 |
| Peak memory | 322496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698721975 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.3698721975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1572587308 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 49585600 ps |
| CPU time | 154.55 seconds |
| Started | Aug 23 11:34:28 AM UTC 24 |
| Finished | Aug 23 11:37:05 AM UTC 24 |
| Peak memory | 287688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572587308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1572587308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1620702230 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3548544300 ps |
| CPU time | 150.26 seconds |
| Started | Aug 23 11:36:46 AM UTC 24 |
| Finished | Aug 23 11:39:19 AM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1620702230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.1620702230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1539192519 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 89060700 ps |
| CPU time | 14.63 seconds |
| Started | Aug 23 11:40:57 AM UTC 24 |
| Finished | Aug 23 11:41:13 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539192519 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1539192519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1256186004 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 34271500 ps |
| CPU time | 17.3 seconds |
| Started | Aug 23 11:40:39 AM UTC 24 |
| Finished | Aug 23 11:40:58 AM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256186004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1256186004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.3970906406 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 21859700 ps |
| CPU time | 22.1 seconds |
| Started | Aug 23 11:40:15 AM UTC 24 |
| Finished | Aug 23 11:40:38 AM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3970906406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ ctrl_disable.3970906406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.899023586 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 10012463500 ps |
| CPU time | 84.32 seconds |
| Started | Aug 23 11:40:42 AM UTC 24 |
| Finished | Aug 23 11:42:08 AM UTC 24 |
| Peak memory | 279316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=899023586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.899023586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1314811120 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 40128235500 ps |
| CPU time | 689.64 seconds |
| Started | Aug 23 11:38:51 AM UTC 24 |
| Finished | Aug 23 11:50:28 AM UTC 24 |
| Peak memory | 277704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314811120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res et.1314811120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1127787793 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 13265119800 ps |
| CPU time | 96.56 seconds |
| Started | Aug 23 11:38:38 AM UTC 24 |
| Finished | Aug 23 11:40:16 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127787793 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.1127787793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3279229415 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1787238700 ps |
| CPU time | 161.27 seconds |
| Started | Aug 23 11:39:46 AM UTC 24 |
| Finished | Aug 23 11:42:30 AM UTC 24 |
| Peak memory | 301928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279229415 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.3279229415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.344632146 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 16634380600 ps |
| CPU time | 115.84 seconds |
| Started | Aug 23 11:39:46 AM UTC 24 |
| Finished | Aug 23 11:41:44 AM UTC 24 |
| Peak memory | 303900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=344632146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 11.flash_ctrl_intr_rd_slow_flash.344632146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1322891523 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 8743186300 ps |
| CPU time | 56.14 seconds |
| Started | Aug 23 11:39:09 AM UTC 24 |
| Finished | Aug 23 11:40:07 AM UTC 24 |
| Peak memory | 275064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322891523 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1322891523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.808864240 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 120561400 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 11:40:41 AM UTC 24 |
| Finished | Aug 23 11:40:57 AM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=808864240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_lcmgr_intg.808864240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.1457199902 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 6029349300 ps |
| CPU time | 378.6 seconds |
| Started | Aug 23 11:39:04 AM UTC 24 |
| Finished | Aug 23 11:45:27 AM UTC 24 |
| Peak memory | 283372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1457199902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.1457199902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.2702232516 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 41355500 ps |
| CPU time | 147.53 seconds |
| Started | Aug 23 11:39:04 AM UTC 24 |
| Finished | Aug 23 11:41:34 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702232516 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.2702232516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.1434663581 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 8490992900 ps |
| CPU time | 640.81 seconds |
| Started | Aug 23 11:38:36 AM UTC 24 |
| Finished | Aug 23 11:49:23 AM UTC 24 |
| Peak memory | 278068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434663581 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1434663581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.1952045457 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 453265000 ps |
| CPU time | 20.61 seconds |
| Started | Aug 23 11:39:53 AM UTC 24 |
| Finished | Aug 23 11:40:14 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952045457 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.1952045457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1344120259 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 224809300 ps |
| CPU time | 416.31 seconds |
| Started | Aug 23 11:38:32 AM UTC 24 |
| Finished | Aug 23 11:45:33 AM UTC 24 |
| Peak memory | 289476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344120259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1344120259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3653552441 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 200835300 ps |
| CPU time | 32.22 seconds |
| Started | Aug 23 11:40:08 AM UTC 24 |
| Finished | Aug 23 11:40:41 AM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653552441 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.3653552441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.824892169 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 516956700 ps |
| CPU time | 81.72 seconds |
| Started | Aug 23 11:39:36 AM UTC 24 |
| Finished | Aug 23 11:41:00 AM UTC 24 |
| Peak memory | 301944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=824892169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.824892169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.998506754 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 5534180500 ps |
| CPU time | 386.99 seconds |
| Started | Aug 23 11:39:41 AM UTC 24 |
| Finished | Aug 23 11:46:13 AM UTC 24 |
| Peak memory | 336740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998506754 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.998506754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3657345721 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 72938800 ps |
| CPU time | 30.84 seconds |
| Started | Aug 23 11:40:08 AM UTC 24 |
| Finished | Aug 23 11:40:40 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657345721 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.3657345721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2573599807 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 41634000 ps |
| CPU time | 32.47 seconds |
| Started | Aug 23 11:40:08 AM UTC 24 |
| Finished | Aug 23 11:40:42 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2573599807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c trl_rw_evict_all_en.2573599807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2161670330 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 417626500 ps |
| CPU time | 53 seconds |
| Started | Aug 23 11:40:17 AM UTC 24 |
| Finished | Aug 23 11:41:12 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161670330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2161670330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.452282647 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 91253000 ps |
| CPU time | 79.99 seconds |
| Started | Aug 23 11:38:30 AM UTC 24 |
| Finished | Aug 23 11:39:51 AM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452282647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.452282647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.3662681085 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2459982400 ps |
| CPU time | 161.38 seconds |
| Started | Aug 23 11:39:19 AM UTC 24 |
| Finished | Aug 23 11:42:03 AM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3662681085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.3662681085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.91786100 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 100030500 ps |
| CPU time | 14.61 seconds |
| Started | Aug 23 11:44:24 AM UTC 24 |
| Finished | Aug 23 11:44:39 AM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91786100 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.91786100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.379457151 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 50438100 ps |
| CPU time | 17.24 seconds |
| Started | Aug 23 11:44:04 AM UTC 24 |
| Finished | Aug 23 11:44:23 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379457151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.379457151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.703615049 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 10012071600 ps |
| CPU time | 119.37 seconds |
| Started | Aug 23 11:44:24 AM UTC 24 |
| Finished | Aug 23 11:46:25 AM UTC 24 |
| Peak memory | 373784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=703615049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.703615049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.4230959588 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 80140505300 ps |
| CPU time | 713.4 seconds |
| Started | Aug 23 11:41:13 AM UTC 24 |
| Finished | Aug 23 11:53:14 AM UTC 24 |
| Peak memory | 275648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230959588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res et.4230959588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3640682490 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2491118800 ps |
| CPU time | 132.27 seconds |
| Started | Aug 23 11:41:01 AM UTC 24 |
| Finished | Aug 23 11:43:15 AM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640682490 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.3640682490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3478386241 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2037051300 ps |
| CPU time | 120.4 seconds |
| Started | Aug 23 11:42:32 AM UTC 24 |
| Finished | Aug 23 11:44:34 AM UTC 24 |
| Peak memory | 306080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478386241 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.3478386241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1491147472 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 17118220500 ps |
| CPU time | 180.81 seconds |
| Started | Aug 23 11:42:49 AM UTC 24 |
| Finished | Aug 23 11:45:52 AM UTC 24 |
| Peak memory | 293660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1491147472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_intr_rd_slow_flash.1491147472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.1227010506 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4181569100 ps |
| CPU time | 60.9 seconds |
| Started | Aug 23 11:41:45 AM UTC 24 |
| Finished | Aug 23 11:42:48 AM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227010506 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1227010506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.2296242660 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 24866400 ps |
| CPU time | 14.36 seconds |
| Started | Aug 23 11:44:07 AM UTC 24 |
| Finished | Aug 23 11:44:23 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2296242660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_lcmgr_intg.2296242660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.3670953067 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 21506175600 ps |
| CPU time | 211.13 seconds |
| Started | Aug 23 11:41:35 AM UTC 24 |
| Finished | Aug 23 11:45:09 AM UTC 24 |
| Peak memory | 283380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3670953067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3670953067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1881636011 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 42867500 ps |
| CPU time | 146.44 seconds |
| Started | Aug 23 11:41:14 AM UTC 24 |
| Finished | Aug 23 11:43:43 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881636011 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.1881636011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.371459068 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1406816900 ps |
| CPU time | 305.66 seconds |
| Started | Aug 23 11:41:01 AM UTC 24 |
| Finished | Aug 23 11:46:10 AM UTC 24 |
| Peak memory | 273088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371459068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.371459068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3376872291 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4516761700 ps |
| CPU time | 638.05 seconds |
| Started | Aug 23 11:40:59 AM UTC 24 |
| Finished | Aug 23 11:51:43 AM UTC 24 |
| Peak memory | 296360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376872291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3376872291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2339503105 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 338883200 ps |
| CPU time | 35.33 seconds |
| Started | Aug 23 11:43:33 AM UTC 24 |
| Finished | Aug 23 11:44:10 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339503105 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2339503105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2904318858 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1068217100 ps |
| CPU time | 78.94 seconds |
| Started | Aug 23 11:42:07 AM UTC 24 |
| Finished | Aug 23 11:43:28 AM UTC 24 |
| Peak memory | 303992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2904318858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.2904318858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.4013453904 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3838935700 ps |
| CPU time | 361.82 seconds |
| Started | Aug 23 11:42:09 AM UTC 24 |
| Finished | Aug 23 11:48:16 AM UTC 24 |
| Peak memory | 330700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013453904 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.4013453904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.2083613676 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 31278300 ps |
| CPU time | 31.12 seconds |
| Started | Aug 23 11:43:29 AM UTC 24 |
| Finished | Aug 23 11:44:01 AM UTC 24 |
| Peak memory | 285888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083613676 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.2083613676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2598939895 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 43290700 ps |
| CPU time | 30.34 seconds |
| Started | Aug 23 11:43:32 AM UTC 24 |
| Finished | Aug 23 11:44:04 AM UTC 24 |
| Peak memory | 281540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2598939895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c trl_rw_evict_all_en.2598939895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3662271231 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 39439600 ps |
| CPU time | 151.76 seconds |
| Started | Aug 23 11:40:59 AM UTC 24 |
| Finished | Aug 23 11:43:33 AM UTC 24 |
| Peak memory | 287624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662271231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.3662271231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.797495744 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2030973300 ps |
| CPU time | 136.61 seconds |
| Started | Aug 23 11:42:04 AM UTC 24 |
| Finished | Aug 23 11:44:23 AM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =797495744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.797495744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.1469660017 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 82088000 ps |
| CPU time | 14.59 seconds |
| Started | Aug 23 11:47:48 AM UTC 24 |
| Finished | Aug 23 11:48:04 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469660017 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.1469660017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.3406756712 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 22812400 ps |
| CPU time | 16.99 seconds |
| Started | Aug 23 11:47:38 AM UTC 24 |
| Finished | Aug 23 11:47:56 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406756712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3406756712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1703019119 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 70444100 ps |
| CPU time | 22.92 seconds |
| Started | Aug 23 11:47:08 AM UTC 24 |
| Finished | Aug 23 11:47:32 AM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1703019119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ ctrl_disable.1703019119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.4057290818 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 25242700 ps |
| CPU time | 14.52 seconds |
| Started | Aug 23 11:47:44 AM UTC 24 |
| Finished | Aug 23 11:48:00 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4057290818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.4057290818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1706835580 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 160184892400 ps |
| CPU time | 711.35 seconds |
| Started | Aug 23 11:44:40 AM UTC 24 |
| Finished | Aug 23 11:56:39 AM UTC 24 |
| Peak memory | 277776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706835580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res et.1706835580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.4128911278 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2669658900 ps |
| CPU time | 84.37 seconds |
| Started | Aug 23 11:44:35 AM UTC 24 |
| Finished | Aug 23 11:46:01 AM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128911278 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.4128911278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.3198943840 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3206746400 ps |
| CPU time | 178.43 seconds |
| Started | Aug 23 11:46:11 AM UTC 24 |
| Finished | Aug 23 11:49:12 AM UTC 24 |
| Peak memory | 293864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198943840 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.3198943840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.319569957 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 24818902900 ps |
| CPU time | 223.3 seconds |
| Started | Aug 23 11:46:14 AM UTC 24 |
| Finished | Aug 23 11:50:00 AM UTC 24 |
| Peak memory | 293692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=319569957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 13.flash_ctrl_intr_rd_slow_flash.319569957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.4211677587 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 132720500 ps |
| CPU time | 14.31 seconds |
| Started | Aug 23 11:47:40 AM UTC 24 |
| Finished | Aug 23 11:47:55 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4211677587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.4211677587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.1519419492 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 22630839800 ps |
| CPU time | 188.12 seconds |
| Started | Aug 23 11:45:10 AM UTC 24 |
| Finished | Aug 23 11:48:21 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1519419492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.1519419492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.2463934583 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 130524600 ps |
| CPU time | 151.63 seconds |
| Started | Aug 23 11:45:09 AM UTC 24 |
| Finished | Aug 23 11:47:43 AM UTC 24 |
| Peak memory | 270892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463934583 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.2463934583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.227694873 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 60067000 ps |
| CPU time | 255.34 seconds |
| Started | Aug 23 11:44:32 AM UTC 24 |
| Finished | Aug 23 11:48:50 AM UTC 24 |
| Peak memory | 275132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227694873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.227694873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1178233823 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2782597900 ps |
| CPU time | 144.47 seconds |
| Started | Aug 23 11:46:26 AM UTC 24 |
| Finished | Aug 23 11:48:53 AM UTC 24 |
| Peak memory | 275328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178233823 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.1178233823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.1399005679 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 45559800 ps |
| CPU time | 210.13 seconds |
| Started | Aug 23 11:44:27 AM UTC 24 |
| Finished | Aug 23 11:48:00 AM UTC 24 |
| Peak memory | 291520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399005679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1399005679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.1833885196 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 262479700 ps |
| CPU time | 33.55 seconds |
| Started | Aug 23 11:47:04 AM UTC 24 |
| Finished | Aug 23 11:47:39 AM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833885196 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.1833885196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.2930573677 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1593801300 ps |
| CPU time | 72.4 seconds |
| Started | Aug 23 11:45:53 AM UTC 24 |
| Finished | Aug 23 11:47:07 AM UTC 24 |
| Peak memory | 292040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2930573677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.2930573677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2254886999 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 31661500 ps |
| CPU time | 32.81 seconds |
| Started | Aug 23 11:47:02 AM UTC 24 |
| Finished | Aug 23 11:47:37 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2254886999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c trl_rw_evict_all_en.2254886999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2689203325 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 13128168500 ps |
| CPU time | 70.93 seconds |
| Started | Aug 23 11:47:33 AM UTC 24 |
| Finished | Aug 23 11:48:45 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689203325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2689203325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1678172663 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 37912500 ps |
| CPU time | 200.37 seconds |
| Started | Aug 23 11:44:24 AM UTC 24 |
| Finished | Aug 23 11:47:47 AM UTC 24 |
| Peak memory | 289476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678172663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1678172663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.2154978941 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3777196000 ps |
| CPU time | 126.08 seconds |
| Started | Aug 23 11:45:34 AM UTC 24 |
| Finished | Aug 23 11:47:43 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2154978941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.2154978941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.552387692 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 62034300 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 11:50:27 AM UTC 24 |
| Finished | Aug 23 11:50:43 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552387692 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.552387692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.989090405 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 27201500 ps |
| CPU time | 17.25 seconds |
| Started | Aug 23 11:50:03 AM UTC 24 |
| Finished | Aug 23 11:50:21 AM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989090405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.989090405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.4018429579 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 15808100 ps |
| CPU time | 22.19 seconds |
| Started | Aug 23 11:50:00 AM UTC 24 |
| Finished | Aug 23 11:50:23 AM UTC 24 |
| Peak memory | 285836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4018429579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.4018429579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3664315595 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 10012619100 ps |
| CPU time | 116.2 seconds |
| Started | Aug 23 11:50:24 AM UTC 24 |
| Finished | Aug 23 11:52:22 AM UTC 24 |
| Peak memory | 369456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3664315595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3664315595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.618924029 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 15669400 ps |
| CPU time | 14.4 seconds |
| Started | Aug 23 11:50:22 AM UTC 24 |
| Finished | Aug 23 11:50:37 AM UTC 24 |
| Peak memory | 275488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=618924029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.flash_ctrl_hw_read_seed_err.618924029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.886666609 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 270248650700 ps |
| CPU time | 760.73 seconds |
| Started | Aug 23 11:48:04 AM UTC 24 |
| Finished | Aug 23 12:00:53 PM UTC 24 |
| Peak memory | 277760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886666609 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_reset.886666609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.3947829537 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2072437700 ps |
| CPU time | 115.82 seconds |
| Started | Aug 23 11:48:00 AM UTC 24 |
| Finished | Aug 23 11:49:58 AM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947829537 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.3947829537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.3396922808 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4706669500 ps |
| CPU time | 127.01 seconds |
| Started | Aug 23 11:49:13 AM UTC 24 |
| Finished | Aug 23 11:51:22 AM UTC 24 |
| Peak memory | 306120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396922808 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.3396922808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1792145904 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5671255500 ps |
| CPU time | 115.74 seconds |
| Started | Aug 23 11:49:24 AM UTC 24 |
| Finished | Aug 23 11:51:22 AM UTC 24 |
| Peak memory | 304224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1792145904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.1792145904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.2496767425 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1630551600 ps |
| CPU time | 57.77 seconds |
| Started | Aug 23 11:48:46 AM UTC 24 |
| Finished | Aug 23 11:49:45 AM UTC 24 |
| Peak memory | 270972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496767425 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2496767425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.426959967 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 201938300 ps |
| CPU time | 14.24 seconds |
| Started | Aug 23 11:50:11 AM UTC 24 |
| Finished | Aug 23 11:50:26 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=426959967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_lcmgr_intg.426959967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.3262990885 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 11801723900 ps |
| CPU time | 233.45 seconds |
| Started | Aug 23 11:48:23 AM UTC 24 |
| Finished | Aug 23 11:52:19 AM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3262990885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.3262990885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1514166124 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 114062900 ps |
| CPU time | 145.59 seconds |
| Started | Aug 23 11:48:16 AM UTC 24 |
| Finished | Aug 23 11:50:44 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514166124 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.1514166124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.4216607563 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 737615600 ps |
| CPU time | 301.38 seconds |
| Started | Aug 23 11:48:00 AM UTC 24 |
| Finished | Aug 23 11:53:05 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216607563 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.4216607563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3463941222 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 62055200 ps |
| CPU time | 14.47 seconds |
| Started | Aug 23 11:49:46 AM UTC 24 |
| Finished | Aug 23 11:50:02 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463941222 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.3463941222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.2931267655 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 150958800 ps |
| CPU time | 112.22 seconds |
| Started | Aug 23 11:47:57 AM UTC 24 |
| Finished | Aug 23 11:49:51 AM UTC 24 |
| Peak memory | 291780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931267655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2931267655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.4271040713 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 209451100 ps |
| CPU time | 35.26 seconds |
| Started | Aug 23 11:49:59 AM UTC 24 |
| Finished | Aug 23 11:50:35 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271040713 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.4271040713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.307859787 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 474232800 ps |
| CPU time | 74.02 seconds |
| Started | Aug 23 11:48:54 AM UTC 24 |
| Finished | Aug 23 11:50:10 AM UTC 24 |
| Peak memory | 291644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=307859787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.307859787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.3252018250 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 59002299600 ps |
| CPU time | 417.63 seconds |
| Started | Aug 23 11:49:05 AM UTC 24 |
| Finished | Aug 23 11:56:08 AM UTC 24 |
| Peak memory | 321472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252018250 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.3252018250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1064772267 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 47086100 ps |
| CPU time | 32.88 seconds |
| Started | Aug 23 11:49:59 AM UTC 24 |
| Finished | Aug 23 11:50:33 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1064772267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.1064772267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.3825637847 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 7101976000 ps |
| CPU time | 62.63 seconds |
| Started | Aug 23 11:50:01 AM UTC 24 |
| Finished | Aug 23 11:51:05 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825637847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3825637847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3426910223 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 48777900 ps |
| CPU time | 180.28 seconds |
| Started | Aug 23 11:47:56 AM UTC 24 |
| Finished | Aug 23 11:50:59 AM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426910223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3426910223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.2495461288 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1859554400 ps |
| CPU time | 124.26 seconds |
| Started | Aug 23 11:48:51 AM UTC 24 |
| Finished | Aug 23 11:50:57 AM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2495461288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.2495461288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3704589558 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 58149300 ps |
| CPU time | 14.59 seconds |
| Started | Aug 23 11:52:20 AM UTC 24 |
| Finished | Aug 23 11:52:36 AM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704589558 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.3704589558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.3449747638 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 14559500 ps |
| CPU time | 14.39 seconds |
| Started | Aug 23 11:51:58 AM UTC 24 |
| Finished | Aug 23 11:52:13 AM UTC 24 |
| Peak memory | 295396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449747638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3449747638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3557863113 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 10012154200 ps |
| CPU time | 122.28 seconds |
| Started | Aug 23 11:52:18 AM UTC 24 |
| Finished | Aug 23 11:54:22 AM UTC 24 |
| Peak memory | 383764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3557863113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3557863113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.2396900823 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 15516700 ps |
| CPU time | 14.59 seconds |
| Started | Aug 23 11:52:14 AM UTC 24 |
| Finished | Aug 23 11:52:30 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2396900823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2396900823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.2085436745 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 40121918300 ps |
| CPU time | 667.79 seconds |
| Started | Aug 23 11:50:38 AM UTC 24 |
| Finished | Aug 23 12:01:53 PM UTC 24 |
| Peak memory | 277704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085436745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.2085436745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.416577547 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 14773262800 ps |
| CPU time | 173.47 seconds |
| Started | Aug 23 11:50:36 AM UTC 24 |
| Finished | Aug 23 11:53:32 AM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416577547 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.416577547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.1189963311 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3330206500 ps |
| CPU time | 203.67 seconds |
| Started | Aug 23 11:51:19 AM UTC 24 |
| Finished | Aug 23 11:54:46 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189963311 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.1189963311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.161923456 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 12687510200 ps |
| CPU time | 239.31 seconds |
| Started | Aug 23 11:51:23 AM UTC 24 |
| Finished | Aug 23 11:55:26 AM UTC 24 |
| Peak memory | 293920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=161923456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 15.flash_ctrl_intr_rd_slow_flash.161923456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1825391663 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1660796100 ps |
| CPU time | 57.08 seconds |
| Started | Aug 23 11:50:58 AM UTC 24 |
| Finished | Aug 23 11:51:56 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825391663 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1825391663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.3494236831 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 25945700 ps |
| CPU time | 15.39 seconds |
| Started | Aug 23 11:52:13 AM UTC 24 |
| Finished | Aug 23 11:52:29 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3494236831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_lcmgr_intg.3494236831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1756059990 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 22703722000 ps |
| CPU time | 258.89 seconds |
| Started | Aug 23 11:50:45 AM UTC 24 |
| Finished | Aug 23 11:55:07 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1756059990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1756059990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.763770060 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 99736600 ps |
| CPU time | 119.06 seconds |
| Started | Aug 23 11:50:44 AM UTC 24 |
| Finished | Aug 23 11:52:45 AM UTC 24 |
| Peak memory | 270876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763770060 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.763770060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.779983509 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 74626600 ps |
| CPU time | 115.8 seconds |
| Started | Aug 23 11:50:33 AM UTC 24 |
| Finished | Aug 23 11:52:31 AM UTC 24 |
| Peak memory | 273044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779983509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.779983509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.4133053701 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 84526000 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 11:51:23 AM UTC 24 |
| Finished | Aug 23 11:51:39 AM UTC 24 |
| Peak memory | 275520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133053701 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.4133053701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.4018963792 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 93874800 ps |
| CPU time | 381.31 seconds |
| Started | Aug 23 11:50:28 AM UTC 24 |
| Finished | Aug 23 11:56:54 AM UTC 24 |
| Peak memory | 291616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018963792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.4018963792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.2147409053 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 65260400 ps |
| CPU time | 35.59 seconds |
| Started | Aug 23 11:51:44 AM UTC 24 |
| Finished | Aug 23 11:52:22 AM UTC 24 |
| Peak memory | 283576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147409053 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.2147409053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.3472296803 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1034492700 ps |
| CPU time | 82.63 seconds |
| Started | Aug 23 11:51:06 AM UTC 24 |
| Finished | Aug 23 11:52:30 AM UTC 24 |
| Peak memory | 291756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3472296803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.3472296803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1189553168 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4179396600 ps |
| CPU time | 426.31 seconds |
| Started | Aug 23 11:51:19 AM UTC 24 |
| Finished | Aug 23 11:58:30 AM UTC 24 |
| Peak memory | 324992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189553168 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.1189553168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.1983246702 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 134108400 ps |
| CPU time | 31.31 seconds |
| Started | Aug 23 11:51:24 AM UTC 24 |
| Finished | Aug 23 11:51:57 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983246702 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.1983246702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.3112560972 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 52455600 ps |
| CPU time | 35.17 seconds |
| Started | Aug 23 11:51:40 AM UTC 24 |
| Finished | Aug 23 11:52:17 AM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3112560972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_rw_evict_all_en.3112560972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.1205661514 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4699398000 ps |
| CPU time | 66.11 seconds |
| Started | Aug 23 11:51:58 AM UTC 24 |
| Finished | Aug 23 11:53:05 AM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205661514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1205661514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2108933900 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 87636300 ps |
| CPU time | 54.95 seconds |
| Started | Aug 23 11:50:27 AM UTC 24 |
| Finished | Aug 23 11:51:24 AM UTC 24 |
| Peak memory | 283336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108933900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2108933900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.4040419953 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 7611777600 ps |
| CPU time | 92.77 seconds |
| Started | Aug 23 11:51:00 AM UTC 24 |
| Finished | Aug 23 11:52:34 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4040419953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.4040419953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.4237526124 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 73422700 ps |
| CPU time | 14.47 seconds |
| Started | Aug 23 11:54:56 AM UTC 24 |
| Finished | Aug 23 11:55:12 AM UTC 24 |
| Peak memory | 269320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237526124 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.4237526124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.3063029039 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 15656700 ps |
| CPU time | 17.29 seconds |
| Started | Aug 23 11:54:33 AM UTC 24 |
| Finished | Aug 23 11:54:51 AM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063029039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3063029039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2350307241 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 47825900 ps |
| CPU time | 23.06 seconds |
| Started | Aug 23 11:54:31 AM UTC 24 |
| Finished | Aug 23 11:54:55 AM UTC 24 |
| Peak memory | 285480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2350307241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.2350307241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3570495605 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 10066608700 ps |
| CPU time | 43.04 seconds |
| Started | Aug 23 11:54:52 AM UTC 24 |
| Finished | Aug 23 11:55:36 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3570495605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3570495605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3956802330 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 18635000 ps |
| CPU time | 14.39 seconds |
| Started | Aug 23 11:54:47 AM UTC 24 |
| Finished | Aug 23 11:55:03 AM UTC 24 |
| Peak memory | 269364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3956802330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3956802330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2121695800 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 50130130300 ps |
| CPU time | 713.66 seconds |
| Started | Aug 23 11:52:31 AM UTC 24 |
| Finished | Aug 23 12:04:33 PM UTC 24 |
| Peak memory | 277704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121695800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res et.2121695800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.490641583 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1580406300 ps |
| CPU time | 51.31 seconds |
| Started | Aug 23 11:52:30 AM UTC 24 |
| Finished | Aug 23 11:53:23 AM UTC 24 |
| Peak memory | 272976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490641583 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.490641583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.2509933475 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 637404500 ps |
| CPU time | 99.84 seconds |
| Started | Aug 23 11:53:15 AM UTC 24 |
| Finished | Aug 23 11:54:57 AM UTC 24 |
| Peak memory | 306112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509933475 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.2509933475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3647581923 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 11872359400 ps |
| CPU time | 115.19 seconds |
| Started | Aug 23 11:53:24 AM UTC 24 |
| Finished | Aug 23 11:55:21 AM UTC 24 |
| Peak memory | 303896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3647581923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_intr_rd_slow_flash.3647581923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3466933443 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1636316100 ps |
| CPU time | 58.05 seconds |
| Started | Aug 23 11:52:37 AM UTC 24 |
| Finished | Aug 23 11:53:36 AM UTC 24 |
| Peak memory | 270964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466933443 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3466933443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.3952276151 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 90841600 ps |
| CPU time | 14.62 seconds |
| Started | Aug 23 11:54:46 AM UTC 24 |
| Finished | Aug 23 11:55:02 AM UTC 24 |
| Peak memory | 271132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3952276151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.3952276151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.4095989546 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 19945513800 ps |
| CPU time | 579.42 seconds |
| Started | Aug 23 11:52:36 AM UTC 24 |
| Finished | Aug 23 12:02:21 PM UTC 24 |
| Peak memory | 284488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4095989546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.4095989546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.3337224246 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 42047600 ps |
| CPU time | 146.59 seconds |
| Started | Aug 23 11:52:32 AM UTC 24 |
| Finished | Aug 23 11:55:00 AM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337224246 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.3337224246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.630578102 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 105407000 ps |
| CPU time | 119.85 seconds |
| Started | Aug 23 11:52:30 AM UTC 24 |
| Finished | Aug 23 11:54:32 AM UTC 24 |
| Peak memory | 273344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630578102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.630578102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.189966361 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 8161490300 ps |
| CPU time | 142.32 seconds |
| Started | Aug 23 11:53:33 AM UTC 24 |
| Finished | Aug 23 11:55:58 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189966361 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.189966361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.4045848571 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1539309300 ps |
| CPU time | 680.85 seconds |
| Started | Aug 23 11:52:23 AM UTC 24 |
| Finished | Aug 23 12:03:51 PM UTC 24 |
| Peak memory | 296356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045848571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.4045848571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.4271185458 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 107556100 ps |
| CPU time | 33.58 seconds |
| Started | Aug 23 11:54:23 AM UTC 24 |
| Finished | Aug 23 11:54:58 AM UTC 24 |
| Peak memory | 283840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271185458 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.4271185458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.2709520696 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4178420000 ps |
| CPU time | 83.29 seconds |
| Started | Aug 23 11:53:06 AM UTC 24 |
| Finished | Aug 23 11:54:31 AM UTC 24 |
| Peak memory | 291736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2709520696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.2709520696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.2121183161 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3911858600 ps |
| CPU time | 368.06 seconds |
| Started | Aug 23 11:53:06 AM UTC 24 |
| Finished | Aug 23 11:59:18 AM UTC 24 |
| Peak memory | 320460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121183161 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.2121183161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.2697935413 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 28501700 ps |
| CPU time | 32.78 seconds |
| Started | Aug 23 11:53:37 AM UTC 24 |
| Finished | Aug 23 11:54:12 AM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697935413 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.2697935413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.218221950 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2246705000 ps |
| CPU time | 57.01 seconds |
| Started | Aug 23 11:54:32 AM UTC 24 |
| Finished | Aug 23 11:55:30 AM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218221950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.218221950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.1307363810 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 100541700 ps |
| CPU time | 125.84 seconds |
| Started | Aug 23 11:52:22 AM UTC 24 |
| Finished | Aug 23 11:54:30 AM UTC 24 |
| Peak memory | 287384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307363810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1307363810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.3667672359 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2962421700 ps |
| CPU time | 173.06 seconds |
| Started | Aug 23 11:52:46 AM UTC 24 |
| Finished | Aug 23 11:55:41 AM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3667672359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.3667672359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.737131775 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 71708200 ps |
| CPU time | 14.47 seconds |
| Started | Aug 23 11:56:49 AM UTC 24 |
| Finished | Aug 23 11:57:04 AM UTC 24 |
| Peak memory | 269292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737131775 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.737131775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.4241235318 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 14672300 ps |
| CPU time | 14.15 seconds |
| Started | Aug 23 11:56:32 AM UTC 24 |
| Finished | Aug 23 11:56:48 AM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241235318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4241235318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1947008998 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 17443000 ps |
| CPU time | 23.16 seconds |
| Started | Aug 23 11:56:14 AM UTC 24 |
| Finished | Aug 23 11:56:38 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1947008998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.1947008998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2822779948 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 10088695200 ps |
| CPU time | 37.58 seconds |
| Started | Aug 23 11:56:42 AM UTC 24 |
| Finished | Aug 23 11:57:22 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2822779948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2822779948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.1081483875 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 57975200 ps |
| CPU time | 14.95 seconds |
| Started | Aug 23 11:56:39 AM UTC 24 |
| Finished | Aug 23 11:56:55 AM UTC 24 |
| Peak memory | 275232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1081483875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1081483875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.2837560694 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 80135525400 ps |
| CPU time | 695.83 seconds |
| Started | Aug 23 11:55:02 AM UTC 24 |
| Finished | Aug 23 12:06:46 PM UTC 24 |
| Peak memory | 277768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837560694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res et.2837560694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.701771971 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 17075575100 ps |
| CPU time | 81.71 seconds |
| Started | Aug 23 11:55:01 AM UTC 24 |
| Finished | Aug 23 11:56:25 AM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701771971 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.701771971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1023836339 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2625030800 ps |
| CPU time | 114.44 seconds |
| Started | Aug 23 11:55:37 AM UTC 24 |
| Finished | Aug 23 11:57:34 AM UTC 24 |
| Peak memory | 302248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023836339 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1023836339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2593682748 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5533062100 ps |
| CPU time | 106.48 seconds |
| Started | Aug 23 11:55:42 AM UTC 24 |
| Finished | Aug 23 11:57:31 AM UTC 24 |
| Peak memory | 303900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2593682748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_intr_rd_slow_flash.2593682748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.2696855406 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 13540334400 ps |
| CPU time | 58.42 seconds |
| Started | Aug 23 11:55:13 AM UTC 24 |
| Finished | Aug 23 11:56:13 AM UTC 24 |
| Peak memory | 275064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696855406 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2696855406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1570090787 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 15067200 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 11:56:39 AM UTC 24 |
| Finished | Aug 23 11:56:55 AM UTC 24 |
| Peak memory | 275052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1570090787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_lcmgr_intg.1570090787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.1615708332 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3921916800 ps |
| CPU time | 118.14 seconds |
| Started | Aug 23 11:55:08 AM UTC 24 |
| Finished | Aug 23 11:57:08 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1615708332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.1615708332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.3764951234 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 67148100 ps |
| CPU time | 146.36 seconds |
| Started | Aug 23 11:55:03 AM UTC 24 |
| Finished | Aug 23 11:57:33 AM UTC 24 |
| Peak memory | 271144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764951234 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.3764951234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.2459217800 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1480209400 ps |
| CPU time | 523.79 seconds |
| Started | Aug 23 11:55:00 AM UTC 24 |
| Finished | Aug 23 12:03:50 PM UTC 24 |
| Peak memory | 277872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459217800 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2459217800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.5748665 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 8700680100 ps |
| CPU time | 130.22 seconds |
| Started | Aug 23 11:55:54 AM UTC 24 |
| Finished | Aug 23 11:58:07 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5748665 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.5748665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.3947824129 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 80544600 ps |
| CPU time | 266.05 seconds |
| Started | Aug 23 11:54:58 AM UTC 24 |
| Finished | Aug 23 11:59:28 AM UTC 24 |
| Peak memory | 285636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947824129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3947824129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1607376501 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 73614100 ps |
| CPU time | 35.72 seconds |
| Started | Aug 23 11:56:12 AM UTC 24 |
| Finished | Aug 23 11:56:49 AM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607376501 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.1607376501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.1828462274 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5680840100 ps |
| CPU time | 91.32 seconds |
| Started | Aug 23 11:55:26 AM UTC 24 |
| Finished | Aug 23 11:57:00 AM UTC 24 |
| Peak memory | 292040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1828462274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.1828462274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.688550336 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3084353600 ps |
| CPU time | 311.87 seconds |
| Started | Aug 23 11:55:31 AM UTC 24 |
| Finished | Aug 23 12:00:47 PM UTC 24 |
| Peak memory | 333060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688550336 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.688550336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.2262733711 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 59794600 ps |
| CPU time | 31.33 seconds |
| Started | Aug 23 11:56:09 AM UTC 24 |
| Finished | Aug 23 11:56:42 AM UTC 24 |
| Peak memory | 288004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2262733711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c trl_rw_evict_all_en.2262733711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.686474032 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 20367400 ps |
| CPU time | 54.51 seconds |
| Started | Aug 23 11:54:57 AM UTC 24 |
| Finished | Aug 23 11:55:54 AM UTC 24 |
| Peak memory | 283332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686474032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.686474032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.1269393304 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3924555600 ps |
| CPU time | 112.75 seconds |
| Started | Aug 23 11:55:22 AM UTC 24 |
| Finished | Aug 23 11:57:17 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1269393304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.1269393304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.480529365 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 69432000 ps |
| CPU time | 14.78 seconds |
| Started | Aug 23 11:59:08 AM UTC 24 |
| Finished | Aug 23 11:59:27 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480529365 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.480529365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.1889333344 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 27215200 ps |
| CPU time | 17.51 seconds |
| Started | Aug 23 11:58:45 AM UTC 24 |
| Finished | Aug 23 11:59:04 AM UTC 24 |
| Peak memory | 295328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889333344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1889333344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.2383637448 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 10475600 ps |
| CPU time | 22.22 seconds |
| Started | Aug 23 11:58:35 AM UTC 24 |
| Finished | Aug 23 11:58:58 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2383637448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ ctrl_disable.2383637448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1218067798 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 10035258200 ps |
| CPU time | 92.19 seconds |
| Started | Aug 23 11:59:04 AM UTC 24 |
| Finished | Aug 23 12:00:42 PM UTC 24 |
| Peak memory | 285444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1218067798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1218067798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.804755125 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 27066200 ps |
| CPU time | 14.39 seconds |
| Started | Aug 23 11:58:59 AM UTC 24 |
| Finished | Aug 23 11:59:17 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=804755125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.flash_ctrl_hw_read_seed_err.804755125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.687235173 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 70133794900 ps |
| CPU time | 669.86 seconds |
| Started | Aug 23 11:57:00 AM UTC 24 |
| Finished | Aug 23 12:08:17 PM UTC 24 |
| Peak memory | 277704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687235173 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_reset.687235173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.1004446306 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 7436552100 ps |
| CPU time | 131.21 seconds |
| Started | Aug 23 11:56:56 AM UTC 24 |
| Finished | Aug 23 11:59:09 AM UTC 24 |
| Peak memory | 272976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004446306 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.1004446306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.321669274 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1164856800 ps |
| CPU time | 112.03 seconds |
| Started | Aug 23 11:57:34 AM UTC 24 |
| Finished | Aug 23 11:59:28 AM UTC 24 |
| Peak memory | 302276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321669274 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.321669274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3760402023 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5973107000 ps |
| CPU time | 116.58 seconds |
| Started | Aug 23 11:57:35 AM UTC 24 |
| Finished | Aug 23 11:59:34 AM UTC 24 |
| Peak memory | 303904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3760402023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_intr_rd_slow_flash.3760402023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.1232202187 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1978924400 ps |
| CPU time | 74.06 seconds |
| Started | Aug 23 11:57:18 AM UTC 24 |
| Finished | Aug 23 11:58:33 AM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232202187 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1232202187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.835194647 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 46205100 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 11:58:54 AM UTC 24 |
| Finished | Aug 23 11:59:10 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=835194647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas h_ctrl_lcmgr_intg.835194647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.1747145009 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 40895890300 ps |
| CPU time | 235.58 seconds |
| Started | Aug 23 11:57:10 AM UTC 24 |
| Finished | Aug 23 12:01:10 PM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1747145009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1747145009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.1475699872 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 70771300 ps |
| CPU time | 145.34 seconds |
| Started | Aug 23 11:57:05 AM UTC 24 |
| Finished | Aug 23 11:59:33 AM UTC 24 |
| Peak memory | 275436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475699872 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.1475699872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.3206865342 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 573080900 ps |
| CPU time | 164.3 seconds |
| Started | Aug 23 11:56:56 AM UTC 24 |
| Finished | Aug 23 11:59:43 AM UTC 24 |
| Peak memory | 273084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206865342 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3206865342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.2620532250 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 61663400 ps |
| CPU time | 14.49 seconds |
| Started | Aug 23 11:57:53 AM UTC 24 |
| Finished | Aug 23 11:58:09 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620532250 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.2620532250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.469906912 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 18001500 ps |
| CPU time | 56.09 seconds |
| Started | Aug 23 11:56:55 AM UTC 24 |
| Finished | Aug 23 11:57:52 AM UTC 24 |
| Peak memory | 283588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469906912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.469906912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1099303425 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 228286500 ps |
| CPU time | 33.72 seconds |
| Started | Aug 23 11:58:32 AM UTC 24 |
| Finished | Aug 23 11:59:08 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099303425 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.1099303425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.1676972096 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 482761300 ps |
| CPU time | 79.96 seconds |
| Started | Aug 23 11:57:32 AM UTC 24 |
| Finished | Aug 23 11:58:54 AM UTC 24 |
| Peak memory | 291720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1676972096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.1676972096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.966594186 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 4091421800 ps |
| CPU time | 392.75 seconds |
| Started | Aug 23 11:57:33 AM UTC 24 |
| Finished | Aug 23 12:04:10 PM UTC 24 |
| Peak memory | 330664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966594186 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.966594186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.3130536775 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 72353800 ps |
| CPU time | 34.84 seconds |
| Started | Aug 23 11:58:07 AM UTC 24 |
| Finished | Aug 23 11:58:44 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130536775 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.3130536775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.746075991 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 172231800 ps |
| CPU time | 32.5 seconds |
| Started | Aug 23 11:58:09 AM UTC 24 |
| Finished | Aug 23 11:58:43 AM UTC 24 |
| Peak memory | 288000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=746075991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ct rl_rw_evict_all_en.746075991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.3172715420 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3944808600 ps |
| CPU time | 64.06 seconds |
| Started | Aug 23 11:58:44 AM UTC 24 |
| Finished | Aug 23 11:59:50 AM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172715420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3172715420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2518650796 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 46207400 ps |
| CPU time | 155.45 seconds |
| Started | Aug 23 11:56:50 AM UTC 24 |
| Finished | Aug 23 11:59:28 AM UTC 24 |
| Peak memory | 289608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518650796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2518650796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.1254406583 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 9592440200 ps |
| CPU time | 154.66 seconds |
| Started | Aug 23 11:57:23 AM UTC 24 |
| Finished | Aug 23 12:00:01 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1254406583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.1254406583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.492533581 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 27607700 ps |
| CPU time | 14.43 seconds |
| Started | Aug 23 12:01:04 PM UTC 24 |
| Finished | Aug 23 12:01:20 PM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492533581 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.492533581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.1485776965 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 16768700 ps |
| CPU time | 17.39 seconds |
| Started | Aug 23 12:00:48 PM UTC 24 |
| Finished | Aug 23 12:01:06 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485776965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1485776965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.4240497649 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 18788000 ps |
| CPU time | 23.33 seconds |
| Started | Aug 23 12:00:43 PM UTC 24 |
| Finished | Aug 23 12:01:09 PM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4240497649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ ctrl_disable.4240497649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2349607411 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 10018152800 ps |
| CPU time | 76.29 seconds |
| Started | Aug 23 12:00:59 PM UTC 24 |
| Finished | Aug 23 12:02:17 PM UTC 24 |
| Peak memory | 330544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2349607411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2349607411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3427271128 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 15664800 ps |
| CPU time | 14.21 seconds |
| Started | Aug 23 12:00:56 PM UTC 24 |
| Finished | Aug 23 12:01:12 PM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3427271128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3427271128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3357782718 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 160175682500 ps |
| CPU time | 766.81 seconds |
| Started | Aug 23 11:59:28 AM UTC 24 |
| Finished | Aug 23 12:12:23 PM UTC 24 |
| Peak memory | 277776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357782718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res et.3357782718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.2910220517 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2336484700 ps |
| CPU time | 39.45 seconds |
| Started | Aug 23 11:59:19 AM UTC 24 |
| Finished | Aug 23 12:00:00 PM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910220517 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.2910220517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.2320111476 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1443235300 ps |
| CPU time | 146.85 seconds |
| Started | Aug 23 11:59:44 AM UTC 24 |
| Finished | Aug 23 12:02:17 PM UTC 24 |
| Peak memory | 301928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320111476 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.2320111476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.4268041529 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 12188311500 ps |
| CPU time | 114.53 seconds |
| Started | Aug 23 11:59:51 AM UTC 24 |
| Finished | Aug 23 12:01:48 PM UTC 24 |
| Peak memory | 306044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4268041529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_intr_rd_slow_flash.4268041529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.1381813317 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 6530135700 ps |
| CPU time | 56.58 seconds |
| Started | Aug 23 11:59:29 AM UTC 24 |
| Finished | Aug 23 12:00:27 PM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381813317 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1381813317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.2470295028 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 15388400 ps |
| CPU time | 14.45 seconds |
| Started | Aug 23 12:00:54 PM UTC 24 |
| Finished | Aug 23 12:01:10 PM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2470295028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.2470295028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.298480738 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 8912228200 ps |
| CPU time | 129 seconds |
| Started | Aug 23 11:59:29 AM UTC 24 |
| Finished | Aug 23 12:01:40 PM UTC 24 |
| Peak memory | 273152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=298480738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_mp_regions.298480738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.3115004820 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 292432300 ps |
| CPU time | 148.28 seconds |
| Started | Aug 23 11:59:28 AM UTC 24 |
| Finished | Aug 23 12:01:59 PM UTC 24 |
| Peak memory | 275456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115004820 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.3115004820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1212652146 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 27883700 ps |
| CPU time | 118.53 seconds |
| Started | Aug 23 11:59:18 AM UTC 24 |
| Finished | Aug 23 12:01:18 PM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212652146 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1212652146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.4165154958 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 56275700 ps |
| CPU time | 14.64 seconds |
| Started | Aug 23 12:00:00 PM UTC 24 |
| Finished | Aug 23 12:00:16 PM UTC 24 |
| Peak memory | 268980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165154958 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.4165154958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2654826356 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1186720300 ps |
| CPU time | 752.09 seconds |
| Started | Aug 23 11:59:11 AM UTC 24 |
| Finished | Aug 23 12:11:51 PM UTC 24 |
| Peak memory | 296312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654826356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2654826356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.3481814526 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 63951600 ps |
| CPU time | 32.62 seconds |
| Started | Aug 23 12:00:28 PM UTC 24 |
| Finished | Aug 23 12:01:03 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481814526 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.3481814526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.348692972 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 9936769000 ps |
| CPU time | 81.03 seconds |
| Started | Aug 23 11:59:36 AM UTC 24 |
| Finished | Aug 23 12:00:59 PM UTC 24 |
| Peak memory | 291756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=348692972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.348692972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.1834334909 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5844670400 ps |
| CPU time | 315.85 seconds |
| Started | Aug 23 11:59:39 AM UTC 24 |
| Finished | Aug 23 12:04:59 PM UTC 24 |
| Peak memory | 320648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834334909 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.1834334909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.2176739460 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 78695500 ps |
| CPU time | 32.36 seconds |
| Started | Aug 23 12:00:17 PM UTC 24 |
| Finished | Aug 23 12:00:55 PM UTC 24 |
| Peak memory | 281540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2176739460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_rw_evict_all_en.2176739460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.4279146669 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2098211700 ps |
| CPU time | 60.83 seconds |
| Started | Aug 23 12:00:44 PM UTC 24 |
| Finished | Aug 23 12:01:47 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279146669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.4279146669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1816679914 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 45498400 ps |
| CPU time | 160.89 seconds |
| Started | Aug 23 11:59:11 AM UTC 24 |
| Finished | Aug 23 12:01:55 PM UTC 24 |
| Peak memory | 289424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816679914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1816679914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.3733713523 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 6185274000 ps |
| CPU time | 102.43 seconds |
| Started | Aug 23 11:59:34 AM UTC 24 |
| Finished | Aug 23 12:01:19 PM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3733713523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.3733713523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3714317260 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 39935700 ps |
| CPU time | 14.55 seconds |
| Started | Aug 23 10:44:23 AM UTC 24 |
| Finished | Aug 23 10:44:39 AM UTC 24 |
| Peak memory | 273304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3714317260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3714317260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1137554760 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 38705900 ps |
| CPU time | 14.68 seconds |
| Started | Aug 23 10:45:17 AM UTC 24 |
| Finished | Aug 23 10:45:33 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137554760 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1137554760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.1425197203 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 52779000 ps |
| CPU time | 14.69 seconds |
| Started | Aug 23 10:44:50 AM UTC 24 |
| Finished | Aug 23 10:45:05 AM UTC 24 |
| Peak memory | 273104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425197203 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.1425197203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.97168675 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 81204300 ps |
| CPU time | 14.36 seconds |
| Started | Aug 23 10:43:50 AM UTC 24 |
| Finished | Aug 23 10:44:06 AM UTC 24 |
| Peak memory | 295328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97168675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.97168675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.790124310 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 111463300 ps |
| CPU time | 22.93 seconds |
| Started | Aug 23 10:43:28 AM UTC 24 |
| Finished | Aug 23 10:43:52 AM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=790124310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_disable.790124310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.3554840051 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2129910200 ps |
| CPU time | 394.9 seconds |
| Started | Aug 23 10:34:20 AM UTC 24 |
| Finished | Aug 23 10:41:00 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554840051 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3554840051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1059718429 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4632890700 ps |
| CPU time | 2448.32 seconds |
| Started | Aug 23 10:36:55 AM UTC 24 |
| Finished | Aug 23 11:18:07 AM UTC 24 |
| Peak memory | 275872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059718429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1059718429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1690114407 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3630446300 ps |
| CPU time | 862.33 seconds |
| Started | Aug 23 10:35:59 AM UTC 24 |
| Finished | Aug 23 10:50:30 AM UTC 24 |
| Peak memory | 285396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690114407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1690114407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.4264096012 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1148201000 ps |
| CPU time | 24.84 seconds |
| Started | Aug 23 10:35:32 AM UTC 24 |
| Finished | Aug 23 10:35:58 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 64096012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc h_code.4264096012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2533927963 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 624030900 ps |
| CPU time | 34.13 seconds |
| Started | Aug 23 10:44:28 AM UTC 24 |
| Finished | Aug 23 10:45:04 AM UTC 24 |
| Peak memory | 273212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533927 963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f s_sup.2533927963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.823013431 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 489694087500 ps |
| CPU time | 2131.82 seconds |
| Started | Aug 23 10:35:53 AM UTC 24 |
| Finished | Aug 23 11:11:46 AM UTC 24 |
| Peak memory | 278204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823013431 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.823013431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2321620466 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 52723000 ps |
| CPU time | 32.01 seconds |
| Started | Aug 23 10:45:06 AM UTC 24 |
| Finished | Aug 23 10:45:39 AM UTC 24 |
| Peak memory | 281400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232162046 6 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho st_addr_infection.2321620466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3919439695 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 243512810700 ps |
| CPU time | 2371.61 seconds |
| Started | Aug 23 10:34:46 AM UTC 24 |
| Finished | Aug 23 11:14:39 AM UTC 24 |
| Peak memory | 277944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919439695 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.3919439695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.4038873450 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 126276600 ps |
| CPU time | 97.1 seconds |
| Started | Aug 23 10:33:52 AM UTC 24 |
| Finished | Aug 23 10:35:31 AM UTC 24 |
| Peak memory | 275136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038873450 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4038873450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3483788835 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 10012043400 ps |
| CPU time | 100.01 seconds |
| Started | Aug 23 10:45:05 AM UTC 24 |
| Finished | Aug 23 10:46:47 AM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3483788835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3483788835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.585879710 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 15027000 ps |
| CPU time | 14.52 seconds |
| Started | Aug 23 10:45:05 AM UTC 24 |
| Finished | Aug 23 10:45:20 AM UTC 24 |
| Peak memory | 269264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=585879710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_hw_read_seed_err.585879710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.654966323 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 341225533400 ps |
| CPU time | 1488.64 seconds |
| Started | Aug 23 10:34:21 AM UTC 24 |
| Finished | Aug 23 10:59:25 AM UTC 24 |
| Peak memory | 273744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654966323 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.654966323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.294159004 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 160175967400 ps |
| CPU time | 672.11 seconds |
| Started | Aug 23 10:34:27 AM UTC 24 |
| Finished | Aug 23 10:45:46 AM UTC 24 |
| Peak memory | 274916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294159004 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.294159004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1619069913 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 11240738800 ps |
| CPU time | 177.27 seconds |
| Started | Aug 23 10:34:16 AM UTC 24 |
| Finished | Aug 23 10:37:16 AM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619069913 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.1619069913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3552425146 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 16781384400 ps |
| CPU time | 442.59 seconds |
| Started | Aug 23 10:41:01 AM UTC 24 |
| Finished | Aug 23 10:48:29 AM UTC 24 |
| Peak memory | 336864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3552425146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr ity.3552425146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2738037225 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1413121700 ps |
| CPU time | 160.63 seconds |
| Started | Aug 23 10:41:04 AM UTC 24 |
| Finished | Aug 23 10:43:47 AM UTC 24 |
| Peak memory | 294092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738037225 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.2738037225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2400444614 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 23817169700 ps |
| CPU time | 68.05 seconds |
| Started | Aug 23 10:41:12 AM UTC 24 |
| Finished | Aug 23 10:42:22 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400444614 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.2400444614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.958669691 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 76024114100 ps |
| CPU time | 197.43 seconds |
| Started | Aug 23 10:42:12 AM UTC 24 |
| Finished | Aug 23 10:45:33 AM UTC 24 |
| Peak memory | 271144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958669691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.958669691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.493821493 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4174931100 ps |
| CPU time | 57.09 seconds |
| Started | Aug 23 10:36:56 AM UTC 24 |
| Finished | Aug 23 10:37:55 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493821493 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.493821493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3912003533 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 15453800 ps |
| CPU time | 14.3 seconds |
| Started | Aug 23 10:45:01 AM UTC 24 |
| Finished | Aug 23 10:45:16 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3912003533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_lcmgr_intg.3912003533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.782500967 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 953889200 ps |
| CPU time | 70.82 seconds |
| Started | Aug 23 10:37:00 AM UTC 24 |
| Finished | Aug 23 10:38:12 AM UTC 24 |
| Peak memory | 270892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782500967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.782500967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.2708498054 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4893618500 ps |
| CPU time | 107.36 seconds |
| Started | Aug 23 10:35:09 AM UTC 24 |
| Finished | Aug 23 10:36:58 AM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2708498054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2708498054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2287935471 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1553513900 ps |
| CPU time | 150.99 seconds |
| Started | Aug 23 10:40:34 AM UTC 24 |
| Finished | Aug 23 10:43:07 AM UTC 24 |
| Peak memory | 306340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2287935471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2287935471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.1649669404 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 14812500 ps |
| CPU time | 14.78 seconds |
| Started | Aug 23 10:44:48 AM UTC 24 |
| Finished | Aug 23 10:45:04 AM UTC 24 |
| Peak memory | 275528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649669404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1649669404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.511594845 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 457316600 ps |
| CPU time | 420.08 seconds |
| Started | Aug 23 10:34:06 AM UTC 24 |
| Finished | Aug 23 10:41:11 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511594845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.511594845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.1903829199 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 15309100 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 10:44:39 AM UTC 24 |
| Finished | Aug 23 10:44:56 AM UTC 24 |
| Peak memory | 273468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1903829199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1903829199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3665627232 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 131468200 ps |
| CPU time | 14.25 seconds |
| Started | Aug 23 10:42:23 AM UTC 24 |
| Finished | Aug 23 10:42:38 AM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665627232 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.3665627232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1214390400 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3284618500 ps |
| CPU time | 875.73 seconds |
| Started | Aug 23 10:33:49 AM UTC 24 |
| Finished | Aug 23 10:48:34 AM UTC 24 |
| Peak memory | 293828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214390400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1214390400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2859323982 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 305662300 ps |
| CPU time | 110.3 seconds |
| Started | Aug 23 10:34:00 AM UTC 24 |
| Finished | Aug 23 10:35:53 AM UTC 24 |
| Peak memory | 273080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859323982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2859323982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3806589261 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 113913400 ps |
| CPU time | 33.16 seconds |
| Started | Aug 23 10:43:53 AM UTC 24 |
| Finished | Aug 23 10:44:28 AM UTC 24 |
| Peak memory | 287548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380658926 1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.3806589261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1417095547 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 124193700 ps |
| CPU time | 35.13 seconds |
| Started | Aug 23 10:43:13 AM UTC 24 |
| Finished | Aug 23 10:43:49 AM UTC 24 |
| Peak memory | 287744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417095547 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.1417095547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.4204167538 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 93534400 ps |
| CPU time | 23.94 seconds |
| Started | Aug 23 10:40:08 AM UTC 24 |
| Finished | Aug 23 10:40:33 AM UTC 24 |
| Peak memory | 275648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4204167538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_read_word_sweep_derr.4204167538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.1290306460 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 83867400 ps |
| CPU time | 23.08 seconds |
| Started | Aug 23 10:38:13 AM UTC 24 |
| Finished | Aug 23 10:38:38 AM UTC 24 |
| Peak memory | 275584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290306460 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.1290306460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2060362997 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 41795960700 ps |
| CPU time | 737.25 seconds |
| Started | Aug 23 10:44:57 AM UTC 24 |
| Finished | Aug 23 10:57:21 AM UTC 24 |
| Peak memory | 273048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2060362997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. flash_ctrl_rma_err.2060362997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3014689687 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 612950000 ps |
| CPU time | 85.83 seconds |
| Started | Aug 23 10:37:31 AM UTC 24 |
| Finished | Aug 23 10:38:58 AM UTC 24 |
| Peak memory | 308024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3014689687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.3014689687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3989820292 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1427089100 ps |
| CPU time | 100.94 seconds |
| Started | Aug 23 10:40:13 AM UTC 24 |
| Finished | Aug 23 10:41:56 AM UTC 24 |
| Peak memory | 291776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989820292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3989820292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.747111698 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2670053600 ps |
| CPU time | 102.82 seconds |
| Started | Aug 23 10:38:39 AM UTC 24 |
| Finished | Aug 23 10:40:24 AM UTC 24 |
| Peak memory | 291748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=747111698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ ctrl_ro_serr.747111698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1573539207 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7954918500 ps |
| CPU time | 387.94 seconds |
| Started | Aug 23 10:37:56 AM UTC 24 |
| Finished | Aug 23 10:44:28 AM UTC 24 |
| Peak memory | 330612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573539207 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.1573539207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4197061220 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1699415100 ps |
| CPU time | 185.5 seconds |
| Started | Aug 23 10:40:25 AM UTC 24 |
| Finished | Aug 23 10:43:33 AM UTC 24 |
| Peak memory | 299972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4197061220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rw_derr.4197061220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3402751864 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2158411700 ps |
| CPU time | 128.14 seconds |
| Started | Aug 23 10:38:53 AM UTC 24 |
| Finished | Aug 23 10:41:03 AM UTC 24 |
| Peak memory | 291748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3402751864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.3402751864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.4111207747 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1201342700 ps |
| CPU time | 5374.26 seconds |
| Started | Aug 23 10:43:34 AM UTC 24 |
| Finished | Aug 23 12:13:59 PM UTC 24 |
| Peak memory | 312388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111207747 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.4111207747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3300596393 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8754453400 ps |
| CPU time | 66.11 seconds |
| Started | Aug 23 10:43:41 AM UTC 24 |
| Finished | Aug 23 10:44:49 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300596393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3300596393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.1720346337 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 955539800 ps |
| CPU time | 69.65 seconds |
| Started | Aug 23 10:39:00 AM UTC 24 |
| Finished | Aug 23 10:40:12 AM UTC 24 |
| Peak memory | 285892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172 0346337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser r_address.1720346337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1657498505 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1675965100 ps |
| CPU time | 65.97 seconds |
| Started | Aug 23 10:38:59 AM UTC 24 |
| Finished | Aug 23 10:40:07 AM UTC 24 |
| Peak memory | 285736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 57498505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.1657498505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3315045127 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 45901700 ps |
| CPU time | 128.4 seconds |
| Started | Aug 23 10:33:47 AM UTC 24 |
| Finished | Aug 23 10:35:58 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315045127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3315045127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.379398261 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 16469000 ps |
| CPU time | 25.37 seconds |
| Started | Aug 23 10:33:49 AM UTC 24 |
| Finished | Aug 23 10:34:16 AM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379398261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.379398261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.2647495678 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 390020500 ps |
| CPU time | 914.36 seconds |
| Started | Aug 23 10:43:48 AM UTC 24 |
| Finished | Aug 23 10:59:11 AM UTC 24 |
| Peak memory | 293524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647495678 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.2647495678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.124981519 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 47905800 ps |
| CPU time | 29.26 seconds |
| Started | Aug 23 10:33:49 AM UTC 24 |
| Finished | Aug 23 10:34:20 AM UTC 24 |
| Peak memory | 271124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124981519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.124981519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.313499328 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4294625500 ps |
| CPU time | 100.99 seconds |
| Started | Aug 23 10:37:17 AM UTC 24 |
| Finished | Aug 23 10:39:00 AM UTC 24 |
| Peak memory | 271416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =313499328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.313499328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2715256630 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 164398700 ps |
| CPU time | 15.74 seconds |
| Started | Aug 23 10:44:06 AM UTC 24 |
| Finished | Aug 23 10:44:23 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715256630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_wr_intg.2715256630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1754479354 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 210920500 ps |
| CPU time | 14.51 seconds |
| Started | Aug 23 12:01:48 PM UTC 24 |
| Finished | Aug 23 12:02:04 PM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754479354 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1754479354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.3479988233 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 46099700 ps |
| CPU time | 17.21 seconds |
| Started | Aug 23 12:01:44 PM UTC 24 |
| Finished | Aug 23 12:02:05 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479988233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3479988233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.3532057034 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2098647400 ps |
| CPU time | 64.43 seconds |
| Started | Aug 23 12:01:09 PM UTC 24 |
| Finished | Aug 23 12:02:16 PM UTC 24 |
| Peak memory | 272976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532057034 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.3532057034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.4050412231 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1833018000 ps |
| CPU time | 213.4 seconds |
| Started | Aug 23 12:01:12 PM UTC 24 |
| Finished | Aug 23 12:04:48 PM UTC 24 |
| Peak memory | 293732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050412231 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.4050412231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1940425564 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5972266800 ps |
| CPU time | 109.69 seconds |
| Started | Aug 23 12:01:13 PM UTC 24 |
| Finished | Aug 23 12:03:05 PM UTC 24 |
| Peak memory | 303900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1940425564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.flash_ctrl_intr_rd_slow_flash.1940425564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2164146299 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 69292000 ps |
| CPU time | 144.72 seconds |
| Started | Aug 23 12:01:10 PM UTC 24 |
| Finished | Aug 23 12:03:38 PM UTC 24 |
| Peak memory | 271032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164146299 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.2164146299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.3220330558 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 183460100 ps |
| CPU time | 22.54 seconds |
| Started | Aug 23 12:01:19 PM UTC 24 |
| Finished | Aug 23 12:01:43 PM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220330558 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.3220330558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.1952798973 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 68411300 ps |
| CPU time | 32.38 seconds |
| Started | Aug 23 12:01:20 PM UTC 24 |
| Finished | Aug 23 12:01:54 PM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952798973 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.1952798973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.736866928 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 27912900 ps |
| CPU time | 30.52 seconds |
| Started | Aug 23 12:01:21 PM UTC 24 |
| Finished | Aug 23 12:01:53 PM UTC 24 |
| Peak memory | 281532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=736866928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ct rl_rw_evict_all_en.736866928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3930815455 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2744276400 ps |
| CPU time | 63 seconds |
| Started | Aug 23 12:01:43 PM UTC 24 |
| Finished | Aug 23 12:02:51 PM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930815455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3930815455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.93793197 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 44030900 ps |
| CPU time | 129.71 seconds |
| Started | Aug 23 12:01:07 PM UTC 24 |
| Finished | Aug 23 12:03:19 PM UTC 24 |
| Peak memory | 289536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93793197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.93793197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.285296152 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 99049000 ps |
| CPU time | 14.72 seconds |
| Started | Aug 23 12:02:18 PM UTC 24 |
| Finished | Aug 23 12:02:36 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285296152 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.285296152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.988401690 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 17257300 ps |
| CPU time | 17.25 seconds |
| Started | Aug 23 12:02:18 PM UTC 24 |
| Finished | Aug 23 12:02:38 PM UTC 24 |
| Peak memory | 295332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988401690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.988401690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1974516086 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 14524800 ps |
| CPU time | 23.27 seconds |
| Started | Aug 23 12:02:12 PM UTC 24 |
| Finished | Aug 23 12:02:39 PM UTC 24 |
| Peak memory | 285540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1974516086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.1974516086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.1526600828 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4909848700 ps |
| CPU time | 122.46 seconds |
| Started | Aug 23 12:01:54 PM UTC 24 |
| Finished | Aug 23 12:04:00 PM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526600828 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.1526600828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.1644309588 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 14724780700 ps |
| CPU time | 160.03 seconds |
| Started | Aug 23 12:01:56 PM UTC 24 |
| Finished | Aug 23 12:04:40 PM UTC 24 |
| Peak memory | 301744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644309588 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.1644309588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.934374112 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 24979889400 ps |
| CPU time | 237.64 seconds |
| Started | Aug 23 12:01:56 PM UTC 24 |
| Finished | Aug 23 12:05:58 PM UTC 24 |
| Peak memory | 293468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=934374112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 21.flash_ctrl_intr_rd_slow_flash.934374112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.1965108010 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 43338200 ps |
| CPU time | 145.91 seconds |
| Started | Aug 23 12:01:54 PM UTC 24 |
| Finished | Aug 23 12:04:24 PM UTC 24 |
| Peak memory | 271616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965108010 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.1965108010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.4015882369 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 10843948000 ps |
| CPU time | 190.34 seconds |
| Started | Aug 23 12:02:00 PM UTC 24 |
| Finished | Aug 23 12:05:15 PM UTC 24 |
| Peak memory | 271188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015882369 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.4015882369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.469651525 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 44716800 ps |
| CPU time | 32.51 seconds |
| Started | Aug 23 12:02:05 PM UTC 24 |
| Finished | Aug 23 12:02:43 PM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469651525 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.469651525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.1499028716 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 29727500 ps |
| CPU time | 32.61 seconds |
| Started | Aug 23 12:02:06 PM UTC 24 |
| Finished | Aug 23 12:02:44 PM UTC 24 |
| Peak memory | 287708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1499028716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c trl_rw_evict_all_en.1499028716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.4126155542 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 8325381800 ps |
| CPU time | 61.71 seconds |
| Started | Aug 23 12:02:16 PM UTC 24 |
| Finished | Aug 23 12:03:23 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126155542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.4126155542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2241438335 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 18460300 ps |
| CPU time | 79.78 seconds |
| Started | Aug 23 12:01:49 PM UTC 24 |
| Finished | Aug 23 12:03:11 PM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241438335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2241438335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.1750465701 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 150825800 ps |
| CPU time | 14.52 seconds |
| Started | Aug 23 12:03:25 PM UTC 24 |
| Finished | Aug 23 12:03:40 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750465701 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.1750465701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.564911175 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 39093200 ps |
| CPU time | 14.25 seconds |
| Started | Aug 23 12:03:20 PM UTC 24 |
| Finished | Aug 23 12:03:36 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564911175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.564911175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.3815320349 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 20636400 ps |
| CPU time | 22.35 seconds |
| Started | Aug 23 12:03:05 PM UTC 24 |
| Finished | Aug 23 12:03:31 PM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3815320349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ ctrl_disable.3815320349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2447720771 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 8438842800 ps |
| CPU time | 76.28 seconds |
| Started | Aug 23 12:02:37 PM UTC 24 |
| Finished | Aug 23 12:03:57 PM UTC 24 |
| Peak memory | 273236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447720771 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.2447720771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2373838822 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4288522100 ps |
| CPU time | 169.92 seconds |
| Started | Aug 23 12:02:40 PM UTC 24 |
| Finished | Aug 23 12:05:34 PM UTC 24 |
| Peak memory | 301928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373838822 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.2373838822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2071776685 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 12411011600 ps |
| CPU time | 216.95 seconds |
| Started | Aug 23 12:02:44 PM UTC 24 |
| Finished | Aug 23 12:06:24 PM UTC 24 |
| Peak memory | 301852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2071776685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.flash_ctrl_intr_rd_slow_flash.2071776685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.287276050 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 38438300 ps |
| CPU time | 147.39 seconds |
| Started | Aug 23 12:02:39 PM UTC 24 |
| Finished | Aug 23 12:05:10 PM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287276050 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.287276050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.337807974 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 81204000 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 12:02:45 PM UTC 24 |
| Finished | Aug 23 12:03:00 PM UTC 24 |
| Peak memory | 271060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337807974 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.337807974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.823370790 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 34550100 ps |
| CPU time | 33.23 seconds |
| Started | Aug 23 12:02:52 PM UTC 24 |
| Finished | Aug 23 12:03:27 PM UTC 24 |
| Peak memory | 285888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823370790 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.823370790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3574775755 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1641322900 ps |
| CPU time | 50.53 seconds |
| Started | Aug 23 12:03:12 PM UTC 24 |
| Finished | Aug 23 12:04:04 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574775755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3574775755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.62613112 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 18172800 ps |
| CPU time | 83.54 seconds |
| Started | Aug 23 12:02:23 PM UTC 24 |
| Finished | Aug 23 12:03:49 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62613112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.62613112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1270494353 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 28036500 ps |
| CPU time | 14.39 seconds |
| Started | Aug 23 12:04:01 PM UTC 24 |
| Finished | Aug 23 12:04:18 PM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270494353 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1270494353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.3649321550 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 74512000 ps |
| CPU time | 14.35 seconds |
| Started | Aug 23 12:03:58 PM UTC 24 |
| Finished | Aug 23 12:04:14 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649321550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3649321550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.1390788708 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 38982600 ps |
| CPU time | 23.1 seconds |
| Started | Aug 23 12:03:53 PM UTC 24 |
| Finished | Aug 23 12:04:17 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1390788708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ ctrl_disable.1390788708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.1902479216 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4164938800 ps |
| CPU time | 69.36 seconds |
| Started | Aug 23 12:03:32 PM UTC 24 |
| Finished | Aug 23 12:04:43 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902479216 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.1902479216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3589746789 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 692840700 ps |
| CPU time | 115.24 seconds |
| Started | Aug 23 12:03:38 PM UTC 24 |
| Finished | Aug 23 12:05:35 PM UTC 24 |
| Peak memory | 302024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589746789 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.3589746789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2411714520 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 74720567000 ps |
| CPU time | 246.52 seconds |
| Started | Aug 23 12:03:39 PM UTC 24 |
| Finished | Aug 23 12:07:49 PM UTC 24 |
| Peak memory | 303936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2411714520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.flash_ctrl_intr_rd_slow_flash.2411714520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3957503750 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 43986900 ps |
| CPU time | 146.4 seconds |
| Started | Aug 23 12:03:37 PM UTC 24 |
| Finished | Aug 23 12:06:06 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957503750 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.3957503750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.3143964688 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 19990300 ps |
| CPU time | 14.57 seconds |
| Started | Aug 23 12:03:41 PM UTC 24 |
| Finished | Aug 23 12:03:57 PM UTC 24 |
| Peak memory | 271124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143964688 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.3143964688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.532266012 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 45244500 ps |
| CPU time | 34.28 seconds |
| Started | Aug 23 12:03:49 PM UTC 24 |
| Finished | Aug 23 12:04:26 PM UTC 24 |
| Peak memory | 281792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532266012 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.532266012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3837251018 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 76926900 ps |
| CPU time | 32.89 seconds |
| Started | Aug 23 12:03:51 PM UTC 24 |
| Finished | Aug 23 12:04:25 PM UTC 24 |
| Peak memory | 287708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3837251018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_rw_evict_all_en.3837251018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.874303219 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 7682986700 ps |
| CPU time | 52.12 seconds |
| Started | Aug 23 12:03:58 PM UTC 24 |
| Finished | Aug 23 12:04:52 PM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874303219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.874303219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.1930473485 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 83340600 ps |
| CPU time | 129.33 seconds |
| Started | Aug 23 12:03:28 PM UTC 24 |
| Finished | Aug 23 12:05:39 PM UTC 24 |
| Peak memory | 289732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930473485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1930473485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.3293406751 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 134813400 ps |
| CPU time | 14.8 seconds |
| Started | Aug 23 12:04:44 PM UTC 24 |
| Finished | Aug 23 12:05:00 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293406751 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.3293406751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.1379577696 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 15564700 ps |
| CPU time | 14.53 seconds |
| Started | Aug 23 12:04:44 PM UTC 24 |
| Finished | Aug 23 12:04:59 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379577696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1379577696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.512312108 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 10445600 ps |
| CPU time | 23.17 seconds |
| Started | Aug 23 12:04:33 PM UTC 24 |
| Finished | Aug 23 12:04:58 PM UTC 24 |
| Peak memory | 285540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=512312108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_disable.512312108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.3172958043 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1106103500 ps |
| CPU time | 40.05 seconds |
| Started | Aug 23 12:04:11 PM UTC 24 |
| Finished | Aug 23 12:04:53 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172958043 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.3172958043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.3446150608 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3136809000 ps |
| CPU time | 150.55 seconds |
| Started | Aug 23 12:04:19 PM UTC 24 |
| Finished | Aug 23 12:06:52 PM UTC 24 |
| Peak memory | 301928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446150608 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.3446150608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.422328254 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5854117700 ps |
| CPU time | 130.31 seconds |
| Started | Aug 23 12:04:19 PM UTC 24 |
| Finished | Aug 23 12:06:32 PM UTC 24 |
| Peak memory | 303928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=422328254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 24.flash_ctrl_intr_rd_slow_flash.422328254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.2615339766 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 267683000 ps |
| CPU time | 144.8 seconds |
| Started | Aug 23 12:04:15 PM UTC 24 |
| Finished | Aug 23 12:06:43 PM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615339766 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.2615339766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.1105697078 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 19395600 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 12:04:25 PM UTC 24 |
| Finished | Aug 23 12:04:42 PM UTC 24 |
| Peak memory | 269236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105697078 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.1105697078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3094926953 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 30261300 ps |
| CPU time | 32.53 seconds |
| Started | Aug 23 12:04:26 PM UTC 24 |
| Finished | Aug 23 12:05:01 PM UTC 24 |
| Peak memory | 281792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094926953 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.3094926953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3331882952 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 44030300 ps |
| CPU time | 32.38 seconds |
| Started | Aug 23 12:04:27 PM UTC 24 |
| Finished | Aug 23 12:05:01 PM UTC 24 |
| Peak memory | 285636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3331882952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_rw_evict_all_en.3331882952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.2250924951 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 678747100 ps |
| CPU time | 61.82 seconds |
| Started | Aug 23 12:04:40 PM UTC 24 |
| Finished | Aug 23 12:05:44 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250924951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2250924951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.3071186840 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 93091300 ps |
| CPU time | 152.33 seconds |
| Started | Aug 23 12:04:05 PM UTC 24 |
| Finished | Aug 23 12:06:40 PM UTC 24 |
| Peak memory | 287752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071186840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3071186840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1764060913 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 141709400 ps |
| CPU time | 14.87 seconds |
| Started | Aug 23 12:05:17 PM UTC 24 |
| Finished | Aug 23 12:05:34 PM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764060913 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.1764060913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.215386156 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 16819800 ps |
| CPU time | 17.27 seconds |
| Started | Aug 23 12:05:16 PM UTC 24 |
| Finished | Aug 23 12:05:35 PM UTC 24 |
| Peak memory | 285088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215386156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.215386156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.1260006002 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 15453100 ps |
| CPU time | 23.27 seconds |
| Started | Aug 23 12:05:03 PM UTC 24 |
| Finished | Aug 23 12:05:28 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1260006002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ ctrl_disable.1260006002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.2728362065 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 10705145000 ps |
| CPU time | 91.41 seconds |
| Started | Aug 23 12:04:53 PM UTC 24 |
| Finished | Aug 23 12:06:27 PM UTC 24 |
| Peak memory | 272980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728362065 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.2728362065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3475108421 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 539904500 ps |
| CPU time | 104.3 seconds |
| Started | Aug 23 12:04:59 PM UTC 24 |
| Finished | Aug 23 12:06:46 PM UTC 24 |
| Peak memory | 306116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475108421 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.3475108421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1370514270 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 24628139500 ps |
| CPU time | 223.29 seconds |
| Started | Aug 23 12:05:01 PM UTC 24 |
| Finished | Aug 23 12:08:48 PM UTC 24 |
| Peak memory | 304160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1370514270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_intr_rd_slow_flash.1370514270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.868657311 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 93371000 ps |
| CPU time | 144.77 seconds |
| Started | Aug 23 12:04:54 PM UTC 24 |
| Finished | Aug 23 12:07:22 PM UTC 24 |
| Peak memory | 271552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868657311 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.868657311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.2828601827 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 48763300 ps |
| CPU time | 14.27 seconds |
| Started | Aug 23 12:05:01 PM UTC 24 |
| Finished | Aug 23 12:05:17 PM UTC 24 |
| Peak memory | 275392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828601827 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.2828601827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.4031243452 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 38195100 ps |
| CPU time | 33.61 seconds |
| Started | Aug 23 12:05:01 PM UTC 24 |
| Finished | Aug 23 12:05:36 PM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031243452 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.4031243452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.3389796031 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3400841200 ps |
| CPU time | 59.01 seconds |
| Started | Aug 23 12:05:11 PM UTC 24 |
| Finished | Aug 23 12:06:12 PM UTC 24 |
| Peak memory | 270996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389796031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3389796031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.2911871999 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 60709200 ps |
| CPU time | 52.05 seconds |
| Started | Aug 23 12:04:49 PM UTC 24 |
| Finished | Aug 23 12:05:43 PM UTC 24 |
| Peak memory | 283336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911871999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2911871999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.968573187 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 42119100 ps |
| CPU time | 14.45 seconds |
| Started | Aug 23 12:05:55 PM UTC 24 |
| Finished | Aug 23 12:06:16 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968573187 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.968573187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.617997539 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 22302300 ps |
| CPU time | 14.31 seconds |
| Started | Aug 23 12:05:46 PM UTC 24 |
| Finished | Aug 23 12:06:06 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617997539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.617997539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.3287226555 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5806063000 ps |
| CPU time | 93.47 seconds |
| Started | Aug 23 12:05:35 PM UTC 24 |
| Finished | Aug 23 12:07:10 PM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287226555 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.3287226555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.3102396039 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3484568600 ps |
| CPU time | 194.25 seconds |
| Started | Aug 23 12:05:36 PM UTC 24 |
| Finished | Aug 23 12:08:53 PM UTC 24 |
| Peak memory | 293732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102396039 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.3102396039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3918260151 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 12807587500 ps |
| CPU time | 115.63 seconds |
| Started | Aug 23 12:05:36 PM UTC 24 |
| Finished | Aug 23 12:07:34 PM UTC 24 |
| Peak memory | 303904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3918260151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.flash_ctrl_intr_rd_slow_flash.3918260151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.3843275892 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 140157100 ps |
| CPU time | 146.92 seconds |
| Started | Aug 23 12:05:35 PM UTC 24 |
| Finished | Aug 23 12:08:04 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843275892 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.3843275892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.3571214471 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 47040700 ps |
| CPU time | 14.9 seconds |
| Started | Aug 23 12:05:37 PM UTC 24 |
| Finished | Aug 23 12:05:54 PM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571214471 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.3571214471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.1476189652 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 49641600 ps |
| CPU time | 32.88 seconds |
| Started | Aug 23 12:05:37 PM UTC 24 |
| Finished | Aug 23 12:06:12 PM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476189652 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.1476189652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.2611697951 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 42662400 ps |
| CPU time | 32.46 seconds |
| Started | Aug 23 12:05:40 PM UTC 24 |
| Finished | Aug 23 12:06:16 PM UTC 24 |
| Peak memory | 287684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2611697951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_rw_evict_all_en.2611697951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.1910331776 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 25998600 ps |
| CPU time | 78.86 seconds |
| Started | Aug 23 12:05:28 PM UTC 24 |
| Finished | Aug 23 12:06:49 PM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910331776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1910331776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.3096859876 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 462262800 ps |
| CPU time | 14.58 seconds |
| Started | Aug 23 12:06:39 PM UTC 24 |
| Finished | Aug 23 12:07:00 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096859876 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.3096859876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.228224810 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 16110000 ps |
| CPU time | 17.08 seconds |
| Started | Aug 23 12:06:32 PM UTC 24 |
| Finished | Aug 23 12:06:51 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228224810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.228224810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.3467999374 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4696473500 ps |
| CPU time | 77.46 seconds |
| Started | Aug 23 12:06:06 PM UTC 24 |
| Finished | Aug 23 12:07:26 PM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467999374 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.3467999374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.673181360 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3116607400 ps |
| CPU time | 112.91 seconds |
| Started | Aug 23 12:06:13 PM UTC 24 |
| Finished | Aug 23 12:08:09 PM UTC 24 |
| Peak memory | 293340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673181360 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.673181360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2832593454 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 5957473100 ps |
| CPU time | 127.23 seconds |
| Started | Aug 23 12:06:13 PM UTC 24 |
| Finished | Aug 23 12:08:23 PM UTC 24 |
| Peak memory | 303572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2832593454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.flash_ctrl_intr_rd_slow_flash.2832593454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.2894072113 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 40512500 ps |
| CPU time | 148.26 seconds |
| Started | Aug 23 12:06:06 PM UTC 24 |
| Finished | Aug 23 12:08:37 PM UTC 24 |
| Peak memory | 271552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894072113 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.2894072113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2479317491 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 198000800 ps |
| CPU time | 22.95 seconds |
| Started | Aug 23 12:06:14 PM UTC 24 |
| Finished | Aug 23 12:06:39 PM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479317491 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2479317491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2799287119 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 43268900 ps |
| CPU time | 32.68 seconds |
| Started | Aug 23 12:06:17 PM UTC 24 |
| Finished | Aug 23 12:06:52 PM UTC 24 |
| Peak memory | 281824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799287119 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.2799287119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.1015532660 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 29871800 ps |
| CPU time | 32.88 seconds |
| Started | Aug 23 12:06:17 PM UTC 24 |
| Finished | Aug 23 12:06:52 PM UTC 24 |
| Peak memory | 281564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1015532660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_rw_evict_all_en.1015532660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2061782251 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 16984737700 ps |
| CPU time | 68.88 seconds |
| Started | Aug 23 12:06:27 PM UTC 24 |
| Finished | Aug 23 12:07:38 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061782251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2061782251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.2265237596 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 43232900 ps |
| CPU time | 128.82 seconds |
| Started | Aug 23 12:05:59 PM UTC 24 |
| Finished | Aug 23 12:08:12 PM UTC 24 |
| Peak memory | 289800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265237596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2265237596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.2279784357 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 84005300 ps |
| CPU time | 14.6 seconds |
| Started | Aug 23 12:07:11 PM UTC 24 |
| Finished | Aug 23 12:07:28 PM UTC 24 |
| Peak memory | 269320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279784357 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.2279784357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.968967624 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 29136500 ps |
| CPU time | 17.17 seconds |
| Started | Aug 23 12:07:01 PM UTC 24 |
| Finished | Aug 23 12:07:22 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968967624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.968967624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3568756829 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15217500 ps |
| CPU time | 22.13 seconds |
| Started | Aug 23 12:06:54 PM UTC 24 |
| Finished | Aug 23 12:07:23 PM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3568756829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ ctrl_disable.3568756829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.3067968896 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2570913000 ps |
| CPU time | 50.07 seconds |
| Started | Aug 23 12:06:44 PM UTC 24 |
| Finished | Aug 23 12:07:40 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067968896 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.3067968896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.3497117559 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4832269100 ps |
| CPU time | 171.98 seconds |
| Started | Aug 23 12:06:47 PM UTC 24 |
| Finished | Aug 23 12:09:47 PM UTC 24 |
| Peak memory | 293832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497117559 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.3497117559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2127852000 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 11633593100 ps |
| CPU time | 134.47 seconds |
| Started | Aug 23 12:06:50 PM UTC 24 |
| Finished | Aug 23 12:09:16 PM UTC 24 |
| Peak memory | 303900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2127852000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.flash_ctrl_intr_rd_slow_flash.2127852000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.617458368 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 568632100 ps |
| CPU time | 118.36 seconds |
| Started | Aug 23 12:06:47 PM UTC 24 |
| Finished | Aug 23 12:08:55 PM UTC 24 |
| Peak memory | 270824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617458368 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.617458368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.3481152218 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 183257500 ps |
| CPU time | 14.53 seconds |
| Started | Aug 23 12:06:51 PM UTC 24 |
| Finished | Aug 23 12:07:15 PM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481152218 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.3481152218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.3616089379 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 195877200 ps |
| CPU time | 30.71 seconds |
| Started | Aug 23 12:06:52 PM UTC 24 |
| Finished | Aug 23 12:07:30 PM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616089379 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.3616089379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.3970469320 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 62239900 ps |
| CPU time | 30.54 seconds |
| Started | Aug 23 12:06:53 PM UTC 24 |
| Finished | Aug 23 12:07:30 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3970469320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_rw_evict_all_en.3970469320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.4234918037 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 556963800 ps |
| CPU time | 59.32 seconds |
| Started | Aug 23 12:06:54 PM UTC 24 |
| Finished | Aug 23 12:08:00 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234918037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4234918037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.2940127652 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 69852800 ps |
| CPU time | 54.56 seconds |
| Started | Aug 23 12:06:41 PM UTC 24 |
| Finished | Aug 23 12:07:41 PM UTC 24 |
| Peak memory | 285380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940127652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2940127652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.4102351380 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 157479000 ps |
| CPU time | 14.71 seconds |
| Started | Aug 23 12:07:41 PM UTC 24 |
| Finished | Aug 23 12:07:57 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102351380 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.4102351380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1868287579 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 46435200 ps |
| CPU time | 17.32 seconds |
| Started | Aug 23 12:07:39 PM UTC 24 |
| Finished | Aug 23 12:07:58 PM UTC 24 |
| Peak memory | 295392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868287579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1868287579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.4229844456 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 10564200 ps |
| CPU time | 23.01 seconds |
| Started | Aug 23 12:07:31 PM UTC 24 |
| Finished | Aug 23 12:08:00 PM UTC 24 |
| Peak memory | 285052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4229844456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ ctrl_disable.4229844456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.3855623270 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 5388616600 ps |
| CPU time | 35.7 seconds |
| Started | Aug 23 12:07:16 PM UTC 24 |
| Finished | Aug 23 12:07:54 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855623270 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.3855623270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.675484110 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 641234100 ps |
| CPU time | 103.25 seconds |
| Started | Aug 23 12:07:23 PM UTC 24 |
| Finished | Aug 23 12:09:08 PM UTC 24 |
| Peak memory | 306116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675484110 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.675484110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1511168093 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 25862713200 ps |
| CPU time | 243.49 seconds |
| Started | Aug 23 12:07:24 PM UTC 24 |
| Finished | Aug 23 12:11:31 PM UTC 24 |
| Peak memory | 306716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1511168093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.flash_ctrl_intr_rd_slow_flash.1511168093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.418971089 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 71348000 ps |
| CPU time | 146.06 seconds |
| Started | Aug 23 12:07:23 PM UTC 24 |
| Finished | Aug 23 12:09:51 PM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418971089 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.418971089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.3393677114 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 34785200 ps |
| CPU time | 14.43 seconds |
| Started | Aug 23 12:07:27 PM UTC 24 |
| Finished | Aug 23 12:07:44 PM UTC 24 |
| Peak memory | 271028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393677114 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.3393677114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.1420307048 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 150017300 ps |
| CPU time | 32.73 seconds |
| Started | Aug 23 12:07:29 PM UTC 24 |
| Finished | Aug 23 12:08:06 PM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420307048 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.1420307048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.2620821592 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 36513900 ps |
| CPU time | 32.76 seconds |
| Started | Aug 23 12:07:31 PM UTC 24 |
| Finished | Aug 23 12:08:10 PM UTC 24 |
| Peak memory | 285308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2620821592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c trl_rw_evict_all_en.2620821592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.2291615475 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1720031500 ps |
| CPU time | 58.87 seconds |
| Started | Aug 23 12:07:35 PM UTC 24 |
| Finished | Aug 23 12:08:39 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291615475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2291615475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.2478848393 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 39324000 ps |
| CPU time | 129.11 seconds |
| Started | Aug 23 12:07:12 PM UTC 24 |
| Finished | Aug 23 12:09:25 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478848393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2478848393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2250512777 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 71155700 ps |
| CPU time | 14.48 seconds |
| Started | Aug 23 10:57:59 AM UTC 24 |
| Finished | Aug 23 10:58:15 AM UTC 24 |
| Peak memory | 269032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250512777 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2250512777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2836980928 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 64313700 ps |
| CPU time | 14.85 seconds |
| Started | Aug 23 10:57:42 AM UTC 24 |
| Finished | Aug 23 10:57:58 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836980928 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2836980928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.365778370 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 16036000 ps |
| CPU time | 17.43 seconds |
| Started | Aug 23 10:57:13 AM UTC 24 |
| Finished | Aug 23 10:57:31 AM UTC 24 |
| Peak memory | 295332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365778370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.365778370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.3202192135 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3480388100 ps |
| CPU time | 177.47 seconds |
| Started | Aug 23 10:54:12 AM UTC 24 |
| Finished | Aug 23 10:57:12 AM UTC 24 |
| Peak memory | 289728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3202192135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.3202192135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3510721200 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 27080200 ps |
| CPU time | 22.35 seconds |
| Started | Aug 23 10:56:59 AM UTC 24 |
| Finished | Aug 23 10:57:22 AM UTC 24 |
| Peak memory | 285612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3510721200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_disable.3510721200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.3634203810 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2956670500 ps |
| CPU time | 364.7 seconds |
| Started | Aug 23 10:46:06 AM UTC 24 |
| Finished | Aug 23 10:52:15 AM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634203810 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3634203810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1771934416 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4661948900 ps |
| CPU time | 2405.73 seconds |
| Started | Aug 23 10:48:29 AM UTC 24 |
| Finished | Aug 23 11:28:58 AM UTC 24 |
| Peak memory | 278252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771934416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1771934416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.3702949336 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 652156700 ps |
| CPU time | 1939.34 seconds |
| Started | Aug 23 10:48:14 AM UTC 24 |
| Finished | Aug 23 11:20:51 AM UTC 24 |
| Peak memory | 277984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 02949336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _error_prog_type.3702949336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1230493350 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 14661999000 ps |
| CPU time | 1099.22 seconds |
| Started | Aug 23 10:48:17 AM UTC 24 |
| Finished | Aug 23 11:06:47 AM UTC 24 |
| Peak memory | 288184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230493350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1230493350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.1439307560 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 330504600 ps |
| CPU time | 33.23 seconds |
| Started | Aug 23 10:57:22 AM UTC 24 |
| Finished | Aug 23 10:57:56 AM UTC 24 |
| Peak memory | 275544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439307 560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.1439307560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2405768964 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 93112961600 ps |
| CPU time | 1945.02 seconds |
| Started | Aug 23 10:48:13 AM UTC 24 |
| Finished | Aug 23 11:20:57 AM UTC 24 |
| Peak memory | 277812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405768964 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.2405768964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2317405433 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 573837676100 ps |
| CPU time | 1999.91 seconds |
| Started | Aug 23 10:47:08 AM UTC 24 |
| Finished | Aug 23 11:20:46 AM UTC 24 |
| Peak memory | 277984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317405433 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.2317405433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2325000027 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 70903300 ps |
| CPU time | 64.05 seconds |
| Started | Aug 23 10:45:40 AM UTC 24 |
| Finished | Aug 23 10:46:46 AM UTC 24 |
| Peak memory | 273088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325000027 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2325000027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2055594274 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 10062374800 ps |
| CPU time | 43.8 seconds |
| Started | Aug 23 10:57:57 AM UTC 24 |
| Finished | Aug 23 10:58:42 AM UTC 24 |
| Peak memory | 279348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2055594274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2055594274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.360419317 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 15651600 ps |
| CPU time | 14.33 seconds |
| Started | Aug 23 10:57:50 AM UTC 24 |
| Finished | Aug 23 10:58:06 AM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=360419317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_hw_read_seed_err.360419317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.3667500770 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 80153625500 ps |
| CPU time | 685.69 seconds |
| Started | Aug 23 10:46:47 AM UTC 24 |
| Finished | Aug 23 10:58:19 AM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667500770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.3667500770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3878294386 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15637489900 ps |
| CPU time | 126.01 seconds |
| Started | Aug 23 10:46:04 AM UTC 24 |
| Finished | Aug 23 10:48:12 AM UTC 24 |
| Peak memory | 272980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878294386 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.3878294386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.3135903101 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 17621033000 ps |
| CPU time | 441.63 seconds |
| Started | Aug 23 10:54:32 AM UTC 24 |
| Finished | Aug 23 11:01:59 AM UTC 24 |
| Peak memory | 349128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3135903101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr ity.3135903101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2223099216 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3072073200 ps |
| CPU time | 123.17 seconds |
| Started | Aug 23 10:54:52 AM UTC 24 |
| Finished | Aug 23 10:56:57 AM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223099216 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.2223099216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1073531158 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 34372632000 ps |
| CPU time | 203.06 seconds |
| Started | Aug 23 10:55:37 AM UTC 24 |
| Finished | Aug 23 10:59:06 AM UTC 24 |
| Peak memory | 293696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1073531158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.1073531158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2618656063 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 6688562700 ps |
| CPU time | 62.2 seconds |
| Started | Aug 23 10:55:17 AM UTC 24 |
| Finished | Aug 23 10:56:21 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618656063 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.2618656063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1525033590 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 181635635500 ps |
| CPU time | 228.64 seconds |
| Started | Aug 23 10:55:56 AM UTC 24 |
| Finished | Aug 23 10:59:48 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525033590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1525033590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1409877433 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6512309300 ps |
| CPU time | 65.83 seconds |
| Started | Aug 23 10:48:34 AM UTC 24 |
| Finished | Aug 23 10:49:42 AM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409877433 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1409877433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1187478843 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1846043300 ps |
| CPU time | 72.46 seconds |
| Started | Aug 23 10:48:51 AM UTC 24 |
| Finished | Aug 23 10:50:05 AM UTC 24 |
| Peak memory | 270892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187478843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1187478843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2725878170 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 22884591500 ps |
| CPU time | 851.76 seconds |
| Started | Aug 23 10:47:38 AM UTC 24 |
| Finished | Aug 23 11:01:59 AM UTC 24 |
| Peak memory | 284484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2725878170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2725878170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1020583400 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 35604400 ps |
| CPU time | 120.57 seconds |
| Started | Aug 23 10:46:48 AM UTC 24 |
| Finished | Aug 23 10:48:50 AM UTC 24 |
| Peak memory | 270888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020583400 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.1020583400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.2666964669 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 6047293800 ps |
| CPU time | 142.08 seconds |
| Started | Aug 23 10:54:28 AM UTC 24 |
| Finished | Aug 23 10:56:52 AM UTC 24 |
| Peak memory | 291740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2666964669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2666964669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.658125874 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 24062100 ps |
| CPU time | 15.88 seconds |
| Started | Aug 23 10:57:32 AM UTC 24 |
| Finished | Aug 23 10:57:49 AM UTC 24 |
| Peak memory | 293416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658125874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.658125874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.4095838318 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 128556600 ps |
| CPU time | 120.68 seconds |
| Started | Aug 23 10:45:47 AM UTC 24 |
| Finished | Aug 23 10:47:50 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095838318 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.4095838318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1859155042 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 775648800 ps |
| CPU time | 17.13 seconds |
| Started | Aug 23 10:57:23 AM UTC 24 |
| Finished | Aug 23 10:57:41 AM UTC 24 |
| Peak memory | 273560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1859155042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1859155042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.715391937 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 23201300 ps |
| CPU time | 14.92 seconds |
| Started | Aug 23 10:56:21 AM UTC 24 |
| Finished | Aug 23 10:56:38 AM UTC 24 |
| Peak memory | 271088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715391937 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.715391937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.341914351 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5180065400 ps |
| CPU time | 156.42 seconds |
| Started | Aug 23 10:45:34 AM UTC 24 |
| Finished | Aug 23 10:48:13 AM UTC 24 |
| Peak memory | 291524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341914351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.341914351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1064335861 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 75303700 ps |
| CPU time | 35.95 seconds |
| Started | Aug 23 10:56:53 AM UTC 24 |
| Finished | Aug 23 10:57:31 AM UTC 24 |
| Peak memory | 283840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064335861 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.1064335861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3066298142 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 41553400 ps |
| CPU time | 24.07 seconds |
| Started | Aug 23 10:53:11 AM UTC 24 |
| Finished | Aug 23 10:53:36 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3066298142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_read_word_sweep_derr.3066298142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.3644949943 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 65999800 ps |
| CPU time | 24.11 seconds |
| Started | Aug 23 10:51:24 AM UTC 24 |
| Finished | Aug 23 10:51:49 AM UTC 24 |
| Peak memory | 275328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644949943 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.3644949943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2705706761 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1000344200 ps |
| CPU time | 76.15 seconds |
| Started | Aug 23 10:50:06 AM UTC 24 |
| Finished | Aug 23 10:51:24 AM UTC 24 |
| Peak memory | 291700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2705706761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.2705706761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.2312805626 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 845800200 ps |
| CPU time | 109.46 seconds |
| Started | Aug 23 10:53:25 AM UTC 24 |
| Finished | Aug 23 10:55:16 AM UTC 24 |
| Peak memory | 291768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312805626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2312805626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2196448808 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1920440800 ps |
| CPU time | 94.09 seconds |
| Started | Aug 23 10:51:48 AM UTC 24 |
| Finished | Aug 23 10:53:24 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2196448808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_ro_serr.2196448808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1639180190 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 11433554000 ps |
| CPU time | 383.92 seconds |
| Started | Aug 23 10:50:31 AM UTC 24 |
| Finished | Aug 23 10:56:59 AM UTC 24 |
| Peak memory | 320392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639180190 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.1639180190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2441974253 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1212786900 ps |
| CPU time | 136.45 seconds |
| Started | Aug 23 10:53:37 AM UTC 24 |
| Finished | Aug 23 10:55:56 AM UTC 24 |
| Peak memory | 293800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2441974253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.2441974253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4273691740 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 117619900 ps |
| CPU time | 32.27 seconds |
| Started | Aug 23 10:56:36 AM UTC 24 |
| Finished | Aug 23 10:57:10 AM UTC 24 |
| Peak memory | 281792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273691740 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.4273691740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2949385558 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 28536600 ps |
| CPU time | 30.38 seconds |
| Started | Aug 23 10:56:38 AM UTC 24 |
| Finished | Aug 23 10:57:10 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2949385558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_rw_evict_all_en.2949385558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.782707853 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3263489300 ps |
| CPU time | 158.08 seconds |
| Started | Aug 23 10:51:50 AM UTC 24 |
| Finished | Aug 23 10:54:31 AM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=782707853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.782707853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.3301137375 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6106062900 ps |
| CPU time | 5466.33 seconds |
| Started | Aug 23 10:57:01 AM UTC 24 |
| Finished | Aug 23 12:28:58 PM UTC 24 |
| Peak memory | 316460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301137375 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3301137375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.489400048 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1585440500 ps |
| CPU time | 63.18 seconds |
| Started | Aug 23 10:57:11 AM UTC 24 |
| Finished | Aug 23 10:58:16 AM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489400048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.489400048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1267757184 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3831288100 ps |
| CPU time | 82.91 seconds |
| Started | Aug 23 10:53:03 AM UTC 24 |
| Finished | Aug 23 10:54:27 AM UTC 24 |
| Peak memory | 285936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126 7757184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_address.1267757184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1657169533 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 701640600 ps |
| CPU time | 52.28 seconds |
| Started | Aug 23 10:52:16 AM UTC 24 |
| Finished | Aug 23 10:53:10 AM UTC 24 |
| Peak memory | 285632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 57169533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se rr_counter.1657169533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1131440574 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2697187400 ps |
| CPU time | 104.13 seconds |
| Started | Aug 23 10:45:21 AM UTC 24 |
| Finished | Aug 23 10:47:07 AM UTC 24 |
| Peak memory | 291476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131440574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1131440574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.3605236513 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 18710300 ps |
| CPU time | 28.76 seconds |
| Started | Aug 23 10:45:33 AM UTC 24 |
| Finished | Aug 23 10:46:03 AM UTC 24 |
| Peak memory | 271120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605236513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3605236513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1466215520 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 556145700 ps |
| CPU time | 679.22 seconds |
| Started | Aug 23 10:57:11 AM UTC 24 |
| Finished | Aug 23 11:08:37 AM UTC 24 |
| Peak memory | 291472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466215520 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.1466215520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1613280193 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 36696900 ps |
| CPU time | 29.26 seconds |
| Started | Aug 23 10:45:35 AM UTC 24 |
| Finished | Aug 23 10:46:06 AM UTC 24 |
| Peak memory | 271188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613280193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1613280193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.2222118405 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2379738600 ps |
| CPU time | 122.75 seconds |
| Started | Aug 23 10:49:43 AM UTC 24 |
| Finished | Aug 23 10:51:48 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2222118405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.2222118405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.589134606 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 26633700 ps |
| CPU time | 14.63 seconds |
| Started | Aug 23 12:08:10 PM UTC 24 |
| Finished | Aug 23 12:08:27 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589134606 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.589134606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.1663266445 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 28386700 ps |
| CPU time | 14.49 seconds |
| Started | Aug 23 12:08:07 PM UTC 24 |
| Finished | Aug 23 12:08:23 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663266445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1663266445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.561136720 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 13392200 ps |
| CPU time | 23.25 seconds |
| Started | Aug 23 12:08:02 PM UTC 24 |
| Finished | Aug 23 12:08:26 PM UTC 24 |
| Peak memory | 285540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=561136720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_disable.561136720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.1783240799 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 935369100 ps |
| CPU time | 69.84 seconds |
| Started | Aug 23 12:07:45 PM UTC 24 |
| Finished | Aug 23 12:08:57 PM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783240799 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.1783240799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.1056979529 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2458888300 ps |
| CPU time | 103.64 seconds |
| Started | Aug 23 12:07:55 PM UTC 24 |
| Finished | Aug 23 12:09:41 PM UTC 24 |
| Peak memory | 306376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056979529 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.1056979529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2344951719 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 12943388500 ps |
| CPU time | 124.81 seconds |
| Started | Aug 23 12:07:57 PM UTC 24 |
| Finished | Aug 23 12:10:04 PM UTC 24 |
| Peak memory | 303900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2344951719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.flash_ctrl_intr_rd_slow_flash.2344951719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.1999286205 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 43049200 ps |
| CPU time | 121.01 seconds |
| Started | Aug 23 12:07:50 PM UTC 24 |
| Finished | Aug 23 12:09:53 PM UTC 24 |
| Peak memory | 271616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999286205 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.1999286205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.1808124455 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 30347700 ps |
| CPU time | 30.57 seconds |
| Started | Aug 23 12:08:01 PM UTC 24 |
| Finished | Aug 23 12:08:32 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1808124455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_rw_evict_all_en.1808124455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.3813268169 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1070052700 ps |
| CPU time | 57.44 seconds |
| Started | Aug 23 12:08:05 PM UTC 24 |
| Finished | Aug 23 12:09:04 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813268169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.3813268169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.39675292 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 263582700 ps |
| CPU time | 181.39 seconds |
| Started | Aug 23 12:07:42 PM UTC 24 |
| Finished | Aug 23 12:10:46 PM UTC 24 |
| Peak memory | 289476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39675292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.39675292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.3180374530 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 159942600 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 12:08:40 PM UTC 24 |
| Finished | Aug 23 12:09:03 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180374530 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.3180374530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.1535346073 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 15692800 ps |
| CPU time | 17.12 seconds |
| Started | Aug 23 12:08:38 PM UTC 24 |
| Finished | Aug 23 12:09:06 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535346073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1535346073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1555484060 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 28386500 ps |
| CPU time | 23.44 seconds |
| Started | Aug 23 12:08:33 PM UTC 24 |
| Finished | Aug 23 12:09:04 PM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1555484060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ ctrl_disable.1555484060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.3500247960 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4433428100 ps |
| CPU time | 85.18 seconds |
| Started | Aug 23 12:08:13 PM UTC 24 |
| Finished | Aug 23 12:09:45 PM UTC 24 |
| Peak memory | 272976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500247960 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.3500247960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.3239262958 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 9277796200 ps |
| CPU time | 116.82 seconds |
| Started | Aug 23 12:08:24 PM UTC 24 |
| Finished | Aug 23 12:10:28 PM UTC 24 |
| Peak memory | 306084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239262958 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.3239262958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.908089708 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 6035709400 ps |
| CPU time | 113.43 seconds |
| Started | Aug 23 12:08:25 PM UTC 24 |
| Finished | Aug 23 12:10:27 PM UTC 24 |
| Peak memory | 303928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=908089708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 31.flash_ctrl_intr_rd_slow_flash.908089708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2975721276 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 462501400 ps |
| CPU time | 146.06 seconds |
| Started | Aug 23 12:08:18 PM UTC 24 |
| Finished | Aug 23 12:10:53 PM UTC 24 |
| Peak memory | 273464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975721276 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2975721276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.2763579496 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 33336600 ps |
| CPU time | 31.55 seconds |
| Started | Aug 23 12:08:27 PM UTC 24 |
| Finished | Aug 23 12:09:06 PM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763579496 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.2763579496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.167353405 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 90587300 ps |
| CPU time | 32.23 seconds |
| Started | Aug 23 12:08:28 PM UTC 24 |
| Finished | Aug 23 12:09:07 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=167353405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ct rl_rw_evict_all_en.167353405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.162294078 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2074547700 ps |
| CPU time | 66.46 seconds |
| Started | Aug 23 12:08:34 PM UTC 24 |
| Finished | Aug 23 12:09:49 PM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162294078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.162294078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.1427940522 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 36051900 ps |
| CPU time | 134.96 seconds |
| Started | Aug 23 12:08:10 PM UTC 24 |
| Finished | Aug 23 12:10:29 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427940522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1427940522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.1813879132 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 113920200 ps |
| CPU time | 14.6 seconds |
| Started | Aug 23 12:09:09 PM UTC 24 |
| Finished | Aug 23 12:09:25 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813879132 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.1813879132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.543926151 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 17986600 ps |
| CPU time | 17.29 seconds |
| Started | Aug 23 12:09:08 PM UTC 24 |
| Finished | Aug 23 12:09:27 PM UTC 24 |
| Peak memory | 284956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543926151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.543926151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.315982052 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 10548800 ps |
| CPU time | 23.3 seconds |
| Started | Aug 23 12:09:05 PM UTC 24 |
| Finished | Aug 23 12:09:31 PM UTC 24 |
| Peak memory | 285544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=315982052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_disable.315982052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.452486595 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 11048256200 ps |
| CPU time | 120.52 seconds |
| Started | Aug 23 12:08:54 PM UTC 24 |
| Finished | Aug 23 12:10:56 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452486595 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.452486595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.176480747 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 27839271800 ps |
| CPU time | 181.8 seconds |
| Started | Aug 23 12:08:57 PM UTC 24 |
| Finished | Aug 23 12:12:03 PM UTC 24 |
| Peak memory | 302024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176480747 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.176480747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3509556919 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 11313548900 ps |
| CPU time | 113.59 seconds |
| Started | Aug 23 12:09:03 PM UTC 24 |
| Finished | Aug 23 12:11:00 PM UTC 24 |
| Peak memory | 306048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3509556919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.flash_ctrl_intr_rd_slow_flash.3509556919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.4084050118 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 71387500 ps |
| CPU time | 144.54 seconds |
| Started | Aug 23 12:08:56 PM UTC 24 |
| Finished | Aug 23 12:11:23 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084050118 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.4084050118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.3993417695 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 75516100 ps |
| CPU time | 32.3 seconds |
| Started | Aug 23 12:09:05 PM UTC 24 |
| Finished | Aug 23 12:09:40 PM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3993417695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_rw_evict_all_en.3993417695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.4242170639 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2072908900 ps |
| CPU time | 67.7 seconds |
| Started | Aug 23 12:09:08 PM UTC 24 |
| Finished | Aug 23 12:10:18 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242170639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.4242170639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.3687928921 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 27317700 ps |
| CPU time | 129.97 seconds |
| Started | Aug 23 12:08:50 PM UTC 24 |
| Finished | Aug 23 12:11:04 PM UTC 24 |
| Peak memory | 287384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687928921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3687928921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.908100440 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 25612100 ps |
| CPU time | 14.18 seconds |
| Started | Aug 23 12:09:48 PM UTC 24 |
| Finished | Aug 23 12:10:07 PM UTC 24 |
| Peak memory | 269032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908100440 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.908100440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.4052649648 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 175154800 ps |
| CPU time | 17.15 seconds |
| Started | Aug 23 12:09:46 PM UTC 24 |
| Finished | Aug 23 12:10:07 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052649648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.4052649648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.805443709 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 36687600 ps |
| CPU time | 23.13 seconds |
| Started | Aug 23 12:09:41 PM UTC 24 |
| Finished | Aug 23 12:10:07 PM UTC 24 |
| Peak memory | 285484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=805443709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c trl_disable.805443709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.3243398967 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3890537000 ps |
| CPU time | 114.71 seconds |
| Started | Aug 23 12:09:16 PM UTC 24 |
| Finished | Aug 23 12:11:13 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243398967 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.3243398967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3423536191 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 783374200 ps |
| CPU time | 111.42 seconds |
| Started | Aug 23 12:09:26 PM UTC 24 |
| Finished | Aug 23 12:11:21 PM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423536191 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.3423536191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4042839313 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 13540461200 ps |
| CPU time | 237.96 seconds |
| Started | Aug 23 12:09:28 PM UTC 24 |
| Finished | Aug 23 12:13:30 PM UTC 24 |
| Peak memory | 296448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4042839313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.flash_ctrl_intr_rd_slow_flash.4042839313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.2910701643 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 50932700 ps |
| CPU time | 118.69 seconds |
| Started | Aug 23 12:09:25 PM UTC 24 |
| Finished | Aug 23 12:11:27 PM UTC 24 |
| Peak memory | 271032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910701643 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.2910701643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.2112154571 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 81553100 ps |
| CPU time | 30.22 seconds |
| Started | Aug 23 12:09:41 PM UTC 24 |
| Finished | Aug 23 12:10:14 PM UTC 24 |
| Peak memory | 287940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2112154571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c trl_rw_evict_all_en.2112154571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.3644275260 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 4728251200 ps |
| CPU time | 64.31 seconds |
| Started | Aug 23 12:09:42 PM UTC 24 |
| Finished | Aug 23 12:10:49 PM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644275260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.3644275260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.4175040473 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2805238400 ps |
| CPU time | 130.26 seconds |
| Started | Aug 23 12:09:09 PM UTC 24 |
| Finished | Aug 23 12:11:22 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175040473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4175040473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.1944614759 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 40240800 ps |
| CPU time | 14.71 seconds |
| Started | Aug 23 12:10:28 PM UTC 24 |
| Finished | Aug 23 12:10:44 PM UTC 24 |
| Peak memory | 269256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944614759 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.1944614759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.2867717452 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 15718300 ps |
| CPU time | 17.06 seconds |
| Started | Aug 23 12:10:19 PM UTC 24 |
| Finished | Aug 23 12:10:38 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867717452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2867717452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.695026064 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 20822400 ps |
| CPU time | 22.51 seconds |
| Started | Aug 23 12:10:08 PM UTC 24 |
| Finished | Aug 23 12:10:33 PM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=695026064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_disable.695026064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.2088516262 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 67913925900 ps |
| CPU time | 126.31 seconds |
| Started | Aug 23 12:09:53 PM UTC 24 |
| Finished | Aug 23 12:12:05 PM UTC 24 |
| Peak memory | 275020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088516262 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.2088516262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2932577470 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 10954759700 ps |
| CPU time | 155.59 seconds |
| Started | Aug 23 12:10:05 PM UTC 24 |
| Finished | Aug 23 12:12:43 PM UTC 24 |
| Peak memory | 302184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932577470 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2932577470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2408344630 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 6783387900 ps |
| CPU time | 108.04 seconds |
| Started | Aug 23 12:10:08 PM UTC 24 |
| Finished | Aug 23 12:11:59 PM UTC 24 |
| Peak memory | 303904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2408344630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.2408344630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.714141991 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 42145700 ps |
| CPU time | 120.77 seconds |
| Started | Aug 23 12:09:54 PM UTC 24 |
| Finished | Aug 23 12:12:00 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714141991 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.714141991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.3250285683 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 30222900 ps |
| CPU time | 30.18 seconds |
| Started | Aug 23 12:10:08 PM UTC 24 |
| Finished | Aug 23 12:10:40 PM UTC 24 |
| Peak memory | 287940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3250285683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.3250285683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.38946707 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 39849500 ps |
| CPU time | 181.87 seconds |
| Started | Aug 23 12:09:49 PM UTC 24 |
| Finished | Aug 23 12:12:57 PM UTC 24 |
| Peak memory | 289472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38946707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.38946707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.3243889062 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 50477500 ps |
| CPU time | 14.71 seconds |
| Started | Aug 23 12:10:57 PM UTC 24 |
| Finished | Aug 23 12:11:14 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243889062 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.3243889062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.1709812101 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 13766500 ps |
| CPU time | 17.17 seconds |
| Started | Aug 23 12:10:53 PM UTC 24 |
| Finished | Aug 23 12:11:12 PM UTC 24 |
| Peak memory | 295208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709812101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1709812101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.1242658024 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 19792300 ps |
| CPU time | 22.99 seconds |
| Started | Aug 23 12:10:47 PM UTC 24 |
| Finished | Aug 23 12:11:11 PM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1242658024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ ctrl_disable.1242658024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.2251381976 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2093445600 ps |
| CPU time | 73.28 seconds |
| Started | Aug 23 12:10:29 PM UTC 24 |
| Finished | Aug 23 12:11:44 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251381976 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.2251381976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.2328581813 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 436183000 ps |
| CPU time | 93.25 seconds |
| Started | Aug 23 12:10:38 PM UTC 24 |
| Finished | Aug 23 12:12:14 PM UTC 24 |
| Peak memory | 306120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328581813 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.2328581813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3329344721 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 94831150000 ps |
| CPU time | 280.25 seconds |
| Started | Aug 23 12:10:41 PM UTC 24 |
| Finished | Aug 23 12:15:25 PM UTC 24 |
| Peak memory | 296452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3329344721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.flash_ctrl_intr_rd_slow_flash.3329344721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.3302552552 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 77149800 ps |
| CPU time | 145.42 seconds |
| Started | Aug 23 12:10:33 PM UTC 24 |
| Finished | Aug 23 12:13:01 PM UTC 24 |
| Peak memory | 271148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302552552 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.3302552552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.854910431 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 34974600 ps |
| CPU time | 33.15 seconds |
| Started | Aug 23 12:10:44 PM UTC 24 |
| Finished | Aug 23 12:11:18 PM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854910431 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.854910431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.220755457 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 66248200 ps |
| CPU time | 32.62 seconds |
| Started | Aug 23 12:10:45 PM UTC 24 |
| Finished | Aug 23 12:11:19 PM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=220755457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ct rl_rw_evict_all_en.220755457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.1327635770 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1943355000 ps |
| CPU time | 66.49 seconds |
| Started | Aug 23 12:10:50 PM UTC 24 |
| Finished | Aug 23 12:11:58 PM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327635770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1327635770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.3660978377 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 22052000 ps |
| CPU time | 54.43 seconds |
| Started | Aug 23 12:10:29 PM UTC 24 |
| Finished | Aug 23 12:11:25 PM UTC 24 |
| Peak memory | 285372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660978377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3660978377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.1632824710 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 47546100 ps |
| CPU time | 14.65 seconds |
| Started | Aug 23 12:11:23 PM UTC 24 |
| Finished | Aug 23 12:11:39 PM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632824710 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.1632824710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.1542933674 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 16172000 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 12:11:23 PM UTC 24 |
| Finished | Aug 23 12:11:39 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542933674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1542933674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.508618172 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 17051800 ps |
| CPU time | 24.19 seconds |
| Started | Aug 23 12:11:19 PM UTC 24 |
| Finished | Aug 23 12:11:45 PM UTC 24 |
| Peak memory | 285000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=508618172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_disable.508618172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.1839810490 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 1654677900 ps |
| CPU time | 50.9 seconds |
| Started | Aug 23 12:11:05 PM UTC 24 |
| Finished | Aug 23 12:12:04 PM UTC 24 |
| Peak memory | 270928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839810490 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.1839810490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.948195579 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2785354800 ps |
| CPU time | 106.98 seconds |
| Started | Aug 23 12:11:13 PM UTC 24 |
| Finished | Aug 23 12:13:04 PM UTC 24 |
| Peak memory | 301988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948195579 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.948195579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3952405099 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 50738902400 ps |
| CPU time | 265 seconds |
| Started | Aug 23 12:11:14 PM UTC 24 |
| Finished | Aug 23 12:15:45 PM UTC 24 |
| Peak memory | 293756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3952405099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.flash_ctrl_intr_rd_slow_flash.3952405099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.2654447064 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 42991700 ps |
| CPU time | 148.1 seconds |
| Started | Aug 23 12:11:13 PM UTC 24 |
| Finished | Aug 23 12:13:46 PM UTC 24 |
| Peak memory | 271552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654447064 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.2654447064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.665240531 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 28201300 ps |
| CPU time | 32.44 seconds |
| Started | Aug 23 12:11:15 PM UTC 24 |
| Finished | Aug 23 12:11:51 PM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665240531 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.665240531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.2482474434 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 446696600 ps |
| CPU time | 51.69 seconds |
| Started | Aug 23 12:11:22 PM UTC 24 |
| Finished | Aug 23 12:12:15 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482474434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2482474434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.286383530 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 37112700 ps |
| CPU time | 161.8 seconds |
| Started | Aug 23 12:11:01 PM UTC 24 |
| Finished | Aug 23 12:13:50 PM UTC 24 |
| Peak memory | 289736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286383530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.286383530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.3098189939 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 61796200 ps |
| CPU time | 14.48 seconds |
| Started | Aug 23 12:11:54 PM UTC 24 |
| Finished | Aug 23 12:12:10 PM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098189939 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.3098189939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.2921571698 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 16311300 ps |
| CPU time | 17.27 seconds |
| Started | Aug 23 12:11:52 PM UTC 24 |
| Finished | Aug 23 12:12:11 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921571698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2921571698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.1087147076 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 22218600 ps |
| CPU time | 23.43 seconds |
| Started | Aug 23 12:11:46 PM UTC 24 |
| Finished | Aug 23 12:12:11 PM UTC 24 |
| Peak memory | 285476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1087147076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ ctrl_disable.1087147076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.2580405179 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 29915919800 ps |
| CPU time | 71.74 seconds |
| Started | Aug 23 12:11:26 PM UTC 24 |
| Finished | Aug 23 12:12:40 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580405179 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.2580405179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.775082339 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1755299700 ps |
| CPU time | 162.75 seconds |
| Started | Aug 23 12:11:32 PM UTC 24 |
| Finished | Aug 23 12:14:19 PM UTC 24 |
| Peak memory | 301924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775082339 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.775082339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2969938722 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 9121161400 ps |
| CPU time | 181.79 seconds |
| Started | Aug 23 12:11:39 PM UTC 24 |
| Finished | Aug 23 12:14:44 PM UTC 24 |
| Peak memory | 303996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2969938722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.flash_ctrl_intr_rd_slow_flash.2969938722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.1482975640 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 73787600 ps |
| CPU time | 144.85 seconds |
| Started | Aug 23 12:11:27 PM UTC 24 |
| Finished | Aug 23 12:13:55 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482975640 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.1482975640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.1611880004 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 29605900 ps |
| CPU time | 32.91 seconds |
| Started | Aug 23 12:11:46 PM UTC 24 |
| Finished | Aug 23 12:12:21 PM UTC 24 |
| Peak memory | 287940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1611880004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c trl_rw_evict_all_en.1611880004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2268371324 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 6714367300 ps |
| CPU time | 63.46 seconds |
| Started | Aug 23 12:11:52 PM UTC 24 |
| Finished | Aug 23 12:12:58 PM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268371324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2268371324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.247772996 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 45140700 ps |
| CPU time | 129.95 seconds |
| Started | Aug 23 12:11:24 PM UTC 24 |
| Finished | Aug 23 12:13:37 PM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247772996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.247772996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.1388035061 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 108434300 ps |
| CPU time | 14.78 seconds |
| Started | Aug 23 12:12:15 PM UTC 24 |
| Finished | Aug 23 12:12:31 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388035061 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.1388035061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.4176603498 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 218786100 ps |
| CPU time | 17.38 seconds |
| Started | Aug 23 12:12:15 PM UTC 24 |
| Finished | Aug 23 12:12:34 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176603498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.4176603498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.4096465025 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 11237900 ps |
| CPU time | 23.04 seconds |
| Started | Aug 23 12:12:12 PM UTC 24 |
| Finished | Aug 23 12:12:37 PM UTC 24 |
| Peak memory | 274976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4096465025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ ctrl_disable.4096465025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.1957366176 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 8775763700 ps |
| CPU time | 147.31 seconds |
| Started | Aug 23 12:12:00 PM UTC 24 |
| Finished | Aug 23 12:14:29 PM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957366176 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.1957366176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.3390199842 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2780657600 ps |
| CPU time | 103.59 seconds |
| Started | Aug 23 12:12:04 PM UTC 24 |
| Finished | Aug 23 12:13:50 PM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390199842 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.3390199842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1743668881 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 5759655300 ps |
| CPU time | 138.49 seconds |
| Started | Aug 23 12:12:04 PM UTC 24 |
| Finished | Aug 23 12:14:25 PM UTC 24 |
| Peak memory | 304156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1743668881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.flash_ctrl_intr_rd_slow_flash.1743668881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.807281988 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 37979000 ps |
| CPU time | 120.65 seconds |
| Started | Aug 23 12:12:01 PM UTC 24 |
| Finished | Aug 23 12:14:04 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807281988 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.807281988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.3179259175 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 42123800 ps |
| CPU time | 32.47 seconds |
| Started | Aug 23 12:12:06 PM UTC 24 |
| Finished | Aug 23 12:12:40 PM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179259175 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.3179259175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2651307613 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2826918200 ps |
| CPU time | 69.87 seconds |
| Started | Aug 23 12:12:12 PM UTC 24 |
| Finished | Aug 23 12:13:24 PM UTC 24 |
| Peak memory | 274652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651307613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2651307613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.319225223 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 422315200 ps |
| CPU time | 180.74 seconds |
| Started | Aug 23 12:12:00 PM UTC 24 |
| Finished | Aug 23 12:15:03 PM UTC 24 |
| Peak memory | 289672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319225223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.319225223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.2840738602 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 167375000 ps |
| CPU time | 15.01 seconds |
| Started | Aug 23 12:12:57 PM UTC 24 |
| Finished | Aug 23 12:13:14 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840738602 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.2840738602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2738374903 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 16289800 ps |
| CPU time | 17.09 seconds |
| Started | Aug 23 12:12:44 PM UTC 24 |
| Finished | Aug 23 12:13:03 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738374903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2738374903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.3470077992 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 23616600 ps |
| CPU time | 23.25 seconds |
| Started | Aug 23 12:12:41 PM UTC 24 |
| Finished | Aug 23 12:13:06 PM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3470077992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ ctrl_disable.3470077992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.1289178970 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2958321700 ps |
| CPU time | 71.82 seconds |
| Started | Aug 23 12:12:22 PM UTC 24 |
| Finished | Aug 23 12:13:36 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289178970 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.1289178970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.2408932769 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 2541040900 ps |
| CPU time | 163.81 seconds |
| Started | Aug 23 12:12:31 PM UTC 24 |
| Finished | Aug 23 12:15:19 PM UTC 24 |
| Peak memory | 301924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408932769 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.2408932769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1208645456 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 11892094700 ps |
| CPU time | 122.76 seconds |
| Started | Aug 23 12:12:34 PM UTC 24 |
| Finished | Aug 23 12:14:40 PM UTC 24 |
| Peak memory | 306048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1208645456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.1208645456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.2562246398 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 368705100 ps |
| CPU time | 147.03 seconds |
| Started | Aug 23 12:12:24 PM UTC 24 |
| Finished | Aug 23 12:14:55 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562246398 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.2562246398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.181970215 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 32763600 ps |
| CPU time | 32.8 seconds |
| Started | Aug 23 12:12:38 PM UTC 24 |
| Finished | Aug 23 12:13:13 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181970215 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.181970215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.1591323220 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 43111700 ps |
| CPU time | 30.06 seconds |
| Started | Aug 23 12:12:41 PM UTC 24 |
| Finished | Aug 23 12:13:13 PM UTC 24 |
| Peak memory | 288028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1591323220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c trl_rw_evict_all_en.1591323220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.1979474034 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 5891474400 ps |
| CPU time | 60.46 seconds |
| Started | Aug 23 12:12:44 PM UTC 24 |
| Finished | Aug 23 12:13:47 PM UTC 24 |
| Peak memory | 271000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979474034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1979474034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.2896619144 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 123611000 ps |
| CPU time | 80.04 seconds |
| Started | Aug 23 12:12:16 PM UTC 24 |
| Finished | Aug 23 12:13:38 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896619144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2896619144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.3790157112 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 115454500 ps |
| CPU time | 14.63 seconds |
| Started | Aug 23 11:08:54 AM UTC 24 |
| Finished | Aug 23 11:09:10 AM UTC 24 |
| Peak memory | 269312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790157112 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3790157112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3658129553 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 36795200 ps |
| CPU time | 14.76 seconds |
| Started | Aug 23 11:08:38 AM UTC 24 |
| Finished | Aug 23 11:08:54 AM UTC 24 |
| Peak memory | 275108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658129553 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.3658129553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3220922759 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 12929800 ps |
| CPU time | 14.43 seconds |
| Started | Aug 23 11:08:09 AM UTC 24 |
| Finished | Aug 23 11:08:24 AM UTC 24 |
| Peak memory | 294852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220922759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3220922759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.1657675949 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 783189700 ps |
| CPU time | 174.73 seconds |
| Started | Aug 23 11:04:37 AM UTC 24 |
| Finished | Aug 23 11:07:34 AM UTC 24 |
| Peak memory | 289700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1657675949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.1657675949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.1147792167 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 41560700 ps |
| CPU time | 23.68 seconds |
| Started | Aug 23 11:07:36 AM UTC 24 |
| Finished | Aug 23 11:08:01 AM UTC 24 |
| Peak memory | 285480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1147792167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_disable.1147792167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2489215479 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 12400085800 ps |
| CPU time | 653.93 seconds |
| Started | Aug 23 10:58:49 AM UTC 24 |
| Finished | Aug 23 11:09:50 AM UTC 24 |
| Peak memory | 276184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489215479 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2489215479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.221434141 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4486315200 ps |
| CPU time | 2467.6 seconds |
| Started | Aug 23 11:00:36 AM UTC 24 |
| Finished | Aug 23 11:42:07 AM UTC 24 |
| Peak memory | 275880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221434141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.221434141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.3279031623 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1817528700 ps |
| CPU time | 1819.24 seconds |
| Started | Aug 23 10:59:54 AM UTC 24 |
| Finished | Aug 23 11:30:30 AM UTC 24 |
| Peak memory | 277992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 79031623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _error_prog_type.3279031623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.559358656 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 656431500 ps |
| CPU time | 914.67 seconds |
| Started | Aug 23 11:00:33 AM UTC 24 |
| Finished | Aug 23 11:15:57 AM UTC 24 |
| Peak memory | 286492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559358656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.559358656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1102584248 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1474168100 ps |
| CPU time | 25.31 seconds |
| Started | Aug 23 10:59:27 AM UTC 24 |
| Finished | Aug 23 10:59:53 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 02584248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.1102584248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.800884560 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 307608300 ps |
| CPU time | 35 seconds |
| Started | Aug 23 11:08:10 AM UTC 24 |
| Finished | Aug 23 11:08:47 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8008845 60 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fs _sup.800884560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.4092124683 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 330658988900 ps |
| CPU time | 2192.01 seconds |
| Started | Aug 23 10:59:49 AM UTC 24 |
| Finished | Aug 23 11:36:42 AM UTC 24 |
| Peak memory | 288124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092124683 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.4092124683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3336631344 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 465679384300 ps |
| CPU time | 2177.34 seconds |
| Started | Aug 23 10:59:20 AM UTC 24 |
| Finished | Aug 23 11:35:58 AM UTC 24 |
| Peak memory | 277984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336631344 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3336631344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.9495285 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 17637000 ps |
| CPU time | 25.72 seconds |
| Started | Aug 23 10:58:21 AM UTC 24 |
| Finished | Aug 23 10:58:48 AM UTC 24 |
| Peak memory | 273408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9495285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ba se_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.9495285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3092637374 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 10012710700 ps |
| CPU time | 95.16 seconds |
| Started | Aug 23 11:08:47 AM UTC 24 |
| Finished | Aug 23 11:10:24 AM UTC 24 |
| Peak memory | 277456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3092637374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3092637374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1603063373 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 18838000 ps |
| CPU time | 14.43 seconds |
| Started | Aug 23 11:08:47 AM UTC 24 |
| Finished | Aug 23 11:09:03 AM UTC 24 |
| Peak memory | 275668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1603063373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1603063373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.707457083 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 60130388400 ps |
| CPU time | 738.29 seconds |
| Started | Aug 23 10:59:07 AM UTC 24 |
| Finished | Aug 23 11:11:33 AM UTC 24 |
| Peak memory | 277768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707457083 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.707457083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.2672177043 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5876483300 ps |
| CPU time | 101.94 seconds |
| Started | Aug 23 10:58:48 AM UTC 24 |
| Finished | Aug 23 11:00:32 AM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672177043 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.2672177043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.3302820920 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 27434038200 ps |
| CPU time | 425.2 seconds |
| Started | Aug 23 11:04:56 AM UTC 24 |
| Finished | Aug 23 11:12:06 AM UTC 24 |
| Peak memory | 336836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3302820920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr ity.3302820920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.976671636 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 50215399600 ps |
| CPU time | 272.82 seconds |
| Started | Aug 23 11:06:33 AM UTC 24 |
| Finished | Aug 23 11:11:09 AM UTC 24 |
| Peak memory | 293660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=976671636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_rd_slow_flash.976671636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.225178074 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 13383860500 ps |
| CPU time | 65.71 seconds |
| Started | Aug 23 11:06:28 AM UTC 24 |
| Finished | Aug 23 11:07:35 AM UTC 24 |
| Peak memory | 275244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225178074 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.225178074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2545103521 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48018363000 ps |
| CPU time | 179.1 seconds |
| Started | Aug 23 11:06:48 AM UTC 24 |
| Finished | Aug 23 11:09:50 AM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545103521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2545103521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1407777165 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1820459700 ps |
| CPU time | 73.67 seconds |
| Started | Aug 23 11:01:32 AM UTC 24 |
| Finished | Aug 23 11:02:48 AM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407777165 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1407777165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3077855240 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 26626600 ps |
| CPU time | 14.42 seconds |
| Started | Aug 23 11:08:42 AM UTC 24 |
| Finished | Aug 23 11:08:58 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3077855240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_lcmgr_intg.3077855240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.557500511 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 30405082000 ps |
| CPU time | 416.51 seconds |
| Started | Aug 23 10:59:25 AM UTC 24 |
| Finished | Aug 23 11:06:27 AM UTC 24 |
| Peak memory | 283420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=557500511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_mp_regions.557500511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.1326504515 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5842692800 ps |
| CPU time | 165.38 seconds |
| Started | Aug 23 11:04:43 AM UTC 24 |
| Finished | Aug 23 11:07:31 AM UTC 24 |
| Peak memory | 306104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1326504515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1326504515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2428291700 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25283700 ps |
| CPU time | 14.97 seconds |
| Started | Aug 23 11:08:30 AM UTC 24 |
| Finished | Aug 23 11:08:46 AM UTC 24 |
| Peak memory | 293384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428291700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2428291700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3155377897 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 74761300 ps |
| CPU time | 165.07 seconds |
| Started | Aug 23 10:58:44 AM UTC 24 |
| Finished | Aug 23 11:01:31 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155377897 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3155377897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.605712719 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 24826200 ps |
| CPU time | 15.2 seconds |
| Started | Aug 23 11:08:25 AM UTC 24 |
| Finished | Aug 23 11:08:41 AM UTC 24 |
| Peak memory | 273728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=605712719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.605712719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1127887491 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2276903000 ps |
| CPU time | 153.28 seconds |
| Started | Aug 23 11:06:57 AM UTC 24 |
| Finished | Aug 23 11:09:33 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127887491 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.1127887491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1884069589 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 66718500 ps |
| CPU time | 359.37 seconds |
| Started | Aug 23 10:58:15 AM UTC 24 |
| Finished | Aug 23 11:04:20 AM UTC 24 |
| Peak memory | 285380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884069589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1884069589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3525998150 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1522174400 ps |
| CPU time | 116.5 seconds |
| Started | Aug 23 10:58:37 AM UTC 24 |
| Finished | Aug 23 11:00:35 AM UTC 24 |
| Peak memory | 273088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525998150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3525998150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2510817369 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 78453700 ps |
| CPU time | 36.59 seconds |
| Started | Aug 23 11:07:35 AM UTC 24 |
| Finished | Aug 23 11:08:13 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510817369 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.2510817369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3584271438 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 27995200 ps |
| CPU time | 24.47 seconds |
| Started | Aug 23 11:04:17 AM UTC 24 |
| Finished | Aug 23 11:04:42 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3584271438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_read_word_sweep_derr.3584271438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.10423624 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 79431700 ps |
| CPU time | 22.7 seconds |
| Started | Aug 23 11:02:49 AM UTC 24 |
| Finished | Aug 23 11:03:13 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10423624 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.10423624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.3738256697 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1456583000 ps |
| CPU time | 70.28 seconds |
| Started | Aug 23 11:02:00 AM UTC 24 |
| Finished | Aug 23 11:03:12 AM UTC 24 |
| Peak memory | 307840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3738256697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.3738256697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3969240505 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2387666700 ps |
| CPU time | 128.44 seconds |
| Started | Aug 23 11:04:21 AM UTC 24 |
| Finished | Aug 23 11:06:32 AM UTC 24 |
| Peak memory | 291776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969240505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3969240505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.2421389851 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1163196500 ps |
| CPU time | 97.02 seconds |
| Started | Aug 23 11:02:57 AM UTC 24 |
| Finished | Aug 23 11:04:36 AM UTC 24 |
| Peak memory | 306084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2421389851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_ro_serr.2421389851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3007607033 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 13281909000 ps |
| CPU time | 450.55 seconds |
| Started | Aug 23 11:02:33 AM UTC 24 |
| Finished | Aug 23 11:10:09 AM UTC 24 |
| Peak memory | 320336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007607033 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.3007607033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.3240278372 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 30350633900 ps |
| CPU time | 189.29 seconds |
| Started | Aug 23 11:04:22 AM UTC 24 |
| Finished | Aug 23 11:07:34 AM UTC 24 |
| Peak memory | 299972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3240278372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_rw_derr.3240278372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3132355666 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 78663100 ps |
| CPU time | 34.02 seconds |
| Started | Aug 23 11:07:32 AM UTC 24 |
| Finished | Aug 23 11:08:07 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132355666 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.3132355666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2174738055 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 42530300 ps |
| CPU time | 32.41 seconds |
| Started | Aug 23 11:07:35 AM UTC 24 |
| Finished | Aug 23 11:08:09 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2174738055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_rw_evict_all_en.2174738055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.1367672880 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1927122100 ps |
| CPU time | 166.12 seconds |
| Started | Aug 23 11:03:08 AM UTC 24 |
| Finished | Aug 23 11:05:57 AM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1367672880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.1367672880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.964631884 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 5777333700 ps |
| CPU time | 5458.14 seconds |
| Started | Aug 23 11:07:51 AM UTC 24 |
| Finished | Aug 23 12:39:42 PM UTC 24 |
| Peak memory | 312372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964631884 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.964631884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2591136564 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1517216200 ps |
| CPU time | 62.45 seconds |
| Started | Aug 23 11:08:01 AM UTC 24 |
| Finished | Aug 23 11:09:05 AM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591136564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2591136564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3235599440 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2125074200 ps |
| CPU time | 60.9 seconds |
| Started | Aug 23 11:03:13 AM UTC 24 |
| Finished | Aug 23 11:04:16 AM UTC 24 |
| Peak memory | 275392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323 5599440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.3235599440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.306001922 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1276371900 ps |
| CPU time | 101.17 seconds |
| Started | Aug 23 11:03:12 AM UTC 24 |
| Finished | Aug 23 11:04:55 AM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 6001922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_counter.306001922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.4273389622 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 18488200 ps |
| CPU time | 80.03 seconds |
| Started | Aug 23 10:58:04 AM UTC 24 |
| Finished | Aug 23 10:59:26 AM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273389622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4273389622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.4009216376 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 52353800 ps |
| CPU time | 28.22 seconds |
| Started | Aug 23 10:58:06 AM UTC 24 |
| Finished | Aug 23 10:58:36 AM UTC 24 |
| Peak memory | 270860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009216376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.4009216376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1188134022 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 114986400 ps |
| CPU time | 141.78 seconds |
| Started | Aug 23 11:08:09 AM UTC 24 |
| Finished | Aug 23 11:10:33 AM UTC 24 |
| Peak memory | 288892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188134022 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.1188134022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.332028965 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 20955500 ps |
| CPU time | 28.9 seconds |
| Started | Aug 23 10:58:16 AM UTC 24 |
| Finished | Aug 23 10:58:47 AM UTC 24 |
| Peak memory | 270872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332028965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.332028965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.327195550 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3765111200 ps |
| CPU time | 138.96 seconds |
| Started | Aug 23 11:02:00 AM UTC 24 |
| Finished | Aug 23 11:04:21 AM UTC 24 |
| Peak memory | 274844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =327195550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.327195550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1283885818 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 25795500 ps |
| CPU time | 14.49 seconds |
| Started | Aug 23 12:13:14 PM UTC 24 |
| Finished | Aug 23 12:13:30 PM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283885818 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.1283885818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.281466115 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 27118100 ps |
| CPU time | 14.42 seconds |
| Started | Aug 23 12:13:14 PM UTC 24 |
| Finished | Aug 23 12:13:30 PM UTC 24 |
| Peak memory | 295328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281466115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.281466115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.2373595077 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 20135000 ps |
| CPU time | 23.14 seconds |
| Started | Aug 23 12:13:05 PM UTC 24 |
| Finished | Aug 23 12:13:29 PM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2373595077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ ctrl_disable.2373595077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.4097999347 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2683915400 ps |
| CPU time | 62.19 seconds |
| Started | Aug 23 12:13:02 PM UTC 24 |
| Finished | Aug 23 12:14:06 PM UTC 24 |
| Peak memory | 273172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097999347 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.4097999347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.2299115607 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 39341600 ps |
| CPU time | 146.27 seconds |
| Started | Aug 23 12:13:04 PM UTC 24 |
| Finished | Aug 23 12:15:32 PM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299115607 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.2299115607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.1684220378 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 2132010700 ps |
| CPU time | 63.68 seconds |
| Started | Aug 23 12:13:07 PM UTC 24 |
| Finished | Aug 23 12:14:12 PM UTC 24 |
| Peak memory | 270996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684220378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1684220378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.2220012298 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 31396600 ps |
| CPU time | 178.86 seconds |
| Started | Aug 23 12:12:59 PM UTC 24 |
| Finished | Aug 23 12:16:01 PM UTC 24 |
| Peak memory | 287528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220012298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2220012298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.1361282061 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 153874200 ps |
| CPU time | 15.31 seconds |
| Started | Aug 23 12:13:37 PM UTC 24 |
| Finished | Aug 23 12:13:53 PM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361282061 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.1361282061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3606262010 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 17380800 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 12:13:31 PM UTC 24 |
| Finished | Aug 23 12:13:47 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606262010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3606262010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.3053830104 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 26984900 ps |
| CPU time | 23.38 seconds |
| Started | Aug 23 12:13:31 PM UTC 24 |
| Finished | Aug 23 12:13:56 PM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3053830104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ ctrl_disable.3053830104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.1512751313 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2158109800 ps |
| CPU time | 58.2 seconds |
| Started | Aug 23 12:13:25 PM UTC 24 |
| Finished | Aug 23 12:14:25 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512751313 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.1512751313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.2168306039 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 38917500 ps |
| CPU time | 146.67 seconds |
| Started | Aug 23 12:13:31 PM UTC 24 |
| Finished | Aug 23 12:16:00 PM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168306039 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.2168306039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.2467770059 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 5880502500 ps |
| CPU time | 63.37 seconds |
| Started | Aug 23 12:13:31 PM UTC 24 |
| Finished | Aug 23 12:14:36 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467770059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2467770059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.3480759007 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 109757800 ps |
| CPU time | 129.05 seconds |
| Started | Aug 23 12:13:14 PM UTC 24 |
| Finished | Aug 23 12:15:26 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480759007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3480759007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.3422339963 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 168150800 ps |
| CPU time | 14.52 seconds |
| Started | Aug 23 12:13:51 PM UTC 24 |
| Finished | Aug 23 12:14:07 PM UTC 24 |
| Peak memory | 269384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422339963 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.3422339963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.2536976712 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 18694700 ps |
| CPU time | 17.42 seconds |
| Started | Aug 23 12:13:51 PM UTC 24 |
| Finished | Aug 23 12:14:09 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536976712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2536976712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.151899305 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 20376100 ps |
| CPU time | 22.99 seconds |
| Started | Aug 23 12:13:48 PM UTC 24 |
| Finished | Aug 23 12:14:12 PM UTC 24 |
| Peak memory | 285804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=151899305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_c trl_disable.151899305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.1528240009 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 11984490200 ps |
| CPU time | 199.6 seconds |
| Started | Aug 23 12:13:38 PM UTC 24 |
| Finished | Aug 23 12:17:01 PM UTC 24 |
| Peak memory | 276124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528240009 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.1528240009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.3388935875 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 77227900 ps |
| CPU time | 119.98 seconds |
| Started | Aug 23 12:13:46 PM UTC 24 |
| Finished | Aug 23 12:15:49 PM UTC 24 |
| Peak memory | 271208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388935875 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.3388935875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.3544044014 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1472577300 ps |
| CPU time | 54.71 seconds |
| Started | Aug 23 12:13:48 PM UTC 24 |
| Finished | Aug 23 12:14:44 PM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544044014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3544044014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3919422896 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 75464400 ps |
| CPU time | 76.15 seconds |
| Started | Aug 23 12:13:38 PM UTC 24 |
| Finished | Aug 23 12:14:56 PM UTC 24 |
| Peak memory | 277448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919422896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3919422896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.3596533028 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 103486400 ps |
| CPU time | 14.36 seconds |
| Started | Aug 23 12:14:07 PM UTC 24 |
| Finished | Aug 23 12:14:23 PM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596533028 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.3596533028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.758004303 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 13046400 ps |
| CPU time | 17.5 seconds |
| Started | Aug 23 12:14:07 PM UTC 24 |
| Finished | Aug 23 12:14:26 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758004303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.758004303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.3202700618 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 173821400 ps |
| CPU time | 23.41 seconds |
| Started | Aug 23 12:14:00 PM UTC 24 |
| Finished | Aug 23 12:14:24 PM UTC 24 |
| Peak memory | 285612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3202700618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ ctrl_disable.3202700618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.2739086857 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 1513209100 ps |
| CPU time | 36.04 seconds |
| Started | Aug 23 12:13:56 PM UTC 24 |
| Finished | Aug 23 12:14:34 PM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739086857 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.2739086857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1470247350 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 39252000 ps |
| CPU time | 145.78 seconds |
| Started | Aug 23 12:13:56 PM UTC 24 |
| Finished | Aug 23 12:16:24 PM UTC 24 |
| Peak memory | 271296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470247350 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.1470247350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.338467226 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 6614000000 ps |
| CPU time | 59.65 seconds |
| Started | Aug 23 12:14:05 PM UTC 24 |
| Finished | Aug 23 12:15:06 PM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338467226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.338467226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3145901881 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 47221400 ps |
| CPU time | 104.77 seconds |
| Started | Aug 23 12:13:54 PM UTC 24 |
| Finished | Aug 23 12:15:41 PM UTC 24 |
| Peak memory | 287688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145901881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3145901881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.3020632766 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 42310200 ps |
| CPU time | 14.63 seconds |
| Started | Aug 23 12:14:26 PM UTC 24 |
| Finished | Aug 23 12:14:42 PM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020632766 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.3020632766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.2926951794 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 34576700 ps |
| CPU time | 17.18 seconds |
| Started | Aug 23 12:14:25 PM UTC 24 |
| Finished | Aug 23 12:14:43 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926951794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2926951794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2680219317 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 10133200 ps |
| CPU time | 23.11 seconds |
| Started | Aug 23 12:14:20 PM UTC 24 |
| Finished | Aug 23 12:14:45 PM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2680219317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ ctrl_disable.2680219317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.1895886739 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 1550913700 ps |
| CPU time | 90.27 seconds |
| Started | Aug 23 12:14:13 PM UTC 24 |
| Finished | Aug 23 12:15:46 PM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895886739 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.1895886739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.4039176600 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 134697200 ps |
| CPU time | 118.72 seconds |
| Started | Aug 23 12:14:13 PM UTC 24 |
| Finished | Aug 23 12:16:15 PM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039176600 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.4039176600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.508041789 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1158258500 ps |
| CPU time | 58.73 seconds |
| Started | Aug 23 12:14:24 PM UTC 24 |
| Finished | Aug 23 12:15:24 PM UTC 24 |
| Peak memory | 273304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508041789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.508041789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.998089309 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 19915000 ps |
| CPU time | 76.11 seconds |
| Started | Aug 23 12:14:10 PM UTC 24 |
| Finished | Aug 23 12:15:28 PM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998089309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.998089309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.746911540 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 24416400 ps |
| CPU time | 14.35 seconds |
| Started | Aug 23 12:14:43 PM UTC 24 |
| Finished | Aug 23 12:14:59 PM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746911540 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.746911540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.3832770622 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 16987300 ps |
| CPU time | 17.32 seconds |
| Started | Aug 23 12:14:41 PM UTC 24 |
| Finished | Aug 23 12:15:00 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832770622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3832770622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.3228542552 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 15656600 ps |
| CPU time | 23.39 seconds |
| Started | Aug 23 12:14:35 PM UTC 24 |
| Finished | Aug 23 12:15:00 PM UTC 24 |
| Peak memory | 285484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3228542552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ ctrl_disable.3228542552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.76609451 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4613106500 ps |
| CPU time | 148.68 seconds |
| Started | Aug 23 12:14:27 PM UTC 24 |
| Finished | Aug 23 12:16:59 PM UTC 24 |
| Peak memory | 275028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76609451 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.76609451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.1487454849 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 76120300 ps |
| CPU time | 146.22 seconds |
| Started | Aug 23 12:14:30 PM UTC 24 |
| Finished | Aug 23 12:16:59 PM UTC 24 |
| Peak memory | 271100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487454849 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.1487454849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.3825592027 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 44976400 ps |
| CPU time | 235.11 seconds |
| Started | Aug 23 12:14:26 PM UTC 24 |
| Finished | Aug 23 12:18:25 PM UTC 24 |
| Peak memory | 292260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825592027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3825592027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.3412931574 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 53137700 ps |
| CPU time | 14.59 seconds |
| Started | Aug 23 12:14:59 PM UTC 24 |
| Finished | Aug 23 12:15:15 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412931574 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.3412931574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.3267257384 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 20777000 ps |
| CPU time | 17.31 seconds |
| Started | Aug 23 12:14:57 PM UTC 24 |
| Finished | Aug 23 12:15:16 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267257384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3267257384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.734476016 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 17630700 ps |
| CPU time | 23.05 seconds |
| Started | Aug 23 12:14:46 PM UTC 24 |
| Finished | Aug 23 12:15:10 PM UTC 24 |
| Peak memory | 285544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=734476016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_c trl_disable.734476016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.2996120274 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 22737485600 ps |
| CPU time | 52.75 seconds |
| Started | Aug 23 12:14:45 PM UTC 24 |
| Finished | Aug 23 12:15:39 PM UTC 24 |
| Peak memory | 272980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996120274 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.2996120274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.435926046 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 274460200 ps |
| CPU time | 145.36 seconds |
| Started | Aug 23 12:14:45 PM UTC 24 |
| Finished | Aug 23 12:17:13 PM UTC 24 |
| Peak memory | 274920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435926046 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.435926046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.2320342881 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 4227905800 ps |
| CPU time | 66.74 seconds |
| Started | Aug 23 12:14:56 PM UTC 24 |
| Finished | Aug 23 12:16:05 PM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320342881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2320342881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1615217142 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2852457400 ps |
| CPU time | 204.13 seconds |
| Started | Aug 23 12:14:45 PM UTC 24 |
| Finished | Aug 23 12:18:12 PM UTC 24 |
| Peak memory | 291784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615217142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1615217142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.3207429892 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 94696700 ps |
| CPU time | 14.49 seconds |
| Started | Aug 23 12:15:16 PM UTC 24 |
| Finished | Aug 23 12:15:32 PM UTC 24 |
| Peak memory | 269360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207429892 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.3207429892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.3808820308 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 13095500 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 12:15:16 PM UTC 24 |
| Finished | Aug 23 12:15:32 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808820308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3808820308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.2847516831 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 10481400 ps |
| CPU time | 22.97 seconds |
| Started | Aug 23 12:15:07 PM UTC 24 |
| Finished | Aug 23 12:15:32 PM UTC 24 |
| Peak memory | 275596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2847516831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ ctrl_disable.2847516831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.320070271 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 7904715800 ps |
| CPU time | 97.45 seconds |
| Started | Aug 23 12:15:01 PM UTC 24 |
| Finished | Aug 23 12:16:40 PM UTC 24 |
| Peak memory | 275032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320070271 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.320070271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.5080415 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 221721800 ps |
| CPU time | 145.51 seconds |
| Started | Aug 23 12:15:04 PM UTC 24 |
| Finished | Aug 23 12:17:33 PM UTC 24 |
| Peak memory | 271552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5080415 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.5080415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2756433930 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 2361285900 ps |
| CPU time | 56.87 seconds |
| Started | Aug 23 12:15:11 PM UTC 24 |
| Finished | Aug 23 12:16:10 PM UTC 24 |
| Peak memory | 275352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756433930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2756433930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.2050459438 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 35428300 ps |
| CPU time | 157.2 seconds |
| Started | Aug 23 12:15:01 PM UTC 24 |
| Finished | Aug 23 12:17:41 PM UTC 24 |
| Peak memory | 287748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050459438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2050459438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1063334301 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 53629000 ps |
| CPU time | 14.4 seconds |
| Started | Aug 23 12:15:34 PM UTC 24 |
| Finished | Aug 23 12:15:50 PM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063334301 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1063334301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.3719921794 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 21095400 ps |
| CPU time | 14.35 seconds |
| Started | Aug 23 12:15:32 PM UTC 24 |
| Finished | Aug 23 12:15:48 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719921794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3719921794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.2425026516 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 77439300 ps |
| CPU time | 23.28 seconds |
| Started | Aug 23 12:15:26 PM UTC 24 |
| Finished | Aug 23 12:15:51 PM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2425026516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.2425026516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.1465850988 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 839512600 ps |
| CPU time | 33.84 seconds |
| Started | Aug 23 12:15:25 PM UTC 24 |
| Finished | Aug 23 12:16:00 PM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465850988 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.1465850988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.895246186 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 43250300 ps |
| CPU time | 146.81 seconds |
| Started | Aug 23 12:15:26 PM UTC 24 |
| Finished | Aug 23 12:17:55 PM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895246186 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.895246186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.2773014761 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 4826268500 ps |
| CPU time | 58.29 seconds |
| Started | Aug 23 12:15:29 PM UTC 24 |
| Finished | Aug 23 12:16:29 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773014761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2773014761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3268941633 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 122548400 ps |
| CPU time | 103.06 seconds |
| Started | Aug 23 12:15:20 PM UTC 24 |
| Finished | Aug 23 12:17:05 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268941633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3268941633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1928270929 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 19053300 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 12:15:48 PM UTC 24 |
| Finished | Aug 23 12:16:03 PM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928270929 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.1928270929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1687019604 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 47451000 ps |
| CPU time | 17.27 seconds |
| Started | Aug 23 12:15:46 PM UTC 24 |
| Finished | Aug 23 12:16:04 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687019604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1687019604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1123012871 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 18578400 ps |
| CPU time | 22.08 seconds |
| Started | Aug 23 12:15:40 PM UTC 24 |
| Finished | Aug 23 12:16:04 PM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1123012871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ ctrl_disable.1123012871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.2205699789 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 901878100 ps |
| CPU time | 33.23 seconds |
| Started | Aug 23 12:15:34 PM UTC 24 |
| Finished | Aug 23 12:16:09 PM UTC 24 |
| Peak memory | 270932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205699789 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.2205699789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.3649744332 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 211471400 ps |
| CPU time | 119.52 seconds |
| Started | Aug 23 12:15:38 PM UTC 24 |
| Finished | Aug 23 12:17:40 PM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649744332 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.3649744332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.4135684484 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3358605600 ps |
| CPU time | 54.66 seconds |
| Started | Aug 23 12:15:41 PM UTC 24 |
| Finished | Aug 23 12:16:38 PM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135684484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.4135684484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.1989612846 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 46306400 ps |
| CPU time | 103.19 seconds |
| Started | Aug 23 12:15:34 PM UTC 24 |
| Finished | Aug 23 12:17:19 PM UTC 24 |
| Peak memory | 277184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989612846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1989612846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2775157748 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 48228700 ps |
| CPU time | 14.63 seconds |
| Started | Aug 23 11:13:29 AM UTC 24 |
| Finished | Aug 23 11:13:45 AM UTC 24 |
| Peak memory | 269292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775157748 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2775157748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.2369025305 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 74199600 ps |
| CPU time | 17.32 seconds |
| Started | Aug 23 11:13:11 AM UTC 24 |
| Finished | Aug 23 11:13:30 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369025305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2369025305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.2298119120 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 35043500 ps |
| CPU time | 23.12 seconds |
| Started | Aug 23 11:12:53 AM UTC 24 |
| Finished | Aug 23 11:13:17 AM UTC 24 |
| Peak memory | 285548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2298119120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c trl_disable.2298119120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.911599915 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 10667412000 ps |
| CPU time | 2355.43 seconds |
| Started | Aug 23 11:10:20 AM UTC 24 |
| Finished | Aug 23 11:49:59 AM UTC 24 |
| Peak memory | 277928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911599915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.911599915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2141742478 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3073051000 ps |
| CPU time | 985.14 seconds |
| Started | Aug 23 11:10:10 AM UTC 24 |
| Finished | Aug 23 11:26:45 AM UTC 24 |
| Peak memory | 288192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141742478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2141742478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.3793430977 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 687184300 ps |
| CPU time | 23.81 seconds |
| Started | Aug 23 11:09:59 AM UTC 24 |
| Finished | Aug 23 11:10:24 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 93430977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc h_code.3793430977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3561942848 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10019186100 ps |
| CPU time | 76.36 seconds |
| Started | Aug 23 11:13:20 AM UTC 24 |
| Finished | Aug 23 11:14:38 AM UTC 24 |
| Peak memory | 330516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3561942848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3561942848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.2895464515 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 48237800 ps |
| CPU time | 14.59 seconds |
| Started | Aug 23 11:13:18 AM UTC 24 |
| Finished | Aug 23 11:13:34 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2895464515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2895464515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.1985328004 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 80139660100 ps |
| CPU time | 750.27 seconds |
| Started | Aug 23 11:09:34 AM UTC 24 |
| Finished | Aug 23 11:22:12 AM UTC 24 |
| Peak memory | 277708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985328004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.1985328004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2215355880 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 14907095300 ps |
| CPU time | 103.53 seconds |
| Started | Aug 23 11:09:11 AM UTC 24 |
| Finished | Aug 23 11:10:56 AM UTC 24 |
| Peak memory | 272980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215355880 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.2215355880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.4157459373 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1696274700 ps |
| CPU time | 155.91 seconds |
| Started | Aug 23 11:11:34 AM UTC 24 |
| Finished | Aug 23 11:14:12 AM UTC 24 |
| Peak memory | 301920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157459373 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.4157459373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1443475766 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 9043596300 ps |
| CPU time | 119.93 seconds |
| Started | Aug 23 11:12:07 AM UTC 24 |
| Finished | Aug 23 11:14:09 AM UTC 24 |
| Peak memory | 306012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1443475766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_intr_rd_slow_flash.1443475766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.848670003 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 9024576800 ps |
| CPU time | 61.23 seconds |
| Started | Aug 23 11:11:50 AM UTC 24 |
| Finished | Aug 23 11:12:52 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848670003 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.848670003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3066543608 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 103863740500 ps |
| CPU time | 256.59 seconds |
| Started | Aug 23 11:12:19 AM UTC 24 |
| Finished | Aug 23 11:16:38 AM UTC 24 |
| Peak memory | 271140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066543608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3066543608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1111804245 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1008791500 ps |
| CPU time | 63.94 seconds |
| Started | Aug 23 11:10:21 AM UTC 24 |
| Finished | Aug 23 11:11:27 AM UTC 24 |
| Peak memory | 275064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111804245 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1111804245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.2452650092 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 15398500 ps |
| CPU time | 14.46 seconds |
| Started | Aug 23 11:13:12 AM UTC 24 |
| Finished | Aug 23 11:13:28 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2452650092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.2452650092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.56890864 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 26578055900 ps |
| CPU time | 887.76 seconds |
| Started | Aug 23 11:09:51 AM UTC 24 |
| Finished | Aug 23 11:24:48 AM UTC 24 |
| Peak memory | 286200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=56890864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.flash_ctrl_mp_regions.56890864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.986574822 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 131498300 ps |
| CPU time | 145.08 seconds |
| Started | Aug 23 11:09:51 AM UTC 24 |
| Finished | Aug 23 11:12:18 AM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986574822 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.986574822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2318521331 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 34208900 ps |
| CPU time | 71.26 seconds |
| Started | Aug 23 11:09:06 AM UTC 24 |
| Finished | Aug 23 11:10:19 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318521331 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2318521331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.864288247 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 72958000 ps |
| CPU time | 14.4 seconds |
| Started | Aug 23 11:12:21 AM UTC 24 |
| Finished | Aug 23 11:12:36 AM UTC 24 |
| Peak memory | 268984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864288247 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.864288247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2361780536 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 36732900 ps |
| CPU time | 53.08 seconds |
| Started | Aug 23 11:09:03 AM UTC 24 |
| Finished | Aug 23 11:09:58 AM UTC 24 |
| Peak memory | 273348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361780536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2361780536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1264505682 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 65504700 ps |
| CPU time | 35.27 seconds |
| Started | Aug 23 11:12:42 AM UTC 24 |
| Finished | Aug 23 11:13:19 AM UTC 24 |
| Peak memory | 288000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264505682 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.1264505682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1995389169 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 609352800 ps |
| CPU time | 115.53 seconds |
| Started | Aug 23 11:10:25 AM UTC 24 |
| Finished | Aug 23 11:12:23 AM UTC 24 |
| Peak memory | 302020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1995389169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.1995389169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2317795482 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4771450900 ps |
| CPU time | 140.58 seconds |
| Started | Aug 23 11:11:11 AM UTC 24 |
| Finished | Aug 23 11:13:34 AM UTC 24 |
| Peak memory | 291752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317795482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2317795482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.2254678547 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 10229215900 ps |
| CPU time | 104.39 seconds |
| Started | Aug 23 11:10:33 AM UTC 24 |
| Finished | Aug 23 11:12:20 AM UTC 24 |
| Peak memory | 306108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2254678547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_ro_serr.2254678547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3532282517 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3809441400 ps |
| CPU time | 379.16 seconds |
| Started | Aug 23 11:10:25 AM UTC 24 |
| Finished | Aug 23 11:16:49 AM UTC 24 |
| Peak memory | 330660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532282517 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.3532282517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.687003165 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3396217100 ps |
| CPU time | 154.34 seconds |
| Started | Aug 23 11:11:28 AM UTC 24 |
| Finished | Aug 23 11:14:05 AM UTC 24 |
| Peak memory | 294024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=687003165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_rw_derr.687003165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.489280723 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 66503000 ps |
| CPU time | 32.93 seconds |
| Started | Aug 23 11:12:24 AM UTC 24 |
| Finished | Aug 23 11:12:58 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489280723 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.489280723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.429653221 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2222389400 ps |
| CPU time | 130.88 seconds |
| Started | Aug 23 11:10:57 AM UTC 24 |
| Finished | Aug 23 11:13:11 AM UTC 24 |
| Peak memory | 306088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=429653221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.429653221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.1406638285 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1805730200 ps |
| CPU time | 53.63 seconds |
| Started | Aug 23 11:12:59 AM UTC 24 |
| Finished | Aug 23 11:13:54 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406638285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1406638285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.312151477 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 75982200 ps |
| CPU time | 80.65 seconds |
| Started | Aug 23 11:08:58 AM UTC 24 |
| Finished | Aug 23 11:10:21 AM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312151477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.312151477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2628144308 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2444259300 ps |
| CPU time | 134.62 seconds |
| Started | Aug 23 11:10:24 AM UTC 24 |
| Finished | Aug 23 11:12:41 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2628144308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.2628144308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.2996074657 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 31106600 ps |
| CPU time | 17.25 seconds |
| Started | Aug 23 12:15:50 PM UTC 24 |
| Finished | Aug 23 12:16:09 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996074657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2996074657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.2855835446 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 72550100 ps |
| CPU time | 120.45 seconds |
| Started | Aug 23 12:15:49 PM UTC 24 |
| Finished | Aug 23 12:17:52 PM UTC 24 |
| Peak memory | 271148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855835446 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.2855835446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.1466322077 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 18995200 ps |
| CPU time | 14.39 seconds |
| Started | Aug 23 12:15:51 PM UTC 24 |
| Finished | Aug 23 12:16:07 PM UTC 24 |
| Peak memory | 295396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466322077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1466322077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.3478152552 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 40281500 ps |
| CPU time | 147.64 seconds |
| Started | Aug 23 12:15:50 PM UTC 24 |
| Finished | Aug 23 12:18:20 PM UTC 24 |
| Peak memory | 273472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478152552 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.3478152552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.143969702 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 22392800 ps |
| CPU time | 17.31 seconds |
| Started | Aug 23 12:16:02 PM UTC 24 |
| Finished | Aug 23 12:16:20 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143969702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.143969702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1609576702 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 38662100 ps |
| CPU time | 146.01 seconds |
| Started | Aug 23 12:16:00 PM UTC 24 |
| Finished | Aug 23 12:18:29 PM UTC 24 |
| Peak memory | 271032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609576702 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.1609576702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.569811732 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 49638600 ps |
| CPU time | 17.08 seconds |
| Started | Aug 23 12:16:04 PM UTC 24 |
| Finished | Aug 23 12:16:23 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569811732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.569811732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1311781264 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 43141700 ps |
| CPU time | 146.24 seconds |
| Started | Aug 23 12:16:02 PM UTC 24 |
| Finished | Aug 23 12:18:31 PM UTC 24 |
| Peak memory | 270828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311781264 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.1311781264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.2352780757 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 13815000 ps |
| CPU time | 17.22 seconds |
| Started | Aug 23 12:16:05 PM UTC 24 |
| Finished | Aug 23 12:16:24 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352780757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2352780757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3833279577 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 96147700 ps |
| CPU time | 146.31 seconds |
| Started | Aug 23 12:16:05 PM UTC 24 |
| Finished | Aug 23 12:18:34 PM UTC 24 |
| Peak memory | 275436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833279577 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.3833279577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.4242792574 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 40295000 ps |
| CPU time | 17.04 seconds |
| Started | Aug 23 12:16:08 PM UTC 24 |
| Finished | Aug 23 12:16:26 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242792574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4242792574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.2486659467 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 441002500 ps |
| CPU time | 146.49 seconds |
| Started | Aug 23 12:16:05 PM UTC 24 |
| Finished | Aug 23 12:18:34 PM UTC 24 |
| Peak memory | 271104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486659467 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.2486659467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1669018509 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 26591700 ps |
| CPU time | 17.27 seconds |
| Started | Aug 23 12:16:10 PM UTC 24 |
| Finished | Aug 23 12:16:29 PM UTC 24 |
| Peak memory | 284956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669018509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1669018509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.2568465959 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 169880300 ps |
| CPU time | 146.72 seconds |
| Started | Aug 23 12:16:10 PM UTC 24 |
| Finished | Aug 23 12:18:40 PM UTC 24 |
| Peak memory | 275292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568465959 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.2568465959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.3129308601 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 23115400 ps |
| CPU time | 14.37 seconds |
| Started | Aug 23 12:16:16 PM UTC 24 |
| Finished | Aug 23 12:16:32 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129308601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3129308601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.2124677771 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 24814300 ps |
| CPU time | 17.2 seconds |
| Started | Aug 23 12:16:24 PM UTC 24 |
| Finished | Aug 23 12:16:42 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124677771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2124677771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3139895208 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 40824700 ps |
| CPU time | 145.59 seconds |
| Started | Aug 23 12:16:21 PM UTC 24 |
| Finished | Aug 23 12:18:49 PM UTC 24 |
| Peak memory | 275456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139895208 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.3139895208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.758958594 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 32834600 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 12:16:26 PM UTC 24 |
| Finished | Aug 23 12:16:41 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758958594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.758958594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1542241219 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 50495900 ps |
| CPU time | 145.18 seconds |
| Started | Aug 23 12:16:25 PM UTC 24 |
| Finished | Aug 23 12:18:52 PM UTC 24 |
| Peak memory | 270992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542241219 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.1542241219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3941288323 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 87512200 ps |
| CPU time | 14.45 seconds |
| Started | Aug 23 11:18:45 AM UTC 24 |
| Finished | Aug 23 11:19:00 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941288323 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3941288323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1829771194 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 25399100 ps |
| CPU time | 17.32 seconds |
| Started | Aug 23 11:18:27 AM UTC 24 |
| Finished | Aug 23 11:18:46 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829771194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1829771194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1964392962 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 11103300 ps |
| CPU time | 23.31 seconds |
| Started | Aug 23 11:18:07 AM UTC 24 |
| Finished | Aug 23 11:18:32 AM UTC 24 |
| Peak memory | 285476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1964392962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c trl_disable.1964392962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.903653954 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 7825772200 ps |
| CPU time | 2398.63 seconds |
| Started | Aug 23 11:14:38 AM UTC 24 |
| Finished | Aug 23 11:55:00 AM UTC 24 |
| Peak memory | 277928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903653954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.903653954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.1080194721 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3142092800 ps |
| CPU time | 948.58 seconds |
| Started | Aug 23 11:14:38 AM UTC 24 |
| Finished | Aug 23 11:30:37 AM UTC 24 |
| Peak memory | 288192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080194721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1080194721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.633628917 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 275334400 ps |
| CPU time | 23.09 seconds |
| Started | Aug 23 11:14:13 AM UTC 24 |
| Finished | Aug 23 11:14:38 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63 3628917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch _code.633628917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.778296381 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 10019485400 ps |
| CPU time | 76.12 seconds |
| Started | Aug 23 11:18:35 AM UTC 24 |
| Finished | Aug 23 11:19:52 AM UTC 24 |
| Peak memory | 330548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=778296381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.778296381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1265255512 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 15839200 ps |
| CPU time | 14.31 seconds |
| Started | Aug 23 11:18:32 AM UTC 24 |
| Finished | Aug 23 11:18:48 AM UTC 24 |
| Peak memory | 269228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1265255512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1265255512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3484477509 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 40122670200 ps |
| CPU time | 669.17 seconds |
| Started | Aug 23 11:13:55 AM UTC 24 |
| Finished | Aug 23 11:25:11 AM UTC 24 |
| Peak memory | 276088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484477509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.3484477509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1976583776 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 15263589200 ps |
| CPU time | 107.35 seconds |
| Started | Aug 23 11:13:46 AM UTC 24 |
| Finished | Aug 23 11:15:35 AM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976583776 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.1976583776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.3176245957 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1428632600 ps |
| CPU time | 184.44 seconds |
| Started | Aug 23 11:16:48 AM UTC 24 |
| Finished | Aug 23 11:19:56 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176245957 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.3176245957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2274659732 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 22992237500 ps |
| CPU time | 116.45 seconds |
| Started | Aug 23 11:17:19 AM UTC 24 |
| Finished | Aug 23 11:19:17 AM UTC 24 |
| Peak memory | 304192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2274659732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_intr_rd_slow_flash.2274659732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.4158082520 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 8669235100 ps |
| CPU time | 63.08 seconds |
| Started | Aug 23 11:16:50 AM UTC 24 |
| Finished | Aug 23 11:17:54 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158082520 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.4158082520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.140229072 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 80485222800 ps |
| CPU time | 232.01 seconds |
| Started | Aug 23 11:17:19 AM UTC 24 |
| Finished | Aug 23 11:21:14 AM UTC 24 |
| Peak memory | 271488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140229072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.140229072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.4240642831 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3415772700 ps |
| CPU time | 57.14 seconds |
| Started | Aug 23 11:14:39 AM UTC 24 |
| Finished | Aug 23 11:15:38 AM UTC 24 |
| Peak memory | 270980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240642831 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.4240642831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3404589049 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 15504700 ps |
| CPU time | 14.31 seconds |
| Started | Aug 23 11:18:29 AM UTC 24 |
| Finished | Aug 23 11:18:45 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3404589049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.3404589049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.1230208821 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 64850234700 ps |
| CPU time | 297.49 seconds |
| Started | Aug 23 11:14:09 AM UTC 24 |
| Finished | Aug 23 11:19:10 AM UTC 24 |
| Peak memory | 283392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1230208821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.1230208821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.1208747907 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 150888600 ps |
| CPU time | 144.36 seconds |
| Started | Aug 23 11:14:05 AM UTC 24 |
| Finished | Aug 23 11:16:32 AM UTC 24 |
| Peak memory | 271100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208747907 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.1208747907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1093626655 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 415161100 ps |
| CPU time | 190.16 seconds |
| Started | Aug 23 11:13:35 AM UTC 24 |
| Finished | Aug 23 11:16:48 AM UTC 24 |
| Peak memory | 272884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093626655 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1093626655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.250765662 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 34974400 ps |
| CPU time | 14.31 seconds |
| Started | Aug 23 11:17:31 AM UTC 24 |
| Finished | Aug 23 11:17:46 AM UTC 24 |
| Peak memory | 269000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250765662 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.250765662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.330687041 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 39128000 ps |
| CPU time | 110.82 seconds |
| Started | Aug 23 11:13:35 AM UTC 24 |
| Finished | Aug 23 11:15:28 AM UTC 24 |
| Peak memory | 278848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330687041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.330687041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2794513669 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 205100600 ps |
| CPU time | 35.36 seconds |
| Started | Aug 23 11:18:07 AM UTC 24 |
| Finished | Aug 23 11:18:44 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794513669 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2794513669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.480210625 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 597468200 ps |
| CPU time | 107.49 seconds |
| Started | Aug 23 11:15:29 AM UTC 24 |
| Finished | Aug 23 11:17:18 AM UTC 24 |
| Peak memory | 302044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=480210625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.480210625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.4066163165 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 490173300 ps |
| CPU time | 91.98 seconds |
| Started | Aug 23 11:16:32 AM UTC 24 |
| Finished | Aug 23 11:18:06 AM UTC 24 |
| Peak memory | 292032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066163165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.4066163165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.137457232 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2407021900 ps |
| CPU time | 96.56 seconds |
| Started | Aug 23 11:15:39 AM UTC 24 |
| Finished | Aug 23 11:17:18 AM UTC 24 |
| Peak memory | 306348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=137457232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ ctrl_ro_serr.137457232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2428215911 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2618958600 ps |
| CPU time | 147.02 seconds |
| Started | Aug 23 11:16:39 AM UTC 24 |
| Finished | Aug 23 11:19:09 AM UTC 24 |
| Peak memory | 296104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2428215911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_rw_derr.2428215911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3510771562 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28492600 ps |
| CPU time | 32.64 seconds |
| Started | Aug 23 11:17:47 AM UTC 24 |
| Finished | Aug 23 11:18:21 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510771562 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.3510771562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.938982132 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 32365500 ps |
| CPU time | 32.67 seconds |
| Started | Aug 23 11:17:55 AM UTC 24 |
| Finished | Aug 23 11:18:29 AM UTC 24 |
| Peak memory | 281528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=938982132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr l_rw_evict_all_en.938982132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.3591971276 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2985721200 ps |
| CPU time | 146.98 seconds |
| Started | Aug 23 11:15:57 AM UTC 24 |
| Finished | Aug 23 11:18:26 AM UTC 24 |
| Peak memory | 306412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3591971276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.3591971276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.918333651 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5952498500 ps |
| CPU time | 62.03 seconds |
| Started | Aug 23 11:18:21 AM UTC 24 |
| Finished | Aug 23 11:19:25 AM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918333651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.918333651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.1837943690 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 73396900 ps |
| CPU time | 82.07 seconds |
| Started | Aug 23 11:13:31 AM UTC 24 |
| Finished | Aug 23 11:14:54 AM UTC 24 |
| Peak memory | 287432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837943690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1837943690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1906892518 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 9246221100 ps |
| CPU time | 151.8 seconds |
| Started | Aug 23 11:14:56 AM UTC 24 |
| Finished | Aug 23 11:17:30 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1906892518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.1906892518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3429163772 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 34504500 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 12:16:30 PM UTC 24 |
| Finished | Aug 23 12:16:46 PM UTC 24 |
| Peak memory | 295332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429163772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3429163772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3209542549 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 40847700 ps |
| CPU time | 145.61 seconds |
| Started | Aug 23 12:16:27 PM UTC 24 |
| Finished | Aug 23 12:18:55 PM UTC 24 |
| Peak memory | 271104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209542549 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.3209542549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.2475660829 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 13989200 ps |
| CPU time | 14.33 seconds |
| Started | Aug 23 12:16:33 PM UTC 24 |
| Finished | Aug 23 12:16:50 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475660829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2475660829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3696003125 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 75949600 ps |
| CPU time | 145.96 seconds |
| Started | Aug 23 12:16:30 PM UTC 24 |
| Finished | Aug 23 12:18:59 PM UTC 24 |
| Peak memory | 271032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696003125 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.3696003125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.1441816787 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 41878500 ps |
| CPU time | 17.36 seconds |
| Started | Aug 23 12:16:41 PM UTC 24 |
| Finished | Aug 23 12:17:00 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441816787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1441816787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.565909879 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 178654500 ps |
| CPU time | 118.93 seconds |
| Started | Aug 23 12:16:39 PM UTC 24 |
| Finished | Aug 23 12:18:40 PM UTC 24 |
| Peak memory | 275432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565909879 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.565909879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.2128135658 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 19368600 ps |
| CPU time | 17.08 seconds |
| Started | Aug 23 12:16:43 PM UTC 24 |
| Finished | Aug 23 12:17:02 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128135658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2128135658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3990590906 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 128306200 ps |
| CPU time | 146.89 seconds |
| Started | Aug 23 12:16:42 PM UTC 24 |
| Finished | Aug 23 12:19:12 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990590906 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.3990590906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.594004020 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 16637800 ps |
| CPU time | 14.36 seconds |
| Started | Aug 23 12:16:50 PM UTC 24 |
| Finished | Aug 23 12:17:06 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594004020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.594004020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.962830344 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 41065200 ps |
| CPU time | 118.71 seconds |
| Started | Aug 23 12:16:47 PM UTC 24 |
| Finished | Aug 23 12:18:48 PM UTC 24 |
| Peak memory | 271148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962830344 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.962830344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.3966873107 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 49595400 ps |
| CPU time | 17.22 seconds |
| Started | Aug 23 12:17:00 PM UTC 24 |
| Finished | Aug 23 12:17:18 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966873107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3966873107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3970354788 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 76763000 ps |
| CPU time | 144.44 seconds |
| Started | Aug 23 12:17:00 PM UTC 24 |
| Finished | Aug 23 12:19:27 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970354788 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.3970354788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.657134782 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 15524200 ps |
| CPU time | 14.37 seconds |
| Started | Aug 23 12:17:02 PM UTC 24 |
| Finished | Aug 23 12:17:18 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657134782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.657134782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.39075109 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 139707800 ps |
| CPU time | 118.86 seconds |
| Started | Aug 23 12:17:01 PM UTC 24 |
| Finished | Aug 23 12:19:02 PM UTC 24 |
| Peak memory | 273388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39075109 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.39075109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.609565860 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 37951800 ps |
| CPU time | 17.26 seconds |
| Started | Aug 23 12:17:05 PM UTC 24 |
| Finished | Aug 23 12:17:24 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609565860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.609565860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.873536804 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 211555600 ps |
| CPU time | 119.25 seconds |
| Started | Aug 23 12:17:02 PM UTC 24 |
| Finished | Aug 23 12:19:04 PM UTC 24 |
| Peak memory | 275132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873536804 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.873536804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.1860341658 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 14422200 ps |
| CPU time | 17.28 seconds |
| Started | Aug 23 12:17:14 PM UTC 24 |
| Finished | Aug 23 12:17:32 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860341658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1860341658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1189401271 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 69929500 ps |
| CPU time | 145.28 seconds |
| Started | Aug 23 12:17:07 PM UTC 24 |
| Finished | Aug 23 12:19:35 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189401271 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.1189401271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.3666775470 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 40718700 ps |
| CPU time | 14.2 seconds |
| Started | Aug 23 12:17:19 PM UTC 24 |
| Finished | Aug 23 12:17:35 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666775470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3666775470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.4163920687 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 139198600 ps |
| CPU time | 145.09 seconds |
| Started | Aug 23 12:17:19 PM UTC 24 |
| Finished | Aug 23 12:19:47 PM UTC 24 |
| Peak memory | 271140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163920687 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.4163920687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.2310808854 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 27796300 ps |
| CPU time | 14.32 seconds |
| Started | Aug 23 11:23:38 AM UTC 24 |
| Finished | Aug 23 11:23:54 AM UTC 24 |
| Peak memory | 269292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310808854 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2310808854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.4082167226 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 27402600 ps |
| CPU time | 14.21 seconds |
| Started | Aug 23 11:23:18 AM UTC 24 |
| Finished | Aug 23 11:23:33 AM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082167226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.4082167226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1627805845 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 14319400 ps |
| CPU time | 23.1 seconds |
| Started | Aug 23 11:23:14 AM UTC 24 |
| Finished | Aug 23 11:23:38 AM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1627805845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.1627805845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1669548416 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 25731753200 ps |
| CPU time | 2362.62 seconds |
| Started | Aug 23 11:19:54 AM UTC 24 |
| Finished | Aug 23 11:59:38 AM UTC 24 |
| Peak memory | 277924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669548416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1669548416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3425575373 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1403686700 ps |
| CPU time | 1060.67 seconds |
| Started | Aug 23 11:19:50 AM UTC 24 |
| Finished | Aug 23 11:37:41 AM UTC 24 |
| Peak memory | 288192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425575373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3425575373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.4233056563 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 158050100 ps |
| CPU time | 21.75 seconds |
| Started | Aug 23 11:19:25 AM UTC 24 |
| Finished | Aug 23 11:19:49 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 33056563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc h_code.4233056563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3349884588 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 10030186700 ps |
| CPU time | 55 seconds |
| Started | Aug 23 11:23:35 AM UTC 24 |
| Finished | Aug 23 11:24:32 AM UTC 24 |
| Peak memory | 295700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3349884588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3349884588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2952744442 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 46263100 ps |
| CPU time | 14.22 seconds |
| Started | Aug 23 11:23:34 AM UTC 24 |
| Finished | Aug 23 11:23:50 AM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2952744442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2952744442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3805343564 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 760532972700 ps |
| CPU time | 1213.13 seconds |
| Started | Aug 23 11:19:10 AM UTC 24 |
| Finished | Aug 23 11:39:35 AM UTC 24 |
| Peak memory | 277772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805343564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.3805343564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3278892586 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 22552587400 ps |
| CPU time | 204.64 seconds |
| Started | Aug 23 11:19:01 AM UTC 24 |
| Finished | Aug 23 11:22:29 AM UTC 24 |
| Peak memory | 272984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278892586 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.3278892586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.4002401590 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 16857068600 ps |
| CPU time | 168.3 seconds |
| Started | Aug 23 11:21:20 AM UTC 24 |
| Finished | Aug 23 11:24:11 AM UTC 24 |
| Peak memory | 301928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002401590 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.4002401590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3641118062 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 12526151600 ps |
| CPU time | 236.72 seconds |
| Started | Aug 23 11:22:12 AM UTC 24 |
| Finished | Aug 23 11:26:12 AM UTC 24 |
| Peak memory | 303936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3641118062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_intr_rd_slow_flash.3641118062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.894562151 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2325059000 ps |
| CPU time | 60.27 seconds |
| Started | Aug 23 11:22:12 AM UTC 24 |
| Finished | Aug 23 11:23:14 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894562151 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.894562151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.313326137 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 39976900600 ps |
| CPU time | 158.48 seconds |
| Started | Aug 23 11:22:30 AM UTC 24 |
| Finished | Aug 23 11:25:11 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313326137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.313326137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.411625560 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 8387936700 ps |
| CPU time | 63.99 seconds |
| Started | Aug 23 11:19:57 AM UTC 24 |
| Finished | Aug 23 11:21:02 AM UTC 24 |
| Peak memory | 275072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411625560 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.411625560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3681448275 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 5152812300 ps |
| CPU time | 118.7 seconds |
| Started | Aug 23 11:19:18 AM UTC 24 |
| Finished | Aug 23 11:21:19 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3681448275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3681448275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3017753813 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 82159100 ps |
| CPU time | 118.81 seconds |
| Started | Aug 23 11:19:11 AM UTC 24 |
| Finished | Aug 23 11:21:12 AM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017753813 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.3017753813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1414182918 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 58245200 ps |
| CPU time | 254.15 seconds |
| Started | Aug 23 11:18:49 AM UTC 24 |
| Finished | Aug 23 11:23:06 AM UTC 24 |
| Peak memory | 275136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414182918 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1414182918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.3910637707 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 8395967700 ps |
| CPU time | 143.27 seconds |
| Started | Aug 23 11:22:38 AM UTC 24 |
| Finished | Aug 23 11:25:03 AM UTC 24 |
| Peak memory | 271144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910637707 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.3910637707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3213448058 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4385457300 ps |
| CPU time | 783.02 seconds |
| Started | Aug 23 11:18:47 AM UTC 24 |
| Finished | Aug 23 11:31:58 AM UTC 24 |
| Peak memory | 298404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213448058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3213448058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3486596699 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1006677400 ps |
| CPU time | 82.66 seconds |
| Started | Aug 23 11:20:47 AM UTC 24 |
| Finished | Aug 23 11:22:12 AM UTC 24 |
| Peak memory | 302012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3486596699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.3486596699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1863383076 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1384034500 ps |
| CPU time | 96.05 seconds |
| Started | Aug 23 11:21:01 AM UTC 24 |
| Finished | Aug 23 11:22:39 AM UTC 24 |
| Peak memory | 306412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1863383076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_ro_serr.1863383076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1831894276 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 8007015000 ps |
| CPU time | 402.23 seconds |
| Started | Aug 23 11:20:52 AM UTC 24 |
| Finished | Aug 23 11:27:39 AM UTC 24 |
| Peak memory | 336828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831894276 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.1831894276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3459288888 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5916941400 ps |
| CPU time | 173.09 seconds |
| Started | Aug 23 11:21:15 AM UTC 24 |
| Finished | Aug 23 11:24:11 AM UTC 24 |
| Peak memory | 294120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3459288888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_rw_derr.3459288888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3654141224 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 27032600 ps |
| CPU time | 31.91 seconds |
| Started | Aug 23 11:22:40 AM UTC 24 |
| Finished | Aug 23 11:23:13 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654141224 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.3654141224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1724357990 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5130454700 ps |
| CPU time | 131.99 seconds |
| Started | Aug 23 11:21:03 AM UTC 24 |
| Finished | Aug 23 11:23:17 AM UTC 24 |
| Peak memory | 291752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1724357990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.1724357990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.4179962022 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 738029700 ps |
| CPU time | 51.21 seconds |
| Started | Aug 23 11:23:15 AM UTC 24 |
| Finished | Aug 23 11:24:08 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179962022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.4179962022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1123011759 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 86068700 ps |
| CPU time | 79.24 seconds |
| Started | Aug 23 11:18:46 AM UTC 24 |
| Finished | Aug 23 11:20:07 AM UTC 24 |
| Peak memory | 285336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123011759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1123011759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1455112756 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2551211200 ps |
| CPU time | 147.05 seconds |
| Started | Aug 23 11:20:08 AM UTC 24 |
| Finished | Aug 23 11:22:37 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1455112756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.1455112756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.4198735126 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 24113400 ps |
| CPU time | 17.15 seconds |
| Started | Aug 23 12:17:24 PM UTC 24 |
| Finished | Aug 23 12:17:43 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198735126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4198735126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.3797111887 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 42717500 ps |
| CPU time | 149.65 seconds |
| Started | Aug 23 12:17:20 PM UTC 24 |
| Finished | Aug 23 12:19:52 PM UTC 24 |
| Peak memory | 271204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797111887 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.3797111887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.2652188115 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 27132700 ps |
| CPU time | 14.3 seconds |
| Started | Aug 23 12:17:34 PM UTC 24 |
| Finished | Aug 23 12:17:49 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652188115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2652188115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1934592559 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 71587100 ps |
| CPU time | 144.4 seconds |
| Started | Aug 23 12:17:34 PM UTC 24 |
| Finished | Aug 23 12:20:01 PM UTC 24 |
| Peak memory | 270824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934592559 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.1934592559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1327150659 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 14008300 ps |
| CPU time | 14.33 seconds |
| Started | Aug 23 12:17:41 PM UTC 24 |
| Finished | Aug 23 12:17:57 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327150659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1327150659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2407981012 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 331534700 ps |
| CPU time | 145.85 seconds |
| Started | Aug 23 12:17:35 PM UTC 24 |
| Finished | Aug 23 12:20:03 PM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407981012 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.2407981012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.1441355970 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 52536400 ps |
| CPU time | 14.19 seconds |
| Started | Aug 23 12:17:44 PM UTC 24 |
| Finished | Aug 23 12:18:00 PM UTC 24 |
| Peak memory | 295332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441355970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1441355970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.908122291 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 40712100 ps |
| CPU time | 144.13 seconds |
| Started | Aug 23 12:17:42 PM UTC 24 |
| Finished | Aug 23 12:20:09 PM UTC 24 |
| Peak memory | 274916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908122291 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.908122291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.2005372106 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 65910200 ps |
| CPU time | 17.4 seconds |
| Started | Aug 23 12:17:53 PM UTC 24 |
| Finished | Aug 23 12:18:11 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005372106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2005372106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.2503213752 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 40026600 ps |
| CPU time | 145.2 seconds |
| Started | Aug 23 12:17:51 PM UTC 24 |
| Finished | Aug 23 12:20:18 PM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503213752 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.2503213752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.708941656 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 20272700 ps |
| CPU time | 14.37 seconds |
| Started | Aug 23 12:17:58 PM UTC 24 |
| Finished | Aug 23 12:18:14 PM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708941656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.708941656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1686502920 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 39236700 ps |
| CPU time | 119.46 seconds |
| Started | Aug 23 12:17:56 PM UTC 24 |
| Finished | Aug 23 12:19:58 PM UTC 24 |
| Peak memory | 270828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686502920 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.1686502920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3009668703 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 27496600 ps |
| CPU time | 17.16 seconds |
| Started | Aug 23 12:18:12 PM UTC 24 |
| Finished | Aug 23 12:18:31 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009668703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3009668703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2640812263 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 42461000 ps |
| CPU time | 145.91 seconds |
| Started | Aug 23 12:18:01 PM UTC 24 |
| Finished | Aug 23 12:20:30 PM UTC 24 |
| Peak memory | 275292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640812263 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.2640812263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3363654033 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 15235900 ps |
| CPU time | 17.2 seconds |
| Started | Aug 23 12:18:16 PM UTC 24 |
| Finished | Aug 23 12:18:35 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363654033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3363654033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2939482644 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 254611100 ps |
| CPU time | 146.95 seconds |
| Started | Aug 23 12:18:12 PM UTC 24 |
| Finished | Aug 23 12:20:42 PM UTC 24 |
| Peak memory | 271712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939482644 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.2939482644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.203892898 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 28864600 ps |
| CPU time | 17.84 seconds |
| Started | Aug 23 12:18:26 PM UTC 24 |
| Finished | Aug 23 12:18:45 PM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203892898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.203892898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1514484788 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 69997100 ps |
| CPU time | 143.05 seconds |
| Started | Aug 23 12:18:21 PM UTC 24 |
| Finished | Aug 23 12:20:48 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514484788 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.1514484788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2274282793 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 24937400 ps |
| CPU time | 17.48 seconds |
| Started | Aug 23 12:18:31 PM UTC 24 |
| Finished | Aug 23 12:18:50 PM UTC 24 |
| Peak memory | 295200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274282793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2274282793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.840914418 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 139139000 ps |
| CPU time | 146.44 seconds |
| Started | Aug 23 12:18:30 PM UTC 24 |
| Finished | Aug 23 12:20:59 PM UTC 24 |
| Peak memory | 271136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840914418 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.840914418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.1073721830 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 157320300 ps |
| CPU time | 14.75 seconds |
| Started | Aug 23 11:29:06 AM UTC 24 |
| Finished | Aug 23 11:29:22 AM UTC 24 |
| Peak memory | 269312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073721830 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1073721830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3884455924 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 25262000 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 11:28:50 AM UTC 24 |
| Finished | Aug 23 11:29:06 AM UTC 24 |
| Peak memory | 295196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884455924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3884455924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1804057850 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 35591200 ps |
| CPU time | 22.3 seconds |
| Started | Aug 23 11:28:30 AM UTC 24 |
| Finished | Aug 23 11:28:53 AM UTC 24 |
| Peak memory | 285476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1804057850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c trl_disable.1804057850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1700675437 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 23353762000 ps |
| CPU time | 2422.55 seconds |
| Started | Aug 23 11:24:59 AM UTC 24 |
| Finished | Aug 23 12:05:45 PM UTC 24 |
| Peak memory | 277972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700675437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1700675437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1807819395 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1068662900 ps |
| CPU time | 804.29 seconds |
| Started | Aug 23 11:24:48 AM UTC 24 |
| Finished | Aug 23 11:38:21 AM UTC 24 |
| Peak memory | 288188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807819395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1807819395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.2735479986 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1106241900 ps |
| CPU time | 24.35 seconds |
| Started | Aug 23 11:24:33 AM UTC 24 |
| Finished | Aug 23 11:24:59 AM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 35479986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc h_code.2735479986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.989519219 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10012773500 ps |
| CPU time | 115.84 seconds |
| Started | Aug 23 11:29:02 AM UTC 24 |
| Finished | Aug 23 11:31:00 AM UTC 24 |
| Peak memory | 336848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=989519219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.989519219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3314889176 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 15935600 ps |
| CPU time | 14.44 seconds |
| Started | Aug 23 11:28:58 AM UTC 24 |
| Finished | Aug 23 11:29:14 AM UTC 24 |
| Peak memory | 269492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3314889176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3314889176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.1517047645 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 630371831500 ps |
| CPU time | 872.48 seconds |
| Started | Aug 23 11:24:09 AM UTC 24 |
| Finished | Aug 23 11:38:50 AM UTC 24 |
| Peak memory | 277768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517047645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.1517047645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.3270509842 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2769522600 ps |
| CPU time | 84.46 seconds |
| Started | Aug 23 11:23:55 AM UTC 24 |
| Finished | Aug 23 11:25:21 AM UTC 24 |
| Peak memory | 275032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270509842 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.3270509842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3426679021 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 544657000 ps |
| CPU time | 107.66 seconds |
| Started | Aug 23 11:26:39 AM UTC 24 |
| Finished | Aug 23 11:28:29 AM UTC 24 |
| Peak memory | 306080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426679021 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.3426679021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4273189535 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 15113075300 ps |
| CPU time | 121.01 seconds |
| Started | Aug 23 11:27:26 AM UTC 24 |
| Finished | Aug 23 11:29:30 AM UTC 24 |
| Peak memory | 303932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4273189535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_intr_rd_slow_flash.4273189535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2669947372 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4718528100 ps |
| CPU time | 60.46 seconds |
| Started | Aug 23 11:26:45 AM UTC 24 |
| Finished | Aug 23 11:27:48 AM UTC 24 |
| Peak memory | 275584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669947372 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.2669947372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.274413971 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 21432776800 ps |
| CPU time | 167.98 seconds |
| Started | Aug 23 11:27:39 AM UTC 24 |
| Finished | Aug 23 11:30:30 AM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274413971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.274413971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3674754661 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3923869000 ps |
| CPU time | 74.49 seconds |
| Started | Aug 23 11:25:04 AM UTC 24 |
| Finished | Aug 23 11:26:21 AM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674754661 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3674754661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1703753683 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 35214400 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 11:28:54 AM UTC 24 |
| Finished | Aug 23 11:29:10 AM UTC 24 |
| Peak memory | 271124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1703753683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_lcmgr_intg.1703753683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3834287157 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 7324667100 ps |
| CPU time | 451.5 seconds |
| Started | Aug 23 11:24:12 AM UTC 24 |
| Finished | Aug 23 11:31:49 AM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3834287157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.3834287157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3618190259 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 39969500 ps |
| CPU time | 145.66 seconds |
| Started | Aug 23 11:24:11 AM UTC 24 |
| Finished | Aug 23 11:26:39 AM UTC 24 |
| Peak memory | 271552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618190259 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.3618190259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.3475765556 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2693818600 ps |
| CPU time | 622.99 seconds |
| Started | Aug 23 11:23:51 AM UTC 24 |
| Finished | Aug 23 11:34:20 AM UTC 24 |
| Peak memory | 273344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475765556 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3475765556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.575375628 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 16906808300 ps |
| CPU time | 140.69 seconds |
| Started | Aug 23 11:27:49 AM UTC 24 |
| Finished | Aug 23 11:30:12 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575375628 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.575375628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2243182291 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 834366100 ps |
| CPU time | 910.45 seconds |
| Started | Aug 23 11:23:44 AM UTC 24 |
| Finished | Aug 23 11:39:03 AM UTC 24 |
| Peak memory | 298400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243182291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2243182291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.911182681 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 55136200 ps |
| CPU time | 34.65 seconds |
| Started | Aug 23 11:28:26 AM UTC 24 |
| Finished | Aug 23 11:29:02 AM UTC 24 |
| Peak memory | 283576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911182681 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.911182681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.3943940377 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 392511300 ps |
| CPU time | 71.66 seconds |
| Started | Aug 23 11:25:13 AM UTC 24 |
| Finished | Aug 23 11:26:27 AM UTC 24 |
| Peak memory | 291716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3943940377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.3943940377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2668252020 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2579855400 ps |
| CPU time | 111.47 seconds |
| Started | Aug 23 11:26:21 AM UTC 24 |
| Finished | Aug 23 11:28:15 AM UTC 24 |
| Peak memory | 291776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668252020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2668252020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3637761526 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1263398400 ps |
| CPU time | 96.3 seconds |
| Started | Aug 23 11:26:13 AM UTC 24 |
| Finished | Aug 23 11:27:51 AM UTC 24 |
| Peak memory | 302020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3637761526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.3637761526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.3163535378 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6778748000 ps |
| CPU time | 367.74 seconds |
| Started | Aug 23 11:25:22 AM UTC 24 |
| Finished | Aug 23 11:31:34 AM UTC 24 |
| Peak memory | 320372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163535378 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.3163535378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3689205688 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2045213300 ps |
| CPU time | 193.13 seconds |
| Started | Aug 23 11:26:27 AM UTC 24 |
| Finished | Aug 23 11:29:43 AM UTC 24 |
| Peak memory | 297892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3689205688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.3689205688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3999523146 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 28350500 ps |
| CPU time | 32.25 seconds |
| Started | Aug 23 11:27:52 AM UTC 24 |
| Finished | Aug 23 11:28:25 AM UTC 24 |
| Peak memory | 287968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999523146 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3999523146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.2191429977 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2174818400 ps |
| CPU time | 130.47 seconds |
| Started | Aug 23 11:26:20 AM UTC 24 |
| Finished | Aug 23 11:28:33 AM UTC 24 |
| Peak memory | 292076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2191429977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.2191429977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.278159164 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2104772100 ps |
| CPU time | 66.28 seconds |
| Started | Aug 23 11:28:33 AM UTC 24 |
| Finished | Aug 23 11:29:41 AM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278159164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.278159164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1295482260 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 18229400 ps |
| CPU time | 156.83 seconds |
| Started | Aug 23 11:23:40 AM UTC 24 |
| Finished | Aug 23 11:26:19 AM UTC 24 |
| Peak memory | 289472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295482260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1295482260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1346431714 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4736154000 ps |
| CPU time | 131.38 seconds |
| Started | Aug 23 11:25:12 AM UTC 24 |
| Finished | Aug 23 11:27:26 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1346431714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.1346431714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1555065628 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 169704100 ps |
| CPU time | 14.58 seconds |
| Started | Aug 23 11:34:26 AM UTC 24 |
| Finished | Aug 23 11:34:41 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555065628 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1555065628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2481577520 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 28931400 ps |
| CPU time | 17.17 seconds |
| Started | Aug 23 11:34:08 AM UTC 24 |
| Finished | Aug 23 11:34:27 AM UTC 24 |
| Peak memory | 295204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481577520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2481577520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.945296474 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 10721100 ps |
| CPU time | 22.02 seconds |
| Started | Aug 23 11:33:45 AM UTC 24 |
| Finished | Aug 23 11:34:08 AM UTC 24 |
| Peak memory | 285544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=945296474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_disable.945296474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3339530448 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2090250700 ps |
| CPU time | 2288.96 seconds |
| Started | Aug 23 11:30:31 AM UTC 24 |
| Finished | Aug 23 12:09:02 PM UTC 24 |
| Peak memory | 277936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339530448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.3339530448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.4152204372 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 922329500 ps |
| CPU time | 1247.91 seconds |
| Started | Aug 23 11:30:17 AM UTC 24 |
| Finished | Aug 23 11:51:17 AM UTC 24 |
| Peak memory | 288448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152204372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.4152204372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2507387872 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 4976452300 ps |
| CPU time | 26.74 seconds |
| Started | Aug 23 11:30:12 AM UTC 24 |
| Finished | Aug 23 11:30:40 AM UTC 24 |
| Peak memory | 273416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 07387872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.2507387872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1479259855 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 10033956500 ps |
| CPU time | 82.87 seconds |
| Started | Aug 23 11:34:21 AM UTC 24 |
| Finished | Aug 23 11:35:46 AM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1479259855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1479259855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3500034672 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 213421100 ps |
| CPU time | 14.56 seconds |
| Started | Aug 23 11:34:18 AM UTC 24 |
| Finished | Aug 23 11:34:34 AM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3500034672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3500034672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.2757630067 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 80135710500 ps |
| CPU time | 670.82 seconds |
| Started | Aug 23 11:29:42 AM UTC 24 |
| Finished | Aug 23 11:41:00 AM UTC 24 |
| Peak memory | 277708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757630067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.2757630067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3124569635 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1778635700 ps |
| CPU time | 43.82 seconds |
| Started | Aug 23 11:29:31 AM UTC 24 |
| Finished | Aug 23 11:30:16 AM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124569635 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.3124569635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2064501584 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 5889448600 ps |
| CPU time | 124.38 seconds |
| Started | Aug 23 11:32:51 AM UTC 24 |
| Finished | Aug 23 11:34:57 AM UTC 24 |
| Peak memory | 303908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2064501584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_intr_rd_slow_flash.2064501584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2244633366 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 9155901900 ps |
| CPU time | 58.8 seconds |
| Started | Aug 23 11:32:12 AM UTC 24 |
| Finished | Aug 23 11:33:13 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244633366 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2244633366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1315406077 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 409839249600 ps |
| CPU time | 386.99 seconds |
| Started | Aug 23 11:33:14 AM UTC 24 |
| Finished | Aug 23 11:39:45 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315406077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1315406077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3013995036 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4617317900 ps |
| CPU time | 57.98 seconds |
| Started | Aug 23 11:30:31 AM UTC 24 |
| Finished | Aug 23 11:31:31 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013995036 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3013995036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.3837028610 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 15746900 ps |
| CPU time | 14.27 seconds |
| Started | Aug 23 11:34:09 AM UTC 24 |
| Finished | Aug 23 11:34:25 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3837028610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.3837028610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.449056916 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 12643736000 ps |
| CPU time | 413.41 seconds |
| Started | Aug 23 11:30:05 AM UTC 24 |
| Finished | Aug 23 11:37:03 AM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=449056916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_mp_regions.449056916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2375934400 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2900060100 ps |
| CPU time | 448.32 seconds |
| Started | Aug 23 11:29:22 AM UTC 24 |
| Finished | Aug 23 11:36:56 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375934400 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2375934400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2043853080 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 227016300 ps |
| CPU time | 14.55 seconds |
| Started | Aug 23 11:33:18 AM UTC 24 |
| Finished | Aug 23 11:33:33 AM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043853080 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.2043853080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1639920741 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1478752400 ps |
| CPU time | 1230.65 seconds |
| Started | Aug 23 11:29:14 AM UTC 24 |
| Finished | Aug 23 11:49:57 AM UTC 24 |
| Peak memory | 300448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639920741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1639920741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.2169759263 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 219144200 ps |
| CPU time | 35.55 seconds |
| Started | Aug 23 11:33:41 AM UTC 24 |
| Finished | Aug 23 11:34:18 AM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169759263 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.2169759263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1286232004 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 6839683900 ps |
| CPU time | 81.1 seconds |
| Started | Aug 23 11:30:40 AM UTC 24 |
| Finished | Aug 23 11:32:03 AM UTC 24 |
| Peak memory | 302016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1286232004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1286232004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.783749935 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1201403100 ps |
| CPU time | 103.51 seconds |
| Started | Aug 23 11:31:50 AM UTC 24 |
| Finished | Aug 23 11:33:36 AM UTC 24 |
| Peak memory | 291748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783749935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.783749935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.371110509 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2836752700 ps |
| CPU time | 103.4 seconds |
| Started | Aug 23 11:31:32 AM UTC 24 |
| Finished | Aug 23 11:33:17 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=371110509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ ctrl_ro_serr.371110509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.2294580153 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 21581343300 ps |
| CPU time | 357.46 seconds |
| Started | Aug 23 11:31:00 AM UTC 24 |
| Finished | Aug 23 11:37:02 AM UTC 24 |
| Peak memory | 324544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294580153 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.2294580153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.1915249997 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4563140800 ps |
| CPU time | 216.72 seconds |
| Started | Aug 23 11:31:59 AM UTC 24 |
| Finished | Aug 23 11:35:39 AM UTC 24 |
| Peak memory | 293816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1915249997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.flash_ctrl_rw_derr.1915249997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1371214659 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 74107900 ps |
| CPU time | 32.35 seconds |
| Started | Aug 23 11:33:34 AM UTC 24 |
| Finished | Aug 23 11:34:08 AM UTC 24 |
| Peak memory | 281792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371214659 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.1371214659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3981968696 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 41824800 ps |
| CPU time | 30.19 seconds |
| Started | Aug 23 11:33:36 AM UTC 24 |
| Finished | Aug 23 11:34:07 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3981968696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_rw_evict_all_en.3981968696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3989667716 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 7440728400 ps |
| CPU time | 123.77 seconds |
| Started | Aug 23 11:31:35 AM UTC 24 |
| Finished | Aug 23 11:33:41 AM UTC 24 |
| Peak memory | 306084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3989667716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.3989667716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3383460639 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1333671700 ps |
| CPU time | 63.08 seconds |
| Started | Aug 23 11:34:08 AM UTC 24 |
| Finished | Aug 23 11:35:13 AM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383460639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3383460639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3764037929 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 23690400 ps |
| CPU time | 51.95 seconds |
| Started | Aug 23 11:29:10 AM UTC 24 |
| Finished | Aug 23 11:30:04 AM UTC 24 |
| Peak memory | 283336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764037929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3764037929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3000855989 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3862432200 ps |
| CPU time | 129.95 seconds |
| Started | Aug 23 11:30:37 AM UTC 24 |
| Finished | Aug 23 11:32:49 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3000855989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.3000855989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
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