Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.25	100.00	96.23		100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.74	100.00	85.85		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	98.87	100.00	94.34		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.74	100.00	85.85		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	97.07	92.64	96.90	100.00	99.29	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.22	97.67	88.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.65	100.00	96.92	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	96.93	97.64	92.83	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	94.34		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	97.07	93.19	100.00	100.00	99.65	97.06

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.22	97.67	88.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.74	100.00	98.46	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	96.95	97.64	92.91	100.00		99.37	94.83
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

151                       always_ff @(posedge clk_i or negedge rst_ni) begin
152        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
153        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T3 
154        1/1              end else if (ctrl_rsp_vld) begin
           Tests:       T1 T2 T3 
155        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T3 
156        1/1              end else if (inc_arb_cnt) begin
           Tests:       T1 T2 T3 
157        1/1                arb_cnt <= arb_cnt + 1'b1;
           Tests:       T15 T10 T58 
158                         end
                        MISSING_ELSE
159                       end
160                     
161                       import prim_mubi_pkg::mubi4_test_false_strict;
162                       import prim_mubi_pkg::mubi4_test_true_loose;
163                     
164                       // SEC_CM: PHY.FSM.SPARSE
165        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
165.1                   `ifdef SIMULATION                                   
165.2                       prim_sparse_fsm_flop #(                           
165.3                         .StateEnumT(state_e),                            
165.4                         .Width($bits(state_e)),                          
165.5                         .ResetValue($bits(state_e)'(StIdle)),          
165.6                         .EnableAlertTriggerSVA(1), 
165.7                         .CustomForceName("state_q")          
165.8                       ) u_state_regs (                                        
165.9                         .clk_i   ( clk_i   ),                           
165.10                        .rst_ni  ( rst_ni ),                           
165.11                        .state_i ( state_d     ),                           
165.12                        .state_o (         )                            
165.13                      );                                                
165.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
165.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
165.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
165.17                      end else begin                                    
165.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
165.19                      end                                               
165.20                    end  
165.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
165.22                      else begin                                                                           
165.23                        `ifdef UVM                                                                               
165.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
165.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv", 165, "", 1);                                
165.26                  `else                                                                                    
165.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
165.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
165.29                  `endif                                                              
165.30                      end 
165.31                    `else                                               
165.32                      prim_sparse_fsm_flop #(                           
165.33                        .StateEnumT(state_e),                            
165.34                        .Width($bits(state_e)),                          
165.35                        .ResetValue($bits(state_e)'(StIdle)),          
165.36                        .EnableAlertTriggerSVA(1)  
165.37                      ) u_state_regs (                                        
165.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
165.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
165.40                        .state_i ( state_d     ),                           
165.41                        .state_o ( state_q     )                            
165.42                      );                                                
165.43                    `endif166                     
167                       typedef enum logic [2:0] {
168                         HostDisableIdx,
169                         CtrlDisableIdx,
170                         FsmDisableIdx,
171                         ProgFsmDisableIdx,
172                         LastDisableIdx
173                       } phy_core_disable_e;
174                     
175                       prim_mubi_pkg::mubi4_t [LastDisableIdx-1:0] flash_disable;
176                       prim_mubi4_sync #(
177                         .NumCopies(int'(LastDisableIdx)),
178                         .AsyncOn(0)
179                       ) u_disable_buf (
180                         .clk_i,
181                         .rst_ni,
182                         .mubi_i(flash_disable_i),
183                         .mubi_o(flash_disable)
184                       );
185                     
186                       // Oustanding width is slightly larger to ensure a faulty increment is able to reach
187                       // the higher value. For example if RspOrderDepth were 3, a clog2 of 3 would still be 2
188                       // and not allow the counter to increment to 4.
189                       localparam int OutstandingRdWidth = $clog2(RspOrderDepth+2);
190                       logic [OutstandingRdWidth-1:0] host_outstanding;
191                       logic ctrl_fsm_idle;
192                       logic host_req;
193                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
194                       // A host transaction was granted to the muxed partition, this is illegal
195                       logic host_gnt_err_event;
196        1/1            assign host_gnt_err_event = (host_gnt && muxed_part != flash_ctrl_pkg::FlashPartData);
           Tests:       T1 T2 T3 
197                       // Controller fsm became non idle when there are pending host transactions, this is
198                       // illegal.
199                       logic host_outstanding_err_event;
200        1/1            assign host_outstanding_err_event = |host_outstanding & !ctrl_fsm_idle;
           Tests:       T1 T2 T3 
201                     
202                       always_ff @(posedge clk_i or negedge rst_ni) begin
203        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
204        1/1                host_gnt_err_o <= '0;
           Tests:       T1 T2 T3 
205        1/1              end else if (host_gnt_err_event | host_outstanding_err_event) begin
           Tests:       T1 T2 T3 
206        1/1                host_gnt_err_o <= 1'b1;
           Tests:       T10 T180 T228 
207                         end
                        MISSING_ELSE
208                       end
209                     
210                       // When host grant errors occur, also create in band error responses.
211                       // The error condition is held until all existing host transactions are
212                       // processed.
213                       logic host_gnt_rd_err;
214                       always_ff @(posedge clk_i or negedge rst_ni) begin
215        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
216        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
217        1/1              end else if (host_outstanding == '0) begin
           Tests:       T1 T2 T3 
218        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
219        1/1              end else if (host_gnt_err_event) begin
           Tests:       T2 T3 T20 
220        1/1                host_gnt_rd_err <= 1'b1;
           Tests:       T10 T228 T11 
221                         end
                        MISSING_ELSE
222                       end
223                     
224                       // When host outstanding errors occur, also create in band error responses.
225                       // The error condition is held until all existing host and controller
226                       // transactions are processed.
227                       logic host_outstanding_rd_err;
228                       always_ff @(posedge clk_i or negedge rst_ni) begin
229        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
230        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
231        1/1              end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
           Tests:       T1 T2 T3 
232        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
233        1/1              end else if (host_outstanding_err_event) begin
           Tests:       T1 T2 T3 
234        1/1                host_outstanding_rd_err <= 1'b1;
           Tests:       T10 T11 
235                         end
                        MISSING_ELSE
236                       end
237                     
238                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
239                       prim_count #(
240                         .Width(OutstandingRdWidth),
241                         .ResetValue('0)
242                       ) u_host_outstanding_cnt (
243                         .clk_i,
244                         .rst_ni,
245                         .clr_i('0),
246                         .set_i('0),
247                         .set_cnt_i('0),
248                         .incr_en_i(host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)),
249                         .decr_en_i(!host_gnt && host_req_done_o && |host_outstanding),
250                         .step_i(OutstandingRdWidth'(1'b1)),
251                         .commit_i(1'b1),
252                         .cnt_o(host_outstanding),
253                         .cnt_after_commit_o(),
254                         .err_o(cnt_err_o)
255                       );
256                     
257                       // If host_outstanding is non-zero, the controller fsm must be idle..
258                       // This assertion needs to be disabled for sec_cm testing
259                       `ASSERT(HostTransIdleChk_A, |host_outstanding |-> ctrl_fsm_idle)
260                     
261                       //always_ff @(posedge clk_i or negedge rst_ni) begin
262                       //  if (!rst_ni) begin
263                       //    host_outstanding <= '0;
264                       //  end else if (host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)) begin
265                       //    host_outstanding <= host_outstanding + 1'b1;
266                       //  end else if (!host_gnt && host_req_done_o && |host_outstanding) begin
267                       //    host_outstanding <= host_outstanding - 1'b1;
268                       //  end
269                       //end
270                     
271                       `ASSERT(RdTxnCheck_A, host_outstanding <= RspOrderDepth)
272                     
273                       // The host request is suppressed under a variety of conditions:
274                       // 1. If a controller transaction is already ongoing.
275                       // 2. If a grant or outstanding error has already been observed but not yet
276                       //    fully processed.
277        1/1            assign host_req = host_req_i & (arb_cnt < ArbCnt[CntWidth-1:0]) & ctrl_fsm_idle &
           Tests:       T1 T2 T3 
278                                         !host_gnt_rd_err & !host_outstanding_rd_err &
279                                         mubi4_test_false_strict(flash_disable[HostDisableIdx]);
280        1/1            assign host_sel = host_req;
           Tests:       T1 T2 T3 
281        1/1            assign host_gnt = host_req & host_req_rdy_o;
           Tests:       T1 T2 T3 
282        1/1            assign host_req_done_o = |host_outstanding & rd_stage_data_valid;
           Tests:       T1 T2 T3 
283                     
284                       // controller request can only win after the entire read pipeline
285                       // clears
286                       logic ctrl_req;
287        1/1            assign ctrl_req = req_i & rd_stage_idle &
           Tests:       T1 T2 T3 
288                                         !host_gnt_rd_err & !host_outstanding_rd_err &
289                                         mubi4_test_false_strict(flash_disable[CtrlDisableIdx]);
290                     
291                       logic [1:0] data_tie_off [2];
292                       assign data_tie_off = '{default: '0};
293                     
294                       // SEC_CM: PHY_ARBITER.CTRL.REDUN
295                       logic phy_req;
296                       logic phy_rdy;
297                     
298                       prim_arbiter_tree_dup #(
299                         .N(2),
300                         .DW(2),
301                         .EnDataPort('0),
302                         .FixedArb(1)
303                       ) u_host_arb (
304                         .clk_i,
305                         .rst_ni,
306                         .req_chk_i('0),
307                         .req_i({ctrl_req, host_req}),
308                         .data_i(data_tie_off),
309                         .gnt_o({ctrl_gnt, host_req_rdy_o}),
310                         .idx_o(),
311                         .valid_o(phy_req),
312                         .data_o(),
313                         .ready_i(phy_rdy),
314                         .err_o(arb_err_o)
315                       );
316                     
317        1/1            assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
           Tests:       T1 T2 T3 
318                     
319                     
320                       // if request happens at the same time as a host grant, increment count
321        1/1            assign inc_arb_cnt = req_i & host_gnt;
           Tests:       T1 T2 T3 
322                     
323                       logic fsm_err;
324                       always_comb begin
325        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
326        1/1              reqs = '0;
           Tests:       T1 T2 T3 
327        1/1              ctrl_rsp_vld = '0;
           Tests:       T1 T2 T3 
328        1/1              fsm_err = '0;
           Tests:       T1 T2 T3 
329        1/1              ctrl_fsm_idle = '0;
           Tests:       T1 T2 T3 
330                     
331        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
332                           StIdle: begin
333        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T1 T2 T3 
334        1/1                  if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
           Tests:       T1 T2 T3 
335        1/1                    state_d = StDisable;
           Tests:       T7 T8 T9 
336        1/1                  end else if (ctrl_gnt && rd_i) begin
           Tests:       T1 T2 T3 
337        1/1                    state_d = StCtrlRead;
           Tests:       T1 T2 T3 
338        1/1                  end else if (ctrl_gnt && prog_i) begin
           Tests:       T1 T2 T3 
339        1/1                    state_d = StCtrlProg;
           Tests:       T1 T12 T20 
340        1/1                  end else if (ctrl_gnt) begin
           Tests:       T1 T2 T3 
341        1/1                    state_d = StCtrl;
           Tests:       T12 T23 T14 
342                             end
                        MISSING_ELSE
343                           end
344                     
345                           // Controller reads are very slow.
346                           StCtrlRead: begin
347        1/1                  if (rd_stage_data_valid) begin
           Tests:       T1 T2 T3 
348        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T1 T2 T3 
349        1/1                    state_d = StIdle;
           Tests:       T1 T2 T3 
350                             end
                        MISSING_ELSE
351                           end
352                     
353                           // Controller program data may be packed based on
354                           // address alignment
355                           StCtrlProg: begin
356        1/1                  reqs[PhyProg] = 1'b1;
           Tests:       T1 T12 T20 
357        1/1                  if (prog_ack) begin
           Tests:       T1 T12 T20 
358        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T1 T12 T20 
359        1/1                    state_d = StIdle;
           Tests:       T1 T12 T20 
360                             end
                        MISSING_ELSE
361                           end
362                     
363                           // other controller operations directly interface with flash
364                           StCtrl: begin
365        1/1                  reqs[PhyPgErase] = pg_erase_i;
           Tests:       T12 T23 T14 
366        1/1                  reqs[PhyBkErase] = bk_erase_i;
           Tests:       T12 T23 T14 
367        1/1                  if (erase_ack) begin
           Tests:       T12 T23 T14 
368        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T12 T23 T14 
369        1/1                    state_d = StIdle;
           Tests:       T12 T23 T14 
370                             end
                        MISSING_ELSE
371                           end
372                     
373                           StDisable: begin
374        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T7 T8 T9 
375        1/1                  state_d = StDisable;
           Tests:       T7 T8 T9 
376                           end
377                     
378                           default: begin
379                             ctrl_fsm_idle = 1'b1;
380                             fsm_err = 1'b1;
381                           end
382                     
383                         endcase // unique case (state_q)
384                       end // always_comb
385                     
386                       // determine spurious acks
387                       // SEC_CM: PHY_ACK.CTRL.CONSISTENCY
388        1/1            assign spurious_ack_o = (ctrl_fsm_idle & ctrl_rsp_vld) |
           Tests:       T1 T2 T3 
389                                               ((host_outstanding == '0) & host_req_done_o);
390                     
391                       // transactions coming from flash controller are always data type
392        1/1            assign muxed_addr = host_sel ? host_addr_i : addr_i;
           Tests:       T1 T2 T3 
393        1/1            assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
           Tests:       T1 T2 T3 
394        1/1            assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
           Tests:       T1 T2 T3 
395        1/1            assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
           Tests:       T1 T2 T3 
396        1/1            assign rd_done_o = ctrl_rsp_vld & rd_i;
           Tests:       T1 T2 T3 
397        1/1            assign prog_done_o = ctrl_rsp_vld & prog_i;
           Tests:       T1 T2 T3 
398        1/1            assign erase_done_o = ctrl_rsp_vld & (pg_erase_i | bk_erase_i);
           Tests:       T1 T2 T3 
399                     
400                       ////////////////////////
401                       // read pipeline
402                       ////////////////////////
403                     
404                       logic flash_rd_req;
405                       logic [FullDataWidth-1:0] flash_rdata;
406                       logic rd_calc_req;
407                       logic [BankAddrW-1:0] rd_calc_addr;
408                       logic rd_op_req;
409                       logic [DataWidth-1:0] rd_scrambled_data;
410                       logic [DataWidth-1:0] rd_descrambled_data;
411                     
412                       // if host grant is encountered, transactions return in-band
413                       // error until all transactions are flushed.
414                       logic phy_rd_err;
415        1/1            assign rd_err_o = phy_rd_err;
           Tests:       T1 T2 T3 
416                     
417                     
418                       // After host_gnt_rd_err asserts, no more host requests
419                       // are granted until all transactions are flushed. This means
420                       // the last outstanding transaction is by definition the "error".
421                       //
422                       // If ctrl_fsm_idle inexplicably goes low while there are host transactions
423                       // the transaction handling may be irreversibly broken.
424                       // The host_oustanding_rd_err makes a best effort attempt to cleanly
425                       // recover.  It responds with in-band error controller transactions until the
426                       // all pending transactions are flushed.
427                       logic arb_host_gnt_err;
428        1/1            assign arb_host_gnt_err = (host_gnt_rd_err & host_outstanding == 1'b1) |
           Tests:       T1 T2 T3 
429                                                 (host_outstanding_rd_err);
430                     
431                       flash_phy_rd u_rd (
432                         .clk_i,
433                         .rst_ni,
434                         .buf_en_i(rd_buf_en_i),
435                         //.req_i(reqs[PhyRead] | host_req),
436                         .req_i(phy_req & (rd_i | host_req)),
437                         .descramble_i(muxed_scramble_en),
438                         .ecc_i(muxed_ecc_en),
439                         .prog_i(reqs[PhyProg]),
440                         .pg_erase_i(reqs[PhyPgErase]),
441                         .bk_erase_i(reqs[PhyBkErase]),
442                         .addr_i(muxed_addr),
443                         .part_i(muxed_part),
444                         // info select cannot be generated by the host
445                         .info_sel_i(info_sel_i),
446                         .rdy_o(rd_stage_rdy),
447                         .data_valid_o(rd_stage_data_valid),
448                         .data_err_o(phy_rd_err),
449                         .data_host_o(rd_data_host_o),
450                         .data_ctrl_o(rd_data_ctrl_o),
451                         .idle_o(rd_stage_idle),
452                          // a catastrophic arbitration error has been observed, just dump
453                          // dump returns until all transactions are flushed.
454                         .arb_err_i(arb_host_gnt_err),
455                         .req_o(flash_rd_req),
456                         .ack_i(ack),
457                         .done_i(done),
458                         .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
459                         //scramble unit interface
460                         .calc_req_o(rd_calc_req),
461                         .calc_addr_o(rd_calc_addr),
462                         .descramble_req_o(rd_op_req),
463                         .scrambled_data_o(rd_scrambled_data),
464                         .calc_ack_i(calc_ack),
465                         .descramble_ack_i(op_ack),
466                         .mask_i(scramble_mask),
467                         .descrambled_data_i(rd_descrambled_data),
468                         .ecc_single_err_o,
469                         .ecc_addr_o,
470                         .relbl_ecc_err_o,
471                         .intg_ecc_err_o,
472                         .fifo_err_o
473                         );
474                     
475                       ////////////////////////
476                       // program pipeline
477                       ////////////////////////
478                     
479                       logic [FullDataWidth-1:0] prog_full_data;
480                       logic [DataWidth-1:0] prog_scrambled_data;
481                       logic [DataWidth-1:0] prog_data;
482                       logic prog_last;
483                       logic flash_prog_req;
484                       logic prog_calc_req;
485                       logic prog_op_req;
486                       logic prog_fsm_err;
487                     
488                       if (WidthMultiple == 1) begin : gen_single_prog_data
489                         assign flash_prog_req = reqs[PhyProg];
490                         assign prog_data = prog_data_i[BusWidth-1:0];
491                         assign prog_fsm_err = '0;
492                       end else begin : gen_prog_data
493                     
494                         // SEC_CM: MEM.INTEGRITY
495                         flash_phy_prog u_prog (
496                           .clk_i,
497                           .rst_ni,
498                           .req_i(reqs[PhyProg]),
499                           .disable_i(flash_disable[ProgFsmDisableIdx]),
500                           .scramble_i(muxed_scramble_en),
501                           .ecc_i(muxed_ecc_en),
502                           .sel_i(addr_i[0 +: WordSelW]),
503                           .data_i(prog_data_i),
504                           .last_i(prog_last_i),
505                           .ack_i(ack),
506                           .done_i(done),
507                           .calc_ack_i(calc_ack),
508                           .scramble_ack_i(op_ack),
509                           .mask_i(scramble_mask),
510                           .scrambled_data_i(prog_scrambled_data),
511                           .calc_req_o(prog_calc_req),
512                           .scramble_req_o(prog_op_req),
513                           .req_o(flash_prog_req),
514                           .last_o(prog_last),
515                           .ack_o(prog_ack),
516                           .block_data_o(prog_data),
517                           .data_o(prog_full_data),
518                           .fsm_err_o(prog_fsm_err),
519                           .intg_err_o(prog_intg_err_o)
520                         );
521                       end
522                     
523        1/1            assign fsm_err_o = fsm_err | prog_fsm_err;
           Tests:       T1 T2 T3 
524                     
525                       ////////////////////////
526                       // erase pipeline
527                       ////////////////////////
528                     
529                       logic flash_pg_erase_req;
530                       logic flash_bk_erase_req;
531                       logic erase_suspend_req;
532                       flash_phy_erase u_erase (
533                         .clk_i,
534                         .rst_ni,
535                         .pg_erase_req_i(reqs[PhyPgErase]),
536                         .bk_erase_req_i(reqs[PhyBkErase]),
537                         .suspend_req_i(erase_suspend_req_i),
538                         .ack_o(erase_ack),
539                         .pg_erase_req_o(flash_pg_erase_req),
540                         .bk_erase_req_o(flash_bk_erase_req),
541                         .suspend_req_o(erase_suspend_req),
542                         .ack_i(ack),
543                         .done_i(done)
544                       );
545                     
546                       ////////////////////////
547                       // bundle data to send to shared scrambling module
548                       ////////////////////////
549                     
550        1/1            assign scramble_req_o.calc_req       = prog_calc_req | rd_calc_req;
           Tests:       T1 T2 T3 
551        1/1            assign scramble_req_o.op_req         = prog_op_req | rd_op_req;
           Tests:       T1 T2 T3 
552        1/1            assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
           Tests:       T1 T2 T3 
553        1/1            assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
           Tests:       T1 T2 T3 
554                                                                              rd_calc_addr;
555        1/1            assign scramble_req_o.plain_data     = prog_data;
           Tests:       T1 T2 T3 
556        1/1            assign scramble_req_o.scrambled_data = rd_scrambled_data;
           Tests:       T1 T2 T3 
557        1/1            assign calc_ack            = scramble_rsp_i.calc_ack;
           Tests:       T1 T2 T3 
558        1/1            assign op_ack              = scramble_rsp_i.op_ack;
           Tests:       T1 T2 T3 
559        1/1            assign scramble_mask       = scramble_rsp_i.mask;
           Tests:       T1 T2 T3 
560        1/1            assign rd_descrambled_data = scramble_rsp_i.plain_data;
           Tests:       T1 T2 T3 
561        1/1            assign prog_scrambled_data = scramble_rsp_i.scrambled_data;
           Tests:       T1 T2 T3 
562                     
563                       ////////////////////////
564                       // Actual connection to flash phy
565                       ////////////////////////
566                     
567                       // Connections to the actual flash macro wrapper
568        1/1            assign prim_flash_req_o = '{
           Tests:       T1 T2 T3 
569                         rd_req: flash_rd_req,
570                         prog_req: flash_prog_req,
571                         prog_last: prog_last,
572                         prog_type: prog_type_i,
573                         pg_erase_req: flash_pg_erase_req,
574                         bk_erase_req: flash_bk_erase_req,
575                         erase_suspend_req: erase_suspend_req,
576                         // high endurance enable does not cause changes to
577                         // transaction protocol and is forwarded directly to the wrapper
578                         he: he_en_i,
579                         addr: muxed_addr[BusBankAddrW-1:LsbAddrBit],
580                         part: muxed_part,
581                         info_sel: info_sel_i,
582                         prog_full_data: prog_full_data
583                       };
584                     
585        1/1            assign ack = prim_flash_rsp_i.ack;
           Tests:       T1 T2 T3 
586        1/1            assign done = prim_flash_rsp_i.done;
           Tests:       T1 T2 T3 
587        1/1            assign flash_rdata = prim_flash_rsp_i.rdata;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	102	96.23
Logical	106	102	96.23
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Covered	T10,T180,T228

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T180,T228

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T20

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T15
1	0	1	Covered	T2,T3,T20
1	1	0	Covered	T58,T62,T63
1	1	1	Covered	T2,T3,T20

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T129,T127
1	0	Covered	T20,T23,T13
1	1	Covered	T2,T3,T20

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T238
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T10,T58

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T20
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T12,T23,T14
1	1	Covered	T1,T12,T20

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T58,T62,T63
1	0	Covered	T239

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T239

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T62,T63

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T20
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T20

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T23,T14

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T74,T25,T65
1	0	Covered	T12,T23,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T228

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T228
1	1	Covered	T228

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T20
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T228

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T43,T44
1	0	Covered	T16,T43,T44

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T8

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T8

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T12,T23,T14
StCtrlProg	339	Covered	T1,T12,T20
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T7,T8,T9
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T12,T23,T14
StCtrlProg->StIdle	359	Covered	T1,T12,T20
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T12,T23,T14
StIdle->StCtrlProg	339	Covered	T1,T12,T20
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T7,T8,T9

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

317          assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

392          assign muxed_addr = host_sel ? host_addr_i : addr_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

393          assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

394          assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

395          assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

552          assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T8
0	Covered	T1,T2,T3

553          assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T8
0	Covered	T1,T2,T3

431          flash_phy_rd u_rd (
                                
432            .clk_i,
                      
433            .rst_ni,
                       
434            .buf_en_i(rd_buf_en_i),
                                      
435            //.req_i(reqs[PhyRead] | host_req),
                                                  
436            .req_i(phy_req & (rd_i | host_req)),
                                                   
437            .descramble_i(muxed_scramble_en),
                                                
438            .ecc_i(muxed_ecc_en),
                                    
439            .prog_i(reqs[PhyProg]),
                                      
440            .pg_erase_i(reqs[PhyPgErase]),
                                             
441            .bk_erase_i(reqs[PhyBkErase]),
                                             
442            .addr_i(muxed_addr),
                                   
443            .part_i(muxed_part),
                                   
444            // info select cannot be generated by the host
                                                             
445            .info_sel_i(info_sel_i),
                                       
446            .rdy_o(rd_stage_rdy),
                                    
447            .data_valid_o(rd_stage_data_valid),
                                                  
448            .data_err_o(phy_rd_err),
                                       
449            .data_host_o(rd_data_host_o),
                                            
450            .data_ctrl_o(rd_data_ctrl_o),
                                            
451            .idle_o(rd_stage_idle),
                                      
452             // a catastrophic arbitration error has been observed, just dump
                                                                                
453             // dump returns until all transactions are flushed.
                                                                   
454            .arb_err_i(arb_host_gnt_err),
                                            
455            .req_o(flash_rd_req),
                                    
456            .ack_i(ack),
                           
457            .done_i(done),
                             
458            .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T228
0	Covered	T1,T2,T3

152            if (!rst_ni) begin
               -1-  
153              arb_cnt <= '0;
                 ==>
154            end else if (ctrl_rsp_vld) begin
                        -2-  
155              arb_cnt <= '0;
                 ==>
156            end else if (inc_arb_cnt) begin
                        -3-  
157              arb_cnt <= arb_cnt + 1'b1;
                 ==>
158            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T10,T58
0	0	0	Covered	T1,T2,T3

165          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

203            if (!rst_ni) begin
               -1-  
204              host_gnt_err_o <= '0;
                 ==>
205            end else if (host_gnt_err_event | host_outstanding_err_event) begin
                        -2-  
206              host_gnt_err_o <= 1'b1;
                 ==>
207            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T180,T228
0	0	Covered	T1,T2,T3

215            if (!rst_ni) begin
               -1-  
216              host_gnt_rd_err <= '0;
                 ==>
217            end else if (host_outstanding == '0) begin
                        -2-  
218              host_gnt_rd_err <= '0;
                 ==>
219            end else if (host_gnt_err_event) begin
                        -3-  
220              host_gnt_rd_err <= 1'b1;
                 ==>
221            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T228,T11
0	0	0	Covered	T2,T3,T20

229            if (!rst_ni) begin
               -1-  
230              host_outstanding_rd_err <= '0;
                 ==>
231            end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
                        -2-  
232              host_outstanding_rd_err <= '0;
                 ==>
233            end else if (host_outstanding_err_event) begin
                        -3-  
234              host_outstanding_rd_err <= 1'b1;
                 ==>
235            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T11
0	0	0	Covered	T1,T2,T3

331            unique case (state_q)
                      -1-  
332              StIdle: begin
333                ctrl_fsm_idle = 1'b1;
334                if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
                   -2-  
335                  state_d = StDisable;
                     ==>
336                end else if (ctrl_gnt && rd_i) begin
                            -3-  
337                  state_d = StCtrlRead;
                     ==>
338                end else if (ctrl_gnt && prog_i) begin
                            -4-  
339                  state_d = StCtrlProg;
                     ==>
340                end else if (ctrl_gnt) begin
                            -5-  
341                  state_d = StCtrl;
                     ==>
342                end
                   MISSING_ELSE
                   ==>
343              end
344        
345              // Controller reads are very slow.
346              StCtrlRead: begin
347                if (rd_stage_data_valid) begin
                   -6-  
348                  ctrl_rsp_vld = 1'b1;
                     ==>
349                  state_d = StIdle;
350                end
                   MISSING_ELSE
                   ==>
351              end
352        
353              // Controller program data may be packed based on
354              // address alignment
355              StCtrlProg: begin
356                reqs[PhyProg] = 1'b1;
357                if (prog_ack) begin
                   -7-  
358                  ctrl_rsp_vld = 1'b1;
                     ==>
359                  state_d = StIdle;
360                end
                   MISSING_ELSE
                   ==>
361              end
362        
363              // other controller operations directly interface with flash
364              StCtrl: begin
365                reqs[PhyPgErase] = pg_erase_i;
366                reqs[PhyBkErase] = bk_erase_i;
367                if (erase_ack) begin
                   -8-  
368                  ctrl_rsp_vld = 1'b1;
                     ==>
369                  state_d = StIdle;
370                end
                   MISSING_ELSE
                   ==>
371              end
372        
373              StDisable: begin
374                ctrl_fsm_idle = 1'b1;
                   ==>
375                state_d = StDisable;
376              end
377        
378              default: begin
379                ctrl_fsm_idle = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T12,T20
StIdle	0	0	0	1	-	-	-	Covered	T12,T23,T14
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T12,T20
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T12,T20
StCtrl	-	-	-	-	-	-	1	Covered	T12,T23,T14
StCtrl	-	-	-	-	-	-	0	Covered	T12,T23,T14
StDisable	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Covered	T10,T11,T16

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	776511532	3093942	0	0
CtrlPrio_A	776511532	3093942	0	0
HostTransIdleChk_A	776511532	43921679	0	0
NoRemainder_A	2114	2114	0	0
OneHotReqs_A	776511532	774831282	0	0
Pow2Multiple_A	2114	2114	0	0
RdTxnCheck_A	776186580	774506330	0	0
u_state_regs_A	776511532	774831282	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	3093942	0	0
T10	1038	5	0	0
T15	59020	74	0	0
T27	451178	0	0	0
T36	0	4770	0	0
T39	0	234	0	0
T41	0	4530	0	0
T47	0	2396	0	0
T48	0	3307	0	0
T51	324582	0	0	0
T54	10472	0	0	0
T55	0	2466	0	0
T58	3052	0	0	0
T59	6970	0	0	0
T64	4336	0	0	0
T66	0	5	0	0
T98	119544	0	0	0
T99	0	10445	0	0
T110	2254	0	0	0
T130	0	4416	0	0
T217	0	2849	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	3093942	0	0
T10	1038	5	0	0
T15	59020	74	0	0
T27	451178	0	0	0
T36	0	4770	0	0
T39	0	234	0	0
T41	0	4530	0	0
T47	0	2396	0	0
T48	0	3307	0	0
T51	324582	0	0	0
T54	10472	0	0	0
T55	0	2466	0	0
T58	3052	0	0	0
T59	6970	0	0	0
T64	4336	0	0	0
T66	0	5	0	0
T98	119544	0	0	0
T99	0	10445	0	0
T110	2254	0	0	0
T130	0	4416	0	0
T217	0	2849	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	43921679	0	0
T2	21696	408	0	0
T3	2448	15	0	0
T4	1780	0	0	0
T7	1944	0	0	0
T10	0	32	0	0
T12	4004	0	0	0
T13	0	40	0	0
T15	0	685	0	0
T17	3088	0	0	0
T18	3900	0	0	0
T19	4606	0	0	0
T20	2946	24	0	0
T23	14598	76	0	0
T39	0	591	0	0
T54	0	881	0	0
T58	0	20	0	0
T59	0	151	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2114	2114	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T7	2	2	0	0
T12	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	774831282	0	0
T1	7812	7706	0	0
T2	21696	21556	0	0
T3	2448	2334	0	0
T4	1780	1680	0	0
T7	1944	1844	0	0
T12	4004	3888	0	0
T17	3088	2978	0	0
T18	3900	3732	0	0
T19	4606	4422	0	0
T20	2946	2676	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2114	2114	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T7	2	2	0	0
T12	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776186580	774506330	0	0
T1	7812	7706	0	0
T2	21696	21556	0	0
T3	2448	2334	0	0
T4	1780	1680	0	0
T7	1944	1844	0	0
T12	4004	3888	0	0
T17	3088	2978	0	0
T18	3900	3732	0	0
T19	4606	4422	0	0
T20	2946	2676	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	774831282	0	0
T1	7812	7706	0	0
T2	21696	21556	0	0
T3	2448	2334	0	0
T4	1780	1680	0	0
T7	1944	1844	0	0
T12	4004	3888	0	0
T17	3088	2978	0	0
T18	3900	3732	0	0
T19	4606	4422	0	0
T20	2946	2676	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

151                       always_ff @(posedge clk_i or negedge rst_ni) begin
152        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
153        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T3 
154        1/1              end else if (ctrl_rsp_vld) begin
           Tests:       T1 T2 T3 
155        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T18 
156        1/1              end else if (inc_arb_cnt) begin
           Tests:       T1 T2 T3 
157        1/1                arb_cnt <= arb_cnt + 1'b1;
           Tests:       T15 T10 T39 
158                         end
                        MISSING_ELSE
159                       end
160                     
161                       import prim_mubi_pkg::mubi4_test_false_strict;
162                       import prim_mubi_pkg::mubi4_test_true_loose;
163                     
164                       // SEC_CM: PHY.FSM.SPARSE
165        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
165.1                   `ifdef SIMULATION                                   
165.2                       prim_sparse_fsm_flop #(                           
165.3                         .StateEnumT(state_e),                            
165.4                         .Width($bits(state_e)),                          
165.5                         .ResetValue($bits(state_e)'(StIdle)),          
165.6                         .EnableAlertTriggerSVA(1), 
165.7                         .CustomForceName("state_q")          
165.8                       ) u_state_regs (                                        
165.9                         .clk_i   ( clk_i   ),                           
165.10                        .rst_ni  ( rst_ni ),                           
165.11                        .state_i ( state_d     ),                           
165.12                        .state_o (         )                            
165.13                      );                                                
165.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
165.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
165.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
165.17                      end else begin                                    
165.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
165.19                      end                                               
165.20                    end  
165.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
165.22                      else begin                                                                           
165.23                        `ifdef UVM                                                                               
165.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
165.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv", 165, "", 1);                                
165.26                  `else                                                                                    
165.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
165.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
165.29                  `endif                                                              
165.30                      end 
165.31                    `else                                               
165.32                      prim_sparse_fsm_flop #(                           
165.33                        .StateEnumT(state_e),                            
165.34                        .Width($bits(state_e)),                          
165.35                        .ResetValue($bits(state_e)'(StIdle)),          
165.36                        .EnableAlertTriggerSVA(1)  
165.37                      ) u_state_regs (                                        
165.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
165.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
165.40                        .state_i ( state_d     ),                           
165.41                        .state_o ( state_q     )                            
165.42                      );                                                
165.43                    `endif166                     
167                       typedef enum logic [2:0] {
168                         HostDisableIdx,
169                         CtrlDisableIdx,
170                         FsmDisableIdx,
171                         ProgFsmDisableIdx,
172                         LastDisableIdx
173                       } phy_core_disable_e;
174                     
175                       prim_mubi_pkg::mubi4_t [LastDisableIdx-1:0] flash_disable;
176                       prim_mubi4_sync #(
177                         .NumCopies(int'(LastDisableIdx)),
178                         .AsyncOn(0)
179                       ) u_disable_buf (
180                         .clk_i,
181                         .rst_ni,
182                         .mubi_i(flash_disable_i),
183                         .mubi_o(flash_disable)
184                       );
185                     
186                       // Oustanding width is slightly larger to ensure a faulty increment is able to reach
187                       // the higher value. For example if RspOrderDepth were 3, a clog2 of 3 would still be 2
188                       // and not allow the counter to increment to 4.
189                       localparam int OutstandingRdWidth = $clog2(RspOrderDepth+2);
190                       logic [OutstandingRdWidth-1:0] host_outstanding;
191                       logic ctrl_fsm_idle;
192                       logic host_req;
193                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
194                       // A host transaction was granted to the muxed partition, this is illegal
195                       logic host_gnt_err_event;
196        1/1            assign host_gnt_err_event = (host_gnt && muxed_part != flash_ctrl_pkg::FlashPartData);
           Tests:       T1 T2 T3 
197                       // Controller fsm became non idle when there are pending host transactions, this is
198                       // illegal.
199                       logic host_outstanding_err_event;
200        1/1            assign host_outstanding_err_event = |host_outstanding & !ctrl_fsm_idle;
           Tests:       T1 T2 T3 
201                     
202                       always_ff @(posedge clk_i or negedge rst_ni) begin
203        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
204        1/1                host_gnt_err_o <= '0;
           Tests:       T1 T2 T3 
205        1/1              end else if (host_gnt_err_event | host_outstanding_err_event) begin
           Tests:       T1 T2 T3 
206        1/1                host_gnt_err_o <= 1'b1;
           Tests:       T10 
207                         end
                        MISSING_ELSE
208                       end
209                     
210                       // When host grant errors occur, also create in band error responses.
211                       // The error condition is held until all existing host transactions are
212                       // processed.
213                       logic host_gnt_rd_err;
214                       always_ff @(posedge clk_i or negedge rst_ni) begin
215        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
216        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
217        1/1              end else if (host_outstanding == '0) begin
           Tests:       T1 T2 T3 
218        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
219        1/1              end else if (host_gnt_err_event) begin
           Tests:       T2 T20 T23 
220        1/1                host_gnt_rd_err <= 1'b1;
           Tests:       T10 
221                         end
                        MISSING_ELSE
222                       end
223                     
224                       // When host outstanding errors occur, also create in band error responses.
225                       // The error condition is held until all existing host and controller
226                       // transactions are processed.
227                       logic host_outstanding_rd_err;
228                       always_ff @(posedge clk_i or negedge rst_ni) begin
229        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
230        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
231        1/1              end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
           Tests:       T1 T2 T3 
232        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
233        1/1              end else if (host_outstanding_err_event) begin
           Tests:       T1 T2 T18 
234        1/1                host_outstanding_rd_err <= 1'b1;
           Tests:       T10 
235                         end
                        MISSING_ELSE
236                       end
237                     
238                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
239                       prim_count #(
240                         .Width(OutstandingRdWidth),
241                         .ResetValue('0)
242                       ) u_host_outstanding_cnt (
243                         .clk_i,
244                         .rst_ni,
245                         .clr_i('0),
246                         .set_i('0),
247                         .set_cnt_i('0),
248                         .incr_en_i(host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)),
249                         .decr_en_i(!host_gnt && host_req_done_o && |host_outstanding),
250                         .step_i(OutstandingRdWidth'(1'b1)),
251                         .commit_i(1'b1),
252                         .cnt_o(host_outstanding),
253                         .cnt_after_commit_o(),
254                         .err_o(cnt_err_o)
255                       );
256                     
257                       // If host_outstanding is non-zero, the controller fsm must be idle..
258                       // This assertion needs to be disabled for sec_cm testing
259                       `ASSERT(HostTransIdleChk_A, |host_outstanding |-> ctrl_fsm_idle)
260                     
261                       //always_ff @(posedge clk_i or negedge rst_ni) begin
262                       //  if (!rst_ni) begin
263                       //    host_outstanding <= '0;
264                       //  end else if (host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)) begin
265                       //    host_outstanding <= host_outstanding + 1'b1;
266                       //  end else if (!host_gnt && host_req_done_o && |host_outstanding) begin
267                       //    host_outstanding <= host_outstanding - 1'b1;
268                       //  end
269                       //end
270                     
271                       `ASSERT(RdTxnCheck_A, host_outstanding <= RspOrderDepth)
272                     
273                       // The host request is suppressed under a variety of conditions:
274                       // 1. If a controller transaction is already ongoing.
275                       // 2. If a grant or outstanding error has already been observed but not yet
276                       //    fully processed.
277        1/1            assign host_req = host_req_i & (arb_cnt < ArbCnt[CntWidth-1:0]) & ctrl_fsm_idle &
           Tests:       T1 T2 T3 
278                                         !host_gnt_rd_err & !host_outstanding_rd_err &
279                                         mubi4_test_false_strict(flash_disable[HostDisableIdx]);
280        1/1            assign host_sel = host_req;
           Tests:       T1 T2 T3 
281        1/1            assign host_gnt = host_req & host_req_rdy_o;
           Tests:       T1 T2 T3 
282        1/1            assign host_req_done_o = |host_outstanding & rd_stage_data_valid;
           Tests:       T1 T2 T3 
283                     
284                       // controller request can only win after the entire read pipeline
285                       // clears
286                       logic ctrl_req;
287        1/1            assign ctrl_req = req_i & rd_stage_idle &
           Tests:       T1 T2 T3 
288                                         !host_gnt_rd_err & !host_outstanding_rd_err &
289                                         mubi4_test_false_strict(flash_disable[CtrlDisableIdx]);
290                     
291                       logic [1:0] data_tie_off [2];
292                       assign data_tie_off = '{default: '0};
293                     
294                       // SEC_CM: PHY_ARBITER.CTRL.REDUN
295                       logic phy_req;
296                       logic phy_rdy;
297                     
298                       prim_arbiter_tree_dup #(
299                         .N(2),
300                         .DW(2),
301                         .EnDataPort('0),
302                         .FixedArb(1)
303                       ) u_host_arb (
304                         .clk_i,
305                         .rst_ni,
306                         .req_chk_i('0),
307                         .req_i({ctrl_req, host_req}),
308                         .data_i(data_tie_off),
309                         .gnt_o({ctrl_gnt, host_req_rdy_o}),
310                         .idx_o(),
311                         .valid_o(phy_req),
312                         .data_o(),
313                         .ready_i(phy_rdy),
314                         .err_o(arb_err_o)
315                       );
316                     
317        1/1            assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
           Tests:       T1 T2 T3 
318                     
319                     
320                       // if request happens at the same time as a host grant, increment count
321        1/1            assign inc_arb_cnt = req_i & host_gnt;
           Tests:       T1 T2 T3 
322                     
323                       logic fsm_err;
324                       always_comb begin
325        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
326        1/1              reqs = '0;
           Tests:       T1 T2 T3 
327        1/1              ctrl_rsp_vld = '0;
           Tests:       T1 T2 T3 
328        1/1              fsm_err = '0;
           Tests:       T1 T2 T3 
329        1/1              ctrl_fsm_idle = '0;
           Tests:       T1 T2 T3 
330                     
331        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
332                           StIdle: begin
333        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T1 T2 T3 
334        1/1                  if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
           Tests:       T1 T2 T3 
335        1/1                    state_d = StDisable;
           Tests:       T7 T8 T9 
336        1/1                  end else if (ctrl_gnt && rd_i) begin
           Tests:       T1 T2 T3 
337        1/1                    state_d = StCtrlRead;
           Tests:       T2 T18 T20 
338        1/1                  end else if (ctrl_gnt && prog_i) begin
           Tests:       T1 T2 T3 
339        1/1                    state_d = StCtrlProg;
           Tests:       T1 T8 T9 
340        1/1                  end else if (ctrl_gnt) begin
           Tests:       T1 T2 T3 
341        1/1                    state_d = StCtrl;
           Tests:       T23 T51 T10 
342                             end
                        MISSING_ELSE
343                           end
344                     
345                           // Controller reads are very slow.
346                           StCtrlRead: begin
347        1/1                  if (rd_stage_data_valid) begin
           Tests:       T2 T18 T20 
348        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T2 T18 T20 
349        1/1                    state_d = StIdle;
           Tests:       T2 T18 T20 
350                             end
                        MISSING_ELSE
351                           end
352                     
353                           // Controller program data may be packed based on
354                           // address alignment
355                           StCtrlProg: begin
356        1/1                  reqs[PhyProg] = 1'b1;
           Tests:       T1 T8 T9 
357        1/1                  if (prog_ack) begin
           Tests:       T1 T8 T9 
358        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T1 T8 T9 
359        1/1                    state_d = StIdle;
           Tests:       T1 T8 T9 
360                             end
                        MISSING_ELSE
361                           end
362                     
363                           // other controller operations directly interface with flash
364                           StCtrl: begin
365        1/1                  reqs[PhyPgErase] = pg_erase_i;
           Tests:       T23 T51 T10 
366        1/1                  reqs[PhyBkErase] = bk_erase_i;
           Tests:       T23 T51 T10 
367        1/1                  if (erase_ack) begin
           Tests:       T23 T51 T10 
368        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T23 T51 T10 
369        1/1                    state_d = StIdle;
           Tests:       T23 T51 T10 
370                             end
                        MISSING_ELSE
371                           end
372                     
373                           StDisable: begin
374        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T7 T8 T9 
375        1/1                  state_d = StDisable;
           Tests:       T7 T8 T9 
376                           end
377                     
378                           default: begin
379                             ctrl_fsm_idle = 1'b1;
380                             fsm_err = 1'b1;
381                           end
382                     
383                         endcase // unique case (state_q)
384                       end // always_comb
385                     
386                       // determine spurious acks
387                       // SEC_CM: PHY_ACK.CTRL.CONSISTENCY
388        1/1            assign spurious_ack_o = (ctrl_fsm_idle & ctrl_rsp_vld) |
           Tests:       T1 T2 T3 
389                                               ((host_outstanding == '0) & host_req_done_o);
390                     
391                       // transactions coming from flash controller are always data type
392        1/1            assign muxed_addr = host_sel ? host_addr_i : addr_i;
           Tests:       T1 T2 T3 
393        1/1            assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
           Tests:       T1 T2 T3 
394        1/1            assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
           Tests:       T1 T2 T3 
395        1/1            assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
           Tests:       T1 T2 T3 
396        1/1            assign rd_done_o = ctrl_rsp_vld & rd_i;
           Tests:       T1 T2 T3 
397        1/1            assign prog_done_o = ctrl_rsp_vld & prog_i;
           Tests:       T1 T2 T3 
398        1/1            assign erase_done_o = ctrl_rsp_vld & (pg_erase_i | bk_erase_i);
           Tests:       T1 T2 T3 
399                     
400                       ////////////////////////
401                       // read pipeline
402                       ////////////////////////
403                     
404                       logic flash_rd_req;
405                       logic [FullDataWidth-1:0] flash_rdata;
406                       logic rd_calc_req;
407                       logic [BankAddrW-1:0] rd_calc_addr;
408                       logic rd_op_req;
409                       logic [DataWidth-1:0] rd_scrambled_data;
410                       logic [DataWidth-1:0] rd_descrambled_data;
411                     
412                       // if host grant is encountered, transactions return in-band
413                       // error until all transactions are flushed.
414                       logic phy_rd_err;
415        1/1            assign rd_err_o = phy_rd_err;
           Tests:       T1 T2 T3 
416                     
417                     
418                       // After host_gnt_rd_err asserts, no more host requests
419                       // are granted until all transactions are flushed. This means
420                       // the last outstanding transaction is by definition the "error".
421                       //
422                       // If ctrl_fsm_idle inexplicably goes low while there are host transactions
423                       // the transaction handling may be irreversibly broken.
424                       // The host_oustanding_rd_err makes a best effort attempt to cleanly
425                       // recover.  It responds with in-band error controller transactions until the
426                       // all pending transactions are flushed.
427                       logic arb_host_gnt_err;
428        1/1            assign arb_host_gnt_err = (host_gnt_rd_err & host_outstanding == 1'b1) |
           Tests:       T1 T2 T3 
429                                                 (host_outstanding_rd_err);
430                     
431                       flash_phy_rd u_rd (
432                         .clk_i,
433                         .rst_ni,
434                         .buf_en_i(rd_buf_en_i),
435                         //.req_i(reqs[PhyRead] | host_req),
436                         .req_i(phy_req & (rd_i | host_req)),
437                         .descramble_i(muxed_scramble_en),
438                         .ecc_i(muxed_ecc_en),
439                         .prog_i(reqs[PhyProg]),
440                         .pg_erase_i(reqs[PhyPgErase]),
441                         .bk_erase_i(reqs[PhyBkErase]),
442                         .addr_i(muxed_addr),
443                         .part_i(muxed_part),
444                         // info select cannot be generated by the host
445                         .info_sel_i(info_sel_i),
446                         .rdy_o(rd_stage_rdy),
447                         .data_valid_o(rd_stage_data_valid),
448                         .data_err_o(phy_rd_err),
449                         .data_host_o(rd_data_host_o),
450                         .data_ctrl_o(rd_data_ctrl_o),
451                         .idle_o(rd_stage_idle),
452                          // a catastrophic arbitration error has been observed, just dump
453                          // dump returns until all transactions are flushed.
454                         .arb_err_i(arb_host_gnt_err),
455                         .req_o(flash_rd_req),
456                         .ack_i(ack),
457                         .done_i(done),
458                         .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
459                         //scramble unit interface
460                         .calc_req_o(rd_calc_req),
461                         .calc_addr_o(rd_calc_addr),
462                         .descramble_req_o(rd_op_req),
463                         .scrambled_data_o(rd_scrambled_data),
464                         .calc_ack_i(calc_ack),
465                         .descramble_ack_i(op_ack),
466                         .mask_i(scramble_mask),
467                         .descrambled_data_i(rd_descrambled_data),
468                         .ecc_single_err_o,
469                         .ecc_addr_o,
470                         .relbl_ecc_err_o,
471                         .intg_ecc_err_o,
472                         .fifo_err_o
473                         );
474                     
475                       ////////////////////////
476                       // program pipeline
477                       ////////////////////////
478                     
479                       logic [FullDataWidth-1:0] prog_full_data;
480                       logic [DataWidth-1:0] prog_scrambled_data;
481                       logic [DataWidth-1:0] prog_data;
482                       logic prog_last;
483                       logic flash_prog_req;
484                       logic prog_calc_req;
485                       logic prog_op_req;
486                       logic prog_fsm_err;
487                     
488                       if (WidthMultiple == 1) begin : gen_single_prog_data
489                         assign flash_prog_req = reqs[PhyProg];
490                         assign prog_data = prog_data_i[BusWidth-1:0];
491                         assign prog_fsm_err = '0;
492                       end else begin : gen_prog_data
493                     
494                         // SEC_CM: MEM.INTEGRITY
495                         flash_phy_prog u_prog (
496                           .clk_i,
497                           .rst_ni,
498                           .req_i(reqs[PhyProg]),
499                           .disable_i(flash_disable[ProgFsmDisableIdx]),
500                           .scramble_i(muxed_scramble_en),
501                           .ecc_i(muxed_ecc_en),
502                           .sel_i(addr_i[0 +: WordSelW]),
503                           .data_i(prog_data_i),
504                           .last_i(prog_last_i),
505                           .ack_i(ack),
506                           .done_i(done),
507                           .calc_ack_i(calc_ack),
508                           .scramble_ack_i(op_ack),
509                           .mask_i(scramble_mask),
510                           .scrambled_data_i(prog_scrambled_data),
511                           .calc_req_o(prog_calc_req),
512                           .scramble_req_o(prog_op_req),
513                           .req_o(flash_prog_req),
514                           .last_o(prog_last),
515                           .ack_o(prog_ack),
516                           .block_data_o(prog_data),
517                           .data_o(prog_full_data),
518                           .fsm_err_o(prog_fsm_err),
519                           .intg_err_o(prog_intg_err_o)
520                         );
521                       end
522                     
523        1/1            assign fsm_err_o = fsm_err | prog_fsm_err;
           Tests:       T1 T2 T3 
524                     
525                       ////////////////////////
526                       // erase pipeline
527                       ////////////////////////
528                     
529                       logic flash_pg_erase_req;
530                       logic flash_bk_erase_req;
531                       logic erase_suspend_req;
532                       flash_phy_erase u_erase (
533                         .clk_i,
534                         .rst_ni,
535                         .pg_erase_req_i(reqs[PhyPgErase]),
536                         .bk_erase_req_i(reqs[PhyBkErase]),
537                         .suspend_req_i(erase_suspend_req_i),
538                         .ack_o(erase_ack),
539                         .pg_erase_req_o(flash_pg_erase_req),
540                         .bk_erase_req_o(flash_bk_erase_req),
541                         .suspend_req_o(erase_suspend_req),
542                         .ack_i(ack),
543                         .done_i(done)
544                       );
545                     
546                       ////////////////////////
547                       // bundle data to send to shared scrambling module
548                       ////////////////////////
549                     
550        1/1            assign scramble_req_o.calc_req       = prog_calc_req | rd_calc_req;
           Tests:       T1 T2 T3 
551        1/1            assign scramble_req_o.op_req         = prog_op_req | rd_op_req;
           Tests:       T1 T2 T3 
552        1/1            assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
           Tests:       T1 T2 T3 
553        1/1            assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
           Tests:       T1 T2 T3 
554                                                                              rd_calc_addr;
555        1/1            assign scramble_req_o.plain_data     = prog_data;
           Tests:       T1 T2 T3 
556        1/1            assign scramble_req_o.scrambled_data = rd_scrambled_data;
           Tests:       T1 T2 T3 
557        1/1            assign calc_ack            = scramble_rsp_i.calc_ack;
           Tests:       T20 T23 T13 
558        1/1            assign op_ack              = scramble_rsp_i.op_ack;
           Tests:       T1 T2 T3 
559        1/1            assign scramble_mask       = scramble_rsp_i.mask;
           Tests:       T1 T2 T3 
560        1/1            assign rd_descrambled_data = scramble_rsp_i.plain_data;
           Tests:       T1 T2 T3 
561        1/1            assign prog_scrambled_data = scramble_rsp_i.scrambled_data;
           Tests:       T1 T2 T3 
562                     
563                       ////////////////////////
564                       // Actual connection to flash phy
565                       ////////////////////////
566                     
567                       // Connections to the actual flash macro wrapper
568        1/1            assign prim_flash_req_o = '{
           Tests:       T1 T2 T3 
569                         rd_req: flash_rd_req,
570                         prog_req: flash_prog_req,
571                         prog_last: prog_last,
572                         prog_type: prog_type_i,
573                         pg_erase_req: flash_pg_erase_req,
574                         bk_erase_req: flash_bk_erase_req,
575                         erase_suspend_req: erase_suspend_req,
576                         // high endurance enable does not cause changes to
577                         // transaction protocol and is forwarded directly to the wrapper
578                         he: he_en_i,
579                         addr: muxed_addr[BusBankAddrW-1:LsbAddrBit],
580                         part: muxed_part,
581                         info_sel: info_sel_i,
582                         prog_full_data: prog_full_data
583                       };
584                     
585        1/1            assign ack = prim_flash_rsp_i.ack;
           Tests:       T1 T2 T3 
586        1/1            assign done = prim_flash_rsp_i.done;
           Tests:       T1 T2 T3 
587        1/1            assign flash_rdata = prim_flash_rsp_i.rdata;
           Tests:       T1 T2 T18 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	91	85.85
Logical	106	91	85.85
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T23
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T20,T23
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T20,T23
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T20,T23
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T15,T54
1	1	0	Not Covered
1	1	1	Covered	T2,T20,T23

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T54
1	0	1	Covered	T2,T20,T23
1	1	0	Not Covered
1	1	1	Covered	T2,T20,T23

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T129,T127
1	0	Covered	T20,T23,T13
1	1	Covered	T2,T20,T23

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T20
1	0	Covered	T2,T20,T23
1	1	Covered	T2,T20,T23

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T238
1	0	Covered	T1,T2,T18
1	1	Covered	T2,T20,T23

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T2,T18
1	1	Covered	T15,T39,T47

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T8
1	1	Covered	T2,T18,T20

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T13
1	0	Covered	T23,T51,T46
1	1	Covered	T1,T8,T9

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T8
1	1	Covered	T2,T18,T20

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T2,T18,T20
1	1	Covered	T1,T8,T9

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T14
1	0	Covered	T1,T2,T18
1	1	Covered	T23,T51,T46

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T74,T25,T65
1	0	Covered	T12,T23,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T23
1	0	Not Covered
1	1	Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T23

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T8
1	1	Covered	T2,T18,T20

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T23
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T43,T44
1	0	Covered	T16,T43,T44

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T23,T13
1	0	Covered	T8,T9,T27

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T23,T13
1	0	Covered	T8,T9,T27

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T27

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T27

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T23,T51,T46
StCtrlProg	339	Covered	T1,T8,T9
StCtrlRead	337	Covered	T2,T18,T20
StDisable	335	Covered	T7,T8,T9
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T23,T51,T46
StCtrlProg->StIdle	359	Covered	T1,T8,T9
StCtrlRead->StIdle	349	Covered	T2,T18,T20
StIdle->StCtrl	341	Covered	T23,T51,T46
StIdle->StCtrlProg	339	Covered	T1,T8,T9
StIdle->StCtrlRead	337	Covered	T2,T18,T20
StIdle->StDisable	335	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	1	50.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

317          assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T23
0	Covered	T1,T2,T3

392          assign muxed_addr = host_sel ? host_addr_i : addr_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T23
0	Covered	T1,T2,T3

393          assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T23
0	Covered	T1,T2,T3

394          assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T23
0	Covered	T1,T2,T3

395          assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T23
0	Covered	T1,T2,T3

552          assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T27
0	Covered	T1,T2,T3

553          assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T27
0	Covered	T1,T2,T3

431          flash_phy_rd u_rd (
                                
432            .clk_i,
                      
433            .rst_ni,
                       
434            .buf_en_i(rd_buf_en_i),
                                      
435            //.req_i(reqs[PhyRead] | host_req),
                                                  
436            .req_i(phy_req & (rd_i | host_req)),
                                                   
437            .descramble_i(muxed_scramble_en),
                                                
438            .ecc_i(muxed_ecc_en),
                                    
439            .prog_i(reqs[PhyProg]),
                                      
440            .pg_erase_i(reqs[PhyPgErase]),
                                             
441            .bk_erase_i(reqs[PhyBkErase]),
                                             
442            .addr_i(muxed_addr),
                                   
443            .part_i(muxed_part),
                                   
444            // info select cannot be generated by the host
                                                             
445            .info_sel_i(info_sel_i),
                                       
446            .rdy_o(rd_stage_rdy),
                                    
447            .data_valid_o(rd_stage_data_valid),
                                                  
448            .data_err_o(phy_rd_err),
                                       
449            .data_host_o(rd_data_host_o),
                                            
450            .data_ctrl_o(rd_data_ctrl_o),
                                            
451            .idle_o(rd_stage_idle),
                                      
452             // a catastrophic arbitration error has been observed, just dump
                                                                                
453             // dump returns until all transactions are flushed.
                                                                   
454            .arb_err_i(arb_host_gnt_err),
                                            
455            .req_o(flash_rd_req),
                                    
456            .ack_i(ack),
                           
457            .done_i(done),
                             
458            .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

152            if (!rst_ni) begin
               -1-  
153              arb_cnt <= '0;
                 ==>
154            end else if (ctrl_rsp_vld) begin
                        -2-  
155              arb_cnt <= '0;
                 ==>
156            end else if (inc_arb_cnt) begin
                        -3-  
157              arb_cnt <= arb_cnt + 1'b1;
                 ==>
158            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T18
0	0	1	Covered	T15,T10,T39
0	0	0	Covered	T1,T2,T3

165          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

203            if (!rst_ni) begin
               -1-  
204              host_gnt_err_o <= '0;
                 ==>
205            end else if (host_gnt_err_event | host_outstanding_err_event) begin
                        -2-  
206              host_gnt_err_o <= 1'b1;
                 ==>
207            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10
0	0	Covered	T1,T2,T3

215            if (!rst_ni) begin
               -1-  
216              host_gnt_rd_err <= '0;
                 ==>
217            end else if (host_outstanding == '0) begin
                        -2-  
218              host_gnt_rd_err <= '0;
                 ==>
219            end else if (host_gnt_err_event) begin
                        -3-  
220              host_gnt_rd_err <= 1'b1;
                 ==>
221            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10
0	0	0	Covered	T2,T20,T23

229            if (!rst_ni) begin
               -1-  
230              host_outstanding_rd_err <= '0;
                 ==>
231            end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
                        -2-  
232              host_outstanding_rd_err <= '0;
                 ==>
233            end else if (host_outstanding_err_event) begin
                        -3-  
234              host_outstanding_rd_err <= 1'b1;
                 ==>
235            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10
0	0	0	Covered	T1,T2,T18

331            unique case (state_q)
                      -1-  
332              StIdle: begin
333                ctrl_fsm_idle = 1'b1;
334                if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
                   -2-  
335                  state_d = StDisable;
                     ==>
336                end else if (ctrl_gnt && rd_i) begin
                            -3-  
337                  state_d = StCtrlRead;
                     ==>
338                end else if (ctrl_gnt && prog_i) begin
                            -4-  
339                  state_d = StCtrlProg;
                     ==>
340                end else if (ctrl_gnt) begin
                            -5-  
341                  state_d = StCtrl;
                     ==>
342                end
                   MISSING_ELSE
                   ==>
343              end
344        
345              // Controller reads are very slow.
346              StCtrlRead: begin
347                if (rd_stage_data_valid) begin
                   -6-  
348                  ctrl_rsp_vld = 1'b1;
                     ==>
349                  state_d = StIdle;
350                end
                   MISSING_ELSE
                   ==>
351              end
352        
353              // Controller program data may be packed based on
354              // address alignment
355              StCtrlProg: begin
356                reqs[PhyProg] = 1'b1;
357                if (prog_ack) begin
                   -7-  
358                  ctrl_rsp_vld = 1'b1;
                     ==>
359                  state_d = StIdle;
360                end
                   MISSING_ELSE
                   ==>
361              end
362        
363              // other controller operations directly interface with flash
364              StCtrl: begin
365                reqs[PhyPgErase] = pg_erase_i;
366                reqs[PhyBkErase] = bk_erase_i;
367                if (erase_ack) begin
                   -8-  
368                  ctrl_rsp_vld = 1'b1;
                     ==>
369                  state_d = StIdle;
370                end
                   MISSING_ELSE
                   ==>
371              end
372        
373              StDisable: begin
374                ctrl_fsm_idle = 1'b1;
                   ==>
375                state_d = StDisable;
376              end
377        
378              default: begin
379                ctrl_fsm_idle = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	Covered	T2,T18,T20
StIdle	0	0	1	-	-	-	-	Covered	T1,T8,T9
StIdle	0	0	0	1	-	-	-	Covered	T23,T51,T10
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T2,T18,T20
StCtrlRead	-	-	-	-	0	-	-	Covered	T2,T18,T20
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T8,T9
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T8,T9
StCtrl	-	-	-	-	-	-	1	Covered	T23,T51,T10
StCtrl	-	-	-	-	-	-	0	Covered	T23,T51,T10
StDisable	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Covered	T10,T16,T43

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	388255766	1448076	0	0
CtrlPrio_A	388255766	1448076	0	0
HostTransIdleChk_A	388255766	21987616	0	0
NoRemainder_A	1057	1057	0	0
OneHotReqs_A	388255766	387415641	0	0
Pow2Multiple_A	1057	1057	0	0
RdTxnCheck_A	388093290	387253165	0	0
u_state_regs_A	388255766	387415641	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1448076	0	0
T10	519	0	0	0
T15	29510	5	0	0
T27	225589	0	0	0
T39	0	234	0	0
T41	0	1269	0	0
T47	0	1181	0	0
T48	0	1193	0	0
T51	162291	0	0	0
T54	5236	0	0	0
T55	0	1405	0	0
T58	1526	0	0	0
T59	3485	0	0	0
T64	2168	0	0	0
T66	0	5	0	0
T98	59772	0	0	0
T99	0	7213	0	0
T110	1127	0	0	0
T130	0	1326	0	0
T217	0	1390	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1448076	0	0
T10	519	0	0	0
T15	29510	5	0	0
T27	225589	0	0	0
T39	0	234	0	0
T41	0	1269	0	0
T47	0	1181	0	0
T48	0	1193	0	0
T51	162291	0	0	0
T54	5236	0	0	0
T55	0	1405	0	0
T58	1526	0	0	0
T59	3485	0	0	0
T64	2168	0	0	0
T66	0	5	0	0
T98	59772	0	0	0
T99	0	7213	0	0
T110	1127	0	0	0
T130	0	1326	0	0
T217	0	1390	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	21987616	0	0
T2	10848	216	0	0
T3	1224	0	0	0
T4	890	0	0	0
T7	972	0	0	0
T10	0	12	0	0
T12	2002	0	0	0
T13	0	20	0	0
T15	0	154	0	0
T17	1544	0	0	0
T18	1950	0	0	0
T19	2303	0	0	0
T20	1473	8	0	0
T23	7299	34	0	0
T39	0	510	0	0
T54	0	350	0	0
T58	0	10	0	0
T59	0	151	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388093290	387253165	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	152	6	6	100.00
ALWAYS	165	3	3	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	203	4	4	100.00
ALWAYS	215	6	6	100.00
ALWAYS	229	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	325	29	29	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	568	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	587	1	1	100.00

151                       always_ff @(posedge clk_i or negedge rst_ni) begin
152        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
153        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T3 
154        1/1              end else if (ctrl_rsp_vld) begin
           Tests:       T1 T2 T3 
155        1/1                arb_cnt <= '0;
           Tests:       T1 T2 T3 
156        1/1              end else if (inc_arb_cnt) begin
           Tests:       T1 T2 T3 
157        1/1                arb_cnt <= arb_cnt + 1'b1;
           Tests:       T15 T10 T58 
158                         end
                        MISSING_ELSE
159                       end
160                     
161                       import prim_mubi_pkg::mubi4_test_false_strict;
162                       import prim_mubi_pkg::mubi4_test_true_loose;
163                     
164                       // SEC_CM: PHY.FSM.SPARSE
165        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
165.1                   `ifdef SIMULATION                                   
165.2                       prim_sparse_fsm_flop #(                           
165.3                         .StateEnumT(state_e),                            
165.4                         .Width($bits(state_e)),                          
165.5                         .ResetValue($bits(state_e)'(StIdle)),          
165.6                         .EnableAlertTriggerSVA(1), 
165.7                         .CustomForceName("state_q")          
165.8                       ) u_state_regs (                                        
165.9                         .clk_i   ( clk_i   ),                           
165.10                        .rst_ni  ( rst_ni ),                           
165.11                        .state_i ( state_d     ),                           
165.12                        .state_o (         )                            
165.13                      );                                                
165.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
165.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
165.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
165.17                      end else begin                                    
165.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
165.19                      end                                               
165.20                    end  
165.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
165.22                      else begin                                                                           
165.23                        `ifdef UVM                                                                               
165.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
165.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv", 165, "", 1);                                
165.26                  `else                                                                                    
165.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
165.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
165.29                  `endif                                                              
165.30                      end 
165.31                    `else                                               
165.32                      prim_sparse_fsm_flop #(                           
165.33                        .StateEnumT(state_e),                            
165.34                        .Width($bits(state_e)),                          
165.35                        .ResetValue($bits(state_e)'(StIdle)),          
165.36                        .EnableAlertTriggerSVA(1)  
165.37                      ) u_state_regs (                                        
165.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
165.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
165.40                        .state_i ( state_d     ),                           
165.41                        .state_o ( state_q     )                            
165.42                      );                                                
165.43                    `endif166                     
167                       typedef enum logic [2:0] {
168                         HostDisableIdx,
169                         CtrlDisableIdx,
170                         FsmDisableIdx,
171                         ProgFsmDisableIdx,
172                         LastDisableIdx
173                       } phy_core_disable_e;
174                     
175                       prim_mubi_pkg::mubi4_t [LastDisableIdx-1:0] flash_disable;
176                       prim_mubi4_sync #(
177                         .NumCopies(int'(LastDisableIdx)),
178                         .AsyncOn(0)
179                       ) u_disable_buf (
180                         .clk_i,
181                         .rst_ni,
182                         .mubi_i(flash_disable_i),
183                         .mubi_o(flash_disable)
184                       );
185                     
186                       // Oustanding width is slightly larger to ensure a faulty increment is able to reach
187                       // the higher value. For example if RspOrderDepth were 3, a clog2 of 3 would still be 2
188                       // and not allow the counter to increment to 4.
189                       localparam int OutstandingRdWidth = $clog2(RspOrderDepth+2);
190                       logic [OutstandingRdWidth-1:0] host_outstanding;
191                       logic ctrl_fsm_idle;
192                       logic host_req;
193                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
194                       // A host transaction was granted to the muxed partition, this is illegal
195                       logic host_gnt_err_event;
196        1/1            assign host_gnt_err_event = (host_gnt && muxed_part != flash_ctrl_pkg::FlashPartData);
           Tests:       T1 T2 T3 
197                       // Controller fsm became non idle when there are pending host transactions, this is
198                       // illegal.
199                       logic host_outstanding_err_event;
200        1/1            assign host_outstanding_err_event = |host_outstanding & !ctrl_fsm_idle;
           Tests:       T1 T2 T3 
201                     
202                       always_ff @(posedge clk_i or negedge rst_ni) begin
203        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
204        1/1                host_gnt_err_o <= '0;
           Tests:       T1 T2 T3 
205        1/1              end else if (host_gnt_err_event | host_outstanding_err_event) begin
           Tests:       T1 T2 T3 
206        1/1                host_gnt_err_o <= 1'b1;
           Tests:       T10 T180 T228 
207                         end
                        MISSING_ELSE
208                       end
209                     
210                       // When host grant errors occur, also create in band error responses.
211                       // The error condition is held until all existing host transactions are
212                       // processed.
213                       logic host_gnt_rd_err;
214                       always_ff @(posedge clk_i or negedge rst_ni) begin
215        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
216        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
217        1/1              end else if (host_outstanding == '0) begin
           Tests:       T1 T2 T3 
218        1/1                host_gnt_rd_err <= '0;
           Tests:       T1 T2 T3 
219        1/1              end else if (host_gnt_err_event) begin
           Tests:       T2 T3 T20 
220        1/1                host_gnt_rd_err <= 1'b1;
           Tests:       T10 T228 T11 
221                         end
                        MISSING_ELSE
222                       end
223                     
224                       // When host outstanding errors occur, also create in band error responses.
225                       // The error condition is held until all existing host and controller
226                       // transactions are processed.
227                       logic host_outstanding_rd_err;
228                       always_ff @(posedge clk_i or negedge rst_ni) begin
229        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
230        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
231        1/1              end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
           Tests:       T1 T2 T3 
232        1/1                host_outstanding_rd_err <= '0;
           Tests:       T1 T2 T3 
233        1/1              end else if (host_outstanding_err_event) begin
           Tests:       T1 T2 T3 
234        1/1                host_outstanding_rd_err <= 1'b1;
           Tests:       T10 T11 
235                         end
                        MISSING_ELSE
236                       end
237                     
238                       // SEC_CM: PHY_HOST_GRANT.CTRL.CONSISTENCY
239                       prim_count #(
240                         .Width(OutstandingRdWidth),
241                         .ResetValue('0)
242                       ) u_host_outstanding_cnt (
243                         .clk_i,
244                         .rst_ni,
245                         .clr_i('0),
246                         .set_i('0),
247                         .set_cnt_i('0),
248                         .incr_en_i(host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)),
249                         .decr_en_i(!host_gnt && host_req_done_o && |host_outstanding),
250                         .step_i(OutstandingRdWidth'(1'b1)),
251                         .commit_i(1'b1),
252                         .cnt_o(host_outstanding),
253                         .cnt_after_commit_o(),
254                         .err_o(cnt_err_o)
255                       );
256                     
257                       // If host_outstanding is non-zero, the controller fsm must be idle..
258                       // This assertion needs to be disabled for sec_cm testing
259                       `ASSERT(HostTransIdleChk_A, |host_outstanding |-> ctrl_fsm_idle)
260                     
261                       //always_ff @(posedge clk_i or negedge rst_ni) begin
262                       //  if (!rst_ni) begin
263                       //    host_outstanding <= '0;
264                       //  end else if (host_gnt && !host_req_done_o && (host_outstanding <= RspOrderDepth)) begin
265                       //    host_outstanding <= host_outstanding + 1'b1;
266                       //  end else if (!host_gnt && host_req_done_o && |host_outstanding) begin
267                       //    host_outstanding <= host_outstanding - 1'b1;
268                       //  end
269                       //end
270                     
271                       `ASSERT(RdTxnCheck_A, host_outstanding <= RspOrderDepth)
272                     
273                       // The host request is suppressed under a variety of conditions:
274                       // 1. If a controller transaction is already ongoing.
275                       // 2. If a grant or outstanding error has already been observed but not yet
276                       //    fully processed.
277        1/1            assign host_req = host_req_i & (arb_cnt < ArbCnt[CntWidth-1:0]) & ctrl_fsm_idle &
           Tests:       T1 T2 T3 
278                                         !host_gnt_rd_err & !host_outstanding_rd_err &
279                                         mubi4_test_false_strict(flash_disable[HostDisableIdx]);
280        1/1            assign host_sel = host_req;
           Tests:       T1 T2 T3 
281        1/1            assign host_gnt = host_req & host_req_rdy_o;
           Tests:       T1 T2 T3 
282        1/1            assign host_req_done_o = |host_outstanding & rd_stage_data_valid;
           Tests:       T1 T2 T3 
283                     
284                       // controller request can only win after the entire read pipeline
285                       // clears
286                       logic ctrl_req;
287        1/1            assign ctrl_req = req_i & rd_stage_idle &
           Tests:       T1 T2 T3 
288                                         !host_gnt_rd_err & !host_outstanding_rd_err &
289                                         mubi4_test_false_strict(flash_disable[CtrlDisableIdx]);
290                     
291                       logic [1:0] data_tie_off [2];
292                       assign data_tie_off = '{default: '0};
293                     
294                       // SEC_CM: PHY_ARBITER.CTRL.REDUN
295                       logic phy_req;
296                       logic phy_rdy;
297                     
298                       prim_arbiter_tree_dup #(
299                         .N(2),
300                         .DW(2),
301                         .EnDataPort('0),
302                         .FixedArb(1)
303                       ) u_host_arb (
304                         .clk_i,
305                         .rst_ni,
306                         .req_chk_i('0),
307                         .req_i({ctrl_req, host_req}),
308                         .data_i(data_tie_off),
309                         .gnt_o({ctrl_gnt, host_req_rdy_o}),
310                         .idx_o(),
311                         .valid_o(phy_req),
312                         .data_o(),
313                         .ready_i(phy_rdy),
314                         .err_o(arb_err_o)
315                       );
316                     
317        1/1            assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
           Tests:       T1 T2 T3 
318                     
319                     
320                       // if request happens at the same time as a host grant, increment count
321        1/1            assign inc_arb_cnt = req_i & host_gnt;
           Tests:       T1 T2 T3 
322                     
323                       logic fsm_err;
324                       always_comb begin
325        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
326        1/1              reqs = '0;
           Tests:       T1 T2 T3 
327        1/1              ctrl_rsp_vld = '0;
           Tests:       T1 T2 T3 
328        1/1              fsm_err = '0;
           Tests:       T1 T2 T3 
329        1/1              ctrl_fsm_idle = '0;
           Tests:       T1 T2 T3 
330                     
331        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
332                           StIdle: begin
333        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T1 T2 T3 
334        1/1                  if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
           Tests:       T1 T2 T3 
335        1/1                    state_d = StDisable;
           Tests:       T7 T8 T9 
336        1/1                  end else if (ctrl_gnt && rd_i) begin
           Tests:       T1 T2 T3 
337        1/1                    state_d = StCtrlRead;
           Tests:       T1 T2 T3 
338        1/1                  end else if (ctrl_gnt && prog_i) begin
           Tests:       T1 T2 T3 
339        1/1                    state_d = StCtrlProg;
           Tests:       T12 T20 T13 
340        1/1                  end else if (ctrl_gnt) begin
           Tests:       T1 T2 T3 
341        1/1                    state_d = StCtrl;
           Tests:       T12 T23 T14 
342                             end
                        MISSING_ELSE
343                           end
344                     
345                           // Controller reads are very slow.
346                           StCtrlRead: begin
347        1/1                  if (rd_stage_data_valid) begin
           Tests:       T1 T2 T3 
348        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T1 T2 T3 
349        1/1                    state_d = StIdle;
           Tests:       T1 T2 T3 
350                             end
                        MISSING_ELSE
351                           end
352                     
353                           // Controller program data may be packed based on
354                           // address alignment
355                           StCtrlProg: begin
356        1/1                  reqs[PhyProg] = 1'b1;
           Tests:       T12 T20 T13 
357        1/1                  if (prog_ack) begin
           Tests:       T12 T20 T13 
358        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T12 T20 T13 
359        1/1                    state_d = StIdle;
           Tests:       T12 T20 T13 
360                             end
                        MISSING_ELSE
361                           end
362                     
363                           // other controller operations directly interface with flash
364                           StCtrl: begin
365        1/1                  reqs[PhyPgErase] = pg_erase_i;
           Tests:       T12 T23 T14 
366        1/1                  reqs[PhyBkErase] = bk_erase_i;
           Tests:       T12 T23 T14 
367        1/1                  if (erase_ack) begin
           Tests:       T12 T23 T14 
368        1/1                    ctrl_rsp_vld = 1'b1;
           Tests:       T12 T23 T14 
369        1/1                    state_d = StIdle;
           Tests:       T12 T23 T14 
370                             end
                        MISSING_ELSE
371                           end
372                     
373                           StDisable: begin
374        1/1                  ctrl_fsm_idle = 1'b1;
           Tests:       T7 T8 T9 
375        1/1                  state_d = StDisable;
           Tests:       T7 T8 T9 
376                           end
377                     
378                           default: begin
379                             ctrl_fsm_idle = 1'b1;
380                             fsm_err = 1'b1;
381                           end
382                     
383                         endcase // unique case (state_q)
384                       end // always_comb
385                     
386                       // determine spurious acks
387                       // SEC_CM: PHY_ACK.CTRL.CONSISTENCY
388        1/1            assign spurious_ack_o = (ctrl_fsm_idle & ctrl_rsp_vld) |
           Tests:       T1 T2 T3 
389                                               ((host_outstanding == '0) & host_req_done_o);
390                     
391                       // transactions coming from flash controller are always data type
392        1/1            assign muxed_addr = host_sel ? host_addr_i : addr_i;
           Tests:       T1 T2 T3 
393        1/1            assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
           Tests:       T1 T2 T3 
394        1/1            assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
           Tests:       T1 T2 T3 
395        1/1            assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
           Tests:       T1 T2 T3 
396        1/1            assign rd_done_o = ctrl_rsp_vld & rd_i;
           Tests:       T1 T2 T3 
397        1/1            assign prog_done_o = ctrl_rsp_vld & prog_i;
           Tests:       T1 T2 T3 
398        1/1            assign erase_done_o = ctrl_rsp_vld & (pg_erase_i | bk_erase_i);
           Tests:       T1 T2 T3 
399                     
400                       ////////////////////////
401                       // read pipeline
402                       ////////////////////////
403                     
404                       logic flash_rd_req;
405                       logic [FullDataWidth-1:0] flash_rdata;
406                       logic rd_calc_req;
407                       logic [BankAddrW-1:0] rd_calc_addr;
408                       logic rd_op_req;
409                       logic [DataWidth-1:0] rd_scrambled_data;
410                       logic [DataWidth-1:0] rd_descrambled_data;
411                     
412                       // if host grant is encountered, transactions return in-band
413                       // error until all transactions are flushed.
414                       logic phy_rd_err;
415        1/1            assign rd_err_o = phy_rd_err;
           Tests:       T1 T2 T3 
416                     
417                     
418                       // After host_gnt_rd_err asserts, no more host requests
419                       // are granted until all transactions are flushed. This means
420                       // the last outstanding transaction is by definition the "error".
421                       //
422                       // If ctrl_fsm_idle inexplicably goes low while there are host transactions
423                       // the transaction handling may be irreversibly broken.
424                       // The host_oustanding_rd_err makes a best effort attempt to cleanly
425                       // recover.  It responds with in-band error controller transactions until the
426                       // all pending transactions are flushed.
427                       logic arb_host_gnt_err;
428        1/1            assign arb_host_gnt_err = (host_gnt_rd_err & host_outstanding == 1'b1) |
           Tests:       T1 T2 T3 
429                                                 (host_outstanding_rd_err);
430                     
431                       flash_phy_rd u_rd (
432                         .clk_i,
433                         .rst_ni,
434                         .buf_en_i(rd_buf_en_i),
435                         //.req_i(reqs[PhyRead] | host_req),
436                         .req_i(phy_req & (rd_i | host_req)),
437                         .descramble_i(muxed_scramble_en),
438                         .ecc_i(muxed_ecc_en),
439                         .prog_i(reqs[PhyProg]),
440                         .pg_erase_i(reqs[PhyPgErase]),
441                         .bk_erase_i(reqs[PhyBkErase]),
442                         .addr_i(muxed_addr),
443                         .part_i(muxed_part),
444                         // info select cannot be generated by the host
445                         .info_sel_i(info_sel_i),
446                         .rdy_o(rd_stage_rdy),
447                         .data_valid_o(rd_stage_data_valid),
448                         .data_err_o(phy_rd_err),
449                         .data_host_o(rd_data_host_o),
450                         .data_ctrl_o(rd_data_ctrl_o),
451                         .idle_o(rd_stage_idle),
452                          // a catastrophic arbitration error has been observed, just dump
453                          // dump returns until all transactions are flushed.
454                         .arb_err_i(arb_host_gnt_err),
455                         .req_o(flash_rd_req),
456                         .ack_i(ack),
457                         .done_i(done),
458                         .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
459                         //scramble unit interface
460                         .calc_req_o(rd_calc_req),
461                         .calc_addr_o(rd_calc_addr),
462                         .descramble_req_o(rd_op_req),
463                         .scrambled_data_o(rd_scrambled_data),
464                         .calc_ack_i(calc_ack),
465                         .descramble_ack_i(op_ack),
466                         .mask_i(scramble_mask),
467                         .descrambled_data_i(rd_descrambled_data),
468                         .ecc_single_err_o,
469                         .ecc_addr_o,
470                         .relbl_ecc_err_o,
471                         .intg_ecc_err_o,
472                         .fifo_err_o
473                         );
474                     
475                       ////////////////////////
476                       // program pipeline
477                       ////////////////////////
478                     
479                       logic [FullDataWidth-1:0] prog_full_data;
480                       logic [DataWidth-1:0] prog_scrambled_data;
481                       logic [DataWidth-1:0] prog_data;
482                       logic prog_last;
483                       logic flash_prog_req;
484                       logic prog_calc_req;
485                       logic prog_op_req;
486                       logic prog_fsm_err;
487                     
488                       if (WidthMultiple == 1) begin : gen_single_prog_data
489                         assign flash_prog_req = reqs[PhyProg];
490                         assign prog_data = prog_data_i[BusWidth-1:0];
491                         assign prog_fsm_err = '0;
492                       end else begin : gen_prog_data
493                     
494                         // SEC_CM: MEM.INTEGRITY
495                         flash_phy_prog u_prog (
496                           .clk_i,
497                           .rst_ni,
498                           .req_i(reqs[PhyProg]),
499                           .disable_i(flash_disable[ProgFsmDisableIdx]),
500                           .scramble_i(muxed_scramble_en),
501                           .ecc_i(muxed_ecc_en),
502                           .sel_i(addr_i[0 +: WordSelW]),
503                           .data_i(prog_data_i),
504                           .last_i(prog_last_i),
505                           .ack_i(ack),
506                           .done_i(done),
507                           .calc_ack_i(calc_ack),
508                           .scramble_ack_i(op_ack),
509                           .mask_i(scramble_mask),
510                           .scrambled_data_i(prog_scrambled_data),
511                           .calc_req_o(prog_calc_req),
512                           .scramble_req_o(prog_op_req),
513                           .req_o(flash_prog_req),
514                           .last_o(prog_last),
515                           .ack_o(prog_ack),
516                           .block_data_o(prog_data),
517                           .data_o(prog_full_data),
518                           .fsm_err_o(prog_fsm_err),
519                           .intg_err_o(prog_intg_err_o)
520                         );
521                       end
522                     
523        1/1            assign fsm_err_o = fsm_err | prog_fsm_err;
           Tests:       T1 T2 T3 
524                     
525                       ////////////////////////
526                       // erase pipeline
527                       ////////////////////////
528                     
529                       logic flash_pg_erase_req;
530                       logic flash_bk_erase_req;
531                       logic erase_suspend_req;
532                       flash_phy_erase u_erase (
533                         .clk_i,
534                         .rst_ni,
535                         .pg_erase_req_i(reqs[PhyPgErase]),
536                         .bk_erase_req_i(reqs[PhyBkErase]),
537                         .suspend_req_i(erase_suspend_req_i),
538                         .ack_o(erase_ack),
539                         .pg_erase_req_o(flash_pg_erase_req),
540                         .bk_erase_req_o(flash_bk_erase_req),
541                         .suspend_req_o(erase_suspend_req),
542                         .ack_i(ack),
543                         .done_i(done)
544                       );
545                     
546                       ////////////////////////
547                       // bundle data to send to shared scrambling module
548                       ////////////////////////
549                     
550        1/1            assign scramble_req_o.calc_req       = prog_calc_req | rd_calc_req;
           Tests:       T1 T2 T3 
551        1/1            assign scramble_req_o.op_req         = prog_op_req | rd_op_req;
           Tests:       T1 T2 T3 
552        1/1            assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
           Tests:       T1 T2 T3 
553        1/1            assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
           Tests:       T1 T2 T3 
554                                                                              rd_calc_addr;
555        1/1            assign scramble_req_o.plain_data     = prog_data;
           Tests:       T1 T2 T3 
556        1/1            assign scramble_req_o.scrambled_data = rd_scrambled_data;
           Tests:       T1 T2 T3 
557        1/1            assign calc_ack            = scramble_rsp_i.calc_ack;
           Tests:       T1 T2 T3 
558        1/1            assign op_ack              = scramble_rsp_i.op_ack;
           Tests:       T1 T2 T3 
559        1/1            assign scramble_mask       = scramble_rsp_i.mask;
           Tests:       T1 T2 T3 
560        1/1            assign rd_descrambled_data = scramble_rsp_i.plain_data;
           Tests:       T1 T2 T3 
561        1/1            assign prog_scrambled_data = scramble_rsp_i.scrambled_data;
           Tests:       T1 T2 T3 
562                     
563                       ////////////////////////
564                       // Actual connection to flash phy
565                       ////////////////////////
566                     
567                       // Connections to the actual flash macro wrapper
568        1/1            assign prim_flash_req_o = '{
           Tests:       T1 T2 T3 
569                         rd_req: flash_rd_req,
570                         prog_req: flash_prog_req,
571                         prog_last: prog_last,
572                         prog_type: prog_type_i,
573                         pg_erase_req: flash_pg_erase_req,
574                         bk_erase_req: flash_bk_erase_req,
575                         erase_suspend_req: erase_suspend_req,
576                         // high endurance enable does not cause changes to
577                         // transaction protocol and is forwarded directly to the wrapper
578                         he: he_en_i,
579                         addr: muxed_addr[BusBankAddrW-1:LsbAddrBit],
580                         part: muxed_part,
581                         info_sel: info_sel_i,
582                         prog_full_data: prog_full_data
583                       };
584                     
585        1/1            assign ack = prim_flash_rsp_i.ack;
           Tests:       T1 T2 T3 
586        1/1            assign done = prim_flash_rsp_i.done;
           Tests:       T1 T2 T3 
587        1/1            assign flash_rdata = prim_flash_rsp_i.rdata;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	100	94.34
Logical	106	100	94.34
Non-Logical	0	0
Event	0	0

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Covered	T10,T180,T228

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T180,T228

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T20

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T15
1	0	1	Covered	T2,T3,T20
1	1	0	Covered	T58,T62,T63
1	1	1	Covered	T2,T3,T20

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T20,T23,T13
1	1	Covered	T2,T3,T20

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T20
1	1	Covered	T2,T3,T20

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T10,T58

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T20
1	0	Covered	T12,T20,T23
1	1	Covered	T1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T12,T23,T14
1	1	Covered	T12,T20,T13

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T58,T62,T63
1	0	Covered	T239

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T239

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T58,T62,T63

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T13

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T23,T14

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T74,T25,T65
1	0	Covered	T12,T23,T14

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T228

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T228
1	1	Covered	T228

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T20

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T228

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T43,T44
1	0	Covered	T16,T43,T44

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T8

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T8

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	341	Covered	T12,T23,T14
StCtrlProg	339	Covered	T12,T20,T13
StCtrlRead	337	Covered	T1,T2,T3
StDisable	335	Covered	T7,T8,T9
StIdle	349	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	369	Covered	T12,T23,T14
StCtrlProg->StIdle	359	Covered	T12,T20,T13
StCtrlRead->StIdle	349	Covered	T1,T2,T3
StIdle->StCtrl	341	Covered	T12,T23,T14
StIdle->StCtrlProg	339	Covered	T12,T20,T13
StIdle->StCtrlRead	337	Covered	T1,T2,T3
StIdle->StDisable	335	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	317	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	431	2	2	100.00
IF	152	4	4	100.00
IF	165	2	2	100.00
IF	203	3	3	100.00
IF	215	4	4	100.00
IF	229	4	4	100.00
CASE	331	13	13	100.00

317          assign phy_rdy = phy_req & host_req ? rd_stage_rdy : rd_stage_idle;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

392          assign muxed_addr = host_sel ? host_addr_i : addr_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

393          assign muxed_part = host_sel ? flash_ctrl_pkg::FlashPartData : part_i;
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

394          assign muxed_scramble_en = host_sel ? host_scramble_en_i : scramble_en_i;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

395          assign muxed_ecc_en = host_sel ? host_ecc_en_i : ecc_en_i;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3

552          assign scramble_req_o.op_type        = prog_op_req ? ScrambleOp : DeScrambleOp;
                                                                -1-  
                                                                ==>  
                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T8
0	Covered	T1,T2,T3

553          assign scramble_req_o.addr           = prog_calc_req ? muxed_addr[BusBankAddrW-1:LsbAddrBit] :
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T8
0	Covered	T1,T2,T3

431          flash_phy_rd u_rd (
                                
432            .clk_i,
                      
433            .rst_ni,
                       
434            .buf_en_i(rd_buf_en_i),
                                      
435            //.req_i(reqs[PhyRead] | host_req),
                                                  
436            .req_i(phy_req & (rd_i | host_req)),
                                                   
437            .descramble_i(muxed_scramble_en),
                                                
438            .ecc_i(muxed_ecc_en),
                                    
439            .prog_i(reqs[PhyProg]),
                                      
440            .pg_erase_i(reqs[PhyPgErase]),
                                             
441            .bk_erase_i(reqs[PhyBkErase]),
                                             
442            .addr_i(muxed_addr),
                                   
443            .part_i(muxed_part),
                                   
444            // info select cannot be generated by the host
                                                             
445            .info_sel_i(info_sel_i),
                                       
446            .rdy_o(rd_stage_rdy),
                                    
447            .data_valid_o(rd_stage_data_valid),
                                                  
448            .data_err_o(phy_rd_err),
                                       
449            .data_host_o(rd_data_host_o),
                                            
450            .data_ctrl_o(rd_data_ctrl_o),
                                            
451            .idle_o(rd_stage_idle),
                                      
452             // a catastrophic arbitration error has been observed, just dump
                                                                                
453             // dump returns until all transactions are flushed.
                                                                   
454            .arb_err_i(arb_host_gnt_err),
                                            
455            .req_o(flash_rd_req),
                                    
456            .ack_i(ack),
                           
457            .done_i(done),
                             
458            .data_i(arb_host_gnt_err ? {FullDataWidth{1'b1}} : flash_rdata),
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T228
0	Covered	T1,T2,T3

152            if (!rst_ni) begin
               -1-  
153              arb_cnt <= '0;
                 ==>
154            end else if (ctrl_rsp_vld) begin
                        -2-  
155              arb_cnt <= '0;
                 ==>
156            end else if (inc_arb_cnt) begin
                        -3-  
157              arb_cnt <= arb_cnt + 1'b1;
                 ==>
158            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T15,T10,T58
0	0	0	Covered	T1,T2,T3

165          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

203            if (!rst_ni) begin
               -1-  
204              host_gnt_err_o <= '0;
                 ==>
205            end else if (host_gnt_err_event | host_outstanding_err_event) begin
                        -2-  
206              host_gnt_err_o <= 1'b1;
                 ==>
207            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T180,T228
0	0	Covered	T1,T2,T3

215            if (!rst_ni) begin
               -1-  
216              host_gnt_rd_err <= '0;
                 ==>
217            end else if (host_outstanding == '0) begin
                        -2-  
218              host_gnt_rd_err <= '0;
                 ==>
219            end else if (host_gnt_err_event) begin
                        -3-  
220              host_gnt_rd_err <= 1'b1;
                 ==>
221            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T228,T11
0	0	0	Covered	T2,T3,T20

229            if (!rst_ni) begin
               -1-  
230              host_outstanding_rd_err <= '0;
                 ==>
231            end else if (host_outstanding == '0 && ctrl_fsm_idle) begin
                        -2-  
232              host_outstanding_rd_err <= '0;
                 ==>
233            end else if (host_outstanding_err_event) begin
                        -3-  
234              host_outstanding_rd_err <= 1'b1;
                 ==>
235            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T10,T11
0	0	0	Covered	T1,T2,T3

331            unique case (state_q)
                      -1-  
332              StIdle: begin
333                ctrl_fsm_idle = 1'b1;
334                if (mubi4_test_true_loose(flash_disable[FsmDisableIdx])) begin
                   -2-  
335                  state_d = StDisable;
                     ==>
336                end else if (ctrl_gnt && rd_i) begin
                            -3-  
337                  state_d = StCtrlRead;
                     ==>
338                end else if (ctrl_gnt && prog_i) begin
                            -4-  
339                  state_d = StCtrlProg;
                     ==>
340                end else if (ctrl_gnt) begin
                            -5-  
341                  state_d = StCtrl;
                     ==>
342                end
                   MISSING_ELSE
                   ==>
343              end
344        
345              // Controller reads are very slow.
346              StCtrlRead: begin
347                if (rd_stage_data_valid) begin
                   -6-  
348                  ctrl_rsp_vld = 1'b1;
                     ==>
349                  state_d = StIdle;
350                end
                   MISSING_ELSE
                   ==>
351              end
352        
353              // Controller program data may be packed based on
354              // address alignment
355              StCtrlProg: begin
356                reqs[PhyProg] = 1'b1;
357                if (prog_ack) begin
                   -7-  
358                  ctrl_rsp_vld = 1'b1;
                     ==>
359                  state_d = StIdle;
360                end
                   MISSING_ELSE
                   ==>
361              end
362        
363              // other controller operations directly interface with flash
364              StCtrl: begin
365                reqs[PhyPgErase] = pg_erase_i;
366                reqs[PhyBkErase] = bk_erase_i;
367                if (erase_ack) begin
                   -8-  
368                  ctrl_rsp_vld = 1'b1;
                     ==>
369                  state_d = StIdle;
370                end
                   MISSING_ELSE
                   ==>
371              end
372        
373              StDisable: begin
374                ctrl_fsm_idle = 1'b1;
                   ==>
375                state_d = StDisable;
376              end
377        
378              default: begin
379                ctrl_fsm_idle = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T12,T20,T13
StIdle	0	0	0	1	-	-	-	Covered	T12,T23,T14
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T12,T20,T13
StCtrlProg	-	-	-	-	-	0	-	Covered	T12,T20,T13
StCtrl	-	-	-	-	-	-	1	Covered	T12,T23,T14
StCtrl	-	-	-	-	-	-	0	Covered	T12,T23,T14
StDisable	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	Covered	T10,T11,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	388255766	1645866	0	0
CtrlPrio_A	388255766	1645866	0	0
HostTransIdleChk_A	388255766	21934063	0	0
NoRemainder_A	1057	1057	0	0
OneHotReqs_A	388255766	387415641	0	0
Pow2Multiple_A	1057	1057	0	0
RdTxnCheck_A	388093290	387253165	0	0
u_state_regs_A	388255766	387415641	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1645866	0	0
T10	519	5	0	0
T15	29510	69	0	0
T27	225589	0	0	0
T36	0	4770	0	0
T41	0	3261	0	0
T47	0	1215	0	0
T48	0	2114	0	0
T51	162291	0	0	0
T54	5236	0	0	0
T55	0	1061	0	0
T58	1526	0	0	0
T59	3485	0	0	0
T64	2168	0	0	0
T98	59772	0	0	0
T99	0	3232	0	0
T110	1127	0	0	0
T130	0	3090	0	0
T217	0	1459	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1645866	0	0
T10	519	5	0	0
T15	29510	69	0	0
T27	225589	0	0	0
T36	0	4770	0	0
T41	0	3261	0	0
T47	0	1215	0	0
T48	0	2114	0	0
T51	162291	0	0	0
T54	5236	0	0	0
T55	0	1061	0	0
T58	1526	0	0	0
T59	3485	0	0	0
T64	2168	0	0	0
T98	59772	0	0	0
T99	0	3232	0	0
T110	1127	0	0	0
T130	0	3090	0	0
T217	0	1459	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	21934063	0	0
T2	10848	192	0	0
T3	1224	15	0	0
T4	890	0	0	0
T7	972	0	0	0
T10	0	20	0	0
T12	2002	0	0	0
T13	0	20	0	0
T15	0	531	0	0
T17	1544	0	0	0
T18	1950	0	0	0
T19	2303	0	0	0
T20	1473	16	0	0
T23	7299	42	0	0
T39	0	81	0	0
T54	0	531	0	0
T58	0	10	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388093290	387253165	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0