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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.68 93.90 98.31 92.52 98.21 96.89 98.12


Total test records in report: 1272
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T496 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.959731597 Aug 29 10:02:53 AM UTC 24 Aug 29 10:04:30 AM UTC 24 21294800 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1596807341 Aug 29 09:57:29 AM UTC 24 Aug 29 10:04:45 AM UTC 24 1401076200 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2547753626 Aug 29 10:03:19 AM UTC 24 Aug 29 10:04:45 AM UTC 24 3359556900 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1850684010 Aug 29 10:01:08 AM UTC 24 Aug 29 10:04:50 AM UTC 24 3184621000 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3350301008 Aug 29 10:01:14 AM UTC 24 Aug 29 10:05:00 AM UTC 24 23451056300 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2878845254 Aug 29 10:00:34 AM UTC 24 Aug 29 10:05:10 AM UTC 24 3742689600 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3035669082 Aug 29 10:00:37 AM UTC 24 Aug 29 10:05:16 AM UTC 24 3210999200 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.247120938 Aug 29 10:03:05 AM UTC 24 Aug 29 10:05:37 AM UTC 24 2889122400 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.373827168 Aug 29 09:54:53 AM UTC 24 Aug 29 10:05:45 AM UTC 24 25390636300 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3916786570 Aug 29 10:03:31 AM UTC 24 Aug 29 10:05:47 AM UTC 24 1090703100 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.325528670 Aug 29 09:50:52 AM UTC 24 Aug 29 10:05:48 AM UTC 24 41794359100 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3115719077 Aug 29 10:03:38 AM UTC 24 Aug 29 10:05:58 AM UTC 24 621287900 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.3326772639 Aug 29 10:03:49 AM UTC 24 Aug 29 10:06:00 AM UTC 24 1750839900 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.4016254371 Aug 29 10:01:11 AM UTC 24 Aug 29 10:06:09 AM UTC 24 33820332800 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1254730681 Aug 29 10:03:09 AM UTC 24 Aug 29 10:06:13 AM UTC 24 43021600 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2381909170 Aug 29 10:05:17 AM UTC 24 Aug 29 10:06:15 AM UTC 24 70426600 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1214243666 Aug 29 10:05:50 AM UTC 24 Aug 29 10:06:21 AM UTC 24 47497200 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.2587602784 Aug 29 10:02:05 AM UTC 24 Aug 29 10:06:22 AM UTC 24 185425700 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1788201414 Aug 29 10:05:59 AM UTC 24 Aug 29 10:06:24 AM UTC 24 88690200 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.330960710 Aug 29 10:02:51 AM UTC 24 Aug 29 10:06:24 AM UTC 24 10019428800 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.3172674486 Aug 29 10:05:47 AM UTC 24 Aug 29 10:06:27 AM UTC 24 78789300 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.810249052 Aug 29 10:06:01 AM UTC 24 Aug 29 10:06:29 AM UTC 24 48433400 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.1284389254 Aug 29 10:02:56 AM UTC 24 Aug 29 10:06:34 AM UTC 24 33497700 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.4006844671 Aug 29 10:06:10 AM UTC 24 Aug 29 10:06:35 AM UTC 24 18152300 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.2258117439 Aug 29 10:04:46 AM UTC 24 Aug 29 10:06:45 AM UTC 24 5785607400 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.3470852358 Aug 29 10:05:38 AM UTC 24 Aug 29 10:06:46 AM UTC 24 121851600 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.12935849 Aug 29 10:04:06 AM UTC 24 Aug 29 10:06:49 AM UTC 24 2431729100 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2728657226 Aug 29 09:41:42 AM UTC 24 Aug 29 10:06:50 AM UTC 24 1364114100 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.630717682 Aug 29 10:03:30 AM UTC 24 Aug 29 10:06:52 AM UTC 24 1828265700 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2101875867 Aug 29 10:06:30 AM UTC 24 Aug 29 10:06:54 AM UTC 24 1923548900 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1086806603 Aug 29 09:51:38 AM UTC 24 Aug 29 10:07:00 AM UTC 24 40122201400 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3493345715 Aug 29 10:06:03 AM UTC 24 Aug 29 10:07:03 AM UTC 24 10144691500 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.156792479 Aug 29 09:59:31 AM UTC 24 Aug 29 10:07:12 AM UTC 24 6049435100 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.4253278172 Aug 29 10:05:48 AM UTC 24 Aug 29 10:07:21 AM UTC 24 3652992000 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.353767136 Aug 29 10:06:46 AM UTC 24 Aug 29 10:07:52 AM UTC 24 2169561400 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.3657183361 Aug 29 09:57:48 AM UTC 24 Aug 29 10:07:54 AM UTC 24 4174663200 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2130456381 Aug 29 10:00:44 AM UTC 24 Aug 29 10:08:12 AM UTC 24 7721842100 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.4022252946 Aug 29 10:07:55 AM UTC 24 Aug 29 10:08:20 AM UTC 24 18202400 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.403255554 Aug 29 10:05:01 AM UTC 24 Aug 29 10:08:32 AM UTC 24 4418142700 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.331066114 Aug 29 10:04:07 AM UTC 24 Aug 29 10:08:35 AM UTC 24 1751825600 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3722272047 Aug 29 10:06:50 AM UTC 24 Aug 29 10:08:42 AM UTC 24 628256200 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.2388812371 Aug 29 10:04:31 AM UTC 24 Aug 29 10:08:42 AM UTC 24 1903629600 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.417755494 Aug 29 10:07:22 AM UTC 24 Aug 29 10:08:48 AM UTC 24 7728219100 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3257101403 Aug 29 10:08:00 AM UTC 24 Aug 29 10:08:58 AM UTC 24 69978300 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1687472719 Aug 29 10:06:47 AM UTC 24 Aug 29 10:08:58 AM UTC 24 7976393100 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.3655199340 Aug 29 10:06:53 AM UTC 24 Aug 29 10:09:02 AM UTC 24 4532513200 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2538468483 Aug 29 10:08:44 AM UTC 24 Aug 29 10:09:08 AM UTC 24 44541500 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2477117300 Aug 29 10:06:14 AM UTC 24 Aug 29 10:09:10 AM UTC 24 49300500 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.4148401728 Aug 29 10:08:43 AM UTC 24 Aug 29 10:09:15 AM UTC 24 22390300 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.3110896465 Aug 29 10:08:33 AM UTC 24 Aug 29 10:09:15 AM UTC 24 52667600 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1048572913 Aug 29 10:08:13 AM UTC 24 Aug 29 10:09:16 AM UTC 24 26242900 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1704293642 Aug 29 10:08:49 AM UTC 24 Aug 29 10:09:19 AM UTC 24 48478000 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3346568967 Aug 29 10:08:21 AM UTC 24 Aug 29 10:09:21 AM UTC 24 150412600 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.2069060247 Aug 29 10:08:59 AM UTC 24 Aug 29 10:09:28 AM UTC 24 58756300 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.3565238773 Aug 29 10:06:23 AM UTC 24 Aug 29 10:09:36 AM UTC 24 1899578300 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3585049399 Aug 29 10:09:22 AM UTC 24 Aug 29 10:10:01 AM UTC 24 273677200 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3304284825 Aug 29 10:06:29 AM UTC 24 Aug 29 10:10:02 AM UTC 24 27525131600 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2490428600 Aug 29 10:06:26 AM UTC 24 Aug 29 10:10:03 AM UTC 24 74722000 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1221826391 Aug 29 10:06:55 AM UTC 24 Aug 29 10:10:03 AM UTC 24 7587350400 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2294254781 Aug 29 10:07:01 AM UTC 24 Aug 29 10:10:07 AM UTC 24 689440700 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1792693506 Aug 29 10:04:47 AM UTC 24 Aug 29 10:10:19 AM UTC 24 60779451100 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.600814139 Aug 29 10:07:13 AM UTC 24 Aug 29 10:10:34 AM UTC 24 10383105300 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.2503353208 Aug 29 10:08:35 AM UTC 24 Aug 29 10:10:45 AM UTC 24 10631579700 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2430092800 Aug 29 10:08:59 AM UTC 24 Aug 29 10:10:50 AM UTC 24 10019612900 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2154239401 Aug 29 10:07:53 AM UTC 24 Aug 29 10:10:51 AM UTC 24 63833964400 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.4148994399 Aug 29 10:10:02 AM UTC 24 Aug 29 10:11:23 AM UTC 24 2084343300 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2884882386 Aug 29 09:40:41 AM UTC 24 Aug 29 10:11:27 AM UTC 24 207453900 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2132236815 Aug 29 10:04:51 AM UTC 24 Aug 29 10:11:30 AM UTC 24 111840387100 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2284709174 Aug 29 09:45:19 AM UTC 24 Aug 29 10:11:54 AM UTC 24 1158497600 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.2440470729 Aug 29 10:11:31 AM UTC 24 Aug 29 10:11:55 AM UTC 24 108833500 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1554325348 Aug 29 10:07:04 AM UTC 24 Aug 29 10:11:59 AM UTC 24 1984180200 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2645106650 Aug 29 10:10:51 AM UTC 24 Aug 29 10:12:16 AM UTC 24 6440080900 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1235871577 Aug 29 10:10:03 AM UTC 24 Aug 29 10:12:22 AM UTC 24 517156400 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2552221941 Aug 29 10:11:55 AM UTC 24 Aug 29 10:12:40 AM UTC 24 166321300 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3573817722 Aug 29 09:52:31 AM UTC 24 Aug 29 10:12:47 AM UTC 24 349070000 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.509777860 Aug 29 10:12:00 AM UTC 24 Aug 29 10:12:50 AM UTC 24 91085600 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2165264312 Aug 29 10:10:35 AM UTC 24 Aug 29 10:12:50 AM UTC 24 3568304200 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4073410506 Aug 29 10:06:16 AM UTC 24 Aug 29 10:12:51 AM UTC 24 167438900 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.3030909599 Aug 29 10:10:03 AM UTC 24 Aug 29 10:12:54 AM UTC 24 2499465000 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3722675877 Aug 29 10:12:16 AM UTC 24 Aug 29 10:12:55 AM UTC 24 37261800 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2484750425 Aug 29 10:11:56 AM UTC 24 Aug 29 10:12:56 AM UTC 24 59125300 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.3827449251 Aug 29 10:10:09 AM UTC 24 Aug 29 10:13:03 AM UTC 24 5374893900 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2412428598 Aug 29 10:12:47 AM UTC 24 Aug 29 10:13:07 AM UTC 24 15730600 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2133851167 Aug 29 10:12:41 AM UTC 24 Aug 29 10:13:08 AM UTC 24 24459700 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2021101261 Aug 29 10:12:51 AM UTC 24 Aug 29 10:13:11 AM UTC 24 15521500 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1970487338 Aug 29 10:02:55 AM UTC 24 Aug 29 10:13:13 AM UTC 24 130964000 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1012060452 Aug 29 10:09:03 AM UTC 24 Aug 29 10:13:17 AM UTC 24 40486100 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1852285165 Aug 29 10:12:52 AM UTC 24 Aug 29 10:13:19 AM UTC 24 22667100 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3349857931 Aug 29 10:09:17 AM UTC 24 Aug 29 10:13:27 AM UTC 24 40382200 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2019471493 Aug 29 10:03:38 AM UTC 24 Aug 29 10:13:32 AM UTC 24 51533037900 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1998859227 Aug 29 09:40:13 AM UTC 24 Aug 29 10:13:44 AM UTC 24 167506555800 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3607399919 Aug 29 10:13:13 AM UTC 24 Aug 29 10:13:52 AM UTC 24 413323500 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.153587378 Aug 29 10:10:21 AM UTC 24 Aug 29 10:13:57 AM UTC 24 4186671700 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2705919513 Aug 29 10:10:50 AM UTC 24 Aug 29 10:13:57 AM UTC 24 612242500 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2281646254 Aug 29 10:16:46 AM UTC 24 Aug 29 10:20:08 AM UTC 24 68545100 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.500905584 Aug 29 09:57:59 AM UTC 24 Aug 29 10:14:00 AM UTC 24 160173872400 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.1056661391 Aug 29 10:10:46 AM UTC 24 Aug 29 10:14:07 AM UTC 24 3682681200 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.594995787 Aug 29 10:11:24 AM UTC 24 Aug 29 10:14:08 AM UTC 24 23233579000 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3671282385 Aug 29 10:12:22 AM UTC 24 Aug 29 10:14:10 AM UTC 24 1883059500 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3405407122 Aug 29 10:09:16 AM UTC 24 Aug 29 10:14:20 AM UTC 24 29052387600 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3031196949 Aug 29 10:12:51 AM UTC 24 Aug 29 10:15:04 AM UTC 24 10011932200 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3686475101 Aug 29 10:13:28 AM UTC 24 Aug 29 10:15:23 AM UTC 24 8085152300 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3368701902 Aug 29 10:14:11 AM UTC 24 Aug 29 10:15:44 AM UTC 24 4073007800 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3020868855 Aug 29 10:12:56 AM UTC 24 Aug 29 10:15:50 AM UTC 24 84422000 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3529995153 Aug 29 10:15:24 AM UTC 24 Aug 29 10:15:54 AM UTC 24 64647600 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2695173560 Aug 29 09:46:39 AM UTC 24 Aug 29 10:15:59 AM UTC 24 170379062200 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2242617977 Aug 29 10:13:12 AM UTC 24 Aug 29 10:16:02 AM UTC 24 4588266800 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.2113723009 Aug 29 10:13:45 AM UTC 24 Aug 29 10:16:04 AM UTC 24 952151800 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.2661267991 Aug 29 10:09:11 AM UTC 24 Aug 29 10:16:06 AM UTC 24 45478300 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.94600621 Aug 29 10:16:04 AM UTC 24 Aug 29 10:16:21 AM UTC 24 14228400 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.2735893610 Aug 29 10:13:08 AM UTC 24 Aug 29 10:16:25 AM UTC 24 47641000 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3638010306 Aug 29 10:06:22 AM UTC 24 Aug 29 10:16:30 AM UTC 24 63717500 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.353497151 Aug 29 10:16:00 AM UTC 24 Aug 29 10:16:36 AM UTC 24 40340100 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2052179253 Aug 29 10:16:07 AM UTC 24 Aug 29 10:16:37 AM UTC 24 40821600 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.2565079307 Aug 29 10:15:44 AM UTC 24 Aug 29 10:16:38 AM UTC 24 70735700 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3312744962 Aug 29 10:15:51 AM UTC 24 Aug 29 10:16:42 AM UTC 24 31453200 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3622851714 Aug 29 10:07:22 AM UTC 24 Aug 29 10:16:43 AM UTC 24 24118248300 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1507646104 Aug 29 10:16:22 AM UTC 24 Aug 29 10:16:46 AM UTC 24 98698800 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.900175061 Aug 29 10:15:55 AM UTC 24 Aug 29 10:16:54 AM UTC 24 141672500 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3594904229 Aug 29 10:13:58 AM UTC 24 Aug 29 10:16:56 AM UTC 24 4038340400 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1486942879 Aug 29 10:12:57 AM UTC 24 Aug 29 10:16:58 AM UTC 24 893032300 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.418462973 Aug 29 10:16:31 AM UTC 24 Aug 29 10:16:58 AM UTC 24 496881000 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.272629683 Aug 29 10:13:58 AM UTC 24 Aug 29 10:16:58 AM UTC 24 1616706900 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1328495206 Aug 29 10:13:03 AM UTC 24 Aug 29 10:17:01 AM UTC 24 2560849100 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.1719068861 Aug 29 10:16:03 AM UTC 24 Aug 29 10:17:12 AM UTC 24 668428800 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2369222341 Aug 29 10:14:01 AM UTC 24 Aug 29 10:17:13 AM UTC 24 2800862300 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1213465164 Aug 29 10:13:33 AM UTC 24 Aug 29 10:17:19 AM UTC 24 4731284600 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3661190994 Aug 29 10:11:29 AM UTC 24 Aug 29 10:17:22 AM UTC 24 30182404400 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.273715222 Aug 29 09:58:47 AM UTC 24 Aug 29 10:17:26 AM UTC 24 1070949200 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2612931883 Aug 29 09:42:05 AM UTC 24 Aug 29 10:17:26 AM UTC 24 147890393600 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.443094938 Aug 29 10:14:08 AM UTC 24 Aug 29 10:17:39 AM UTC 24 3671031900 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2179741210 Aug 29 10:16:56 AM UTC 24 Aug 29 10:17:39 AM UTC 24 1578719100 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1165340634 Aug 29 10:09:19 AM UTC 24 Aug 29 10:17:45 AM UTC 24 58672786900 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.1779789482 Aug 29 10:06:51 AM UTC 24 Aug 29 10:17:46 AM UTC 24 36332030200 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2222443408 Aug 29 10:16:26 AM UTC 24 Aug 29 10:17:47 AM UTC 24 10054263900 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3887621311 Aug 29 10:16:43 AM UTC 24 Aug 29 10:17:48 AM UTC 24 4057905300 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2077129106 Aug 29 10:12:55 AM UTC 24 Aug 29 10:17:50 AM UTC 24 218314900 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.2172788172 Aug 29 10:14:07 AM UTC 24 Aug 29 10:17:57 AM UTC 24 8397896200 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2892477934 Aug 29 10:16:37 AM UTC 24 Aug 29 10:18:08 AM UTC 24 22620400 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1354453010 Aug 29 10:10:04 AM UTC 24 Aug 29 10:18:27 AM UTC 24 3737189300 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3374455795 Aug 29 10:17:00 AM UTC 24 Aug 29 10:18:40 AM UTC 24 3911199100 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2855061380 Aug 29 10:17:52 AM UTC 24 Aug 29 10:18:43 AM UTC 24 72594300 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1599393965 Aug 29 10:17:50 AM UTC 24 Aug 29 10:18:43 AM UTC 24 30221200 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.3393780222 Aug 29 10:17:41 AM UTC 24 Aug 29 10:18:52 AM UTC 24 3115142800 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3115066975 Aug 29 10:17:58 AM UTC 24 Aug 29 10:18:54 AM UTC 24 111657100 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.1327875090 Aug 29 10:18:09 AM UTC 24 Aug 29 10:18:55 AM UTC 24 15445800 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2710779301 Aug 29 10:03:10 AM UTC 24 Aug 29 10:18:57 AM UTC 24 25433231400 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3887863891 Aug 29 10:18:40 AM UTC 24 Aug 29 10:19:05 AM UTC 24 39853700 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1747226027 Aug 29 10:18:43 AM UTC 24 Aug 29 10:19:08 AM UTC 24 82792100 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.4263132670 Aug 29 10:18:44 AM UTC 24 Aug 29 10:19:09 AM UTC 24 15950700 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.738701348 Aug 29 10:03:06 AM UTC 24 Aug 29 10:19:16 AM UTC 24 160173070500 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1067264834 Aug 29 10:18:55 AM UTC 24 Aug 29 10:19:21 AM UTC 24 50040900 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2473510860 Aug 29 10:17:13 AM UTC 24 Aug 29 10:19:29 AM UTC 24 482530700 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2576480551 Aug 29 10:15:05 AM UTC 24 Aug 29 10:19:40 AM UTC 24 24092186600 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.424978123 Aug 29 10:06:24 AM UTC 24 Aug 29 10:20:04 AM UTC 24 40124977600 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3252577059 Aug 29 10:17:20 AM UTC 24 Aug 29 10:20:10 AM UTC 24 777741400 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2371322290 Aug 29 10:16:54 AM UTC 24 Aug 29 10:20:10 AM UTC 24 5128109700 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2782115432 Aug 29 10:18:28 AM UTC 24 Aug 29 10:20:21 AM UTC 24 2079433000 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2409175913 Aug 29 10:17:27 AM UTC 24 Aug 29 10:20:25 AM UTC 24 1528220600 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3589971063 Aug 29 10:17:47 AM UTC 24 Aug 29 10:20:31 AM UTC 24 35363471500 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.434210610 Aug 29 10:17:39 AM UTC 24 Aug 29 10:20:31 AM UTC 24 789074700 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2405325907 Aug 29 10:17:23 AM UTC 24 Aug 29 10:20:34 AM UTC 24 4579767300 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2057140688 Aug 29 10:14:21 AM UTC 24 Aug 29 10:20:37 AM UTC 24 26379747900 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.924031579 Aug 29 10:18:57 AM UTC 24 Aug 29 10:20:44 AM UTC 24 14986800 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.764767059 Aug 29 10:20:22 AM UTC 24 Aug 29 10:20:47 AM UTC 24 19282100 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1032157578 Aug 29 10:19:30 AM UTC 24 Aug 29 10:20:50 AM UTC 24 3430139800 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.4240973231 Aug 29 10:13:52 AM UTC 24 Aug 29 10:20:53 AM UTC 24 7599478600 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3038504923 Aug 29 10:18:52 AM UTC 24 Aug 29 10:20:55 AM UTC 24 10018817300 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.677227506 Aug 29 10:17:27 AM UTC 24 Aug 29 10:20:59 AM UTC 24 1347307900 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3321416172 Aug 29 10:17:02 AM UTC 24 Aug 29 10:21:02 AM UTC 24 5001925900 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2700298571 Aug 29 10:20:45 AM UTC 24 Aug 29 10:21:07 AM UTC 24 23421600 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3903214546 Aug 29 10:20:49 AM UTC 24 Aug 29 10:21:11 AM UTC 24 26212800 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.883196223 Aug 29 10:20:36 AM UTC 24 Aug 29 10:21:12 AM UTC 24 24528700 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.49403413 Aug 29 10:20:55 AM UTC 24 Aug 29 10:21:15 AM UTC 24 171331000 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2342518616 Aug 29 10:20:51 AM UTC 24 Aug 29 10:21:16 AM UTC 24 47138700 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2855669112 Aug 29 10:20:26 AM UTC 24 Aug 29 10:21:25 AM UTC 24 26701600 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.1274074266 Aug 29 10:20:32 AM UTC 24 Aug 29 10:21:30 AM UTC 24 377195000 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2872170104 Aug 29 10:20:32 AM UTC 24 Aug 29 10:21:34 AM UTC 24 27138500 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.3265202650 Aug 29 10:20:05 AM UTC 24 Aug 29 10:21:46 AM UTC 24 441336600 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2054908241 Aug 29 10:20:39 AM UTC 24 Aug 29 10:21:52 AM UTC 24 320683200 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3879896461 Aug 29 10:17:47 AM UTC 24 Aug 29 10:21:54 AM UTC 24 9454746400 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.4249140216 Aug 29 10:16:39 AM UTC 24 Aug 29 10:21:57 AM UTC 24 1440432900 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2994978762 Aug 29 10:20:53 AM UTC 24 Aug 29 10:22:15 AM UTC 24 10032571400 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.378857315 Aug 29 10:21:54 AM UTC 24 Aug 29 10:22:20 AM UTC 24 71577200 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2971982302 Aug 29 10:19:17 AM UTC 24 Aug 29 10:22:21 AM UTC 24 171297800 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.885761674 Aug 29 10:09:09 AM UTC 24 Aug 29 10:22:24 AM UTC 24 1386291700 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.3077479275 Aug 29 10:19:41 AM UTC 24 Aug 29 10:22:36 AM UTC 24 9222955300 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2687062062 Aug 29 09:56:30 AM UTC 24 Aug 29 10:22:39 AM UTC 24 333350600 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1378911396 Aug 29 10:21:58 AM UTC 24 Aug 29 10:22:50 AM UTC 24 30462300 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1150264957 Aug 29 10:22:37 AM UTC 24 Aug 29 10:22:54 AM UTC 24 41626700 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.877978139 Aug 29 10:22:22 AM UTC 24 Aug 29 10:22:57 AM UTC 24 23717200 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.4082327974 Aug 29 10:22:16 AM UTC 24 Aug 29 10:23:00 AM UTC 24 42666000 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3974632738 Aug 29 10:19:09 AM UTC 24 Aug 29 10:23:00 AM UTC 24 3242496800 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.107199975 Aug 29 10:22:40 AM UTC 24 Aug 29 10:23:05 AM UTC 24 40257000 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1395718266 Aug 29 10:22:21 AM UTC 24 Aug 29 10:23:09 AM UTC 24 60948600 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3734177025 Aug 29 10:17:47 AM UTC 24 Aug 29 10:23:14 AM UTC 24 21235996200 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.1279523210 Aug 29 10:22:50 AM UTC 24 Aug 29 10:23:15 AM UTC 24 48079300 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1173595931 Aug 29 10:21:18 AM UTC 24 Aug 29 10:23:20 AM UTC 24 5136558700 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1861909819 Aug 29 10:22:57 AM UTC 24 Aug 29 10:23:23 AM UTC 24 129605400 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1406360484 Aug 29 10:22:25 AM UTC 24 Aug 29 10:23:40 AM UTC 24 1177466500 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.1594790368 Aug 29 10:21:17 AM UTC 24 Aug 29 10:23:56 AM UTC 24 155057800 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.441874944 Aug 29 10:21:31 AM UTC 24 Aug 29 10:23:57 AM UTC 24 2101672000 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3440579189 Aug 29 10:09:16 AM UTC 24 Aug 29 10:24:11 AM UTC 24 80136560600 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2512527037 Aug 29 10:22:54 AM UTC 24 Aug 29 10:24:14 AM UTC 24 10043810400 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.36695169 Aug 29 09:40:13 AM UTC 24 Aug 29 10:24:28 AM UTC 24 96891124400 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2791252472 Aug 29 10:03:17 AM UTC 24 Aug 29 10:24:32 AM UTC 24 1012024200 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3466609087 Aug 29 10:20:12 AM UTC 24 Aug 29 10:24:32 AM UTC 24 1606551900 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3247752508 Aug 29 10:21:52 AM UTC 24 Aug 29 10:24:38 AM UTC 24 9194128100 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.238990164 Aug 29 10:21:01 AM UTC 24 Aug 29 10:24:40 AM UTC 24 58510300 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.1274310630 Aug 29 10:23:10 AM UTC 24 Aug 29 10:24:40 AM UTC 24 2784453000 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1786798754 Aug 29 10:21:27 AM UTC 24 Aug 29 10:24:53 AM UTC 24 2114301700 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3127005380 Aug 29 10:21:46 AM UTC 24 Aug 29 10:24:58 AM UTC 24 1524939900 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.832102923 Aug 29 10:24:33 AM UTC 24 Aug 29 10:24:59 AM UTC 24 20947400 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2614870267 Aug 29 10:23:23 AM UTC 24 Aug 29 10:25:00 AM UTC 24 8764543900 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2508421503 Aug 29 09:42:34 AM UTC 24 Aug 29 10:25:02 AM UTC 24 2631914300 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.4150336761 Aug 29 10:24:34 AM UTC 24 Aug 29 10:25:16 AM UTC 24 39241900 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3701580461 Aug 29 10:24:40 AM UTC 24 Aug 29 10:25:19 AM UTC 24 36444700 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.2900960186 Aug 29 10:24:54 AM UTC 24 Aug 29 10:25:21 AM UTC 24 32617700 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.37698824 Aug 29 10:20:12 AM UTC 24 Aug 29 10:25:22 AM UTC 24 12745699500 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.3978604764 Aug 29 10:25:00 AM UTC 24 Aug 29 10:25:23 AM UTC 24 25719600 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.3933824899 Aug 29 10:25:03 AM UTC 24 Aug 29 10:25:28 AM UTC 24 22299800 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1510143626 Aug 29 10:25:00 AM UTC 24 Aug 29 10:25:28 AM UTC 24 49150200 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3136728395 Aug 29 10:09:29 AM UTC 24 Aug 29 10:25:30 AM UTC 24 693328900 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.3029671973 Aug 29 10:24:39 AM UTC 24 Aug 29 10:25:30 AM UTC 24 61428700 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.549966738 Aug 29 10:24:33 AM UTC 24 Aug 29 10:25:31 AM UTC 24 103504800 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.3782291534 Aug 29 10:23:57 AM UTC 24 Aug 29 10:25:35 AM UTC 24 937109600 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1806796193 Aug 29 10:21:13 AM UTC 24 Aug 29 10:25:36 AM UTC 24 3164458700 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3101848065 Aug 29 10:23:01 AM UTC 24 Aug 29 10:25:58 AM UTC 24 74570000 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.1626008576 Aug 29 10:24:41 AM UTC 24 Aug 29 10:26:10 AM UTC 24 1365273800 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2240205755 Aug 29 10:19:22 AM UTC 24 Aug 29 10:26:11 AM UTC 24 16115248100 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2259911225 Aug 29 10:13:07 AM UTC 24 Aug 29 10:26:12 AM UTC 24 160191007700 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2139833051 Aug 29 10:23:21 AM UTC 24 Aug 29 10:26:13 AM UTC 24 6888218600 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1893654829 Aug 29 10:21:03 AM UTC 24 Aug 29 10:26:13 AM UTC 24 64488400 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3448765485 Aug 29 10:19:06 AM UTC 24 Aug 29 10:26:19 AM UTC 24 227493700 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1168285441 Aug 29 10:23:16 AM UTC 24 Aug 29 10:26:32 AM UTC 24 35129900 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.3222597746 Aug 29 09:42:31 AM UTC 24 Aug 29 10:26:35 AM UTC 24 93151159600 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3863744650 Aug 29 10:25:01 AM UTC 24 Aug 29 10:26:39 AM UTC 24 10076372900 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2571857603 Aug 29 10:26:11 AM UTC 24 Aug 29 10:26:39 AM UTC 24 251186700 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2874607599 Aug 29 10:25:22 AM UTC 24 Aug 29 10:26:55 AM UTC 24 4448190700 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.530975042 Aug 29 10:26:15 AM UTC 24 Aug 29 10:26:56 AM UTC 24 113939100 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.321807183 Aug 29 10:26:33 AM UTC 24 Aug 29 10:26:59 AM UTC 24 29099700 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.4060870135 Aug 29 10:25:31 AM UTC 24 Aug 29 10:27:02 AM UTC 24 3208086800 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1404990072 Aug 29 10:17:14 AM UTC 24 Aug 29 10:27:05 AM UTC 24 8081340200 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3096893468 Aug 29 10:26:13 AM UTC 24 Aug 29 10:27:05 AM UTC 24 100165700 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1918739197 Aug 29 10:26:43 AM UTC 24 Aug 29 10:27:06 AM UTC 24 40205300 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3496301916 Aug 29 10:26:13 AM UTC 24 Aug 29 10:27:06 AM UTC 24 223570000 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.516519728 Aug 29 10:26:15 AM UTC 24 Aug 29 10:27:09 AM UTC 24 165589700 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3849255939 Aug 29 10:26:44 AM UTC 24 Aug 29 10:27:09 AM UTC 24 25625800 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.229285228 Aug 29 10:26:55 AM UTC 24 Aug 29 10:27:19 AM UTC 24 157938400 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.4074246754 Aug 29 10:23:41 AM UTC 24 Aug 29 10:27:25 AM UTC 24 9235010300 ps
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