| T91 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.209596096 |
|
|
Aug 29 10:47:38 AM UTC 24 |
Aug 29 10:52:53 AM UTC 24 |
49529796900 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.27335096 |
|
|
Aug 29 10:49:18 AM UTC 24 |
Aug 29 10:52:54 AM UTC 24 |
24002800 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.2687997935 |
|
|
Aug 29 10:49:10 AM UTC 24 |
Aug 29 10:52:56 AM UTC 24 |
126494300 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3686439331 |
|
|
Aug 29 10:50:24 AM UTC 24 |
Aug 29 10:53:03 AM UTC 24 |
147009200 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1521412736 |
|
|
Aug 29 10:50:49 AM UTC 24 |
Aug 29 10:53:04 AM UTC 24 |
144354000 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1145134112 |
|
|
Aug 29 10:50:07 AM UTC 24 |
Aug 29 10:53:18 AM UTC 24 |
37694900 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1772448449 |
|
|
Aug 29 10:49:50 AM UTC 24 |
Aug 29 10:53:20 AM UTC 24 |
133859700 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1845952243 |
|
|
Aug 29 10:50:50 AM UTC 24 |
Aug 29 10:53:35 AM UTC 24 |
36479100 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3883882315 |
|
|
Aug 29 10:50:10 AM UTC 24 |
Aug 29 10:53:36 AM UTC 24 |
127363500 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3771731432 |
|
|
Aug 29 10:50:55 AM UTC 24 |
Aug 29 10:53:37 AM UTC 24 |
77399800 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.1406251068 |
|
|
Aug 29 10:49:36 AM UTC 24 |
Aug 29 10:53:41 AM UTC 24 |
5907102500 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4000572163 |
|
|
Aug 29 10:48:11 AM UTC 24 |
Aug 29 10:53:46 AM UTC 24 |
23482993700 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1509133718 |
|
|
Aug 29 10:51:07 AM UTC 24 |
Aug 29 10:53:47 AM UTC 24 |
38509500 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1389508452 |
|
|
Aug 29 10:50:56 AM UTC 24 |
Aug 29 10:53:49 AM UTC 24 |
40141600 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1334903439 |
|
|
Aug 29 10:50:52 AM UTC 24 |
Aug 29 10:53:56 AM UTC 24 |
71965300 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.808270206 |
|
|
Aug 29 10:49:56 AM UTC 24 |
Aug 29 10:54:00 AM UTC 24 |
75056500 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3192289125 |
|
|
Aug 29 10:51:06 AM UTC 24 |
Aug 29 10:54:02 AM UTC 24 |
48267800 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.316455022 |
|
|
Aug 29 10:50:57 AM UTC 24 |
Aug 29 10:54:02 AM UTC 24 |
39356800 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2711914796 |
|
|
Aug 29 10:50:35 AM UTC 24 |
Aug 29 10:54:08 AM UTC 24 |
36201500 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3088149242 |
|
|
Aug 29 10:51:15 AM UTC 24 |
Aug 29 10:54:09 AM UTC 24 |
57836100 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1016513331 |
|
|
Aug 29 10:51:28 AM UTC 24 |
Aug 29 10:54:11 AM UTC 24 |
149030800 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1197938038 |
|
|
Aug 29 10:51:35 AM UTC 24 |
Aug 29 10:54:12 AM UTC 24 |
149208700 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2420702409 |
|
|
Aug 29 10:51:33 AM UTC 24 |
Aug 29 10:54:14 AM UTC 24 |
81367700 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2049802533 |
|
|
Aug 29 10:51:09 AM UTC 24 |
Aug 29 10:54:18 AM UTC 24 |
44459000 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.966048716 |
|
|
Aug 29 10:51:24 AM UTC 24 |
Aug 29 10:54:19 AM UTC 24 |
145440700 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.502964723 |
|
|
Aug 29 10:51:56 AM UTC 24 |
Aug 29 10:54:19 AM UTC 24 |
40396000 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1332195377 |
|
|
Aug 29 10:51:51 AM UTC 24 |
Aug 29 10:54:28 AM UTC 24 |
146782400 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3319871552 |
|
|
Aug 29 10:51:13 AM UTC 24 |
Aug 29 10:54:33 AM UTC 24 |
128778200 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2433416603 |
|
|
Aug 29 10:51:25 AM UTC 24 |
Aug 29 10:54:35 AM UTC 24 |
38644000 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3198079799 |
|
|
Aug 29 10:51:39 AM UTC 24 |
Aug 29 10:54:38 AM UTC 24 |
37361200 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.761650275 |
|
|
Aug 29 10:51:19 AM UTC 24 |
Aug 29 10:54:41 AM UTC 24 |
36498100 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1776011042 |
|
|
Aug 29 10:51:46 AM UTC 24 |
Aug 29 10:54:42 AM UTC 24 |
42556900 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3214683558 |
|
|
Aug 29 10:50:32 AM UTC 24 |
Aug 29 10:54:45 AM UTC 24 |
26065600 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.1179933155 |
|
|
Aug 29 09:58:15 AM UTC 24 |
Aug 29 10:54:45 AM UTC 24 |
3288109000 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1673656122 |
|
|
Aug 29 10:51:44 AM UTC 24 |
Aug 29 10:54:48 AM UTC 24 |
80526800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1236607269 |
|
|
Aug 29 10:51:53 AM UTC 24 |
Aug 29 10:54:49 AM UTC 24 |
145586500 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.557447581 |
|
|
Aug 29 10:03:19 AM UTC 24 |
Aug 29 10:54:50 AM UTC 24 |
1882418000 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.150807844 |
|
|
Aug 29 10:51:59 AM UTC 24 |
Aug 29 10:54:50 AM UTC 24 |
73433600 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.4126266032 |
|
|
Aug 29 10:51:48 AM UTC 24 |
Aug 29 10:54:51 AM UTC 24 |
76937100 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3353061909 |
|
|
Aug 29 10:52:09 AM UTC 24 |
Aug 29 10:54:51 AM UTC 24 |
202828200 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2243063297 |
|
|
Aug 29 10:52:04 AM UTC 24 |
Aug 29 10:54:54 AM UTC 24 |
81596100 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3020807572 |
|
|
Aug 29 10:50:19 AM UTC 24 |
Aug 29 10:54:57 AM UTC 24 |
113463100 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.4203949908 |
|
|
Aug 29 10:52:12 AM UTC 24 |
Aug 29 10:55:04 AM UTC 24 |
40791400 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2412772195 |
|
|
Aug 29 10:52:13 AM UTC 24 |
Aug 29 10:55:05 AM UTC 24 |
60273100 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3586224395 |
|
|
Aug 29 10:52:19 AM UTC 24 |
Aug 29 10:55:08 AM UTC 24 |
147429300 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.302320914 |
|
|
Aug 29 10:33:19 AM UTC 24 |
Aug 29 10:55:34 AM UTC 24 |
1613241300 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.746509780 |
|
|
Aug 29 10:36:59 AM UTC 24 |
Aug 29 10:56:36 AM UTC 24 |
1584553000 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3737723063 |
|
|
Aug 29 10:06:36 AM UTC 24 |
Aug 29 10:59:13 AM UTC 24 |
4958191200 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3413456138 |
|
|
Aug 29 10:09:37 AM UTC 24 |
Aug 29 10:59:23 AM UTC 24 |
18892738600 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1871175905 |
|
|
Aug 29 10:13:19 AM UTC 24 |
Aug 29 11:01:57 AM UTC 24 |
8551319500 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1595695356 |
|
|
Aug 29 10:16:59 AM UTC 24 |
Aug 29 11:07:24 AM UTC 24 |
4591378400 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.3698332197 |
|
|
Aug 29 09:58:15 AM UTC 24 |
Aug 29 11:07:53 AM UTC 24 |
108589004700 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3081449203 |
|
|
Aug 29 09:45:01 AM UTC 24 |
Aug 29 11:38:41 AM UTC 24 |
2175200400 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1324856420 |
|
|
Aug 29 09:40:38 AM UTC 24 |
Aug 29 11:39:48 AM UTC 24 |
5360615500 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.1492928732 |
|
|
Aug 29 09:49:51 AM UTC 24 |
Aug 29 11:44:09 AM UTC 24 |
1897133800 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3120992155 |
|
|
Aug 29 10:02:01 AM UTC 24 |
Aug 29 12:00:50 PM UTC 24 |
3816432300 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.41654886 |
|
|
Aug 29 09:55:56 AM UTC 24 |
Aug 29 12:04:29 PM UTC 24 |
1674608400 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3603460639 |
|
|
Aug 29 07:31:19 AM UTC 24 |
Aug 29 07:31:45 AM UTC 24 |
57619600 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2140216089 |
|
|
Aug 29 07:31:20 AM UTC 24 |
Aug 29 07:31:47 AM UTC 24 |
63730900 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1082131814 |
|
|
Aug 29 07:31:17 AM UTC 24 |
Aug 29 07:31:47 AM UTC 24 |
32609200 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2416353343 |
|
|
Aug 29 07:31:19 AM UTC 24 |
Aug 29 07:31:47 AM UTC 24 |
28415900 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4197751404 |
|
|
Aug 29 07:31:19 AM UTC 24 |
Aug 29 07:31:48 AM UTC 24 |
23233500 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3844706550 |
|
|
Aug 29 07:31:16 AM UTC 24 |
Aug 29 07:31:51 AM UTC 24 |
115045800 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1020165537 |
|
|
Aug 29 07:31:20 AM UTC 24 |
Aug 29 07:31:52 AM UTC 24 |
27466300 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.305506136 |
|
|
Aug 29 07:31:24 AM UTC 24 |
Aug 29 07:31:56 AM UTC 24 |
169516900 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.223188396 |
|
|
Aug 29 07:31:33 AM UTC 24 |
Aug 29 07:31:58 AM UTC 24 |
975147800 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.319927000 |
|
|
Aug 29 07:31:28 AM UTC 24 |
Aug 29 07:32:03 AM UTC 24 |
656292300 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3188954223 |
|
|
Aug 29 07:31:48 AM UTC 24 |
Aug 29 07:32:09 AM UTC 24 |
25539100 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2840226727 |
|
|
Aug 29 07:31:48 AM UTC 24 |
Aug 29 07:32:13 AM UTC 24 |
21583400 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2269043965 |
|
|
Aug 29 07:31:20 AM UTC 24 |
Aug 29 07:32:13 AM UTC 24 |
95314300 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3975281747 |
|
|
Aug 29 07:31:48 AM UTC 24 |
Aug 29 07:32:13 AM UTC 24 |
149380600 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1252878927 |
|
|
Aug 29 07:31:48 AM UTC 24 |
Aug 29 07:32:15 AM UTC 24 |
28283500 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2886309505 |
|
|
Aug 29 07:31:46 AM UTC 24 |
Aug 29 07:32:16 AM UTC 24 |
24208600 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3039423933 |
|
|
Aug 29 07:31:52 AM UTC 24 |
Aug 29 07:32:23 AM UTC 24 |
213701800 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.250455337 |
|
|
Aug 29 07:31:20 AM UTC 24 |
Aug 29 07:32:27 AM UTC 24 |
1315370000 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1223233630 |
|
|
Aug 29 07:32:00 AM UTC 24 |
Aug 29 07:32:32 AM UTC 24 |
103460000 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3106535968 |
|
|
Aug 29 07:32:14 AM UTC 24 |
Aug 29 07:32:36 AM UTC 24 |
21926200 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1855332928 |
|
|
Aug 29 07:32:13 AM UTC 24 |
Aug 29 07:32:37 AM UTC 24 |
22348300 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.131623759 |
|
|
Aug 29 07:32:04 AM UTC 24 |
Aug 29 07:32:38 AM UTC 24 |
179347800 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1786460623 |
|
|
Aug 29 07:32:14 AM UTC 24 |
Aug 29 07:32:39 AM UTC 24 |
51811300 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2674336320 |
|
|
Aug 29 07:32:07 AM UTC 24 |
Aug 29 07:32:39 AM UTC 24 |
65442000 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1106407903 |
|
|
Aug 29 07:32:14 AM UTC 24 |
Aug 29 07:32:42 AM UTC 24 |
53087600 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1398518249 |
|
|
Aug 29 07:32:15 AM UTC 24 |
Aug 29 07:32:44 AM UTC 24 |
62930500 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3464183792 |
|
|
Aug 29 07:32:16 AM UTC 24 |
Aug 29 07:32:45 AM UTC 24 |
90862700 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.494709394 |
|
|
Aug 29 07:31:49 AM UTC 24 |
Aug 29 07:32:52 AM UTC 24 |
97526200 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1914124038 |
|
|
Aug 29 07:32:35 AM UTC 24 |
Aug 29 07:33:05 AM UTC 24 |
110379600 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1688273592 |
|
|
Aug 29 07:32:37 AM UTC 24 |
Aug 29 07:33:07 AM UTC 24 |
23090200 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1837326634 |
|
|
Aug 29 07:32:39 AM UTC 24 |
Aug 29 07:33:08 AM UTC 24 |
15628400 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4089270956 |
|
|
Aug 29 07:32:33 AM UTC 24 |
Aug 29 07:33:08 AM UTC 24 |
214172500 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1904357161 |
|
|
Aug 29 07:32:40 AM UTC 24 |
Aug 29 07:33:08 AM UTC 24 |
28428000 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3511982723 |
|
|
Aug 29 07:31:21 AM UTC 24 |
Aug 29 07:33:09 AM UTC 24 |
2891030000 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3279127427 |
|
|
Aug 29 07:32:38 AM UTC 24 |
Aug 29 07:33:10 AM UTC 24 |
14812900 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2000005110 |
|
|
Aug 29 07:32:33 AM UTC 24 |
Aug 29 07:33:11 AM UTC 24 |
48936500 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3922910887 |
|
|
Aug 29 07:32:42 AM UTC 24 |
Aug 29 07:33:11 AM UTC 24 |
32545400 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3325093909 |
|
|
Aug 29 07:31:53 AM UTC 24 |
Aug 29 07:33:14 AM UTC 24 |
1587246000 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.888374929 |
|
|
Aug 29 07:32:15 AM UTC 24 |
Aug 29 07:33:14 AM UTC 24 |
416931200 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1448513888 |
|
|
Aug 29 07:32:46 AM UTC 24 |
Aug 29 07:33:16 AM UTC 24 |
62235100 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2882536575 |
|
|
Aug 29 07:33:09 AM UTC 24 |
Aug 29 07:33:29 AM UTC 24 |
29817100 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1288546288 |
|
|
Aug 29 07:32:55 AM UTC 24 |
Aug 29 07:33:30 AM UTC 24 |
151205400 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1892701946 |
|
|
Aug 29 07:33:08 AM UTC 24 |
Aug 29 07:33:32 AM UTC 24 |
36422600 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1960469407 |
|
|
Aug 29 07:32:54 AM UTC 24 |
Aug 29 07:33:32 AM UTC 24 |
1228910500 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.47123409 |
|
|
Aug 29 07:32:23 AM UTC 24 |
Aug 29 07:33:32 AM UTC 24 |
3946618300 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4219202006 |
|
|
Aug 29 07:32:57 AM UTC 24 |
Aug 29 07:33:34 AM UTC 24 |
145986400 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.877108562 |
|
|
Aug 29 07:33:07 AM UTC 24 |
Aug 29 07:33:35 AM UTC 24 |
33995800 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3321500382 |
|
|
Aug 29 07:33:00 AM UTC 24 |
Aug 29 07:33:35 AM UTC 24 |
123816000 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.217060922 |
|
|
Aug 29 07:33:09 AM UTC 24 |
Aug 29 07:33:35 AM UTC 24 |
109694100 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2139104981 |
|
|
Aug 29 07:33:10 AM UTC 24 |
Aug 29 07:33:36 AM UTC 24 |
158367900 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.856342582 |
|
|
Aug 29 07:32:44 AM UTC 24 |
Aug 29 07:33:39 AM UTC 24 |
54387500 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.893522399 |
|
|
Aug 29 07:33:11 AM UTC 24 |
Aug 29 07:33:40 AM UTC 24 |
136282900 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.813914845 |
|
|
Aug 29 07:33:15 AM UTC 24 |
Aug 29 07:33:40 AM UTC 24 |
88196900 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1625619075 |
|
|
Aug 29 07:31:57 AM UTC 24 |
Aug 29 07:33:43 AM UTC 24 |
13870973000 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4275078986 |
|
|
Aug 29 07:32:46 AM UTC 24 |
Aug 29 07:33:45 AM UTC 24 |
670340300 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4032688319 |
|
|
Aug 29 07:33:17 AM UTC 24 |
Aug 29 07:33:49 AM UTC 24 |
84728300 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3388826806 |
|
|
Aug 29 07:32:28 AM UTC 24 |
Aug 29 07:33:52 AM UTC 24 |
9043525000 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.70850629 |
|
|
Aug 29 07:33:35 AM UTC 24 |
Aug 29 07:33:54 AM UTC 24 |
20928800 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.545667557 |
|
|
Aug 29 07:33:19 AM UTC 24 |
Aug 29 07:33:54 AM UTC 24 |
118818000 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.823236064 |
|
|
Aug 29 07:33:33 AM UTC 24 |
Aug 29 07:33:56 AM UTC 24 |
111673800 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2661151052 |
|
|
Aug 29 07:33:31 AM UTC 24 |
Aug 29 07:33:56 AM UTC 24 |
39476800 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2521521112 |
|
|
Aug 29 07:33:30 AM UTC 24 |
Aug 29 07:33:56 AM UTC 24 |
39308200 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4071551049 |
|
|
Aug 29 07:33:34 AM UTC 24 |
Aug 29 07:33:58 AM UTC 24 |
106389800 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.178402517 |
|
|
Aug 29 07:33:10 AM UTC 24 |
Aug 29 07:34:00 AM UTC 24 |
305128300 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.3806952266 |
|
|
Aug 29 07:33:37 AM UTC 24 |
Aug 29 07:34:05 AM UTC 24 |
38740700 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1553973442 |
|
|
Aug 29 07:33:33 AM UTC 24 |
Aug 29 07:34:06 AM UTC 24 |
115859000 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2659421225 |
|
|
Aug 29 07:33:41 AM UTC 24 |
Aug 29 07:34:06 AM UTC 24 |
113381300 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4116552099 |
|
|
Aug 29 07:33:41 AM UTC 24 |
Aug 29 07:34:07 AM UTC 24 |
989112800 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4000880883 |
|
|
Aug 29 07:33:34 AM UTC 24 |
Aug 29 07:34:08 AM UTC 24 |
59253700 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3270102807 |
|
|
Aug 29 07:33:36 AM UTC 24 |
Aug 29 07:34:08 AM UTC 24 |
12222300 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.135782106 |
|
|
Aug 29 07:33:39 AM UTC 24 |
Aug 29 07:34:09 AM UTC 24 |
42341600 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2875065475 |
|
|
Aug 29 07:33:33 AM UTC 24 |
Aug 29 07:34:11 AM UTC 24 |
707206600 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2834834254 |
|
|
Aug 29 07:33:49 AM UTC 24 |
Aug 29 07:34:14 AM UTC 24 |
67681000 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1992195588 |
|
|
Aug 29 07:33:52 AM UTC 24 |
Aug 29 07:34:18 AM UTC 24 |
51983300 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1334714194 |
|
|
Aug 29 07:33:40 AM UTC 24 |
Aug 29 07:34:15 AM UTC 24 |
335567300 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3716297941 |
|
|
Aug 29 07:33:46 AM UTC 24 |
Aug 29 07:34:15 AM UTC 24 |
44580700 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.544506179 |
|
|
Aug 29 07:34:00 AM UTC 24 |
Aug 29 07:34:17 AM UTC 24 |
54437700 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2359280851 |
|
|
Aug 29 07:33:56 AM UTC 24 |
Aug 29 07:34:19 AM UTC 24 |
231075800 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3077235082 |
|
|
Aug 29 07:33:54 AM UTC 24 |
Aug 29 07:34:19 AM UTC 24 |
166354700 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3117730396 |
|
|
Aug 29 07:33:55 AM UTC 24 |
Aug 29 07:34:25 AM UTC 24 |
134624300 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1561267528 |
|
|
Aug 29 07:34:09 AM UTC 24 |
Aug 29 07:34:28 AM UTC 24 |
11512100 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3526582706 |
|
|
Aug 29 07:33:58 AM UTC 24 |
Aug 29 07:34:28 AM UTC 24 |
33439700 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.904127809 |
|
|
Aug 29 07:33:15 AM UTC 24 |
Aug 29 07:34:29 AM UTC 24 |
2574258800 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3999448823 |
|
|
Aug 29 07:34:01 AM UTC 24 |
Aug 29 07:34:29 AM UTC 24 |
13139800 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.3838430543 |
|
|
Aug 29 07:34:11 AM UTC 24 |
Aug 29 07:34:30 AM UTC 24 |
17569000 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.855835448 |
|
|
Aug 29 07:34:03 AM UTC 24 |
Aug 29 07:34:31 AM UTC 24 |
26822700 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1662062824 |
|
|
Aug 29 07:33:13 AM UTC 24 |
Aug 29 07:34:33 AM UTC 24 |
1382883500 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1135754208 |
|
|
Aug 29 07:34:07 AM UTC 24 |
Aug 29 07:34:37 AM UTC 24 |
369081900 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.524597405 |
|
|
Aug 29 07:34:16 AM UTC 24 |
Aug 29 07:34:37 AM UTC 24 |
139826200 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3684791197 |
|
|
Aug 29 07:34:06 AM UTC 24 |
Aug 29 07:34:38 AM UTC 24 |
137438000 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1671827069 |
|
|
Aug 29 07:34:15 AM UTC 24 |
Aug 29 07:34:40 AM UTC 24 |
52703200 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4293759283 |
|
|
Aug 29 07:34:10 AM UTC 24 |
Aug 29 07:34:40 AM UTC 24 |
27755400 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.894836505 |
|
|
Aug 29 07:34:16 AM UTC 24 |
Aug 29 07:34:42 AM UTC 24 |
789573900 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1312894572 |
|
|
Aug 29 07:34:20 AM UTC 24 |
Aug 29 07:34:48 AM UTC 24 |
19693400 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2520827968 |
|
|
Aug 29 07:34:08 AM UTC 24 |
Aug 29 07:34:48 AM UTC 24 |
66228200 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.515786405 |
|
|
Aug 29 07:34:18 AM UTC 24 |
Aug 29 07:34:48 AM UTC 24 |
415344800 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2375704132 |
|
|
Aug 29 07:34:23 AM UTC 24 |
Aug 29 07:34:49 AM UTC 24 |
25300500 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4063466482 |
|
|
Aug 29 07:34:20 AM UTC 24 |
Aug 29 07:34:50 AM UTC 24 |
14438500 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1822704583 |
|
|
Aug 29 07:34:31 AM UTC 24 |
Aug 29 07:34:54 AM UTC 24 |
13315600 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1883174750 |
|
|
Aug 29 07:34:07 AM UTC 24 |
Aug 29 07:34:54 AM UTC 24 |
722111700 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3641554348 |
|
|
Aug 29 07:34:30 AM UTC 24 |
Aug 29 07:34:55 AM UTC 24 |
175555800 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4031911786 |
|
|
Aug 29 07:34:32 AM UTC 24 |
Aug 29 07:34:55 AM UTC 24 |
58517300 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1144144385 |
|
|
Aug 29 07:34:26 AM UTC 24 |
Aug 29 07:34:57 AM UTC 24 |
50837800 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3807839332 |
|
|
Aug 29 07:34:29 AM UTC 24 |
Aug 29 07:34:58 AM UTC 24 |
184676700 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1019135602 |
|
|
Aug 29 07:34:34 AM UTC 24 |
Aug 29 07:35:01 AM UTC 24 |
57194000 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3113562116 |
|
|
Aug 29 07:34:29 AM UTC 24 |
Aug 29 07:35:04 AM UTC 24 |
89126400 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.776132368 |
|
|
Aug 29 07:34:37 AM UTC 24 |
Aug 29 07:35:05 AM UTC 24 |
20348600 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2682318271 |
|
|
Aug 29 07:34:39 AM UTC 24 |
Aug 29 07:35:05 AM UTC 24 |
23338200 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3609470243 |
|
|
Aug 29 07:34:43 AM UTC 24 |
Aug 29 07:35:08 AM UTC 24 |
38263500 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1419826119 |
|
|
Aug 29 07:34:39 AM UTC 24 |
Aug 29 07:35:15 AM UTC 24 |
175527400 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1656969265 |
|
|
Aug 29 07:34:49 AM UTC 24 |
Aug 29 07:35:15 AM UTC 24 |
179199300 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2235860547 |
|
|
Aug 29 07:34:48 AM UTC 24 |
Aug 29 07:35:16 AM UTC 24 |
14019300 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2107563147 |
|
|
Aug 29 07:34:49 AM UTC 24 |
Aug 29 07:35:17 AM UTC 24 |
114745700 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3298544017 |
|
|
Aug 29 07:34:41 AM UTC 24 |
Aug 29 07:35:17 AM UTC 24 |
63045500 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.377291344 |
|
|
Aug 29 07:34:56 AM UTC 24 |
Aug 29 07:35:19 AM UTC 24 |
13470900 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2116843729 |
|
|
Aug 29 07:34:55 AM UTC 24 |
Aug 29 07:35:19 AM UTC 24 |
40866600 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.594109401 |
|
|
Aug 29 07:34:54 AM UTC 24 |
Aug 29 07:35:20 AM UTC 24 |
166367000 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3780305234 |
|
|
Aug 29 07:34:50 AM UTC 24 |
Aug 29 07:35:21 AM UTC 24 |
47973100 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2713236570 |
|
|
Aug 29 07:34:50 AM UTC 24 |
Aug 29 07:35:25 AM UTC 24 |
428985500 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.102286409 |
|
|
Aug 29 07:35:01 AM UTC 24 |
Aug 29 07:35:25 AM UTC 24 |
35150500 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.534581677 |
|
|
Aug 29 07:34:59 AM UTC 24 |
Aug 29 07:35:27 AM UTC 24 |
15275300 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3383375961 |
|
|
Aug 29 07:35:02 AM UTC 24 |
Aug 29 07:35:29 AM UTC 24 |
26508500 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.579474471 |
|
|
Aug 29 07:34:59 AM UTC 24 |
Aug 29 07:35:30 AM UTC 24 |
452173400 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3633574992 |
|
|
Aug 29 07:35:09 AM UTC 24 |
Aug 29 07:35:32 AM UTC 24 |
28304800 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4099858655 |
|
|
Aug 29 07:35:06 AM UTC 24 |
Aug 29 07:35:33 AM UTC 24 |
18262000 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2347510973 |
|
|
Aug 29 07:35:15 AM UTC 24 |
Aug 29 07:35:35 AM UTC 24 |
50037300 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2375668223 |
|
|
Aug 29 07:35:05 AM UTC 24 |
Aug 29 07:35:36 AM UTC 24 |
155415300 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2514540904 |
|
|
Aug 29 07:35:20 AM UTC 24 |
Aug 29 07:35:40 AM UTC 24 |
15373500 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1940123140 |
|
|
Aug 29 07:35:21 AM UTC 24 |
Aug 29 07:35:41 AM UTC 24 |
17300500 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1199586162 |
|
|
Aug 29 07:35:20 AM UTC 24 |
Aug 29 07:35:47 AM UTC 24 |
11949800 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.607927492 |
|
|
Aug 29 07:35:16 AM UTC 24 |
Aug 29 07:35:49 AM UTC 24 |
407558800 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2619309092 |
|
|
Aug 29 07:35:17 AM UTC 24 |
Aug 29 07:35:50 AM UTC 24 |
160088200 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.860288051 |
|
|
Aug 29 07:35:18 AM UTC 24 |
Aug 29 07:35:51 AM UTC 24 |
122105500 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.292230165 |
|
|
Aug 29 07:35:33 AM UTC 24 |
Aug 29 07:35:53 AM UTC 24 |
14063500 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1588284098 |
|
|
Aug 29 07:35:34 AM UTC 24 |
Aug 29 07:35:53 AM UTC 24 |
50025100 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1554941321 |
|
|
Aug 29 07:35:22 AM UTC 24 |
Aug 29 07:35:55 AM UTC 24 |
64705600 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.575893580 |
|
|
Aug 29 07:35:25 AM UTC 24 |
Aug 29 07:35:58 AM UTC 24 |
372896800 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1258995677 |
|
|
Aug 29 07:35:16 AM UTC 24 |
Aug 29 07:35:59 AM UTC 24 |
181923800 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2627856922 |
|
|
Aug 29 07:35:26 AM UTC 24 |
Aug 29 07:35:59 AM UTC 24 |
227491300 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.801561802 |
|
|
Aug 29 07:35:31 AM UTC 24 |
Aug 29 07:36:01 AM UTC 24 |
22384200 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1969097601 |
|
|
Aug 29 07:35:27 AM UTC 24 |
Aug 29 07:36:01 AM UTC 24 |
69049200 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1100578142 |
|
|
Aug 29 07:35:36 AM UTC 24 |
Aug 29 07:36:03 AM UTC 24 |
432374500 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2805732846 |
|
|
Aug 29 07:35:42 AM UTC 24 |
Aug 29 07:36:09 AM UTC 24 |
30729500 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3598556503 |
|
|
Aug 29 07:35:52 AM UTC 24 |
Aug 29 07:36:12 AM UTC 24 |
124196600 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3226353250 |
|
|
Aug 29 07:35:42 AM UTC 24 |
Aug 29 07:36:13 AM UTC 24 |
215425100 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2779029388 |
|
|
Aug 29 07:35:56 AM UTC 24 |
Aug 29 07:36:16 AM UTC 24 |
39252400 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2206147313 |
|
|
Aug 29 07:35:48 AM UTC 24 |
Aug 29 07:36:16 AM UTC 24 |
13227500 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1811775085 |
|
|
Aug 29 07:35:50 AM UTC 24 |
Aug 29 07:36:17 AM UTC 24 |
51154400 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3016567159 |
|
|
Aug 29 07:35:59 AM UTC 24 |
Aug 29 07:36:22 AM UTC 24 |
125745700 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2039144655 |
|
|
Aug 29 07:35:50 AM UTC 24 |
Aug 29 07:36:23 AM UTC 24 |
39090400 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1823099591 |
|
|
Aug 29 07:36:00 AM UTC 24 |
Aug 29 07:36:24 AM UTC 24 |
44759500 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3960628586 |
|
|
Aug 29 07:36:03 AM UTC 24 |
Aug 29 07:36:26 AM UTC 24 |
79541100 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1855533627 |
|
|
Aug 29 07:36:00 AM UTC 24 |
Aug 29 07:36:26 AM UTC 24 |
29205900 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1533856227 |
|
|
Aug 29 07:35:38 AM UTC 24 |
Aug 29 07:36:27 AM UTC 24 |
63059200 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2288923421 |
|
|
Aug 29 07:35:59 AM UTC 24 |
Aug 29 07:36:29 AM UTC 24 |
68421200 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1437839080 |
|
|
Aug 29 07:35:54 AM UTC 24 |
Aug 29 07:36:30 AM UTC 24 |
887943500 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.227380784 |
|
|
Aug 29 07:35:54 AM UTC 24 |
Aug 29 07:36:31 AM UTC 24 |
888954600 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.664641343 |
|
|
Aug 29 07:36:02 AM UTC 24 |
Aug 29 07:36:32 AM UTC 24 |
27151200 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.373858749 |
|
|
Aug 29 07:36:15 AM UTC 24 |
Aug 29 07:36:34 AM UTC 24 |
14616900 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2023966574 |
|
|
Aug 29 07:36:01 AM UTC 24 |
Aug 29 07:36:35 AM UTC 24 |
321396000 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4251186101 |
|
|
Aug 29 07:36:13 AM UTC 24 |
Aug 29 07:36:41 AM UTC 24 |
14806400 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3993881108 |
|
|
Aug 29 07:36:17 AM UTC 24 |
Aug 29 07:36:43 AM UTC 24 |
15175900 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.191983573 |
|
|
Aug 29 07:36:18 AM UTC 24 |
Aug 29 07:36:45 AM UTC 24 |
59257900 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.1799426817 |
|
|
Aug 29 07:36:30 AM UTC 24 |
Aug 29 07:36:48 AM UTC 24 |
29026100 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.598588136 |
|
|
Aug 29 07:36:17 AM UTC 24 |
Aug 29 07:36:50 AM UTC 24 |
41282500 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2682814581 |
|
|
Aug 29 07:36:23 AM UTC 24 |
Aug 29 07:36:51 AM UTC 24 |
219606400 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.588208548 |
|
|
Aug 29 07:36:24 AM UTC 24 |
Aug 29 07:36:51 AM UTC 24 |
15960300 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.249926629 |
|
|
Aug 29 07:36:24 AM UTC 24 |
Aug 29 07:36:52 AM UTC 24 |
63527000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3194593664 |
|
|
Aug 29 07:36:26 AM UTC 24 |
Aug 29 07:36:53 AM UTC 24 |
24502600 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.754426794 |
|
|
Aug 29 07:36:28 AM UTC 24 |
Aug 29 07:36:53 AM UTC 24 |
36174400 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2547711483 |
|
|
Aug 29 07:36:27 AM UTC 24 |
Aug 29 07:36:54 AM UTC 24 |
26775800 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.4037861629 |
|
|
Aug 29 07:36:32 AM UTC 24 |
Aug 29 07:36:58 AM UTC 24 |
32209100 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2767425057 |
|
|
Aug 29 07:36:30 AM UTC 24 |
Aug 29 07:36:58 AM UTC 24 |
41942600 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2650681868 |
|
|
Aug 29 07:36:35 AM UTC 24 |
Aug 29 07:36:59 AM UTC 24 |
16770100 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1956372296 |
|
|
Aug 29 07:36:34 AM UTC 24 |
Aug 29 07:36:59 AM UTC 24 |
15969800 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1779481318 |
|
|
Aug 29 07:36:36 AM UTC 24 |
Aug 29 07:37:02 AM UTC 24 |
28234100 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.3335695755 |
|
|
Aug 29 07:36:42 AM UTC 24 |
Aug 29 07:37:06 AM UTC 24 |
42968400 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.823725753 |
|
|
Aug 29 07:36:44 AM UTC 24 |
Aug 29 07:37:09 AM UTC 24 |
59898600 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2312779909 |
|
|
Aug 29 07:36:46 AM UTC 24 |
Aug 29 07:37:12 AM UTC 24 |
53674100 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3467601712 |
|
|
Aug 29 07:36:52 AM UTC 24 |
Aug 29 07:37:14 AM UTC 24 |
21865000 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2480729196 |
|
|
Aug 29 07:36:48 AM UTC 24 |
Aug 29 07:37:15 AM UTC 24 |
56348700 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.3819080230 |
|
|
Aug 29 07:36:50 AM UTC 24 |
Aug 29 07:37:16 AM UTC 24 |
15626900 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.383479001 |
|
|
Aug 29 07:36:51 AM UTC 24 |
Aug 29 07:37:17 AM UTC 24 |
14735500 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2810333618 |
|
|
Aug 29 07:36:53 AM UTC 24 |
Aug 29 07:37:18 AM UTC 24 |
95642500 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2493461541 |
|
|
Aug 29 07:36:53 AM UTC 24 |
Aug 29 07:37:19 AM UTC 24 |
31973700 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2535674551 |
|
|
Aug 29 07:36:59 AM UTC 24 |
Aug 29 07:37:20 AM UTC 24 |
16589300 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3331177195 |
|
|
Aug 29 07:36:59 AM UTC 24 |
Aug 29 07:37:21 AM UTC 24 |
53574900 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.317440233 |
|
|
Aug 29 07:36:53 AM UTC 24 |
Aug 29 07:37:21 AM UTC 24 |
25070600 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.866565401 |
|
|
Aug 29 07:37:00 AM UTC 24 |
Aug 29 07:37:22 AM UTC 24 |
29925700 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3951192581 |
|
|
Aug 29 07:36:55 AM UTC 24 |
Aug 29 07:37:23 AM UTC 24 |
14343000 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.4190291067 |
|
|
Aug 29 07:37:00 AM UTC 24 |
Aug 29 07:37:23 AM UTC 24 |
57668600 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.3863270250 |
|
|
Aug 29 07:37:03 AM UTC 24 |
Aug 29 07:37:30 AM UTC 24 |
14885000 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3878818585 |
|
|
Aug 29 07:37:12 AM UTC 24 |
Aug 29 07:37:32 AM UTC 24 |
16518300 ps |