| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.23 | 95.68 | 93.90 | 98.31 | 92.52 | 98.21 | 96.89 | 98.12 |
| T1270 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.754390744 | Aug 29 07:37:07 AM UTC 24 | Aug 29 07:37:34 AM UTC 24 | 42732400 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2244570329 | Aug 29 07:37:09 AM UTC 24 | Aug 29 07:37:35 AM UTC 24 | 17833000 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1124331735 | Aug 29 07:32:37 AM UTC 24 | Aug 29 07:42:31 AM UTC 24 | 1373620700 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3974194652 | Aug 29 07:32:10 AM UTC 24 | Aug 29 07:42:46 AM UTC 24 | 697213900 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2933620669 | Aug 29 07:33:44 AM UTC 24 | Aug 29 07:42:52 AM UTC 24 | 371344700 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2163754736 | Aug 29 07:31:17 AM UTC 24 | Aug 29 07:43:22 AM UTC 24 | 707501800 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2855575129 | Aug 29 07:35:30 AM UTC 24 | Aug 29 07:43:56 AM UTC 24 | 2260477100 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3835575878 | Aug 29 07:33:58 AM UTC 24 | Aug 29 07:45:52 AM UTC 24 | 525497800 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3590627388 | Aug 29 07:34:54 AM UTC 24 | Aug 29 07:45:53 AM UTC 24 | 282521900 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4009416629 | Aug 29 07:34:19 AM UTC 24 | Aug 29 07:46:15 AM UTC 24 | 342236000 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2172337119 | Aug 29 07:35:18 AM UTC 24 | Aug 29 07:48:26 AM UTC 24 | 176737400 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.884599627 | Aug 29 07:33:06 AM UTC 24 | Aug 29 07:51:44 AM UTC 24 | 3477076700 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2089319319 | Aug 29 07:31:39 AM UTC 24 | Aug 29 07:52:05 AM UTC 24 | 363813000 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2017336852 | Aug 29 07:33:30 AM UTC 24 | Aug 29 07:52:33 AM UTC 24 | 677084200 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3295015207 | Aug 29 07:33:35 AM UTC 24 | Aug 29 07:53:11 AM UTC 24 | 847557300 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3894996548 | Aug 29 07:35:56 AM UTC 24 | Aug 29 07:54:05 AM UTC 24 | 820592500 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3462398604 | Aug 29 07:34:08 AM UTC 24 | Aug 29 07:54:40 AM UTC 24 | 967509600 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3163804197 | Aug 29 07:34:30 AM UTC 24 | Aug 29 07:54:57 AM UTC 24 | 851450500 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2314566389 | Aug 29 07:35:06 AM UTC 24 | Aug 29 07:55:58 AM UTC 24 | 1176775000 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4077874542 | Aug 29 07:34:41 AM UTC 24 | Aug 29 07:56:04 AM UTC 24 | 965037500 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3291552450 | Aug 29 07:36:10 AM UTC 24 | Aug 29 07:56:26 AM UTC 24 | 348702800 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4132738570 | Aug 29 07:35:45 AM UTC 24 | Aug 29 07:56:32 AM UTC 24 | 1284272700 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.293659085 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 70145100 ps |
| CPU time | 35.3 seconds |
| Started | Aug 29 09:40:25 AM UTC 24 |
| Finished | Aug 29 09:41:02 AM UTC 24 |
| Peak memory | 287736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293659085 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.293659085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3353401679 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 10808637600 ps |
| CPU time | 79.38 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:41:36 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353401679 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3353401679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.319927000 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 656292300 ps |
| CPU time | 32.77 seconds |
| Started | Aug 29 07:31:28 AM UTC 24 |
| Finished | Aug 29 07:32:03 AM UTC 24 |
| Peak memory | 283848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=319927000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.319927000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3733244241 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 84348000 ps |
| CPU time | 25.87 seconds |
| Started | Aug 29 09:40:54 AM UTC 24 |
| Finished | Aug 29 09:41:21 AM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733244241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_wr_intg.3733244241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2054323887 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3734877900 ps |
| CPU time | 181.67 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 09:43:18 AM UTC 24 |
| Peak memory | 275600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2054323887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.2054323887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3268829305 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 40130207200 ps |
| CPU time | 910.63 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 09:55:34 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268829305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.3268829305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.47123409 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3946618300 ps |
| CPU time | 67.22 seconds |
| Started | Aug 29 07:32:23 AM UTC 24 |
| Finished | Aug 29 07:33:32 AM UTC 24 |
| Peak memory | 271568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47123409 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.47123409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3120992155 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3816432300 ps |
| CPU time | 7052.69 seconds |
| Started | Aug 29 10:02:01 AM UTC 24 |
| Finished | Aug 29 12:00:50 PM UTC 24 |
| Peak memory | 314484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120992155 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3120992155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2347577596 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2506452200 ps |
| CPU time | 153.58 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:42:51 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2347577596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_ro_serr.2347577596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.71327039 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1472845600 ps |
| CPU time | 65.53 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:41:19 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71327039 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.71327039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2261666604 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 67006662500 ps |
| CPU time | 871.12 seconds |
| Started | Aug 29 09:42:04 AM UTC 24 |
| Finished | Aug 29 09:56:45 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261666604 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2261666604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.859869906 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3431698000 ps |
| CPU time | 84.83 seconds |
| Started | Aug 29 09:42:53 AM UTC 24 |
| Finished | Aug 29 09:44:20 AM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859869906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.859869906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2481524803 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19900400 ps |
| CPU time | 27.38 seconds |
| Started | Aug 29 09:41:12 AM UTC 24 |
| Finished | Aug 29 09:41:41 AM UTC 24 |
| Peak memory | 273808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2481524803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2481524803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3062836039 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 22707848500 ps |
| CPU time | 318.49 seconds |
| Started | Aug 29 09:40:20 AM UTC 24 |
| Finished | Aug 29 09:45:43 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3062836039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.3062836039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.4169231913 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 37639600 ps |
| CPU time | 230.54 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 09:44:07 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169231913 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.4169231913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3511982723 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2891030000 ps |
| CPU time | 106.02 seconds |
| Started | Aug 29 07:31:21 AM UTC 24 |
| Finished | Aug 29 07:33:09 AM UTC 24 |
| Peak memory | 271504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511982723 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.3511982723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.133322967 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 36734200 ps |
| CPU time | 185.31 seconds |
| Started | Aug 29 10:43:08 AM UTC 24 |
| Finished | Aug 29 10:46:16 AM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133322967 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.133322967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2832574753 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 40193100 ps |
| CPU time | 225.27 seconds |
| Started | Aug 29 09:51:39 AM UTC 24 |
| Finished | Aug 29 09:55:28 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832574753 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.2832574753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3188954223 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 25539100 ps |
| CPU time | 19.31 seconds |
| Started | Aug 29 07:31:48 AM UTC 24 |
| Finished | Aug 29 07:32:09 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188954223 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3188954223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2933620669 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 371344700 ps |
| CPU time | 541.95 seconds |
| Started | Aug 29 07:33:44 AM UTC 24 |
| Finished | Aug 29 07:42:52 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933620669 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.2933620669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3508900836 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1877773400 ps |
| CPU time | 182.68 seconds |
| Started | Aug 29 09:41:50 AM UTC 24 |
| Finished | Aug 29 09:44:55 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508900836 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.3508900836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2855882787 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 10021968700 ps |
| CPU time | 215.96 seconds |
| Started | Aug 29 09:46:02 AM UTC 24 |
| Finished | Aug 29 09:49:42 AM UTC 24 |
| Peak memory | 298108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2855882787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2855882787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1423661186 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3516331100 ps |
| CPU time | 278.54 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:45:00 AM UTC 24 |
| Peak memory | 302268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1423661186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rw_derr.1423661186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1418486628 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 49714942900 ps |
| CPU time | 1061.9 seconds |
| Started | Aug 29 09:45:53 AM UTC 24 |
| Finished | Aug 29 10:03:49 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1418486628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.1418486628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2000005110 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 48936500 ps |
| CPU time | 36.23 seconds |
| Started | Aug 29 07:32:33 AM UTC 24 |
| Finished | Aug 29 07:33:11 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2000005110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2000005110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3266503852 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3504772200 ps |
| CPU time | 96.96 seconds |
| Started | Aug 29 09:49:53 AM UTC 24 |
| Finished | Aug 29 09:51:32 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266503852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3266503852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.371795572 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 987400500 ps |
| CPU time | 24.72 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 09:40:39 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 1795572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch _code.371795572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.951416499 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 71578700 ps |
| CPU time | 25.27 seconds |
| Started | Aug 29 09:41:40 AM UTC 24 |
| Finished | Aug 29 09:42:07 AM UTC 24 |
| Peak memory | 269564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951416499 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.951416499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2071471917 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 25318700 ps |
| CPU time | 27.62 seconds |
| Started | Aug 29 10:02:25 AM UTC 24 |
| Finished | Aug 29 10:02:54 AM UTC 24 |
| Peak memory | 293292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071471917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2071471917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.1700721772 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 567704751600 ps |
| CPU time | 2355.28 seconds |
| Started | Aug 29 09:58:04 AM UTC 24 |
| Finished | Aug 29 10:37:44 AM UTC 24 |
| Peak memory | 278264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700721772 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.1700721772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1507646104 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 98698800 ps |
| CPU time | 22.99 seconds |
| Started | Aug 29 10:16:22 AM UTC 24 |
| Finished | Aug 29 10:16:46 AM UTC 24 |
| Peak memory | 269424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1507646104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1507646104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1407787112 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2671736900 ps |
| CPU time | 120.26 seconds |
| Started | Aug 29 09:52:44 AM UTC 24 |
| Finished | Aug 29 09:54:46 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407787112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1407787112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2520827968 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 66228200 ps |
| CPU time | 38.34 seconds |
| Started | Aug 29 07:34:08 AM UTC 24 |
| Finished | Aug 29 07:34:48 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520827968 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2520827968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2600550880 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2311137400 ps |
| CPU time | 207.12 seconds |
| Started | Aug 29 09:43:50 AM UTC 24 |
| Finished | Aug 29 09:47:20 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2600550880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2600550880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1268845160 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 11963201100 ps |
| CPU time | 326.55 seconds |
| Started | Aug 29 09:46:59 AM UTC 24 |
| Finished | Aug 29 09:52:30 AM UTC 24 |
| Peak memory | 283532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1268845160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.1268845160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1398518249 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 62930500 ps |
| CPU time | 27.35 seconds |
| Started | Aug 29 07:32:15 AM UTC 24 |
| Finished | Aug 29 07:32:44 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398518249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.1398518249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2412428598 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 15730600 ps |
| CPU time | 17.99 seconds |
| Started | Aug 29 10:12:47 AM UTC 24 |
| Finished | Aug 29 10:13:07 AM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2412428598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.2412428598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2705919513 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 612242500 ps |
| CPU time | 184.21 seconds |
| Started | Aug 29 10:10:50 AM UTC 24 |
| Finished | Aug 29 10:13:57 AM UTC 24 |
| Peak memory | 308240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705919513 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2705919513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2017336852 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 677084200 ps |
| CPU time | 1131.03 seconds |
| Started | Aug 29 07:33:30 AM UTC 24 |
| Finished | Aug 29 07:52:33 AM UTC 24 |
| Peak memory | 273684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017336852 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2017336852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.3318940256 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 73020200 ps |
| CPU time | 45.56 seconds |
| Started | Aug 29 09:40:28 AM UTC 24 |
| Finished | Aug 29 09:41:15 AM UTC 24 |
| Peak memory | 287732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318940256 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.3318940256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3321500382 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 123816000 ps |
| CPU time | 33.27 seconds |
| Started | Aug 29 07:33:00 AM UTC 24 |
| Finished | Aug 29 07:33:35 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321500382 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3321500382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4071551049 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 106389800 ps |
| CPU time | 22.67 seconds |
| Started | Aug 29 07:33:34 AM UTC 24 |
| Finished | Aug 29 07:33:58 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4071551049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4071551049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3686475101 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 8085152300 ps |
| CPU time | 112.79 seconds |
| Started | Aug 29 10:13:28 AM UTC 24 |
| Finished | Aug 29 10:15:23 AM UTC 24 |
| Peak memory | 271308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686475101 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3686475101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1847807386 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 14622732200 ps |
| CPU time | 562.78 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:49:45 AM UTC 24 |
| Peak memory | 324604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847807386 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.1847807386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2994978762 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 10032571400 ps |
| CPU time | 80.1 seconds |
| Started | Aug 29 10:20:53 AM UTC 24 |
| Finished | Aug 29 10:22:15 AM UTC 24 |
| Peak memory | 302084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2994978762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2994978762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1342880706 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 27083300 ps |
| CPU time | 47.99 seconds |
| Started | Aug 29 09:40:27 AM UTC 24 |
| Finished | Aug 29 09:41:16 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1342880706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_rw_evict_all_en.1342880706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.430519508 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 22655800 ps |
| CPU time | 28.37 seconds |
| Started | Aug 29 09:50:37 AM UTC 24 |
| Finished | Aug 29 09:51:07 AM UTC 24 |
| Peak memory | 275660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=430519508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.430519508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1674305504 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 82389518300 ps |
| CPU time | 189.78 seconds |
| Started | Aug 29 09:51:30 AM UTC 24 |
| Finished | Aug 29 09:54:43 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674305504 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.1674305504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.3029671973 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 61428700 ps |
| CPU time | 49.37 seconds |
| Started | Aug 29 10:24:39 AM UTC 24 |
| Finished | Aug 29 10:25:30 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029671973 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.3029671973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.41654886 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1674608400 ps |
| CPU time | 7631.45 seconds |
| Started | Aug 29 09:55:56 AM UTC 24 |
| Finished | Aug 29 12:04:29 PM UTC 24 |
| Peak memory | 320652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41654886 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.41654886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2901676564 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 362901400 ps |
| CPU time | 62.39 seconds |
| Started | Aug 29 09:45:39 AM UTC 24 |
| Finished | Aug 29 09:46:43 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901676 564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f s_sup.2901676564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.43688489 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 90159579200 ps |
| CPU time | 855.27 seconds |
| Started | Aug 29 09:42:08 AM UTC 24 |
| Finished | Aug 29 09:56:33 AM UTC 24 |
| Peak memory | 275368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43688489 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.43688489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.3938093881 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1310816800 ps |
| CPU time | 48.58 seconds |
| Started | Aug 29 09:52:07 AM UTC 24 |
| Finished | Aug 29 09:52:57 AM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 38093881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc h_code.3938093881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1899025511 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 720082400 ps |
| CPU time | 28.46 seconds |
| Started | Aug 29 09:41:03 AM UTC 24 |
| Finished | Aug 29 09:41:33 AM UTC 24 |
| Peak memory | 273568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1899025511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1899025511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3454554903 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 19196900 ps |
| CPU time | 26.74 seconds |
| Started | Aug 29 09:46:02 AM UTC 24 |
| Finished | Aug 29 09:46:30 AM UTC 24 |
| Peak memory | 275328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3454554903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3454554903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1837326634 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 15628400 ps |
| CPU time | 26.59 seconds |
| Started | Aug 29 07:32:39 AM UTC 24 |
| Finished | Aug 29 07:33:08 AM UTC 24 |
| Peak memory | 271540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837326634 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1837326634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1406360484 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1177466500 ps |
| CPU time | 72.77 seconds |
| Started | Aug 29 10:22:25 AM UTC 24 |
| Finished | Aug 29 10:23:40 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406360484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1406360484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.4240973231 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 7599478600 ps |
| CPU time | 415.34 seconds |
| Started | Aug 29 10:13:52 AM UTC 24 |
| Finished | Aug 29 10:20:53 AM UTC 24 |
| Peak memory | 330716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240973231 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.4240973231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3216443301 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3538198400 ps |
| CPU time | 157.64 seconds |
| Started | Aug 29 10:31:51 AM UTC 24 |
| Finished | Aug 29 10:34:31 AM UTC 24 |
| Peak memory | 304312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216443301 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.3216443301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.685593555 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 11959200 ps |
| CPU time | 43.53 seconds |
| Started | Aug 29 10:47:46 AM UTC 24 |
| Finished | Aug 29 10:48:31 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=685593555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c trl_disable.685593555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3894996548 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 820592500 ps |
| CPU time | 1077.91 seconds |
| Started | Aug 29 07:35:56 AM UTC 24 |
| Finished | Aug 29 07:54:05 AM UTC 24 |
| Peak memory | 273744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894996548 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.3894996548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2133851167 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 24459700 ps |
| CPU time | 25.12 seconds |
| Started | Aug 29 10:12:41 AM UTC 24 |
| Finished | Aug 29 10:13:08 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133851167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2133851167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3964722915 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9384587200 ps |
| CPU time | 82.02 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:41:41 AM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964722915 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.3964722915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.646566273 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 6318767000 ps |
| CPU time | 431.21 seconds |
| Started | Aug 29 09:47:39 AM UTC 24 |
| Finished | Aug 29 09:54:56 AM UTC 24 |
| Peak memory | 330736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646566273 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.646566273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3922235829 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3611182800 ps |
| CPU time | 3495.62 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 10:39:06 AM UTC 24 |
| Peak memory | 278132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 22235829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _error_prog_type.3922235829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2319662254 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 338639800 ps |
| CPU time | 1199.41 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 10:00:26 AM UTC 24 |
| Peak memory | 283468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319662254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2319662254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.4197987480 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 58093000 ps |
| CPU time | 26.74 seconds |
| Started | Aug 29 09:50:48 AM UTC 24 |
| Finished | Aug 29 09:51:16 AM UTC 24 |
| Peak memory | 275592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=4197987480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.4197987480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1607024146 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 15371500 ps |
| CPU time | 23.47 seconds |
| Started | Aug 29 10:30:54 AM UTC 24 |
| Finished | Aug 29 10:31:19 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1607024146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_lcmgr_intg.1607024146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.291927360 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 10011571800 ps |
| CPU time | 154.5 seconds |
| Started | Aug 29 09:41:23 AM UTC 24 |
| Finished | Aug 29 09:44:00 AM UTC 24 |
| Peak memory | 312676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=291927360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.291927360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.2659897113 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 45193600 ps |
| CPU time | 24.35 seconds |
| Started | Aug 29 09:41:22 AM UTC 24 |
| Finished | Aug 29 09:41:47 AM UTC 24 |
| Peak memory | 269444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2659897113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2659897113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3291552450 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 348702800 ps |
| CPU time | 1202.47 seconds |
| Started | Aug 29 07:36:10 AM UTC 24 |
| Finished | Aug 29 07:56:26 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291552450 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.3291552450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3295015207 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 847557300 ps |
| CPU time | 1162.19 seconds |
| Started | Aug 29 07:33:35 AM UTC 24 |
| Finished | Aug 29 07:53:11 AM UTC 24 |
| Peak memory | 273684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295015207 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.3295015207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.3199630534 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 641152100 ps |
| CPU time | 87.27 seconds |
| Started | Aug 29 10:36:19 AM UTC 24 |
| Finished | Aug 29 10:37:49 AM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199630534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3199630534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3498782107 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 1806958900 ps |
| CPU time | 67.94 seconds |
| Started | Aug 29 10:50:01 AM UTC 24 |
| Finished | Aug 29 10:51:10 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498782107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3498782107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1521412736 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 144354000 ps |
| CPU time | 133.53 seconds |
| Started | Aug 29 10:50:49 AM UTC 24 |
| Finished | Aug 29 10:53:04 AM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521412736 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.1521412736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3346568967 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 150412600 ps |
| CPU time | 58.34 seconds |
| Started | Aug 29 10:08:21 AM UTC 24 |
| Finished | Aug 29 10:09:21 AM UTC 24 |
| Peak memory | 287732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346568967 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.3346568967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.53639149 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 17041900 ps |
| CPU time | 25.43 seconds |
| Started | Aug 29 10:45:51 AM UTC 24 |
| Finished | Aug 29 10:46:18 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=53639149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ct rl_disable.53639149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.515786405 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 415344800 ps |
| CPU time | 28.97 seconds |
| Started | Aug 29 07:34:18 AM UTC 24 |
| Finished | Aug 29 07:34:48 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515786405 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.515786405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2703469323 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 845804300 ps |
| CPU time | 32.22 seconds |
| Started | Aug 29 09:50:47 AM UTC 24 |
| Finished | Aug 29 09:51:20 AM UTC 24 |
| Peak memory | 275588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2703469323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2703469323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.59988607 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 22580100 ps |
| CPU time | 24.21 seconds |
| Started | Aug 29 09:41:15 AM UTC 24 |
| Finished | Aug 29 09:41:41 AM UTC 24 |
| Peak memory | 273248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59988607 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.59988607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2539505956 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10141300 ps |
| CPU time | 38.45 seconds |
| Started | Aug 29 09:40:31 AM UTC 24 |
| Finished | Aug 29 09:41:11 AM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2539505956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_disable.2539505956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3023207109 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 55413900 ps |
| CPU time | 27.02 seconds |
| Started | Aug 29 09:44:57 AM UTC 24 |
| Finished | Aug 29 09:45:25 AM UTC 24 |
| Peak memory | 275672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3023207109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_disable.3023207109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2040002624 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 40686200 ps |
| CPU time | 49.49 seconds |
| Started | Aug 29 09:44:46 AM UTC 24 |
| Finished | Aug 29 09:45:37 AM UTC 24 |
| Peak memory | 287924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040002624 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2040002624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.877978139 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 23717200 ps |
| CPU time | 33.66 seconds |
| Started | Aug 29 10:22:22 AM UTC 24 |
| Finished | Aug 29 10:22:57 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=877978139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c trl_disable.877978139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.4082327974 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 42666000 ps |
| CPU time | 42.73 seconds |
| Started | Aug 29 10:22:16 AM UTC 24 |
| Finished | Aug 29 10:23:00 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4082327974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c trl_rw_evict_all_en.4082327974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.530975042 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 113939100 ps |
| CPU time | 40.04 seconds |
| Started | Aug 29 10:26:15 AM UTC 24 |
| Finished | Aug 29 10:26:56 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=530975042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c trl_disable.530975042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1189302390 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 160189591100 ps |
| CPU time | 1096.27 seconds |
| Started | Aug 29 10:25:25 AM UTC 24 |
| Finished | Aug 29 10:43:54 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189302390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res et.1189302390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.775981748 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 27495177800 ps |
| CPU time | 291.66 seconds |
| Started | Aug 29 10:39:07 AM UTC 24 |
| Finished | Aug 29 10:44:03 AM UTC 24 |
| Peak memory | 294132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775981748 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.775981748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3740490284 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 71494600 ps |
| CPU time | 55.17 seconds |
| Started | Aug 29 10:40:44 AM UTC 24 |
| Finished | Aug 29 10:41:41 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3740490284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_rw_evict_all_en.3740490284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.2126172558 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1433816900 ps |
| CPU time | 94.4 seconds |
| Started | Aug 29 10:46:44 AM UTC 24 |
| Finished | Aug 29 10:48:20 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126172558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2126172558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.237446155 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 336050200 ps |
| CPU time | 38.11 seconds |
| Started | Aug 29 10:02:16 AM UTC 24 |
| Finished | Aug 29 10:02:55 AM UTC 24 |
| Peak memory | 273516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374461 55 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fs _sup.237446155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.1099005852 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 27226300 ps |
| CPU time | 34.48 seconds |
| Started | Aug 29 10:49:11 AM UTC 24 |
| Finished | Aug 29 10:49:47 AM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1099005852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ ctrl_disable.1099005852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.949531490 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1159572000 ps |
| CPU time | 77.29 seconds |
| Started | Aug 29 10:50:39 AM UTC 24 |
| Finished | Aug 29 10:51:58 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949531490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.949531490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2782115432 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2079433000 ps |
| CPU time | 110.26 seconds |
| Started | Aug 29 10:18:28 AM UTC 24 |
| Finished | Aug 29 10:20:21 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782115432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2782115432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.442073973 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 320230996300 ps |
| CPU time | 1143.03 seconds |
| Started | Aug 29 10:19:09 AM UTC 24 |
| Finished | Aug 29 10:38:26 AM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442073973 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_reset.442073973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.131623759 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 179347800 ps |
| CPU time | 32.63 seconds |
| Started | Aug 29 07:32:04 AM UTC 24 |
| Finished | Aug 29 07:32:38 AM UTC 24 |
| Peak memory | 289996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=131623759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.131623759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3966692533 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 67308600 ps |
| CPU time | 144.03 seconds |
| Started | Aug 29 09:46:22 AM UTC 24 |
| Finished | Aug 29 09:48:48 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966692533 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3966692533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.254927383 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 16363400 ps |
| CPU time | 23.97 seconds |
| Started | Aug 29 09:56:46 AM UTC 24 |
| Finished | Aug 29 09:57:11 AM UTC 24 |
| Peak memory | 275620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254927383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.254927383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3181959967 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14938800 ps |
| CPU time | 27.53 seconds |
| Started | Aug 29 09:56:40 AM UTC 24 |
| Finished | Aug 29 09:57:09 AM UTC 24 |
| Peak memory | 275624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3181959967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3181959967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1871175905 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 8551319500 ps |
| CPU time | 2886.19 seconds |
| Started | Aug 29 10:13:19 AM UTC 24 |
| Finished | Aug 29 11:01:57 AM UTC 24 |
| Peak memory | 278064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871175905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1871175905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2089319319 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 363813000 ps |
| CPU time | 1212.84 seconds |
| Started | Aug 29 07:31:39 AM UTC 24 |
| Finished | Aug 29 07:52:05 AM UTC 24 |
| Peak memory | 273556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089319319 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.2089319319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3163804197 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 851450500 ps |
| CPU time | 1213.28 seconds |
| Started | Aug 29 07:34:30 AM UTC 24 |
| Finished | Aug 29 07:54:57 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163804197 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.3163804197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.594109401 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 166367000 ps |
| CPU time | 24.62 seconds |
| Started | Aug 29 07:34:54 AM UTC 24 |
| Finished | Aug 29 07:35:20 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594109401 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.594109401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1221355172 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 19564700 ps |
| CPU time | 20.57 seconds |
| Started | Aug 29 09:41:00 AM UTC 24 |
| Finished | Aug 29 09:41:22 AM UTC 24 |
| Peak memory | 275596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1221355172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1221355172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2922909982 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 652266200 ps |
| CPU time | 1359.32 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 10:03:06 AM UTC 24 |
| Peak memory | 294516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922909982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2922909982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.3155458852 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13856800 ps |
| CPU time | 22.05 seconds |
| Started | Aug 29 09:45:39 AM UTC 24 |
| Finished | Aug 29 09:46:02 AM UTC 24 |
| Peak memory | 273192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3155458852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3155458852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.666669589 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 12339369500 ps |
| CPU time | 211.27 seconds |
| Started | Aug 29 09:48:24 AM UTC 24 |
| Finished | Aug 29 09:51:59 AM UTC 24 |
| Peak memory | 291848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666669589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.666669589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2275094146 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 576932142700 ps |
| CPU time | 2751.05 seconds |
| Started | Aug 29 09:51:47 AM UTC 24 |
| Finished | Aug 29 10:38:08 AM UTC 24 |
| Peak memory | 278256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275094146 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.2275094146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3465236146 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7430896800 ps |
| CPU time | 278.02 seconds |
| Started | Aug 29 09:54:39 AM UTC 24 |
| Finished | Aug 29 09:59:21 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3465236146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.3465236146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2544141464 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 668625900 ps |
| CPU time | 33.74 seconds |
| Started | Aug 29 10:02:17 AM UTC 24 |
| Finished | Aug 29 10:02:52 AM UTC 24 |
| Peak memory | 275588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2544141464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2544141464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.250455337 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1315370000 ps |
| CPU time | 65.35 seconds |
| Started | Aug 29 07:31:20 AM UTC 24 |
| Finished | Aug 29 07:32:27 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250455337 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.250455337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2269043965 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 95314300 ps |
| CPU time | 51.24 seconds |
| Started | Aug 29 07:31:20 AM UTC 24 |
| Finished | Aug 29 07:32:13 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269043965 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.2269043965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1020165537 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27466300 ps |
| CPU time | 31.23 seconds |
| Started | Aug 29 07:31:20 AM UTC 24 |
| Finished | Aug 29 07:31:52 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020165537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.1020165537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3603460639 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 57619600 ps |
| CPU time | 25.38 seconds |
| Started | Aug 29 07:31:19 AM UTC 24 |
| Finished | Aug 29 07:31:45 AM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603460639 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3603460639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2140216089 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 63730900 ps |
| CPU time | 25.86 seconds |
| Started | Aug 29 07:31:20 AM UTC 24 |
| Finished | Aug 29 07:31:47 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140216089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.2140216089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2416353343 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 28415900 ps |
| CPU time | 27.62 seconds |
| Started | Aug 29 07:31:19 AM UTC 24 |
| Finished | Aug 29 07:31:47 AM UTC 24 |
| Peak memory | 271504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416353343 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.2416353343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.305506136 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 169516900 ps |
| CPU time | 30.68 seconds |
| Started | Aug 29 07:31:24 AM UTC 24 |
| Finished | Aug 29 07:31:56 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 305506136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_s ame_csr_outstanding.305506136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1082131814 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 32609200 ps |
| CPU time | 28.53 seconds |
| Started | Aug 29 07:31:17 AM UTC 24 |
| Finished | Aug 29 07:31:47 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108 2131814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha dow_reg_errors.1082131814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4197751404 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 23233500 ps |
| CPU time | 27.91 seconds |
| Started | Aug 29 07:31:19 AM UTC 24 |
| Finished | Aug 29 07:31:48 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4197751404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_shadow_reg_errors_with_csr_rw.4197751404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3844706550 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 115045800 ps |
| CPU time | 33.79 seconds |
| Started | Aug 29 07:31:16 AM UTC 24 |
| Finished | Aug 29 07:31:51 AM UTC 24 |
| Peak memory | 273720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844706550 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3844706550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2163754736 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 707501800 ps |
| CPU time | 715.17 seconds |
| Started | Aug 29 07:31:17 AM UTC 24 |
| Finished | Aug 29 07:43:22 AM UTC 24 |
| Peak memory | 273684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163754736 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.2163754736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1625619075 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 13870973000 ps |
| CPU time | 103.01 seconds |
| Started | Aug 29 07:31:57 AM UTC 24 |
| Finished | Aug 29 07:33:43 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625619075 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.1625619075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3325093909 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1587246000 ps |
| CPU time | 78.86 seconds |
| Started | Aug 29 07:31:53 AM UTC 24 |
| Finished | Aug 29 07:33:14 AM UTC 24 |
| Peak memory | 271568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325093909 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.3325093909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.494709394 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 97526200 ps |
| CPU time | 61.57 seconds |
| Started | Aug 29 07:31:49 AM UTC 24 |
| Finished | Aug 29 07:32:52 AM UTC 24 |
| Peak memory | 271568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494709394 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.494709394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3039423933 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 213701800 ps |
| CPU time | 29.34 seconds |
| Started | Aug 29 07:31:52 AM UTC 24 |
| Finished | Aug 29 07:32:23 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039423933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.3039423933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1252878927 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 28283500 ps |
| CPU time | 25.28 seconds |
| Started | Aug 29 07:31:48 AM UTC 24 |
| Finished | Aug 29 07:32:15 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252878927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1252878927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2840226727 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 21583400 ps |
| CPU time | 23.14 seconds |
| Started | Aug 29 07:31:48 AM UTC 24 |
| Finished | Aug 29 07:32:13 AM UTC 24 |
| Peak memory | 271632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840226727 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2840226727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1223233630 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 103460000 ps |
| CPU time | 30.63 seconds |
| Started | Aug 29 07:32:00 AM UTC 24 |
| Finished | Aug 29 07:32:32 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1223233630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ same_csr_outstanding.1223233630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2886309505 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 24208600 ps |
| CPU time | 28.95 seconds |
| Started | Aug 29 07:31:46 AM UTC 24 |
| Finished | Aug 29 07:32:16 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288 6309505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha dow_reg_errors.2886309505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3975281747 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 149380600 ps |
| CPU time | 23.52 seconds |
| Started | Aug 29 07:31:48 AM UTC 24 |
| Finished | Aug 29 07:32:13 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3975281747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3975281747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.223188396 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 975147800 ps |
| CPU time | 23.61 seconds |
| Started | Aug 29 07:31:33 AM UTC 24 |
| Finished | Aug 29 07:31:58 AM UTC 24 |
| Peak memory | 273532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223188396 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.223188396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3807839332 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 184676700 ps |
| CPU time | 27.68 seconds |
| Started | Aug 29 07:34:29 AM UTC 24 |
| Finished | Aug 29 07:34:58 AM UTC 24 |
| Peak memory | 288080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3807839332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3807839332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1144144385 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 50837800 ps |
| CPU time | 29.72 seconds |
| Started | Aug 29 07:34:26 AM UTC 24 |
| Finished | Aug 29 07:34:57 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144144385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.1144144385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2375704132 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 25300500 ps |
| CPU time | 25.25 seconds |
| Started | Aug 29 07:34:23 AM UTC 24 |
| Finished | Aug 29 07:34:49 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375704132 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.2375704132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3113562116 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 89126400 ps |
| CPU time | 33.49 seconds |
| Started | Aug 29 07:34:29 AM UTC 24 |
| Finished | Aug 29 07:35:04 AM UTC 24 |
| Peak memory | 271432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3113562116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _same_csr_outstanding.3113562116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1312894572 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 19693400 ps |
| CPU time | 26.12 seconds |
| Started | Aug 29 07:34:20 AM UTC 24 |
| Finished | Aug 29 07:34:48 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131 2894572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.1312894572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4063466482 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 14438500 ps |
| CPU time | 28.19 seconds |
| Started | Aug 29 07:34:20 AM UTC 24 |
| Finished | Aug 29 07:34:50 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4063466482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f lash_ctrl_shadow_reg_errors_with_csr_rw.4063466482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4009416629 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 342236000 ps |
| CPU time | 707.24 seconds |
| Started | Aug 29 07:34:19 AM UTC 24 |
| Finished | Aug 29 07:46:15 AM UTC 24 |
| Peak memory | 271504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009416629 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.4009416629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2682318271 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 23338200 ps |
| CPU time | 24.67 seconds |
| Started | Aug 29 07:34:39 AM UTC 24 |
| Finished | Aug 29 07:35:05 AM UTC 24 |
| Peak memory | 283920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2682318271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2682318271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.776132368 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 20348600 ps |
| CPU time | 25.8 seconds |
| Started | Aug 29 07:34:37 AM UTC 24 |
| Finished | Aug 29 07:35:05 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776132368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.776132368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1019135602 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 57194000 ps |
| CPU time | 25.52 seconds |
| Started | Aug 29 07:34:34 AM UTC 24 |
| Finished | Aug 29 07:35:01 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019135602 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.1019135602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1419826119 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 175527400 ps |
| CPU time | 34.45 seconds |
| Started | Aug 29 07:34:39 AM UTC 24 |
| Finished | Aug 29 07:35:15 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1419826119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.1419826119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1822704583 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 13315600 ps |
| CPU time | 21.13 seconds |
| Started | Aug 29 07:34:31 AM UTC 24 |
| Finished | Aug 29 07:34:54 AM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182 2704583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh adow_reg_errors.1822704583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4031911786 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 58517300 ps |
| CPU time | 21.69 seconds |
| Started | Aug 29 07:34:32 AM UTC 24 |
| Finished | Aug 29 07:34:55 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4031911786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f lash_ctrl_shadow_reg_errors_with_csr_rw.4031911786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3641554348 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 175555800 ps |
| CPU time | 23.4 seconds |
| Started | Aug 29 07:34:30 AM UTC 24 |
| Finished | Aug 29 07:34:55 AM UTC 24 |
| Peak memory | 273660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641554348 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.3641554348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3780305234 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 47973100 ps |
| CPU time | 29.19 seconds |
| Started | Aug 29 07:34:50 AM UTC 24 |
| Finished | Aug 29 07:35:21 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3780305234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3780305234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1656969265 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 179199300 ps |
| CPU time | 24.56 seconds |
| Started | Aug 29 07:34:49 AM UTC 24 |
| Finished | Aug 29 07:35:15 AM UTC 24 |
| Peak memory | 273496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656969265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.1656969265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2107563147 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 114745700 ps |
| CPU time | 26.26 seconds |
| Started | Aug 29 07:34:49 AM UTC 24 |
| Finished | Aug 29 07:35:17 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107563147 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.2107563147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2713236570 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 428985500 ps |
| CPU time | 33.03 seconds |
| Started | Aug 29 07:34:50 AM UTC 24 |
| Finished | Aug 29 07:35:25 AM UTC 24 |
| Peak memory | 273684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2713236570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl _same_csr_outstanding.2713236570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3609470243 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 38263500 ps |
| CPU time | 23.97 seconds |
| Started | Aug 29 07:34:43 AM UTC 24 |
| Finished | Aug 29 07:35:08 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360 9470243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh adow_reg_errors.3609470243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2235860547 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 14019300 ps |
| CPU time | 27.25 seconds |
| Started | Aug 29 07:34:48 AM UTC 24 |
| Finished | Aug 29 07:35:16 AM UTC 24 |
| Peak memory | 261200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2235860547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.2235860547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3298544017 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 63045500 ps |
| CPU time | 34.78 seconds |
| Started | Aug 29 07:34:41 AM UTC 24 |
| Finished | Aug 29 07:35:17 AM UTC 24 |
| Peak memory | 273532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298544017 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.3298544017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4077874542 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 965037500 ps |
| CPU time | 1268.61 seconds |
| Started | Aug 29 07:34:41 AM UTC 24 |
| Finished | Aug 29 07:56:04 AM UTC 24 |
| Peak memory | 273680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077874542 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.4077874542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3383375961 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 26508500 ps |
| CPU time | 26.17 seconds |
| Started | Aug 29 07:35:02 AM UTC 24 |
| Finished | Aug 29 07:35:29 AM UTC 24 |
| Peak memory | 273612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3383375961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3383375961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.579474471 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 452173400 ps |
| CPU time | 30.16 seconds |
| Started | Aug 29 07:34:59 AM UTC 24 |
| Finished | Aug 29 07:35:30 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579474471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.579474471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.534581677 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 15275300 ps |
| CPU time | 26.67 seconds |
| Started | Aug 29 07:34:59 AM UTC 24 |
| Finished | Aug 29 07:35:27 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534581677 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.534581677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.102286409 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 35150500 ps |
| CPU time | 23.34 seconds |
| Started | Aug 29 07:35:01 AM UTC 24 |
| Finished | Aug 29 07:35:25 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 102286409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ same_csr_outstanding.102286409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2116843729 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 40866600 ps |
| CPU time | 22.64 seconds |
| Started | Aug 29 07:34:55 AM UTC 24 |
| Finished | Aug 29 07:35:19 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211 6843729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh adow_reg_errors.2116843729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.377291344 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 13470900 ps |
| CPU time | 21.01 seconds |
| Started | Aug 29 07:34:56 AM UTC 24 |
| Finished | Aug 29 07:35:19 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=377291344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_shadow_reg_errors_with_csr_rw.377291344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3590627388 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 282521900 ps |
| CPU time | 650.34 seconds |
| Started | Aug 29 07:34:54 AM UTC 24 |
| Finished | Aug 29 07:45:53 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590627388 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.3590627388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2619309092 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 160088200 ps |
| CPU time | 30.93 seconds |
| Started | Aug 29 07:35:17 AM UTC 24 |
| Finished | Aug 29 07:35:50 AM UTC 24 |
| Peak memory | 283848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2619309092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2619309092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.607927492 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 407558800 ps |
| CPU time | 31.44 seconds |
| Started | Aug 29 07:35:16 AM UTC 24 |
| Finished | Aug 29 07:35:49 AM UTC 24 |
| Peak memory | 273364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607927492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.607927492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2347510973 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 50037300 ps |
| CPU time | 18.78 seconds |
| Started | Aug 29 07:35:15 AM UTC 24 |
| Finished | Aug 29 07:35:35 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347510973 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.2347510973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1258995677 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 181923800 ps |
| CPU time | 41.55 seconds |
| Started | Aug 29 07:35:16 AM UTC 24 |
| Finished | Aug 29 07:35:59 AM UTC 24 |
| Peak memory | 273480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1258995677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _same_csr_outstanding.1258995677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4099858655 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 18262000 ps |
| CPU time | 25.8 seconds |
| Started | Aug 29 07:35:06 AM UTC 24 |
| Finished | Aug 29 07:35:33 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409 9858655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.4099858655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3633574992 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 28304800 ps |
| CPU time | 21.93 seconds |
| Started | Aug 29 07:35:09 AM UTC 24 |
| Finished | Aug 29 07:35:32 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3633574992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f lash_ctrl_shadow_reg_errors_with_csr_rw.3633574992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2375668223 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 155415300 ps |
| CPU time | 30.07 seconds |
| Started | Aug 29 07:35:05 AM UTC 24 |
| Finished | Aug 29 07:35:36 AM UTC 24 |
| Peak memory | 273532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375668223 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.2375668223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2314566389 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1176775000 ps |
| CPU time | 1238.12 seconds |
| Started | Aug 29 07:35:06 AM UTC 24 |
| Finished | Aug 29 07:55:58 AM UTC 24 |
| Peak memory | 273548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314566389 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2314566389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2627856922 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 227491300 ps |
| CPU time | 32.12 seconds |
| Started | Aug 29 07:35:26 AM UTC 24 |
| Finished | Aug 29 07:35:59 AM UTC 24 |
| Peak memory | 283984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2627856922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2627856922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1554941321 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 64705600 ps |
| CPU time | 31.42 seconds |
| Started | Aug 29 07:35:22 AM UTC 24 |
| Finished | Aug 29 07:35:55 AM UTC 24 |
| Peak memory | 273560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554941321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.1554941321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1940123140 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 17300500 ps |
| CPU time | 19.06 seconds |
| Started | Aug 29 07:35:21 AM UTC 24 |
| Finished | Aug 29 07:35:41 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940123140 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.1940123140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.575893580 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 372896800 ps |
| CPU time | 31.93 seconds |
| Started | Aug 29 07:35:25 AM UTC 24 |
| Finished | Aug 29 07:35:58 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 575893580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ same_csr_outstanding.575893580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2514540904 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 15373500 ps |
| CPU time | 19.53 seconds |
| Started | Aug 29 07:35:20 AM UTC 24 |
| Finished | Aug 29 07:35:40 AM UTC 24 |
| Peak memory | 261260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251 4540904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh adow_reg_errors.2514540904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1199586162 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 11949800 ps |
| CPU time | 26.24 seconds |
| Started | Aug 29 07:35:20 AM UTC 24 |
| Finished | Aug 29 07:35:47 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1199586162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f lash_ctrl_shadow_reg_errors_with_csr_rw.1199586162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.860288051 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 122105500 ps |
| CPU time | 31.7 seconds |
| Started | Aug 29 07:35:18 AM UTC 24 |
| Finished | Aug 29 07:35:51 AM UTC 24 |
| Peak memory | 273460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860288051 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.860288051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2172337119 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 176737400 ps |
| CPU time | 779.32 seconds |
| Started | Aug 29 07:35:18 AM UTC 24 |
| Finished | Aug 29 07:48:26 AM UTC 24 |
| Peak memory | 273680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172337119 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.2172337119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2805732846 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 30729500 ps |
| CPU time | 25.93 seconds |
| Started | Aug 29 07:35:42 AM UTC 24 |
| Finished | Aug 29 07:36:09 AM UTC 24 |
| Peak memory | 283852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2805732846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2805732846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1100578142 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 432374500 ps |
| CPU time | 25.79 seconds |
| Started | Aug 29 07:35:36 AM UTC 24 |
| Finished | Aug 29 07:36:03 AM UTC 24 |
| Peak memory | 273560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100578142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.1100578142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1588284098 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 50025100 ps |
| CPU time | 17.65 seconds |
| Started | Aug 29 07:35:34 AM UTC 24 |
| Finished | Aug 29 07:35:53 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588284098 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.1588284098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1533856227 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 63059200 ps |
| CPU time | 48.08 seconds |
| Started | Aug 29 07:35:38 AM UTC 24 |
| Finished | Aug 29 07:36:27 AM UTC 24 |
| Peak memory | 271572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1533856227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _same_csr_outstanding.1533856227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.801561802 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 22384200 ps |
| CPU time | 28.28 seconds |
| Started | Aug 29 07:35:31 AM UTC 24 |
| Finished | Aug 29 07:36:01 AM UTC 24 |
| Peak memory | 261332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801 561802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sha dow_reg_errors.801561802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.292230165 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 14063500 ps |
| CPU time | 18.12 seconds |
| Started | Aug 29 07:35:33 AM UTC 24 |
| Finished | Aug 29 07:35:53 AM UTC 24 |
| Peak memory | 261200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=292230165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_shadow_reg_errors_with_csr_rw.292230165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1969097601 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 69049200 ps |
| CPU time | 32.83 seconds |
| Started | Aug 29 07:35:27 AM UTC 24 |
| Finished | Aug 29 07:36:01 AM UTC 24 |
| Peak memory | 273532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969097601 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.1969097601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2855575129 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2260477100 ps |
| CPU time | 499.99 seconds |
| Started | Aug 29 07:35:30 AM UTC 24 |
| Finished | Aug 29 07:43:56 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855575129 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.2855575129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1437839080 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 887943500 ps |
| CPU time | 34.57 seconds |
| Started | Aug 29 07:35:54 AM UTC 24 |
| Finished | Aug 29 07:36:30 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1437839080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1437839080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3598556503 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 124196600 ps |
| CPU time | 18.9 seconds |
| Started | Aug 29 07:35:52 AM UTC 24 |
| Finished | Aug 29 07:36:12 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598556503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.3598556503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1811775085 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 51154400 ps |
| CPU time | 25.68 seconds |
| Started | Aug 29 07:35:50 AM UTC 24 |
| Finished | Aug 29 07:36:17 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811775085 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.1811775085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.227380784 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 888954600 ps |
| CPU time | 36.11 seconds |
| Started | Aug 29 07:35:54 AM UTC 24 |
| Finished | Aug 29 07:36:31 AM UTC 24 |
| Peak memory | 273624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 227380784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ same_csr_outstanding.227380784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2206147313 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 13227500 ps |
| CPU time | 26.26 seconds |
| Started | Aug 29 07:35:48 AM UTC 24 |
| Finished | Aug 29 07:36:16 AM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220 6147313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh adow_reg_errors.2206147313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2039144655 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 39090400 ps |
| CPU time | 31.2 seconds |
| Started | Aug 29 07:35:50 AM UTC 24 |
| Finished | Aug 29 07:36:23 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2039144655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f lash_ctrl_shadow_reg_errors_with_csr_rw.2039144655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3226353250 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 215425100 ps |
| CPU time | 30.43 seconds |
| Started | Aug 29 07:35:42 AM UTC 24 |
| Finished | Aug 29 07:36:13 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226353250 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.3226353250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4132738570 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 1284272700 ps |
| CPU time | 1231.87 seconds |
| Started | Aug 29 07:35:45 AM UTC 24 |
| Finished | Aug 29 07:56:32 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132738570 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.4132738570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.664641343 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 27151200 ps |
| CPU time | 28.73 seconds |
| Started | Aug 29 07:36:02 AM UTC 24 |
| Finished | Aug 29 07:36:32 AM UTC 24 |
| Peak memory | 287940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=664641343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.664641343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1855533627 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 29205900 ps |
| CPU time | 24.95 seconds |
| Started | Aug 29 07:36:00 AM UTC 24 |
| Finished | Aug 29 07:36:26 AM UTC 24 |
| Peak memory | 273496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855533627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.1855533627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1823099591 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 44759500 ps |
| CPU time | 22.07 seconds |
| Started | Aug 29 07:36:00 AM UTC 24 |
| Finished | Aug 29 07:36:24 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823099591 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.1823099591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2023966574 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 321396000 ps |
| CPU time | 32.31 seconds |
| Started | Aug 29 07:36:01 AM UTC 24 |
| Finished | Aug 29 07:36:35 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2023966574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl _same_csr_outstanding.2023966574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3016567159 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 125745700 ps |
| CPU time | 21.7 seconds |
| Started | Aug 29 07:35:59 AM UTC 24 |
| Finished | Aug 29 07:36:22 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301 6567159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh adow_reg_errors.3016567159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2288923421 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 68421200 ps |
| CPU time | 28.86 seconds |
| Started | Aug 29 07:35:59 AM UTC 24 |
| Finished | Aug 29 07:36:29 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2288923421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f lash_ctrl_shadow_reg_errors_with_csr_rw.2288923421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2779029388 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 39252400 ps |
| CPU time | 18.72 seconds |
| Started | Aug 29 07:35:56 AM UTC 24 |
| Finished | Aug 29 07:36:16 AM UTC 24 |
| Peak memory | 273724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779029388 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.2779029388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2682814581 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 219606400 ps |
| CPU time | 26.39 seconds |
| Started | Aug 29 07:36:23 AM UTC 24 |
| Finished | Aug 29 07:36:51 AM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2682814581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2682814581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.598588136 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 41282500 ps |
| CPU time | 31.33 seconds |
| Started | Aug 29 07:36:17 AM UTC 24 |
| Finished | Aug 29 07:36:50 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598588136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.598588136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3993881108 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 15175900 ps |
| CPU time | 25.18 seconds |
| Started | Aug 29 07:36:17 AM UTC 24 |
| Finished | Aug 29 07:36:43 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993881108 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3993881108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.191983573 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 59257900 ps |
| CPU time | 25.92 seconds |
| Started | Aug 29 07:36:18 AM UTC 24 |
| Finished | Aug 29 07:36:45 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 191983573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ same_csr_outstanding.191983573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4251186101 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 14806400 ps |
| CPU time | 27.5 seconds |
| Started | Aug 29 07:36:13 AM UTC 24 |
| Finished | Aug 29 07:36:41 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425 1186101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.4251186101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.373858749 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 14616900 ps |
| CPU time | 18.03 seconds |
| Started | Aug 29 07:36:15 AM UTC 24 |
| Finished | Aug 29 07:36:34 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=373858749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_shadow_reg_errors_with_csr_rw.373858749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3960628586 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 79541100 ps |
| CPU time | 21.2 seconds |
| Started | Aug 29 07:36:03 AM UTC 24 |
| Finished | Aug 29 07:36:26 AM UTC 24 |
| Peak memory | 273724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960628586 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.3960628586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3388826806 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9043525000 ps |
| CPU time | 81.88 seconds |
| Started | Aug 29 07:32:28 AM UTC 24 |
| Finished | Aug 29 07:33:52 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388826806 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.3388826806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.888374929 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 416931200 ps |
| CPU time | 57.51 seconds |
| Started | Aug 29 07:32:15 AM UTC 24 |
| Finished | Aug 29 07:33:14 AM UTC 24 |
| Peak memory | 271632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888374929 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.888374929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3464183792 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 90862700 ps |
| CPU time | 27.17 seconds |
| Started | Aug 29 07:32:16 AM UTC 24 |
| Finished | Aug 29 07:32:45 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464183792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.3464183792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3106535968 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 21926200 ps |
| CPU time | 21.03 seconds |
| Started | Aug 29 07:32:14 AM UTC 24 |
| Finished | Aug 29 07:32:36 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106535968 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3106535968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1106407903 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 53087600 ps |
| CPU time | 26.16 seconds |
| Started | Aug 29 07:32:14 AM UTC 24 |
| Finished | Aug 29 07:32:42 AM UTC 24 |
| Peak memory | 271500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106407903 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.1106407903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4089270956 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 214172500 ps |
| CPU time | 33.53 seconds |
| Started | Aug 29 07:32:33 AM UTC 24 |
| Finished | Aug 29 07:33:08 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4089270956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.4089270956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1855332928 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 22348300 ps |
| CPU time | 22.55 seconds |
| Started | Aug 29 07:32:13 AM UTC 24 |
| Finished | Aug 29 07:32:37 AM UTC 24 |
| Peak memory | 261128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185 5332928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.1855332928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1786460623 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 51811300 ps |
| CPU time | 23.45 seconds |
| Started | Aug 29 07:32:14 AM UTC 24 |
| Finished | Aug 29 07:32:39 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1786460623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1786460623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2674336320 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 65442000 ps |
| CPU time | 31.24 seconds |
| Started | Aug 29 07:32:07 AM UTC 24 |
| Finished | Aug 29 07:32:39 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674336320 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2674336320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3974194652 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 697213900 ps |
| CPU time | 627.71 seconds |
| Started | Aug 29 07:32:10 AM UTC 24 |
| Finished | Aug 29 07:42:46 AM UTC 24 |
| Peak memory | 273556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974194652 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.3974194652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.249926629 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 63527000 ps |
| CPU time | 26.88 seconds |
| Started | Aug 29 07:36:24 AM UTC 24 |
| Finished | Aug 29 07:36:52 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249926629 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.249926629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.588208548 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 15960300 ps |
| CPU time | 25.59 seconds |
| Started | Aug 29 07:36:24 AM UTC 24 |
| Finished | Aug 29 07:36:51 AM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588208548 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.588208548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3194593664 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 24502600 ps |
| CPU time | 25.21 seconds |
| Started | Aug 29 07:36:26 AM UTC 24 |
| Finished | Aug 29 07:36:53 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194593664 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.3194593664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2547711483 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 26775800 ps |
| CPU time | 25.2 seconds |
| Started | Aug 29 07:36:27 AM UTC 24 |
| Finished | Aug 29 07:36:54 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547711483 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.2547711483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.754426794 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 36174400 ps |
| CPU time | 23.05 seconds |
| Started | Aug 29 07:36:28 AM UTC 24 |
| Finished | Aug 29 07:36:53 AM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754426794 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.754426794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.1799426817 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 29026100 ps |
| CPU time | 15.94 seconds |
| Started | Aug 29 07:36:30 AM UTC 24 |
| Finished | Aug 29 07:36:48 AM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799426817 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.1799426817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2767425057 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 41942600 ps |
| CPU time | 26.33 seconds |
| Started | Aug 29 07:36:30 AM UTC 24 |
| Finished | Aug 29 07:36:58 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767425057 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.2767425057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.4037861629 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 32209100 ps |
| CPU time | 25.14 seconds |
| Started | Aug 29 07:36:32 AM UTC 24 |
| Finished | Aug 29 07:36:58 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037861629 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.4037861629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1956372296 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 15969800 ps |
| CPU time | 24.46 seconds |
| Started | Aug 29 07:36:34 AM UTC 24 |
| Finished | Aug 29 07:36:59 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956372296 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.1956372296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2650681868 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 16770100 ps |
| CPU time | 23.19 seconds |
| Started | Aug 29 07:36:35 AM UTC 24 |
| Finished | Aug 29 07:36:59 AM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650681868 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.2650681868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1960469407 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1228910500 ps |
| CPU time | 36.86 seconds |
| Started | Aug 29 07:32:54 AM UTC 24 |
| Finished | Aug 29 07:33:32 AM UTC 24 |
| Peak memory | 271436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960469407 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1960469407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4275078986 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 670340300 ps |
| CPU time | 57.76 seconds |
| Started | Aug 29 07:32:46 AM UTC 24 |
| Finished | Aug 29 07:33:45 AM UTC 24 |
| Peak memory | 271436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275078986 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.4275078986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.856342582 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 54387500 ps |
| CPU time | 52.83 seconds |
| Started | Aug 29 07:32:44 AM UTC 24 |
| Finished | Aug 29 07:33:39 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856342582 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.856342582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4219202006 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 145986400 ps |
| CPU time | 33.33 seconds |
| Started | Aug 29 07:32:57 AM UTC 24 |
| Finished | Aug 29 07:33:34 AM UTC 24 |
| Peak memory | 284048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4219202006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.4219202006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1448513888 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 62235100 ps |
| CPU time | 29.01 seconds |
| Started | Aug 29 07:32:46 AM UTC 24 |
| Finished | Aug 29 07:33:16 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448513888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1448513888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3922910887 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 32545400 ps |
| CPU time | 27.49 seconds |
| Started | Aug 29 07:32:42 AM UTC 24 |
| Finished | Aug 29 07:33:11 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922910887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.3922910887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1904357161 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 28428000 ps |
| CPU time | 26.64 seconds |
| Started | Aug 29 07:32:40 AM UTC 24 |
| Finished | Aug 29 07:33:08 AM UTC 24 |
| Peak memory | 271632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904357161 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.1904357161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1288546288 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 151205400 ps |
| CPU time | 33.38 seconds |
| Started | Aug 29 07:32:55 AM UTC 24 |
| Finished | Aug 29 07:33:30 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1288546288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ same_csr_outstanding.1288546288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1688273592 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 23090200 ps |
| CPU time | 28.36 seconds |
| Started | Aug 29 07:32:37 AM UTC 24 |
| Finished | Aug 29 07:33:07 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168 8273592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha dow_reg_errors.1688273592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3279127427 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 14812900 ps |
| CPU time | 30.51 seconds |
| Started | Aug 29 07:32:38 AM UTC 24 |
| Finished | Aug 29 07:33:10 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3279127427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3279127427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1914124038 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 110379600 ps |
| CPU time | 28.87 seconds |
| Started | Aug 29 07:32:35 AM UTC 24 |
| Finished | Aug 29 07:33:05 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914124038 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1914124038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1124331735 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1373620700 ps |
| CPU time | 587.55 seconds |
| Started | Aug 29 07:32:37 AM UTC 24 |
| Finished | Aug 29 07:42:31 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124331735 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.1124331735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1779481318 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 28234100 ps |
| CPU time | 25.12 seconds |
| Started | Aug 29 07:36:36 AM UTC 24 |
| Finished | Aug 29 07:37:02 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779481318 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1779481318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.3335695755 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 42968400 ps |
| CPU time | 22.69 seconds |
| Started | Aug 29 07:36:42 AM UTC 24 |
| Finished | Aug 29 07:37:06 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335695755 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.3335695755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.823725753 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 59898600 ps |
| CPU time | 23.34 seconds |
| Started | Aug 29 07:36:44 AM UTC 24 |
| Finished | Aug 29 07:37:09 AM UTC 24 |
| Peak memory | 271416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823725753 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.823725753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.2312779909 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 53674100 ps |
| CPU time | 24.36 seconds |
| Started | Aug 29 07:36:46 AM UTC 24 |
| Finished | Aug 29 07:37:12 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312779909 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.2312779909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2480729196 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 56348700 ps |
| CPU time | 25.76 seconds |
| Started | Aug 29 07:36:48 AM UTC 24 |
| Finished | Aug 29 07:37:15 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480729196 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.2480729196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.3819080230 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 15626900 ps |
| CPU time | 24.83 seconds |
| Started | Aug 29 07:36:50 AM UTC 24 |
| Finished | Aug 29 07:37:16 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819080230 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.3819080230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.383479001 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 14735500 ps |
| CPU time | 24.1 seconds |
| Started | Aug 29 07:36:51 AM UTC 24 |
| Finished | Aug 29 07:37:17 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383479001 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.383479001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3467601712 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 21865000 ps |
| CPU time | 20.57 seconds |
| Started | Aug 29 07:36:52 AM UTC 24 |
| Finished | Aug 29 07:37:14 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467601712 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.3467601712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2493461541 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 31973700 ps |
| CPU time | 23.85 seconds |
| Started | Aug 29 07:36:53 AM UTC 24 |
| Finished | Aug 29 07:37:19 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493461541 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.2493461541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2810333618 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 95642500 ps |
| CPU time | 23.3 seconds |
| Started | Aug 29 07:36:53 AM UTC 24 |
| Finished | Aug 29 07:37:18 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810333618 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.2810333618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.904127809 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 2574258800 ps |
| CPU time | 71.53 seconds |
| Started | Aug 29 07:33:15 AM UTC 24 |
| Finished | Aug 29 07:34:29 AM UTC 24 |
| Peak memory | 271568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904127809 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.904127809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1662062824 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 1382883500 ps |
| CPU time | 78.68 seconds |
| Started | Aug 29 07:33:13 AM UTC 24 |
| Finished | Aug 29 07:34:33 AM UTC 24 |
| Peak memory | 271436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662062824 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.1662062824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.178402517 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 305128300 ps |
| CPU time | 47.51 seconds |
| Started | Aug 29 07:33:10 AM UTC 24 |
| Finished | Aug 29 07:34:00 AM UTC 24 |
| Peak memory | 271432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178402517 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.178402517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4032688319 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 84728300 ps |
| CPU time | 30.4 seconds |
| Started | Aug 29 07:33:17 AM UTC 24 |
| Finished | Aug 29 07:33:49 AM UTC 24 |
| Peak memory | 283984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4032688319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.4032688319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.893522399 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 136282900 ps |
| CPU time | 27.15 seconds |
| Started | Aug 29 07:33:11 AM UTC 24 |
| Finished | Aug 29 07:33:40 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893522399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.893522399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2882536575 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 29817100 ps |
| CPU time | 18.26 seconds |
| Started | Aug 29 07:33:09 AM UTC 24 |
| Finished | Aug 29 07:33:29 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882536575 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2882536575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2139104981 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 158367900 ps |
| CPU time | 24.01 seconds |
| Started | Aug 29 07:33:10 AM UTC 24 |
| Finished | Aug 29 07:33:36 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139104981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.2139104981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.217060922 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 109694100 ps |
| CPU time | 24.86 seconds |
| Started | Aug 29 07:33:09 AM UTC 24 |
| Finished | Aug 29 07:33:35 AM UTC 24 |
| Peak memory | 271632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217060922 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.217060922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.813914845 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 88196900 ps |
| CPU time | 23.71 seconds |
| Started | Aug 29 07:33:15 AM UTC 24 |
| Finished | Aug 29 07:33:40 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 813914845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_s ame_csr_outstanding.813914845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.877108562 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 33995800 ps |
| CPU time | 26.52 seconds |
| Started | Aug 29 07:33:07 AM UTC 24 |
| Finished | Aug 29 07:33:35 AM UTC 24 |
| Peak memory | 261144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877 108562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shad ow_reg_errors.877108562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1892701946 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 36422600 ps |
| CPU time | 22.37 seconds |
| Started | Aug 29 07:33:08 AM UTC 24 |
| Finished | Aug 29 07:33:32 AM UTC 24 |
| Peak memory | 261128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1892701946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1892701946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.884599627 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3477076700 ps |
| CPU time | 1105.52 seconds |
| Started | Aug 29 07:33:06 AM UTC 24 |
| Finished | Aug 29 07:51:44 AM UTC 24 |
| Peak memory | 273556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884599627 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.884599627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.317440233 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 25070600 ps |
| CPU time | 26.01 seconds |
| Started | Aug 29 07:36:53 AM UTC 24 |
| Finished | Aug 29 07:37:21 AM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317440233 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.317440233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3951192581 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 14343000 ps |
| CPU time | 26.63 seconds |
| Started | Aug 29 07:36:55 AM UTC 24 |
| Finished | Aug 29 07:37:23 AM UTC 24 |
| Peak memory | 271548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951192581 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.3951192581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3331177195 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 53574900 ps |
| CPU time | 20.96 seconds |
| Started | Aug 29 07:36:59 AM UTC 24 |
| Finished | Aug 29 07:37:21 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331177195 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.3331177195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2535674551 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 16589300 ps |
| CPU time | 19.8 seconds |
| Started | Aug 29 07:36:59 AM UTC 24 |
| Finished | Aug 29 07:37:20 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535674551 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.2535674551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.866565401 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 29925700 ps |
| CPU time | 21.15 seconds |
| Started | Aug 29 07:37:00 AM UTC 24 |
| Finished | Aug 29 07:37:22 AM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866565401 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.866565401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.4190291067 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 57668600 ps |
| CPU time | 21.98 seconds |
| Started | Aug 29 07:37:00 AM UTC 24 |
| Finished | Aug 29 07:37:23 AM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190291067 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.4190291067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.3863270250 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 14885000 ps |
| CPU time | 25.49 seconds |
| Started | Aug 29 07:37:03 AM UTC 24 |
| Finished | Aug 29 07:37:30 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863270250 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.3863270250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.754390744 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 42732400 ps |
| CPU time | 25.82 seconds |
| Started | Aug 29 07:37:07 AM UTC 24 |
| Finished | Aug 29 07:37:34 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754390744 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.754390744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2244570329 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 17833000 ps |
| CPU time | 24.6 seconds |
| Started | Aug 29 07:37:09 AM UTC 24 |
| Finished | Aug 29 07:37:35 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244570329 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.2244570329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3878818585 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 16518300 ps |
| CPU time | 18.85 seconds |
| Started | Aug 29 07:37:12 AM UTC 24 |
| Finished | Aug 29 07:37:32 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878818585 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.3878818585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1553973442 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 115859000 ps |
| CPU time | 31.1 seconds |
| Started | Aug 29 07:33:33 AM UTC 24 |
| Finished | Aug 29 07:34:06 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553973442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.1553973442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.823236064 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 111673800 ps |
| CPU time | 21.29 seconds |
| Started | Aug 29 07:33:33 AM UTC 24 |
| Finished | Aug 29 07:33:56 AM UTC 24 |
| Peak memory | 271420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823236064 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.823236064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2875065475 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 707206600 ps |
| CPU time | 36.4 seconds |
| Started | Aug 29 07:33:33 AM UTC 24 |
| Finished | Aug 29 07:34:11 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2875065475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ same_csr_outstanding.2875065475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2521521112 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 39308200 ps |
| CPU time | 25.22 seconds |
| Started | Aug 29 07:33:30 AM UTC 24 |
| Finished | Aug 29 07:33:56 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252 1521112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha dow_reg_errors.2521521112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2661151052 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 39476800 ps |
| CPU time | 23.95 seconds |
| Started | Aug 29 07:33:31 AM UTC 24 |
| Finished | Aug 29 07:33:56 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2661151052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2661151052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.545667557 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 118818000 ps |
| CPU time | 33.86 seconds |
| Started | Aug 29 07:33:19 AM UTC 24 |
| Finished | Aug 29 07:33:54 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545667557 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.545667557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4116552099 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 989112800 ps |
| CPU time | 24.9 seconds |
| Started | Aug 29 07:33:41 AM UTC 24 |
| Finished | Aug 29 07:34:07 AM UTC 24 |
| Peak memory | 283852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4116552099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.4116552099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.135782106 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 42341600 ps |
| CPU time | 29.44 seconds |
| Started | Aug 29 07:33:39 AM UTC 24 |
| Finished | Aug 29 07:34:09 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135782106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.135782106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.3806952266 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 38740700 ps |
| CPU time | 27.19 seconds |
| Started | Aug 29 07:33:37 AM UTC 24 |
| Finished | Aug 29 07:34:05 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806952266 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3806952266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1334714194 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 335567300 ps |
| CPU time | 33.71 seconds |
| Started | Aug 29 07:33:40 AM UTC 24 |
| Finished | Aug 29 07:34:15 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1334714194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ same_csr_outstanding.1334714194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.70850629 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 20928800 ps |
| CPU time | 17.22 seconds |
| Started | Aug 29 07:33:35 AM UTC 24 |
| Finished | Aug 29 07:33:54 AM UTC 24 |
| Peak memory | 261272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708 50629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shado w_reg_errors.70850629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3270102807 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 12222300 ps |
| CPU time | 30.07 seconds |
| Started | Aug 29 07:33:36 AM UTC 24 |
| Finished | Aug 29 07:34:08 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3270102807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3270102807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4000880883 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 59253700 ps |
| CPU time | 31.78 seconds |
| Started | Aug 29 07:33:34 AM UTC 24 |
| Finished | Aug 29 07:34:08 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000880883 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.4000880883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2359280851 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 231075800 ps |
| CPU time | 20.95 seconds |
| Started | Aug 29 07:33:56 AM UTC 24 |
| Finished | Aug 29 07:34:19 AM UTC 24 |
| Peak memory | 288080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2359280851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2359280851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3077235082 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 166354700 ps |
| CPU time | 23.32 seconds |
| Started | Aug 29 07:33:54 AM UTC 24 |
| Finished | Aug 29 07:34:19 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077235082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.3077235082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1992195588 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 51983300 ps |
| CPU time | 24.72 seconds |
| Started | Aug 29 07:33:52 AM UTC 24 |
| Finished | Aug 29 07:34:18 AM UTC 24 |
| Peak memory | 271540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992195588 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1992195588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3117730396 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 134624300 ps |
| CPU time | 28.63 seconds |
| Started | Aug 29 07:33:55 AM UTC 24 |
| Finished | Aug 29 07:34:25 AM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3117730396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ same_csr_outstanding.3117730396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3716297941 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 44580700 ps |
| CPU time | 27.32 seconds |
| Started | Aug 29 07:33:46 AM UTC 24 |
| Finished | Aug 29 07:34:15 AM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371 6297941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha dow_reg_errors.3716297941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2834834254 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 67681000 ps |
| CPU time | 23.64 seconds |
| Started | Aug 29 07:33:49 AM UTC 24 |
| Finished | Aug 29 07:34:14 AM UTC 24 |
| Peak memory | 261128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2834834254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2834834254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2659421225 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 113381300 ps |
| CPU time | 23.93 seconds |
| Started | Aug 29 07:33:41 AM UTC 24 |
| Finished | Aug 29 07:34:06 AM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659421225 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2659421225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1135754208 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 369081900 ps |
| CPU time | 28.56 seconds |
| Started | Aug 29 07:34:07 AM UTC 24 |
| Finished | Aug 29 07:34:37 AM UTC 24 |
| Peak memory | 283984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1135754208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1135754208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3684791197 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 137438000 ps |
| CPU time | 30.8 seconds |
| Started | Aug 29 07:34:06 AM UTC 24 |
| Finished | Aug 29 07:34:38 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684791197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.3684791197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.855835448 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 26822700 ps |
| CPU time | 26.47 seconds |
| Started | Aug 29 07:34:03 AM UTC 24 |
| Finished | Aug 29 07:34:31 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855835448 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.855835448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1883174750 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 722111700 ps |
| CPU time | 45.45 seconds |
| Started | Aug 29 07:34:07 AM UTC 24 |
| Finished | Aug 29 07:34:54 AM UTC 24 |
| Peak memory | 273620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1883174750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.1883174750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.544506179 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 54437700 ps |
| CPU time | 15.79 seconds |
| Started | Aug 29 07:34:00 AM UTC 24 |
| Finished | Aug 29 07:34:17 AM UTC 24 |
| Peak memory | 261276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544 506179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shad ow_reg_errors.544506179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3999448823 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 13139800 ps |
| CPU time | 26.75 seconds |
| Started | Aug 29 07:34:01 AM UTC 24 |
| Finished | Aug 29 07:34:29 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3999448823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3999448823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3526582706 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 33439700 ps |
| CPU time | 29.25 seconds |
| Started | Aug 29 07:33:58 AM UTC 24 |
| Finished | Aug 29 07:34:28 AM UTC 24 |
| Peak memory | 273524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526582706 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3526582706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3835575878 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 525497800 ps |
| CPU time | 705.85 seconds |
| Started | Aug 29 07:33:58 AM UTC 24 |
| Finished | Aug 29 07:45:52 AM UTC 24 |
| Peak memory | 273620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835575878 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.3835575878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.524597405 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 139826200 ps |
| CPU time | 20.15 seconds |
| Started | Aug 29 07:34:16 AM UTC 24 |
| Finished | Aug 29 07:34:37 AM UTC 24 |
| Peak memory | 287952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=524597405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.524597405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1671827069 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 52703200 ps |
| CPU time | 23.82 seconds |
| Started | Aug 29 07:34:15 AM UTC 24 |
| Finished | Aug 29 07:34:40 AM UTC 24 |
| Peak memory | 273488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671827069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.1671827069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.3838430543 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 17569000 ps |
| CPU time | 17.55 seconds |
| Started | Aug 29 07:34:11 AM UTC 24 |
| Finished | Aug 29 07:34:30 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838430543 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3838430543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.894836505 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 789573900 ps |
| CPU time | 24.92 seconds |
| Started | Aug 29 07:34:16 AM UTC 24 |
| Finished | Aug 29 07:34:42 AM UTC 24 |
| Peak memory | 273496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 894836505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_s ame_csr_outstanding.894836505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1561267528 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 11512100 ps |
| CPU time | 17.09 seconds |
| Started | Aug 29 07:34:09 AM UTC 24 |
| Finished | Aug 29 07:34:28 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156 1267528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.1561267528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4293759283 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 27755400 ps |
| CPU time | 28.25 seconds |
| Started | Aug 29 07:34:10 AM UTC 24 |
| Finished | Aug 29 07:34:40 AM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4293759283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl ash_ctrl_shadow_reg_errors_with_csr_rw.4293759283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3462398604 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 967509600 ps |
| CPU time | 1217.9 seconds |
| Started | Aug 29 07:34:08 AM UTC 24 |
| Finished | Aug 29 07:54:40 AM UTC 24 |
| Peak memory | 273556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462398604 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.3462398604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1654936065 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 127305400 ps |
| CPU time | 28.5 seconds |
| Started | Aug 29 09:40:43 AM UTC 24 |
| Finished | Aug 29 09:41:13 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654936065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1654936065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.595018293 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 726220700 ps |
| CPU time | 207.98 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:43:48 AM UTC 24 |
| Peak memory | 289780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=595018293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_derr_detect.595018293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.518017523 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3488721900 ps |
| CPU time | 659.8 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 09:51:20 AM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518017523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.518017523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2296113221 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 658886900 ps |
| CPU time | 61.5 seconds |
| Started | Aug 29 09:41:01 AM UTC 24 |
| Finished | Aug 29 09:42:04 AM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296113 221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f s_sup.2296113221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.36695169 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 96891124400 ps |
| CPU time | 2625.09 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 10:24:28 AM UTC 24 |
| Peak memory | 277952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36695169 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.36695169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3841474442 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 27154900 ps |
| CPU time | 54.47 seconds |
| Started | Aug 29 09:41:37 AM UTC 24 |
| Finished | Aug 29 09:42:33 AM UTC 24 |
| Peak memory | 285844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384147444 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.3841474442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.387649147 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 241779707000 ps |
| CPU time | 3330.66 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 10:36:19 AM UTC 24 |
| Peak memory | 278188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387649147 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.387649147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.61732649 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 72510500 ps |
| CPU time | 90.12 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:41:44 AM UTC 24 |
| Peak memory | 273288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61732649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.61732649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1998859227 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 167506555800 ps |
| CPU time | 1988.44 seconds |
| Started | Aug 29 09:40:13 AM UTC 24 |
| Finished | Aug 29 10:13:44 AM UTC 24 |
| Peak memory | 277884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998859227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.1998859227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3988028647 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3590455000 ps |
| CPU time | 479.84 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:48:23 AM UTC 24 |
| Peak memory | 328896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3988028647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr ity.3988028647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.2254312722 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1379921400 ps |
| CPU time | 180.85 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:43:21 AM UTC 24 |
| Peak memory | 306192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254312722 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.2254312722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2858187078 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 91012907600 ps |
| CPU time | 371.16 seconds |
| Started | Aug 29 09:40:22 AM UTC 24 |
| Finished | Aug 29 09:46:39 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858187078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2858187078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1819029427 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 26364800 ps |
| CPU time | 27.87 seconds |
| Started | Aug 29 09:41:19 AM UTC 24 |
| Finished | Aug 29 09:41:49 AM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1819029427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.1819029427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2460680352 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1652212000 ps |
| CPU time | 112.16 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:42:09 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460680352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2460680352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2187376104 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2178637100 ps |
| CPU time | 208.56 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:43:49 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2187376104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2187376104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.1406152470 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 15291900 ps |
| CPU time | 26.88 seconds |
| Started | Aug 29 09:41:14 AM UTC 24 |
| Finished | Aug 29 09:41:43 AM UTC 24 |
| Peak memory | 293264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406152470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1406152470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.2812926101 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4049297400 ps |
| CPU time | 632.51 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:50:51 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812926101 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2812926101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1470655131 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1936719900 ps |
| CPU time | 185.89 seconds |
| Started | Aug 29 09:40:22 AM UTC 24 |
| Finished | Aug 29 09:43:31 AM UTC 24 |
| Peak memory | 271404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470655131 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.1470655131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1352729140 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3341229900 ps |
| CPU time | 166.04 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:43:00 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352729140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1352729140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2388306080 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 209508700 ps |
| CPU time | 54.45 seconds |
| Started | Aug 29 09:40:43 AM UTC 24 |
| Finished | Aug 29 09:41:40 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238830608 0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.2388306080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2106301912 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 37156400 ps |
| CPU time | 84.39 seconds |
| Started | Aug 29 09:41:34 AM UTC 24 |
| Finished | Aug 29 09:43:00 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106301912 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.2106301912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1119690730 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 122155300 ps |
| CPU time | 26.34 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:40:42 AM UTC 24 |
| Peak memory | 269296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119690730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1119690730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.1731490308 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 33678800 ps |
| CPU time | 25.71 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:40:42 AM UTC 24 |
| Peak memory | 275724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1731490308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_read_word_sweep_derr.1731490308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.1540892587 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 23062200 ps |
| CPU time | 36.04 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:40:52 AM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540892587 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.1540892587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.470866617 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 200890508400 ps |
| CPU time | 1080.69 seconds |
| Started | Aug 29 09:41:17 AM UTC 24 |
| Finished | Aug 29 09:59:30 AM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=470866617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.f lash_ctrl_rma_err.470866617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2232478293 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 559549000 ps |
| CPU time | 116.7 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:42:14 AM UTC 24 |
| Peak memory | 304124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2232478293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.2232478293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.2698650148 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2123700000 ps |
| CPU time | 143 seconds |
| Started | Aug 29 09:40:17 AM UTC 24 |
| Finished | Aug 29 09:42:43 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698650148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2698650148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.2469068538 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6907790300 ps |
| CPU time | 262.94 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:44:42 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2469068538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.2469068538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1324856420 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5360615500 ps |
| CPU time | 7074.19 seconds |
| Started | Aug 29 09:40:38 AM UTC 24 |
| Finished | Aug 29 11:39:48 AM UTC 24 |
| Peak memory | 314508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324856420 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1324856420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1625369065 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1932621900 ps |
| CPU time | 108.02 seconds |
| Started | Aug 29 09:40:40 AM UTC 24 |
| Finished | Aug 29 09:42:31 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625369065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1625369065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.4292503575 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2390981500 ps |
| CPU time | 85.76 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:41:43 AM UTC 24 |
| Peak memory | 275708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429 2503575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.4292503575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.1651704293 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1299923200 ps |
| CPU time | 105.19 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:42:03 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 51704293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se rr_counter.1651704293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.688961313 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 72115800 ps |
| CPU time | 157.06 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:42:51 AM UTC 24 |
| Peak memory | 287624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688961313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.688961313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3941450978 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 50993400 ps |
| CPU time | 27.74 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:40:40 AM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941450978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3941450978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2884882386 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 207453900 ps |
| CPU time | 1825.16 seconds |
| Started | Aug 29 09:40:41 AM UTC 24 |
| Finished | Aug 29 10:11:27 AM UTC 24 |
| Peak memory | 308772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884882386 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.2884882386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2074753704 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 41661500 ps |
| CPU time | 47.24 seconds |
| Started | Aug 29 09:40:11 AM UTC 24 |
| Finished | Aug 29 09:41:00 AM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074753704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2074753704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2060500478 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4979404500 ps |
| CPU time | 194.86 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:43:33 AM UTC 24 |
| Peak memory | 271496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2060500478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.2060500478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2038521472 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 39860900 ps |
| CPU time | 21.57 seconds |
| Started | Aug 29 09:40:15 AM UTC 24 |
| Finished | Aug 29 09:40:38 AM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038521472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2038521472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.44167751 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 54672900 ps |
| CPU time | 27.48 seconds |
| Started | Aug 29 09:46:08 AM UTC 24 |
| Finished | Aug 29 09:46:37 AM UTC 24 |
| Peak memory | 269504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44167751 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.44167751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.4029776856 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 33156200 ps |
| CPU time | 27.07 seconds |
| Started | Aug 29 09:45:51 AM UTC 24 |
| Finished | Aug 29 09:46:20 AM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029776856 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.4029776856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2694151513 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 101607800 ps |
| CPU time | 20.75 seconds |
| Started | Aug 29 09:45:28 AM UTC 24 |
| Finished | Aug 29 09:45:50 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694151513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2694151513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.260415553 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 6791955100 ps |
| CPU time | 225.46 seconds |
| Started | Aug 29 09:43:49 AM UTC 24 |
| Finished | Aug 29 09:47:37 AM UTC 24 |
| Peak memory | 289780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=260415553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_derr_detect.260415553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.1930124054 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10707705200 ps |
| CPU time | 3122.61 seconds |
| Started | Aug 29 09:42:35 AM UTC 24 |
| Finished | Aug 29 10:35:10 AM UTC 24 |
| Peak memory | 276192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930124054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.1930124054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2508421503 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2631914300 ps |
| CPU time | 2522.42 seconds |
| Started | Aug 29 09:42:34 AM UTC 24 |
| Finished | Aug 29 10:25:02 AM UTC 24 |
| Peak memory | 278068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 08421503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _error_prog_type.2508421503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2301240615 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1730602700 ps |
| CPU time | 1099.68 seconds |
| Started | Aug 29 09:42:34 AM UTC 24 |
| Finished | Aug 29 10:01:07 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301240615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2301240615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4068482371 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 529449600 ps |
| CPU time | 26.97 seconds |
| Started | Aug 29 09:42:23 AM UTC 24 |
| Finished | Aug 29 09:42:52 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 68482371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc h_code.4068482371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.3222597746 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 93151159600 ps |
| CPU time | 2613.89 seconds |
| Started | Aug 29 09:42:31 AM UTC 24 |
| Finished | Aug 29 10:26:35 AM UTC 24 |
| Peak memory | 276096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222597746 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.3222597746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.3928666912 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 182038200 ps |
| CPU time | 53.25 seconds |
| Started | Aug 29 09:46:04 AM UTC 24 |
| Finished | Aug 29 09:46:59 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392866691 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho st_addr_infection.3928666912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2540289148 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 297984146500 ps |
| CPU time | 3279.79 seconds |
| Started | Aug 29 09:42:15 AM UTC 24 |
| Finished | Aug 29 10:37:30 AM UTC 24 |
| Peak memory | 278260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540289148 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.2540289148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3866063647 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 22044400 ps |
| CPU time | 35.07 seconds |
| Started | Aug 29 09:41:44 AM UTC 24 |
| Finished | Aug 29 09:42:21 AM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866063647 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3866063647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2612931883 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 147890393600 ps |
| CPU time | 2095.72 seconds |
| Started | Aug 29 09:42:05 AM UTC 24 |
| Finished | Aug 29 10:17:26 AM UTC 24 |
| Peak memory | 277952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612931883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2612931883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3684869696 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 11931595400 ps |
| CPU time | 583.81 seconds |
| Started | Aug 29 09:44:01 AM UTC 24 |
| Finished | Aug 29 09:53:52 AM UTC 24 |
| Peak memory | 336912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3684869696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr ity.3684869696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.985561024 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1379550500 ps |
| CPU time | 187.25 seconds |
| Started | Aug 29 09:44:08 AM UTC 24 |
| Finished | Aug 29 09:47:18 AM UTC 24 |
| Peak memory | 306156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985561024 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.985561024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.461629469 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 11737596300 ps |
| CPU time | 286.42 seconds |
| Started | Aug 29 09:44:21 AM UTC 24 |
| Finished | Aug 29 09:49:12 AM UTC 24 |
| Peak memory | 302020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=461629469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_rd_slow_flash.461629469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.2752718494 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2474265700 ps |
| CPU time | 100.37 seconds |
| Started | Aug 29 09:44:16 AM UTC 24 |
| Finished | Aug 29 09:45:59 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752718494 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.2752718494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.392980507 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 23346368100 ps |
| CPU time | 309.15 seconds |
| Started | Aug 29 09:44:38 AM UTC 24 |
| Finished | Aug 29 09:49:52 AM UTC 24 |
| Peak memory | 275368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392980507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.392980507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.1324375283 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1015488200 ps |
| CPU time | 126.38 seconds |
| Started | Aug 29 09:42:44 AM UTC 24 |
| Finished | Aug 29 09:44:53 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324375283 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1324375283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.4292360835 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 28149200 ps |
| CPU time | 26.84 seconds |
| Started | Aug 29 09:45:53 AM UTC 24 |
| Finished | Aug 29 09:46:22 AM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4292360835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_lcmgr_intg.4292360835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3973503029 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1880295100 ps |
| CPU time | 172.29 seconds |
| Started | Aug 29 09:42:22 AM UTC 24 |
| Finished | Aug 29 09:45:17 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3973503029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3973503029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1575426634 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 74427100 ps |
| CPU time | 234.2 seconds |
| Started | Aug 29 09:42:10 AM UTC 24 |
| Finished | Aug 29 09:46:08 AM UTC 24 |
| Peak memory | 271280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575426634 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1575426634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.3364394626 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 26321800 ps |
| CPU time | 25.58 seconds |
| Started | Aug 29 09:45:47 AM UTC 24 |
| Finished | Aug 29 09:46:14 AM UTC 24 |
| Peak memory | 293292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364394626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3364394626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.362109564 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 7956880300 ps |
| CPU time | 549.72 seconds |
| Started | Aug 29 09:41:48 AM UTC 24 |
| Finished | Aug 29 09:51:05 AM UTC 24 |
| Peak memory | 273552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362109564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.362109564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.650925679 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 928784700 ps |
| CPU time | 22.84 seconds |
| Started | Aug 29 09:45:45 AM UTC 24 |
| Finished | Aug 29 09:46:09 AM UTC 24 |
| Peak memory | 275624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=650925679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.650925679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.681835856 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 40996500 ps |
| CPU time | 24.39 seconds |
| Started | Aug 29 09:45:47 AM UTC 24 |
| Finished | Aug 29 09:46:13 AM UTC 24 |
| Peak memory | 275796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=681835856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.681835856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.3823938442 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 60263900 ps |
| CPU time | 28.45 seconds |
| Started | Aug 29 09:44:43 AM UTC 24 |
| Finished | Aug 29 09:45:13 AM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823938442 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.3823938442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2728657226 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1364114100 ps |
| CPU time | 1491.44 seconds |
| Started | Aug 29 09:41:42 AM UTC 24 |
| Finished | Aug 29 10:06:50 AM UTC 24 |
| Peak memory | 294868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728657226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2728657226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.4165306193 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3341855600 ps |
| CPU time | 178.83 seconds |
| Started | Aug 29 09:41:44 AM UTC 24 |
| Finished | Aug 29 09:44:46 AM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165306193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4165306193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.3369282368 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 112858200 ps |
| CPU time | 40.03 seconds |
| Started | Aug 29 09:45:29 AM UTC 24 |
| Finished | Aug 29 09:46:11 AM UTC 24 |
| Peak memory | 285880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336928236 8 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.3369282368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1745342989 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 165029700 ps |
| CPU time | 55.05 seconds |
| Started | Aug 29 09:44:56 AM UTC 24 |
| Finished | Aug 29 09:45:53 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745342989 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.1745342989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.239831925 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 18232500 ps |
| CPU time | 40.39 seconds |
| Started | Aug 29 09:43:33 AM UTC 24 |
| Finished | Aug 29 09:44:15 AM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=239831925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_read_word_sweep_derr.239831925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.1149089172 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 75874000 ps |
| CPU time | 36.5 seconds |
| Started | Aug 29 09:43:01 AM UTC 24 |
| Finished | Aug 29 09:43:38 AM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149089172 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.1149089172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.1696492227 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 525851700 ps |
| CPU time | 119.88 seconds |
| Started | Aug 29 09:42:54 AM UTC 24 |
| Finished | Aug 29 09:44:56 AM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1696492227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.1696492227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3325769922 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 650033500 ps |
| CPU time | 185.24 seconds |
| Started | Aug 29 09:43:35 AM UTC 24 |
| Finished | Aug 29 09:46:44 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325769922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3325769922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3206477426 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 640971400 ps |
| CPU time | 162.08 seconds |
| Started | Aug 29 09:43:01 AM UTC 24 |
| Finished | Aug 29 09:45:45 AM UTC 24 |
| Peak memory | 306360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3206477426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_ro_serr.3206477426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.1123299914 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7319036700 ps |
| CPU time | 455.88 seconds |
| Started | Aug 29 09:42:54 AM UTC 24 |
| Finished | Aug 29 09:50:36 AM UTC 24 |
| Peak memory | 320436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123299914 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.1123299914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.64331102 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5748907800 ps |
| CPU time | 251.9 seconds |
| Started | Aug 29 09:43:40 AM UTC 24 |
| Finished | Aug 29 09:47:55 AM UTC 24 |
| Peak memory | 297972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=64331102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_rw_derr.64331102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1790898803 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 28959200 ps |
| CPU time | 42.93 seconds |
| Started | Aug 29 09:44:54 AM UTC 24 |
| Finished | Aug 29 09:45:38 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1790898803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.1790898803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.780957423 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 11055211500 ps |
| CPU time | 247.52 seconds |
| Started | Aug 29 09:43:19 AM UTC 24 |
| Finished | Aug 29 09:47:31 AM UTC 24 |
| Peak memory | 306428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=780957423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.780957423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3081449203 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2175200400 ps |
| CPU time | 6750.28 seconds |
| Started | Aug 29 09:45:01 AM UTC 24 |
| Finished | Aug 29 11:38:41 AM UTC 24 |
| Peak memory | 312440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081449203 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3081449203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1176233659 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5351139700 ps |
| CPU time | 101.94 seconds |
| Started | Aug 29 09:45:14 AM UTC 24 |
| Finished | Aug 29 09:46:58 AM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176233659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1176233659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3294738995 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1323264200 ps |
| CPU time | 62.97 seconds |
| Started | Aug 29 09:43:32 AM UTC 24 |
| Finished | Aug 29 09:44:37 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329 4738995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser r_address.3294738995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1456274222 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1961453000 ps |
| CPU time | 121.26 seconds |
| Started | Aug 29 09:43:22 AM UTC 24 |
| Finished | Aug 29 09:45:26 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14 56274222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.1456274222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3457495166 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 212417900 ps |
| CPU time | 110.32 seconds |
| Started | Aug 29 09:41:42 AM UTC 24 |
| Finished | Aug 29 09:43:35 AM UTC 24 |
| Peak memory | 287620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457495166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3457495166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3986805794 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15333600 ps |
| CPU time | 48.8 seconds |
| Started | Aug 29 09:41:42 AM UTC 24 |
| Finished | Aug 29 09:42:33 AM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986805794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3986805794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2284709174 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1158497600 ps |
| CPU time | 1578.33 seconds |
| Started | Aug 29 09:45:19 AM UTC 24 |
| Finished | Aug 29 10:11:54 AM UTC 24 |
| Peak memory | 301896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284709174 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.2284709174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1710764980 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 79191400 ps |
| CPU time | 48.6 seconds |
| Started | Aug 29 09:41:43 AM UTC 24 |
| Finished | Aug 29 09:42:33 AM UTC 24 |
| Peak memory | 271244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710764980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1710764980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.3306100882 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3434356900 ps |
| CPU time | 168.43 seconds |
| Started | Aug 29 09:42:54 AM UTC 24 |
| Finished | Aug 29 09:45:46 AM UTC 24 |
| Peak memory | 271240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3306100882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.3306100882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.3980418160 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 305201700 ps |
| CPU time | 22.05 seconds |
| Started | Aug 29 09:45:29 AM UTC 24 |
| Finished | Aug 29 09:45:52 AM UTC 24 |
| Peak memory | 271572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980418160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.3980418160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.49403413 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 171331000 ps |
| CPU time | 18.77 seconds |
| Started | Aug 29 10:20:55 AM UTC 24 |
| Finished | Aug 29 10:21:15 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49403413 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.49403413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2700298571 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 23421600 ps |
| CPU time | 20.97 seconds |
| Started | Aug 29 10:20:45 AM UTC 24 |
| Finished | Aug 29 10:21:07 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700298571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2700298571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.883196223 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 24528700 ps |
| CPU time | 34.06 seconds |
| Started | Aug 29 10:20:36 AM UTC 24 |
| Finished | Aug 29 10:21:12 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=883196223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_disable.883196223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2342518616 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 47138700 ps |
| CPU time | 23.77 seconds |
| Started | Aug 29 10:20:51 AM UTC 24 |
| Finished | Aug 29 10:21:16 AM UTC 24 |
| Peak memory | 269508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2342518616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2342518616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3974632738 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3242496800 ps |
| CPU time | 227.48 seconds |
| Started | Aug 29 10:19:09 AM UTC 24 |
| Finished | Aug 29 10:23:00 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974632738 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.3974632738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3466609087 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1606551900 ps |
| CPU time | 256.6 seconds |
| Started | Aug 29 10:20:12 AM UTC 24 |
| Finished | Aug 29 10:24:32 AM UTC 24 |
| Peak memory | 302072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466609087 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.3466609087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.37698824 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 12745699500 ps |
| CPU time | 305.8 seconds |
| Started | Aug 29 10:20:12 AM UTC 24 |
| Finished | Aug 29 10:25:22 AM UTC 24 |
| Peak memory | 302192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=37698824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.flash_ctrl_intr_rd_slow_flash.37698824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1032157578 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3430139800 ps |
| CPU time | 78.73 seconds |
| Started | Aug 29 10:19:30 AM UTC 24 |
| Finished | Aug 29 10:20:50 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032157578 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1032157578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3903214546 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 26212800 ps |
| CPU time | 20.97 seconds |
| Started | Aug 29 10:20:49 AM UTC 24 |
| Finished | Aug 29 10:21:11 AM UTC 24 |
| Peak memory | 273416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3903214546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_lcmgr_intg.3903214546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2240205755 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 16115248100 ps |
| CPU time | 404.15 seconds |
| Started | Aug 29 10:19:22 AM UTC 24 |
| Finished | Aug 29 10:26:11 AM UTC 24 |
| Peak memory | 283724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2240205755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2240205755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2971982302 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 171297800 ps |
| CPU time | 181.86 seconds |
| Started | Aug 29 10:19:17 AM UTC 24 |
| Finished | Aug 29 10:22:21 AM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971982302 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.2971982302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3448765485 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 227493700 ps |
| CPU time | 427.18 seconds |
| Started | Aug 29 10:19:06 AM UTC 24 |
| Finished | Aug 29 10:26:19 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448765485 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3448765485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.764767059 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 19282100 ps |
| CPU time | 23.45 seconds |
| Started | Aug 29 10:20:22 AM UTC 24 |
| Finished | Aug 29 10:20:47 AM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764767059 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.764767059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.1968998365 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 980224700 ps |
| CPU time | 1102.62 seconds |
| Started | Aug 29 10:18:58 AM UTC 24 |
| Finished | Aug 29 10:37:33 AM UTC 24 |
| Peak memory | 294036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968998365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1968998365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.1274074266 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 377195000 ps |
| CPU time | 56.05 seconds |
| Started | Aug 29 10:20:32 AM UTC 24 |
| Finished | Aug 29 10:21:30 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274074266 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.1274074266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.3265202650 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 441336600 ps |
| CPU time | 98.34 seconds |
| Started | Aug 29 10:20:05 AM UTC 24 |
| Finished | Aug 29 10:21:46 AM UTC 24 |
| Peak memory | 304084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3265202650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.3265202650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.3849595554 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 29355707300 ps |
| CPU time | 539 seconds |
| Started | Aug 29 10:20:09 AM UTC 24 |
| Finished | Aug 29 10:29:16 AM UTC 24 |
| Peak memory | 333012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849595554 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.3849595554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2855669112 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26701600 ps |
| CPU time | 57.52 seconds |
| Started | Aug 29 10:20:26 AM UTC 24 |
| Finished | Aug 29 10:21:25 AM UTC 24 |
| Peak memory | 283824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855669112 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.2855669112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2872170104 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 27138500 ps |
| CPU time | 60.17 seconds |
| Started | Aug 29 10:20:32 AM UTC 24 |
| Finished | Aug 29 10:21:34 AM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2872170104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_rw_evict_all_en.2872170104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2054908241 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 320683200 ps |
| CPU time | 71.16 seconds |
| Started | Aug 29 10:20:39 AM UTC 24 |
| Finished | Aug 29 10:21:52 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054908241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2054908241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.924031579 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 14986800 ps |
| CPU time | 105.14 seconds |
| Started | Aug 29 10:18:57 AM UTC 24 |
| Finished | Aug 29 10:20:44 AM UTC 24 |
| Peak memory | 287624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924031579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.924031579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.3077479275 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 9222955300 ps |
| CPU time | 172.27 seconds |
| Started | Aug 29 10:19:41 AM UTC 24 |
| Finished | Aug 29 10:22:36 AM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3077479275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.3077479275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1861909819 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 129605400 ps |
| CPU time | 23.7 seconds |
| Started | Aug 29 10:22:57 AM UTC 24 |
| Finished | Aug 29 10:23:23 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861909819 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1861909819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1150264957 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 41626700 ps |
| CPU time | 15.29 seconds |
| Started | Aug 29 10:22:37 AM UTC 24 |
| Finished | Aug 29 10:22:54 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150264957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1150264957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2512527037 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10043810400 ps |
| CPU time | 78.11 seconds |
| Started | Aug 29 10:22:54 AM UTC 24 |
| Finished | Aug 29 10:24:14 AM UTC 24 |
| Peak memory | 275876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2512527037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2512527037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.1279523210 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 48079300 ps |
| CPU time | 23.21 seconds |
| Started | Aug 29 10:22:50 AM UTC 24 |
| Finished | Aug 29 10:23:15 AM UTC 24 |
| Peak memory | 269636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1279523210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1279523210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.199068174 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 240212856600 ps |
| CPU time | 1109.76 seconds |
| Started | Aug 29 10:21:13 AM UTC 24 |
| Finished | Aug 29 10:39:56 AM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199068174 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_reset.199068174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1806796193 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3164458700 ps |
| CPU time | 259.3 seconds |
| Started | Aug 29 10:21:13 AM UTC 24 |
| Finished | Aug 29 10:25:36 AM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806796193 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.1806796193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3127005380 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1524939900 ps |
| CPU time | 188.27 seconds |
| Started | Aug 29 10:21:46 AM UTC 24 |
| Finished | Aug 29 10:24:58 AM UTC 24 |
| Peak memory | 304120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127005380 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.3127005380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3247752508 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 9194128100 ps |
| CPU time | 162.86 seconds |
| Started | Aug 29 10:21:52 AM UTC 24 |
| Finished | Aug 29 10:24:38 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3247752508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_intr_rd_slow_flash.3247752508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1173595931 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5136558700 ps |
| CPU time | 119.92 seconds |
| Started | Aug 29 10:21:18 AM UTC 24 |
| Finished | Aug 29 10:23:20 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173595931 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1173595931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.107199975 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 40257000 ps |
| CPU time | 23.26 seconds |
| Started | Aug 29 10:22:40 AM UTC 24 |
| Finished | Aug 29 10:23:05 AM UTC 24 |
| Peak memory | 271596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=107199975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_lcmgr_intg.107199975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3006204789 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 36103180100 ps |
| CPU time | 766.16 seconds |
| Started | Aug 29 10:21:17 AM UTC 24 |
| Finished | Aug 29 10:34:13 AM UTC 24 |
| Peak memory | 283536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3006204789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.3006204789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.1594790368 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 155057800 ps |
| CPU time | 156.51 seconds |
| Started | Aug 29 10:21:17 AM UTC 24 |
| Finished | Aug 29 10:23:56 AM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594790368 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.1594790368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.2426481780 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1409550200 ps |
| CPU time | 722.06 seconds |
| Started | Aug 29 10:21:09 AM UTC 24 |
| Finished | Aug 29 10:33:19 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426481780 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2426481780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.378857315 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 71577200 ps |
| CPU time | 23.9 seconds |
| Started | Aug 29 10:21:54 AM UTC 24 |
| Finished | Aug 29 10:22:20 AM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378857315 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.378857315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1893654829 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 64488400 ps |
| CPU time | 306.02 seconds |
| Started | Aug 29 10:21:03 AM UTC 24 |
| Finished | Aug 29 10:26:13 AM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893654829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1893654829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1395718266 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 60948600 ps |
| CPU time | 46.61 seconds |
| Started | Aug 29 10:22:21 AM UTC 24 |
| Finished | Aug 29 10:23:09 AM UTC 24 |
| Peak memory | 287956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395718266 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.1395718266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.441874944 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2101672000 ps |
| CPU time | 142.8 seconds |
| Started | Aug 29 10:21:31 AM UTC 24 |
| Finished | Aug 29 10:23:57 AM UTC 24 |
| Peak memory | 291920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=441874944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.441874944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3857984162 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 6490083300 ps |
| CPU time | 507.37 seconds |
| Started | Aug 29 10:21:35 AM UTC 24 |
| Finished | Aug 29 10:30:10 AM UTC 24 |
| Peak memory | 320724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857984162 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.3857984162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1378911396 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 30462300 ps |
| CPU time | 50.62 seconds |
| Started | Aug 29 10:21:58 AM UTC 24 |
| Finished | Aug 29 10:22:50 AM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378911396 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1378911396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.238990164 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 58510300 ps |
| CPU time | 215.1 seconds |
| Started | Aug 29 10:21:01 AM UTC 24 |
| Finished | Aug 29 10:24:40 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238990164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.238990164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1786798754 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2114301700 ps |
| CPU time | 202.36 seconds |
| Started | Aug 29 10:21:27 AM UTC 24 |
| Finished | Aug 29 10:24:53 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1786798754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.1786798754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.3933824899 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 22299800 ps |
| CPU time | 23.45 seconds |
| Started | Aug 29 10:25:03 AM UTC 24 |
| Finished | Aug 29 10:25:28 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933824899 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.3933824899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.2900960186 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 32617700 ps |
| CPU time | 26.58 seconds |
| Started | Aug 29 10:24:54 AM UTC 24 |
| Finished | Aug 29 10:25:21 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900960186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2900960186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3701580461 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 36444700 ps |
| CPU time | 37.39 seconds |
| Started | Aug 29 10:24:40 AM UTC 24 |
| Finished | Aug 29 10:25:19 AM UTC 24 |
| Peak memory | 285816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3701580461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.3701580461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3863744650 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10076372900 ps |
| CPU time | 96.1 seconds |
| Started | Aug 29 10:25:01 AM UTC 24 |
| Finished | Aug 29 10:26:39 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3863744650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3863744650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.3978604764 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 25719600 ps |
| CPU time | 22.28 seconds |
| Started | Aug 29 10:25:00 AM UTC 24 |
| Finished | Aug 29 10:25:23 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3978604764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.3978604764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.3124080699 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 160168750000 ps |
| CPU time | 1213.69 seconds |
| Started | Aug 29 10:23:14 AM UTC 24 |
| Finished | Aug 29 10:43:43 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124080699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res et.3124080699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.1274310630 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2784453000 ps |
| CPU time | 88.4 seconds |
| Started | Aug 29 10:23:10 AM UTC 24 |
| Finished | Aug 29 10:24:40 AM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274310630 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.1274310630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.2498380783 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3128567400 ps |
| CPU time | 199.92 seconds |
| Started | Aug 29 10:24:12 AM UTC 24 |
| Finished | Aug 29 10:27:35 AM UTC 24 |
| Peak memory | 293880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498380783 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.2498380783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1196670095 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 24780779700 ps |
| CPU time | 299.82 seconds |
| Started | Aug 29 10:24:15 AM UTC 24 |
| Finished | Aug 29 10:29:19 AM UTC 24 |
| Peak memory | 301984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1196670095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_intr_rd_slow_flash.1196670095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2614870267 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 8764543900 ps |
| CPU time | 94.84 seconds |
| Started | Aug 29 10:23:23 AM UTC 24 |
| Finished | Aug 29 10:25:00 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614870267 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2614870267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1510143626 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 49150200 ps |
| CPU time | 27.41 seconds |
| Started | Aug 29 10:25:00 AM UTC 24 |
| Finished | Aug 29 10:25:28 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1510143626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_lcmgr_intg.1510143626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2139833051 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 6888218600 ps |
| CPU time | 168.64 seconds |
| Started | Aug 29 10:23:21 AM UTC 24 |
| Finished | Aug 29 10:26:13 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2139833051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.2139833051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1168285441 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 35129900 ps |
| CPU time | 192.42 seconds |
| Started | Aug 29 10:23:16 AM UTC 24 |
| Finished | Aug 29 10:26:32 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168285441 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.1168285441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.3686280821 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 73748600 ps |
| CPU time | 440.47 seconds |
| Started | Aug 29 10:23:06 AM UTC 24 |
| Finished | Aug 29 10:30:32 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686280821 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3686280821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.832102923 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 20947400 ps |
| CPU time | 24.65 seconds |
| Started | Aug 29 10:24:33 AM UTC 24 |
| Finished | Aug 29 10:24:59 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832102923 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.832102923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.2290569311 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 117560600 ps |
| CPU time | 1263.33 seconds |
| Started | Aug 29 10:23:01 AM UTC 24 |
| Finished | Aug 29 10:44:18 AM UTC 24 |
| Peak memory | 298068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290569311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2290569311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.3782291534 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 937109600 ps |
| CPU time | 95.99 seconds |
| Started | Aug 29 10:23:57 AM UTC 24 |
| Finished | Aug 29 10:25:35 AM UTC 24 |
| Peak memory | 304124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3782291534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.3782291534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.430266099 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 18684934700 ps |
| CPU time | 600.62 seconds |
| Started | Aug 29 10:23:58 AM UTC 24 |
| Finished | Aug 29 10:34:07 AM UTC 24 |
| Peak memory | 322508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430266099 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.430266099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.549966738 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 103504800 ps |
| CPU time | 55.81 seconds |
| Started | Aug 29 10:24:33 AM UTC 24 |
| Finished | Aug 29 10:25:31 AM UTC 24 |
| Peak memory | 287732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549966738 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.549966738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.4150336761 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 39241900 ps |
| CPU time | 40.77 seconds |
| Started | Aug 29 10:24:34 AM UTC 24 |
| Finished | Aug 29 10:25:16 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4150336761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c trl_rw_evict_all_en.4150336761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.1626008576 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1365273800 ps |
| CPU time | 86.57 seconds |
| Started | Aug 29 10:24:41 AM UTC 24 |
| Finished | Aug 29 10:26:10 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626008576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1626008576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3101848065 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 74570000 ps |
| CPU time | 174.91 seconds |
| Started | Aug 29 10:23:01 AM UTC 24 |
| Finished | Aug 29 10:25:58 AM UTC 24 |
| Peak memory | 287632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101848065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.3101848065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.4074246754 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 9235010300 ps |
| CPU time | 220.67 seconds |
| Started | Aug 29 10:23:41 AM UTC 24 |
| Finished | Aug 29 10:27:25 AM UTC 24 |
| Peak memory | 271220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4074246754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.4074246754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.229285228 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 157938400 ps |
| CPU time | 21.86 seconds |
| Started | Aug 29 10:26:55 AM UTC 24 |
| Finished | Aug 29 10:27:19 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229285228 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.229285228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.321807183 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 29099700 ps |
| CPU time | 25.22 seconds |
| Started | Aug 29 10:26:33 AM UTC 24 |
| Finished | Aug 29 10:26:59 AM UTC 24 |
| Peak memory | 295252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321807183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.321807183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.539264892 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 10012549200 ps |
| CPU time | 142.93 seconds |
| Started | Aug 29 10:26:44 AM UTC 24 |
| Finished | Aug 29 10:29:10 AM UTC 24 |
| Peak memory | 330756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=539264892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.539264892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3849255939 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 25625800 ps |
| CPU time | 23.68 seconds |
| Started | Aug 29 10:26:44 AM UTC 24 |
| Finished | Aug 29 10:27:09 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3849255939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3849255939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2874607599 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4448190700 ps |
| CPU time | 90.25 seconds |
| Started | Aug 29 10:25:22 AM UTC 24 |
| Finished | Aug 29 10:26:55 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874607599 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.2874607599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.2557777128 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 686135600 ps |
| CPU time | 146.84 seconds |
| Started | Aug 29 10:25:37 AM UTC 24 |
| Finished | Aug 29 10:28:07 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557777128 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.2557777128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2643348084 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 11687697600 ps |
| CPU time | 289.47 seconds |
| Started | Aug 29 10:25:59 AM UTC 24 |
| Finished | Aug 29 10:30:53 AM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2643348084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_intr_rd_slow_flash.2643348084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.4060870135 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3208086800 ps |
| CPU time | 88.69 seconds |
| Started | Aug 29 10:25:31 AM UTC 24 |
| Finished | Aug 29 10:27:02 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060870135 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.4060870135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1918739197 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 40205300 ps |
| CPU time | 21.43 seconds |
| Started | Aug 29 10:26:43 AM UTC 24 |
| Finished | Aug 29 10:27:06 AM UTC 24 |
| Peak memory | 271404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1918739197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.1918739197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.2313388700 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 33156661500 ps |
| CPU time | 655.74 seconds |
| Started | Aug 29 10:25:30 AM UTC 24 |
| Finished | Aug 29 10:36:34 AM UTC 24 |
| Peak memory | 283724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2313388700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.2313388700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.3151865670 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 110683400 ps |
| CPU time | 178.24 seconds |
| Started | Aug 29 10:25:29 AM UTC 24 |
| Finished | Aug 29 10:28:30 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151865670 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.3151865670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3996913631 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 852462700 ps |
| CPU time | 299.16 seconds |
| Started | Aug 29 10:25:22 AM UTC 24 |
| Finished | Aug 29 10:30:26 AM UTC 24 |
| Peak memory | 275396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996913631 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3996913631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2571857603 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 251186700 ps |
| CPU time | 26.56 seconds |
| Started | Aug 29 10:26:11 AM UTC 24 |
| Finished | Aug 29 10:26:39 AM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571857603 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.2571857603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.4245173163 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 99283000 ps |
| CPU time | 805.79 seconds |
| Started | Aug 29 10:25:20 AM UTC 24 |
| Finished | Aug 29 10:38:56 AM UTC 24 |
| Peak memory | 291732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245173163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.4245173163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.516519728 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 165589700 ps |
| CPU time | 52.6 seconds |
| Started | Aug 29 10:26:15 AM UTC 24 |
| Finished | Aug 29 10:27:09 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516519728 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.516519728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.3581091684 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1331945300 ps |
| CPU time | 122.93 seconds |
| Started | Aug 29 10:25:32 AM UTC 24 |
| Finished | Aug 29 10:27:37 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3581091684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.3581091684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2603752262 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 17161180800 ps |
| CPU time | 482.94 seconds |
| Started | Aug 29 10:25:35 AM UTC 24 |
| Finished | Aug 29 10:33:44 AM UTC 24 |
| Peak memory | 324748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603752262 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.2603752262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3096893468 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 100165700 ps |
| CPU time | 50.11 seconds |
| Started | Aug 29 10:26:13 AM UTC 24 |
| Finished | Aug 29 10:27:05 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096893468 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3096893468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3496301916 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 223570000 ps |
| CPU time | 51.66 seconds |
| Started | Aug 29 10:26:13 AM UTC 24 |
| Finished | Aug 29 10:27:06 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3496301916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c trl_rw_evict_all_en.3496301916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2166698234 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 619146200 ps |
| CPU time | 93.12 seconds |
| Started | Aug 29 10:26:20 AM UTC 24 |
| Finished | Aug 29 10:27:55 AM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166698234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2166698234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3225364487 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 23650200 ps |
| CPU time | 177.94 seconds |
| Started | Aug 29 10:25:17 AM UTC 24 |
| Finished | Aug 29 10:28:18 AM UTC 24 |
| Peak memory | 287764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225364487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3225364487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.3048481524 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 8063801400 ps |
| CPU time | 134.6 seconds |
| Started | Aug 29 10:25:31 AM UTC 24 |
| Finished | Aug 29 10:27:48 AM UTC 24 |
| Peak memory | 271416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3048481524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.3048481524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.1111164383 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 125259100 ps |
| CPU time | 21.16 seconds |
| Started | Aug 29 10:28:50 AM UTC 24 |
| Finished | Aug 29 10:29:12 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111164383 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.1111164383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.2356093738 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 13826800 ps |
| CPU time | 25.05 seconds |
| Started | Aug 29 10:28:30 AM UTC 24 |
| Finished | Aug 29 10:28:57 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356093738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2356093738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1616882775 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 16149500 ps |
| CPU time | 39.18 seconds |
| Started | Aug 29 10:28:07 AM UTC 24 |
| Finished | Aug 29 10:28:48 AM UTC 24 |
| Peak memory | 285944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1616882775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.1616882775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1087431415 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 10012567100 ps |
| CPU time | 205.5 seconds |
| Started | Aug 29 10:28:49 AM UTC 24 |
| Finished | Aug 29 10:32:18 AM UTC 24 |
| Peak memory | 341000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1087431415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1087431415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.879033450 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 49972800 ps |
| CPU time | 26.85 seconds |
| Started | Aug 29 10:28:34 AM UTC 24 |
| Finished | Aug 29 10:29:02 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=879033450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.flash_ctrl_hw_read_seed_err.879033450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3603627359 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 80139098900 ps |
| CPU time | 987.14 seconds |
| Started | Aug 29 10:27:06 AM UTC 24 |
| Finished | Aug 29 10:43:45 AM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603627359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res et.3603627359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.3073815684 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2461669000 ps |
| CPU time | 56.5 seconds |
| Started | Aug 29 10:27:05 AM UTC 24 |
| Finished | Aug 29 10:28:03 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073815684 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.3073815684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.553946338 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1468712200 ps |
| CPU time | 165.62 seconds |
| Started | Aug 29 10:27:36 AM UTC 24 |
| Finished | Aug 29 10:30:24 AM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553946338 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.553946338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1664368167 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 24207647000 ps |
| CPU time | 289.68 seconds |
| Started | Aug 29 10:27:38 AM UTC 24 |
| Finished | Aug 29 10:32:32 AM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1664368167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.1664368167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.1877679954 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1016719000 ps |
| CPU time | 81.51 seconds |
| Started | Aug 29 10:27:09 AM UTC 24 |
| Finished | Aug 29 10:28:32 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877679954 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1877679954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1356935243 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 21163400 ps |
| CPU time | 26.75 seconds |
| Started | Aug 29 10:28:34 AM UTC 24 |
| Finished | Aug 29 10:29:02 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1356935243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_lcmgr_intg.1356935243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.2075863710 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2275946600 ps |
| CPU time | 230.84 seconds |
| Started | Aug 29 10:27:07 AM UTC 24 |
| Finished | Aug 29 10:31:02 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2075863710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2075863710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.703750341 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 41567400 ps |
| CPU time | 165.95 seconds |
| Started | Aug 29 10:27:07 AM UTC 24 |
| Finished | Aug 29 10:29:56 AM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703750341 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.703750341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.3818235731 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3093508100 ps |
| CPU time | 742.59 seconds |
| Started | Aug 29 10:27:03 AM UTC 24 |
| Finished | Aug 29 10:39:34 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818235731 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3818235731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.875846189 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 7533416700 ps |
| CPU time | 209.65 seconds |
| Started | Aug 29 10:27:49 AM UTC 24 |
| Finished | Aug 29 10:31:22 AM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875846189 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.875846189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3372751410 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 133030500 ps |
| CPU time | 1357.78 seconds |
| Started | Aug 29 10:27:01 AM UTC 24 |
| Finished | Aug 29 10:49:54 AM UTC 24 |
| Peak memory | 296492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372751410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3372751410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.2658241009 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 204045400 ps |
| CPU time | 55.86 seconds |
| Started | Aug 29 10:28:04 AM UTC 24 |
| Finished | Aug 29 10:29:02 AM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658241009 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.2658241009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.57745973 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1845768000 ps |
| CPU time | 99.56 seconds |
| Started | Aug 29 10:27:19 AM UTC 24 |
| Finished | Aug 29 10:29:01 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=57745973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.57745973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2499824090 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3511902400 ps |
| CPU time | 414.2 seconds |
| Started | Aug 29 10:27:25 AM UTC 24 |
| Finished | Aug 29 10:34:26 AM UTC 24 |
| Peak memory | 322472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499824090 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.2499824090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.676443173 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 106406000 ps |
| CPU time | 36.45 seconds |
| Started | Aug 29 10:27:55 AM UTC 24 |
| Finished | Aug 29 10:28:33 AM UTC 24 |
| Peak memory | 281780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676443173 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.676443173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1522672661 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 43764500 ps |
| CPU time | 51.55 seconds |
| Started | Aug 29 10:27:56 AM UTC 24 |
| Finished | Aug 29 10:28:49 AM UTC 24 |
| Peak memory | 287696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1522672661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.1522672661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.4116975103 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 718884300 ps |
| CPU time | 85.68 seconds |
| Started | Aug 29 10:28:19 AM UTC 24 |
| Finished | Aug 29 10:29:47 AM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116975103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.4116975103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.4128531680 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 63175500 ps |
| CPU time | 54.97 seconds |
| Started | Aug 29 10:26:58 AM UTC 24 |
| Finished | Aug 29 10:27:54 AM UTC 24 |
| Peak memory | 285708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128531680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.4128531680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.60548639 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4484419800 ps |
| CPU time | 180.13 seconds |
| Started | Aug 29 10:27:10 AM UTC 24 |
| Finished | Aug 29 10:30:14 AM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =60548639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.60548639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3098194750 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 66323400 ps |
| CPU time | 28.35 seconds |
| Started | Aug 29 10:31:03 AM UTC 24 |
| Finished | Aug 29 10:31:33 AM UTC 24 |
| Peak memory | 269320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098194750 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.3098194750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.283597150 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 14196100 ps |
| CPU time | 31.56 seconds |
| Started | Aug 29 10:30:48 AM UTC 24 |
| Finished | Aug 29 10:31:21 AM UTC 24 |
| Peak memory | 295380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283597150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.283597150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.172266097 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 17359600 ps |
| CPU time | 36.58 seconds |
| Started | Aug 29 10:30:34 AM UTC 24 |
| Finished | Aug 29 10:31:12 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=172266097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_disable.172266097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.996217036 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 10043042900 ps |
| CPU time | 107.31 seconds |
| Started | Aug 29 10:30:58 AM UTC 24 |
| Finished | Aug 29 10:32:48 AM UTC 24 |
| Peak memory | 277464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=996217036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.996217036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.1943698710 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 25152700 ps |
| CPU time | 28.46 seconds |
| Started | Aug 29 10:30:54 AM UTC 24 |
| Finished | Aug 29 10:31:24 AM UTC 24 |
| Peak memory | 271336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1943698710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1943698710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1690801729 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 210197943900 ps |
| CPU time | 953.56 seconds |
| Started | Aug 29 10:29:03 AM UTC 24 |
| Finished | Aug 29 10:45:08 AM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690801729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.1690801729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3588258225 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2548185400 ps |
| CPU time | 97.3 seconds |
| Started | Aug 29 10:29:02 AM UTC 24 |
| Finished | Aug 29 10:30:42 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588258225 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.3588258225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3677113570 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5760754700 ps |
| CPU time | 197.07 seconds |
| Started | Aug 29 10:30:10 AM UTC 24 |
| Finished | Aug 29 10:33:30 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3677113570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_intr_rd_slow_flash.3677113570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.255285526 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 8326520500 ps |
| CPU time | 97.75 seconds |
| Started | Aug 29 10:29:13 AM UTC 24 |
| Finished | Aug 29 10:30:53 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255285526 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.255285526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1769826524 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 17211614600 ps |
| CPU time | 403.85 seconds |
| Started | Aug 29 10:29:10 AM UTC 24 |
| Finished | Aug 29 10:36:00 AM UTC 24 |
| Peak memory | 283528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1769826524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1769826524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.3982569291 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 43493700 ps |
| CPU time | 218.74 seconds |
| Started | Aug 29 10:29:06 AM UTC 24 |
| Finished | Aug 29 10:32:49 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982569291 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.3982569291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.500829576 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 107180300 ps |
| CPU time | 126.82 seconds |
| Started | Aug 29 10:29:02 AM UTC 24 |
| Finished | Aug 29 10:31:12 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500829576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.500829576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.2742826335 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 22642600 ps |
| CPU time | 17.92 seconds |
| Started | Aug 29 10:30:14 AM UTC 24 |
| Finished | Aug 29 10:30:33 AM UTC 24 |
| Peak memory | 271464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742826335 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.2742826335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.3215102121 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 343577000 ps |
| CPU time | 1001.72 seconds |
| Started | Aug 29 10:29:02 AM UTC 24 |
| Finished | Aug 29 10:45:55 AM UTC 24 |
| Peak memory | 293772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215102121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3215102121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.388551163 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 257302100 ps |
| CPU time | 61.31 seconds |
| Started | Aug 29 10:30:32 AM UTC 24 |
| Finished | Aug 29 10:31:35 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388551163 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.388551163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.1411441464 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 983618300 ps |
| CPU time | 119.31 seconds |
| Started | Aug 29 10:29:20 AM UTC 24 |
| Finished | Aug 29 10:31:21 AM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1411441464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.1411441464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1103188980 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3702043300 ps |
| CPU time | 526.77 seconds |
| Started | Aug 29 10:29:48 AM UTC 24 |
| Finished | Aug 29 10:38:41 AM UTC 24 |
| Peak memory | 324548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103188980 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.1103188980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3887682358 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 38704600 ps |
| CPU time | 41.29 seconds |
| Started | Aug 29 10:30:25 AM UTC 24 |
| Finished | Aug 29 10:31:08 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887682358 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.3887682358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.2653487159 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 89252800 ps |
| CPU time | 47.14 seconds |
| Started | Aug 29 10:30:26 AM UTC 24 |
| Finished | Aug 29 10:31:15 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2653487159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_rw_evict_all_en.2653487159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.1631560390 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7061557700 ps |
| CPU time | 75.94 seconds |
| Started | Aug 29 10:30:43 AM UTC 24 |
| Finished | Aug 29 10:32:00 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631560390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1631560390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2236694601 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 53541200 ps |
| CPU time | 215.32 seconds |
| Started | Aug 29 10:28:58 AM UTC 24 |
| Finished | Aug 29 10:32:37 AM UTC 24 |
| Peak memory | 287620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236694601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2236694601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.1752593686 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1755546200 ps |
| CPU time | 150.89 seconds |
| Started | Aug 29 10:29:17 AM UTC 24 |
| Finished | Aug 29 10:31:50 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1752593686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.1752593686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3049654013 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 64176900 ps |
| CPU time | 22.04 seconds |
| Started | Aug 29 10:33:15 AM UTC 24 |
| Finished | Aug 29 10:33:38 AM UTC 24 |
| Peak memory | 274892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049654013 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.3049654013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1458745031 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 42454400 ps |
| CPU time | 24.53 seconds |
| Started | Aug 29 10:32:49 AM UTC 24 |
| Finished | Aug 29 10:33:15 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458745031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1458745031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.1119759813 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 19482300 ps |
| CPU time | 43.78 seconds |
| Started | Aug 29 10:32:37 AM UTC 24 |
| Finished | Aug 29 10:33:23 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1119759813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.1119759813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.971038056 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 10020657400 ps |
| CPU time | 84.84 seconds |
| Started | Aug 29 10:33:06 AM UTC 24 |
| Finished | Aug 29 10:34:33 AM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=971038056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.971038056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3790038428 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 26149500 ps |
| CPU time | 14.94 seconds |
| Started | Aug 29 10:33:02 AM UTC 24 |
| Finished | Aug 29 10:33:18 AM UTC 24 |
| Peak memory | 275396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3790038428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3790038428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.696385748 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 50122679300 ps |
| CPU time | 919.73 seconds |
| Started | Aug 29 10:31:19 AM UTC 24 |
| Finished | Aug 29 10:46:50 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696385748 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_reset.696385748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3006783782 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5668838000 ps |
| CPU time | 85.52 seconds |
| Started | Aug 29 10:31:16 AM UTC 24 |
| Finished | Aug 29 10:32:44 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006783782 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.3006783782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3532468858 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 10692334400 ps |
| CPU time | 221.02 seconds |
| Started | Aug 29 10:32:01 AM UTC 24 |
| Finished | Aug 29 10:35:45 AM UTC 24 |
| Peak memory | 304032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3532468858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_intr_rd_slow_flash.3532468858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.321439074 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3331165400 ps |
| CPU time | 99.22 seconds |
| Started | Aug 29 10:31:23 AM UTC 24 |
| Finished | Aug 29 10:33:05 AM UTC 24 |
| Peak memory | 271380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321439074 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.321439074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.2167160406 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 15085500 ps |
| CPU time | 23.36 seconds |
| Started | Aug 29 10:32:50 AM UTC 24 |
| Finished | Aug 29 10:33:15 AM UTC 24 |
| Peak memory | 271596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2167160406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.2167160406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.2084248934 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6824740900 ps |
| CPU time | 433.8 seconds |
| Started | Aug 29 10:31:22 AM UTC 24 |
| Finished | Aug 29 10:38:42 AM UTC 24 |
| Peak memory | 283532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2084248934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.2084248934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.2029035188 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 79095100 ps |
| CPU time | 202.24 seconds |
| Started | Aug 29 10:31:21 AM UTC 24 |
| Finished | Aug 29 10:34:47 AM UTC 24 |
| Peak memory | 273592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029035188 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.2029035188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.3374900533 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 325989900 ps |
| CPU time | 553.16 seconds |
| Started | Aug 29 10:31:13 AM UTC 24 |
| Finished | Aug 29 10:40:33 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374900533 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3374900533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.455027261 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 55773300 ps |
| CPU time | 25.12 seconds |
| Started | Aug 29 10:32:08 AM UTC 24 |
| Finished | Aug 29 10:32:34 AM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455027261 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.455027261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.4101139484 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 131266400 ps |
| CPU time | 280.28 seconds |
| Started | Aug 29 10:31:13 AM UTC 24 |
| Finished | Aug 29 10:35:58 AM UTC 24 |
| Peak memory | 281420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101139484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.4101139484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.277962048 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 216667100 ps |
| CPU time | 54.13 seconds |
| Started | Aug 29 10:32:35 AM UTC 24 |
| Finished | Aug 29 10:33:31 AM UTC 24 |
| Peak memory | 287988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277962048 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.277962048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3003368387 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 793852000 ps |
| CPU time | 118.31 seconds |
| Started | Aug 29 10:31:34 AM UTC 24 |
| Finished | Aug 29 10:33:35 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3003368387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.3003368387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.4033957984 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 29110800 ps |
| CPU time | 61.93 seconds |
| Started | Aug 29 10:32:18 AM UTC 24 |
| Finished | Aug 29 10:33:22 AM UTC 24 |
| Peak memory | 283888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033957984 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.4033957984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3416501406 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 181189400 ps |
| CPU time | 58.66 seconds |
| Started | Aug 29 10:32:32 AM UTC 24 |
| Finished | Aug 29 10:33:33 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3416501406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c trl_rw_evict_all_en.3416501406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.2210781307 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 33807547000 ps |
| CPU time | 105.63 seconds |
| Started | Aug 29 10:32:46 AM UTC 24 |
| Finished | Aug 29 10:34:34 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210781307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2210781307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3008814486 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 153387800 ps |
| CPU time | 140.96 seconds |
| Started | Aug 29 10:31:09 AM UTC 24 |
| Finished | Aug 29 10:33:33 AM UTC 24 |
| Peak memory | 287816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008814486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3008814486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.3292209789 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 10066141100 ps |
| CPU time | 141.66 seconds |
| Started | Aug 29 10:31:24 AM UTC 24 |
| Finished | Aug 29 10:33:49 AM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3292209789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.3292209789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1587727422 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 18087300 ps |
| CPU time | 22.33 seconds |
| Started | Aug 29 10:34:48 AM UTC 24 |
| Finished | Aug 29 10:35:11 AM UTC 24 |
| Peak memory | 269500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587727422 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.1587727422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.4023866302 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 48679300 ps |
| CPU time | 25.37 seconds |
| Started | Aug 29 10:34:26 AM UTC 24 |
| Finished | Aug 29 10:34:53 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023866302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4023866302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1396957458 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39210600 ps |
| CPU time | 34.3 seconds |
| Started | Aug 29 10:34:20 AM UTC 24 |
| Finished | Aug 29 10:34:56 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1396957458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.1396957458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3691515845 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 10020023200 ps |
| CPU time | 223.71 seconds |
| Started | Aug 29 10:34:35 AM UTC 24 |
| Finished | Aug 29 10:38:22 AM UTC 24 |
| Peak memory | 297912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3691515845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3691515845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.813776637 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 89769000 ps |
| CPU time | 15.24 seconds |
| Started | Aug 29 10:34:34 AM UTC 24 |
| Finished | Aug 29 10:34:50 AM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=813776637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.flash_ctrl_hw_read_seed_err.813776637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.1881859573 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 40122556200 ps |
| CPU time | 801.38 seconds |
| Started | Aug 29 10:33:24 AM UTC 24 |
| Finished | Aug 29 10:46:54 AM UTC 24 |
| Peak memory | 275368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881859573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res et.1881859573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.945030163 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5764315200 ps |
| CPU time | 167.7 seconds |
| Started | Aug 29 10:33:23 AM UTC 24 |
| Finished | Aug 29 10:36:13 AM UTC 24 |
| Peak memory | 271108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945030163 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.945030163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1882342622 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1682625800 ps |
| CPU time | 256.78 seconds |
| Started | Aug 29 10:33:39 AM UTC 24 |
| Finished | Aug 29 10:38:00 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882342622 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1882342622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.959151428 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 39344081100 ps |
| CPU time | 174.64 seconds |
| Started | Aug 29 10:33:45 AM UTC 24 |
| Finished | Aug 29 10:36:43 AM UTC 24 |
| Peak memory | 306356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=959151428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 17.flash_ctrl_intr_rd_slow_flash.959151428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.1706097255 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3336772300 ps |
| CPU time | 90.85 seconds |
| Started | Aug 29 10:33:32 AM UTC 24 |
| Finished | Aug 29 10:35:05 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706097255 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1706097255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.714530944 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 88604800 ps |
| CPU time | 27.87 seconds |
| Started | Aug 29 10:34:33 AM UTC 24 |
| Finished | Aug 29 10:35:02 AM UTC 24 |
| Peak memory | 271296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=714530944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_lcmgr_intg.714530944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.4000281138 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 16025675000 ps |
| CPU time | 564.32 seconds |
| Started | Aug 29 10:33:32 AM UTC 24 |
| Finished | Aug 29 10:43:03 AM UTC 24 |
| Peak memory | 285836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4000281138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.4000281138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.3778545177 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 154240500 ps |
| CPU time | 230.91 seconds |
| Started | Aug 29 10:33:32 AM UTC 24 |
| Finished | Aug 29 10:37:26 AM UTC 24 |
| Peak memory | 271268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778545177 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.3778545177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.999132847 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1616706400 ps |
| CPU time | 369.42 seconds |
| Started | Aug 29 10:33:19 AM UTC 24 |
| Finished | Aug 29 10:39:33 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999132847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.999132847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.851312125 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 20920700 ps |
| CPU time | 26.4 seconds |
| Started | Aug 29 10:33:49 AM UTC 24 |
| Finished | Aug 29 10:34:17 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851312125 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.851312125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.302320914 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 1613241300 ps |
| CPU time | 1320.02 seconds |
| Started | Aug 29 10:33:19 AM UTC 24 |
| Finished | Aug 29 10:55:34 AM UTC 24 |
| Peak memory | 293968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302320914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.302320914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.3209882876 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 235418500 ps |
| CPU time | 41.75 seconds |
| Started | Aug 29 10:34:18 AM UTC 24 |
| Finished | Aug 29 10:35:01 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209882876 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.3209882876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.1583985186 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3163564300 ps |
| CPU time | 110.65 seconds |
| Started | Aug 29 10:33:34 AM UTC 24 |
| Finished | Aug 29 10:35:27 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1583985186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.1583985186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.3380083606 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3715419400 ps |
| CPU time | 452.5 seconds |
| Started | Aug 29 10:33:36 AM UTC 24 |
| Finished | Aug 29 10:41:14 AM UTC 24 |
| Peak memory | 320500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380083606 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.3380083606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.2853184245 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 65494900 ps |
| CPU time | 39.15 seconds |
| Started | Aug 29 10:34:08 AM UTC 24 |
| Finished | Aug 29 10:34:49 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853184245 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.2853184245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.2027629315 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 28700400 ps |
| CPU time | 51.1 seconds |
| Started | Aug 29 10:34:14 AM UTC 24 |
| Finished | Aug 29 10:35:07 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2027629315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c trl_rw_evict_all_en.2027629315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1952098265 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4935463500 ps |
| CPU time | 90.39 seconds |
| Started | Aug 29 10:34:23 AM UTC 24 |
| Finished | Aug 29 10:35:56 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952098265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1952098265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.608191234 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 37956500 ps |
| CPU time | 271.03 seconds |
| Started | Aug 29 10:33:15 AM UTC 24 |
| Finished | Aug 29 10:37:50 AM UTC 24 |
| Peak memory | 289684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608191234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.608191234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.590745149 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1606447800 ps |
| CPU time | 149.06 seconds |
| Started | Aug 29 10:33:33 AM UTC 24 |
| Finished | Aug 29 10:36:05 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =590745149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.590745149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1344955121 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 82933400 ps |
| CPU time | 23.79 seconds |
| Started | Aug 29 10:36:48 AM UTC 24 |
| Finished | Aug 29 10:37:13 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344955121 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1344955121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.540816143 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 16128500 ps |
| CPU time | 28.19 seconds |
| Started | Aug 29 10:36:29 AM UTC 24 |
| Finished | Aug 29 10:36:58 AM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540816143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.540816143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.2546933647 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 114340400 ps |
| CPU time | 30.22 seconds |
| Started | Aug 29 10:36:17 AM UTC 24 |
| Finished | Aug 29 10:36:49 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2546933647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ ctrl_disable.2546933647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.11792850 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 10031804800 ps |
| CPU time | 82.7 seconds |
| Started | Aug 29 10:36:45 AM UTC 24 |
| Finished | Aug 29 10:38:10 AM UTC 24 |
| Peak memory | 281728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=11792850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.11792850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.619571203 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 45808200 ps |
| CPU time | 26.59 seconds |
| Started | Aug 29 10:36:43 AM UTC 24 |
| Finished | Aug 29 10:37:11 AM UTC 24 |
| Peak memory | 271532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=619571203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.flash_ctrl_hw_read_seed_err.619571203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.2269602364 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 80140619400 ps |
| CPU time | 834.99 seconds |
| Started | Aug 29 10:35:02 AM UTC 24 |
| Finished | Aug 29 10:49:07 AM UTC 24 |
| Peak memory | 275360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269602364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res et.2269602364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.1163045389 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2918519400 ps |
| CPU time | 77.59 seconds |
| Started | Aug 29 10:34:57 AM UTC 24 |
| Finished | Aug 29 10:36:17 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163045389 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.1163045389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.2987810270 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4466494900 ps |
| CPU time | 134.82 seconds |
| Started | Aug 29 10:35:46 AM UTC 24 |
| Finished | Aug 29 10:38:03 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987810270 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.2987810270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1116233288 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 48970640400 ps |
| CPU time | 412.2 seconds |
| Started | Aug 29 10:35:56 AM UTC 24 |
| Finished | Aug 29 10:42:54 AM UTC 24 |
| Peak memory | 304076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1116233288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_intr_rd_slow_flash.1116233288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.2472208103 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4328219800 ps |
| CPU time | 96.84 seconds |
| Started | Aug 29 10:35:08 AM UTC 24 |
| Finished | Aug 29 10:36:47 AM UTC 24 |
| Peak memory | 271120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472208103 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2472208103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2932412455 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 15997900 ps |
| CPU time | 23.16 seconds |
| Started | Aug 29 10:36:35 AM UTC 24 |
| Finished | Aug 29 10:36:59 AM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2932412455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_lcmgr_intg.2932412455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.999983893 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 126879005600 ps |
| CPU time | 723.68 seconds |
| Started | Aug 29 10:35:06 AM UTC 24 |
| Finished | Aug 29 10:47:18 AM UTC 24 |
| Peak memory | 283536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=999983893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_mp_regions.999983893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.49421266 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 668780100 ps |
| CPU time | 175.68 seconds |
| Started | Aug 29 10:35:03 AM UTC 24 |
| Finished | Aug 29 10:38:02 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49421266 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.49421266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.3014499310 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 54439500 ps |
| CPU time | 539.5 seconds |
| Started | Aug 29 10:34:54 AM UTC 24 |
| Finished | Aug 29 10:44:00 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014499310 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3014499310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.4151449333 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 58077100 ps |
| CPU time | 28.06 seconds |
| Started | Aug 29 10:35:58 AM UTC 24 |
| Finished | Aug 29 10:36:28 AM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151449333 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.4151449333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1220072125 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 42450100 ps |
| CPU time | 314.4 seconds |
| Started | Aug 29 10:34:51 AM UTC 24 |
| Finished | Aug 29 10:40:10 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220072125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1220072125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1791263776 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 240080400 ps |
| CPU time | 58.55 seconds |
| Started | Aug 29 10:36:14 AM UTC 24 |
| Finished | Aug 29 10:37:14 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791263776 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.1791263776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.14221314 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 526690300 ps |
| CPU time | 139.55 seconds |
| Started | Aug 29 10:35:13 AM UTC 24 |
| Finished | Aug 29 10:37:35 AM UTC 24 |
| Peak memory | 291692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=14221314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.14221314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.1936695107 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15542191900 ps |
| CPU time | 507.88 seconds |
| Started | Aug 29 10:35:28 AM UTC 24 |
| Finished | Aug 29 10:44:03 AM UTC 24 |
| Peak memory | 324596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936695107 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.1936695107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.3578420336 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 77611700 ps |
| CPU time | 42.56 seconds |
| Started | Aug 29 10:36:01 AM UTC 24 |
| Finished | Aug 29 10:36:45 AM UTC 24 |
| Peak memory | 285908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578420336 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.3578420336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.566887640 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 50037800 ps |
| CPU time | 60.77 seconds |
| Started | Aug 29 10:36:05 AM UTC 24 |
| Finished | Aug 29 10:37:07 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=566887640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ct rl_rw_evict_all_en.566887640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2484010844 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 100668800 ps |
| CPU time | 224.44 seconds |
| Started | Aug 29 10:34:50 AM UTC 24 |
| Finished | Aug 29 10:38:38 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484010844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2484010844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.2770363494 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3910466600 ps |
| CPU time | 185.46 seconds |
| Started | Aug 29 10:35:11 AM UTC 24 |
| Finished | Aug 29 10:38:19 AM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2770363494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.2770363494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1219223377 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 44760700 ps |
| CPU time | 20.85 seconds |
| Started | Aug 29 10:38:27 AM UTC 24 |
| Finished | Aug 29 10:38:49 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219223377 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.1219223377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.4173424458 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 16498300 ps |
| CPU time | 28.14 seconds |
| Started | Aug 29 10:38:17 AM UTC 24 |
| Finished | Aug 29 10:38:46 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173424458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.4173424458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1824452436 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 15698200 ps |
| CPU time | 41.51 seconds |
| Started | Aug 29 10:38:08 AM UTC 24 |
| Finished | Aug 29 10:38:51 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1824452436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ ctrl_disable.1824452436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2969191942 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 10019977500 ps |
| CPU time | 155.74 seconds |
| Started | Aug 29 10:38:23 AM UTC 24 |
| Finished | Aug 29 10:41:01 AM UTC 24 |
| Peak memory | 341000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2969191942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2969191942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.2612379492 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 172493200 ps |
| CPU time | 23.33 seconds |
| Started | Aug 29 10:38:21 AM UTC 24 |
| Finished | Aug 29 10:38:45 AM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2612379492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2612379492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3512786323 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 40125538900 ps |
| CPU time | 823.68 seconds |
| Started | Aug 29 10:37:12 AM UTC 24 |
| Finished | Aug 29 10:51:05 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512786323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res et.3512786323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.4083336921 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 2074232000 ps |
| CPU time | 113.59 seconds |
| Started | Aug 29 10:37:08 AM UTC 24 |
| Finished | Aug 29 10:39:04 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083336921 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.4083336921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.476690863 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1800820500 ps |
| CPU time | 181.47 seconds |
| Started | Aug 29 10:37:45 AM UTC 24 |
| Finished | Aug 29 10:40:49 AM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476690863 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.476690863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.316016903 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 23529373300 ps |
| CPU time | 178.99 seconds |
| Started | Aug 29 10:37:50 AM UTC 24 |
| Finished | Aug 29 10:40:52 AM UTC 24 |
| Peak memory | 304332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=316016903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.flash_ctrl_intr_rd_slow_flash.316016903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3805154207 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1673217000 ps |
| CPU time | 60.81 seconds |
| Started | Aug 29 10:37:27 AM UTC 24 |
| Finished | Aug 29 10:38:30 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805154207 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3805154207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3872110880 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 27068200 ps |
| CPU time | 23.04 seconds |
| Started | Aug 29 10:38:20 AM UTC 24 |
| Finished | Aug 29 10:38:44 AM UTC 24 |
| Peak memory | 271596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3872110880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.3872110880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.979407227 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 11437828600 ps |
| CPU time | 335.48 seconds |
| Started | Aug 29 10:37:15 AM UTC 24 |
| Finished | Aug 29 10:42:55 AM UTC 24 |
| Peak memory | 283788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=979407227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_mp_regions.979407227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.263517120 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 41778100 ps |
| CPU time | 212.14 seconds |
| Started | Aug 29 10:37:13 AM UTC 24 |
| Finished | Aug 29 10:40:49 AM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263517120 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.263517120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3422739661 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 113698200 ps |
| CPU time | 380.68 seconds |
| Started | Aug 29 10:37:00 AM UTC 24 |
| Finished | Aug 29 10:43:26 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422739661 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3422739661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.1712443679 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 80725600 ps |
| CPU time | 23.65 seconds |
| Started | Aug 29 10:37:51 AM UTC 24 |
| Finished | Aug 29 10:38:16 AM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712443679 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.1712443679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.746509780 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1584553000 ps |
| CPU time | 1163.91 seconds |
| Started | Aug 29 10:36:59 AM UTC 24 |
| Finished | Aug 29 10:56:36 AM UTC 24 |
| Peak memory | 295820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746509780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.746509780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.3843681070 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 66754600 ps |
| CPU time | 38.53 seconds |
| Started | Aug 29 10:38:04 AM UTC 24 |
| Finished | Aug 29 10:38:44 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843681070 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.3843681070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1210179517 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 617163800 ps |
| CPU time | 131.8 seconds |
| Started | Aug 29 10:37:35 AM UTC 24 |
| Finished | Aug 29 10:39:49 AM UTC 24 |
| Peak memory | 291768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1210179517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1210179517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.4286437901 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3745810800 ps |
| CPU time | 442.65 seconds |
| Started | Aug 29 10:37:36 AM UTC 24 |
| Finished | Aug 29 10:45:04 AM UTC 24 |
| Peak memory | 322668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286437901 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.4286437901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.2368703416 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 42404500 ps |
| CPU time | 52.61 seconds |
| Started | Aug 29 10:38:00 AM UTC 24 |
| Finished | Aug 29 10:38:54 AM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368703416 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.2368703416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.636520532 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 28316400 ps |
| CPU time | 35.32 seconds |
| Started | Aug 29 10:38:02 AM UTC 24 |
| Finished | Aug 29 10:38:39 AM UTC 24 |
| Peak memory | 281592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=636520532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ct rl_rw_evict_all_en.636520532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.268421040 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 11170137200 ps |
| CPU time | 102.62 seconds |
| Started | Aug 29 10:38:10 AM UTC 24 |
| Finished | Aug 29 10:39:55 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268421040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.268421040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1968427750 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 28205400 ps |
| CPU time | 240.81 seconds |
| Started | Aug 29 10:36:50 AM UTC 24 |
| Finished | Aug 29 10:40:54 AM UTC 24 |
| Peak memory | 291720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968427750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1968427750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.2135490969 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 6261942000 ps |
| CPU time | 159.17 seconds |
| Started | Aug 29 10:37:30 AM UTC 24 |
| Finished | Aug 29 10:40:13 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2135490969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.2135490969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1067488910 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 322409600 ps |
| CPU time | 28.03 seconds |
| Started | Aug 29 09:51:09 AM UTC 24 |
| Finished | Aug 29 09:51:39 AM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067488910 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1067488910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.587759175 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 71234600 ps |
| CPU time | 22.63 seconds |
| Started | Aug 29 09:50:51 AM UTC 24 |
| Finished | Aug 29 09:51:15 AM UTC 24 |
| Peak memory | 273248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587759175 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.587759175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.1681057393 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 221540700 ps |
| CPU time | 28.72 seconds |
| Started | Aug 29 09:50:17 AM UTC 24 |
| Finished | Aug 29 09:50:47 AM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681057393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1681057393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.3025004823 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3422893100 ps |
| CPU time | 253.38 seconds |
| Started | Aug 29 09:48:49 AM UTC 24 |
| Finished | Aug 29 09:53:06 AM UTC 24 |
| Peak memory | 292024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3025004823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.3025004823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3291516388 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 20837300 ps |
| CPU time | 43.82 seconds |
| Started | Aug 29 09:49:49 AM UTC 24 |
| Finished | Aug 29 09:50:34 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3291516388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_disable.3291516388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4108973843 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2702401500 ps |
| CPU time | 687.4 seconds |
| Started | Aug 29 09:46:38 AM UTC 24 |
| Finished | Aug 29 09:58:15 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108973843 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4108973843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.4027110767 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 13345363100 ps |
| CPU time | 3052.45 seconds |
| Started | Aug 29 09:47:13 AM UTC 24 |
| Finished | Aug 29 10:38:37 AM UTC 24 |
| Peak memory | 278052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027110767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.4027110767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.441353574 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 729549000 ps |
| CPU time | 3044.81 seconds |
| Started | Aug 29 09:47:02 AM UTC 24 |
| Finished | Aug 29 10:38:19 AM UTC 24 |
| Peak memory | 278128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44 1353574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ error_prog_type.441353574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.3636061383 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1147459600 ps |
| CPU time | 1011.03 seconds |
| Started | Aug 29 09:47:03 AM UTC 24 |
| Finished | Aug 29 10:04:05 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636061383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3636061383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1881752450 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 416285400 ps |
| CPU time | 36.46 seconds |
| Started | Aug 29 09:47:01 AM UTC 24 |
| Finished | Aug 29 09:47:39 AM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 81752450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc h_code.1881752450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3654175268 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1569936000 ps |
| CPU time | 51.3 seconds |
| Started | Aug 29 09:50:45 AM UTC 24 |
| Finished | Aug 29 09:51:37 AM UTC 24 |
| Peak memory | 273520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654175 268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f s_sup.3654175268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1746852419 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 305949500000 ps |
| CPU time | 3207.09 seconds |
| Started | Aug 29 09:47:01 AM UTC 24 |
| Finished | Aug 29 10:41:05 AM UTC 24 |
| Peak memory | 278080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746852419 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.1746852419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2497342497 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 27837600 ps |
| CPU time | 36.37 seconds |
| Started | Aug 29 09:51:08 AM UTC 24 |
| Finished | Aug 29 09:51:46 AM UTC 24 |
| Peak memory | 287600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249734249 7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho st_addr_infection.2497342497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.4262902875 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 585269199500 ps |
| CPU time | 2514.24 seconds |
| Started | Aug 29 09:46:45 AM UTC 24 |
| Finished | Aug 29 10:29:05 AM UTC 24 |
| Peak memory | 278260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262902875 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.4262902875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1312195954 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 10012267700 ps |
| CPU time | 154.12 seconds |
| Started | Aug 29 09:51:06 AM UTC 24 |
| Finished | Aug 29 09:53:44 AM UTC 24 |
| Peak memory | 351276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1312195954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1312195954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.4253340935 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 15886100 ps |
| CPU time | 20.27 seconds |
| Started | Aug 29 09:51:05 AM UTC 24 |
| Finished | Aug 29 09:51:27 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4253340935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.4253340935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2695173560 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 170379062200 ps |
| CPU time | 1739.68 seconds |
| Started | Aug 29 09:46:39 AM UTC 24 |
| Finished | Aug 29 10:15:59 AM UTC 24 |
| Peak memory | 276260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695173560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.2695173560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.317635354 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 160184708100 ps |
| CPU time | 982.37 seconds |
| Started | Aug 29 09:46:40 AM UTC 24 |
| Finished | Aug 29 10:03:14 AM UTC 24 |
| Peak memory | 275364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317635354 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.317635354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1403853092 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 10962798500 ps |
| CPU time | 218.79 seconds |
| Started | Aug 29 09:46:33 AM UTC 24 |
| Finished | Aug 29 09:50:16 AM UTC 24 |
| Peak memory | 273356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403853092 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.1403853092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3095787443 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3516514300 ps |
| CPU time | 449.85 seconds |
| Started | Aug 29 09:49:03 AM UTC 24 |
| Finished | Aug 29 09:56:39 AM UTC 24 |
| Peak memory | 324624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3095787443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr ity.3095787443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.1373669037 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1653421100 ps |
| CPU time | 208.23 seconds |
| Started | Aug 29 09:49:11 AM UTC 24 |
| Finished | Aug 29 09:52:43 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373669037 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.1373669037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.578162267 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 8092441200 ps |
| CPU time | 192.32 seconds |
| Started | Aug 29 09:49:22 AM UTC 24 |
| Finished | Aug 29 09:52:37 AM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=578162267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_rd_slow_flash.578162267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2925218203 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4551331100 ps |
| CPU time | 95.74 seconds |
| Started | Aug 29 09:49:13 AM UTC 24 |
| Finished | Aug 29 09:50:50 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925218203 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.2925218203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.72304909 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 52470092900 ps |
| CPU time | 215.08 seconds |
| Started | Aug 29 09:49:25 AM UTC 24 |
| Finished | Aug 29 09:53:03 AM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72304909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.72304909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.4011920852 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6801214800 ps |
| CPU time | 95.32 seconds |
| Started | Aug 29 09:47:19 AM UTC 24 |
| Finished | Aug 29 09:48:57 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011920852 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.4011920852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.1267129700 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 48775500 ps |
| CPU time | 24.68 seconds |
| Started | Aug 29 09:51:03 AM UTC 24 |
| Finished | Aug 29 09:51:29 AM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1267129700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_lcmgr_intg.1267129700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.841035678 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1278403300 ps |
| CPU time | 120.5 seconds |
| Started | Aug 29 09:47:21 AM UTC 24 |
| Finished | Aug 29 09:49:24 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841035678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.841035678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3976390285 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 82695000 ps |
| CPU time | 166.88 seconds |
| Started | Aug 29 09:46:44 AM UTC 24 |
| Finished | Aug 29 09:49:33 AM UTC 24 |
| Peak memory | 275832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976390285 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.3976390285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1303000503 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4121315400 ps |
| CPU time | 198.34 seconds |
| Started | Aug 29 09:48:57 AM UTC 24 |
| Finished | Aug 29 09:52:19 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1303000503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1303000503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.4269351580 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 16521000 ps |
| CPU time | 25.5 seconds |
| Started | Aug 29 09:50:49 AM UTC 24 |
| Finished | Aug 29 09:51:16 AM UTC 24 |
| Peak memory | 293288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269351580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.4269351580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.864024350 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 741510700 ps |
| CPU time | 678.77 seconds |
| Started | Aug 29 09:46:32 AM UTC 24 |
| Finished | Aug 29 09:57:59 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864024350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.864024350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1482937913 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 21085500 ps |
| CPU time | 28.28 seconds |
| Started | Aug 29 09:49:34 AM UTC 24 |
| Finished | Aug 29 09:50:03 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482937913 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.1482937913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2274872560 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 15336279400 ps |
| CPU time | 940.04 seconds |
| Started | Aug 29 09:46:15 AM UTC 24 |
| Finished | Aug 29 10:02:04 AM UTC 24 |
| Peak memory | 295824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274872560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2274872560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1367868482 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 741892500 ps |
| CPU time | 163.84 seconds |
| Started | Aug 29 09:46:24 AM UTC 24 |
| Finished | Aug 29 09:49:10 AM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367868482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1367868482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3873402863 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 415199800 ps |
| CPU time | 45.19 seconds |
| Started | Aug 29 09:50:21 AM UTC 24 |
| Finished | Aug 29 09:51:08 AM UTC 24 |
| Peak memory | 287768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387340286 3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.3873402863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.184012663 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 63422300 ps |
| CPU time | 58.75 seconds |
| Started | Aug 29 09:49:48 AM UTC 24 |
| Finished | Aug 29 09:50:48 AM UTC 24 |
| Peak memory | 287316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184012663 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.184012663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.1723323146 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 57794800 ps |
| CPU time | 39.07 seconds |
| Started | Aug 29 09:48:22 AM UTC 24 |
| Finished | Aug 29 09:49:02 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1723323146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_read_word_sweep_derr.1723323146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.2161820428 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 46612500 ps |
| CPU time | 40.12 seconds |
| Started | Aug 29 09:47:40 AM UTC 24 |
| Finished | Aug 29 09:48:21 AM UTC 24 |
| Peak memory | 275436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161820428 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.2161820428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.325528670 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 41794359100 ps |
| CPU time | 886.13 seconds |
| Started | Aug 29 09:50:52 AM UTC 24 |
| Finished | Aug 29 10:05:48 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=325528670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.f lash_ctrl_rma_err.325528670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.1242562445 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 425174200 ps |
| CPU time | 127.34 seconds |
| Started | Aug 29 09:47:38 AM UTC 24 |
| Finished | Aug 29 09:49:47 AM UTC 24 |
| Peak memory | 291988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1242562445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.1242562445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.1166760623 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1087823400 ps |
| CPU time | 166.76 seconds |
| Started | Aug 29 09:47:56 AM UTC 24 |
| Finished | Aug 29 09:50:46 AM UTC 24 |
| Peak memory | 306164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1166760623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_ro_serr.1166760623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.3481844897 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1458009800 ps |
| CPU time | 263.42 seconds |
| Started | Aug 29 09:48:29 AM UTC 24 |
| Finished | Aug 29 09:52:57 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3481844897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rw_derr.3481844897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.4003689517 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 52966700 ps |
| CPU time | 54.81 seconds |
| Started | Aug 29 09:49:48 AM UTC 24 |
| Finished | Aug 29 09:50:44 AM UTC 24 |
| Peak memory | 287400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4003689517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_rw_evict_all_en.4003689517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.473970330 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2592078700 ps |
| CPU time | 184.64 seconds |
| Started | Aug 29 09:48:04 AM UTC 24 |
| Finished | Aug 29 09:51:12 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=473970330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.473970330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.1492928732 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1897133800 ps |
| CPU time | 6788.68 seconds |
| Started | Aug 29 09:49:51 AM UTC 24 |
| Finished | Aug 29 11:44:09 AM UTC 24 |
| Peak memory | 314444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492928732 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1492928732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.4065629409 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1076061200 ps |
| CPU time | 59.47 seconds |
| Started | Aug 29 09:48:20 AM UTC 24 |
| Finished | Aug 29 09:49:21 AM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406 5629409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser r_address.4065629409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1790501147 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 608529900 ps |
| CPU time | 96.28 seconds |
| Started | Aug 29 09:48:12 AM UTC 24 |
| Finished | Aug 29 09:49:50 AM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 90501147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.1790501147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3301682033 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 71426400 ps |
| CPU time | 134.66 seconds |
| Started | Aug 29 09:46:10 AM UTC 24 |
| Finished | Aug 29 09:48:28 AM UTC 24 |
| Peak memory | 287892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301682033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3301682033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.328167427 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 46288600 ps |
| CPU time | 45.47 seconds |
| Started | Aug 29 09:46:12 AM UTC 24 |
| Finished | Aug 29 09:46:59 AM UTC 24 |
| Peak memory | 271056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328167427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.328167427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.3993952030 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1008791700 ps |
| CPU time | 2418.19 seconds |
| Started | Aug 29 09:50:04 AM UTC 24 |
| Finished | Aug 29 10:30:47 AM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993952030 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.3993952030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3017110482 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 26254000 ps |
| CPU time | 44.76 seconds |
| Started | Aug 29 09:46:15 AM UTC 24 |
| Finished | Aug 29 09:47:01 AM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017110482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3017110482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.725313167 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3060996000 ps |
| CPU time | 208.69 seconds |
| Started | Aug 29 09:47:32 AM UTC 24 |
| Finished | Aug 29 09:51:05 AM UTC 24 |
| Peak memory | 271220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =725313167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.725313167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3705660582 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 160432500 ps |
| CPU time | 25.81 seconds |
| Started | Aug 29 09:50:35 AM UTC 24 |
| Finished | Aug 29 09:51:03 AM UTC 24 |
| Peak memory | 271376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705660582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_wr_intg.3705660582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1689967639 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 121344400 ps |
| CPU time | 23.58 seconds |
| Started | Aug 29 10:38:53 AM UTC 24 |
| Finished | Aug 29 10:39:18 AM UTC 24 |
| Peak memory | 275644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689967639 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1689967639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.1121882019 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 14244100 ps |
| CPU time | 26.66 seconds |
| Started | Aug 29 10:38:50 AM UTC 24 |
| Finished | Aug 29 10:39:18 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121882019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1121882019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.2021621175 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 44596400 ps |
| CPU time | 37.06 seconds |
| Started | Aug 29 10:38:46 AM UTC 24 |
| Finished | Aug 29 10:39:25 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2021621175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.2021621175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.3095401087 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5346242400 ps |
| CPU time | 185.05 seconds |
| Started | Aug 29 10:38:38 AM UTC 24 |
| Finished | Aug 29 10:41:47 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095401087 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.3095401087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1987796632 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 10696200500 ps |
| CPU time | 205.25 seconds |
| Started | Aug 29 10:38:39 AM UTC 24 |
| Finished | Aug 29 10:42:08 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987796632 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.1987796632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.474256322 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 6003130700 ps |
| CPU time | 156.11 seconds |
| Started | Aug 29 10:38:43 AM UTC 24 |
| Finished | Aug 29 10:41:22 AM UTC 24 |
| Peak memory | 304332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=474256322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 20.flash_ctrl_intr_rd_slow_flash.474256322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.1330430601 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 36663600 ps |
| CPU time | 141.82 seconds |
| Started | Aug 29 10:38:38 AM UTC 24 |
| Finished | Aug 29 10:41:03 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330430601 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.1330430601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1523323409 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 92003900 ps |
| CPU time | 31.97 seconds |
| Started | Aug 29 10:38:43 AM UTC 24 |
| Finished | Aug 29 10:39:16 AM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523323409 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.1523323409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.2769618241 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 223506300 ps |
| CPU time | 58.5 seconds |
| Started | Aug 29 10:38:45 AM UTC 24 |
| Finished | Aug 29 10:39:45 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769618241 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.2769618241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.567187565 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 47805200 ps |
| CPU time | 34.11 seconds |
| Started | Aug 29 10:38:45 AM UTC 24 |
| Finished | Aug 29 10:39:21 AM UTC 24 |
| Peak memory | 287928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=567187565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ct rl_rw_evict_all_en.567187565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2724891318 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4977590800 ps |
| CPU time | 110.22 seconds |
| Started | Aug 29 10:38:46 AM UTC 24 |
| Finished | Aug 29 10:40:39 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724891318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2724891318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2364633403 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 39784500 ps |
| CPU time | 155.57 seconds |
| Started | Aug 29 10:38:31 AM UTC 24 |
| Finished | Aug 29 10:41:10 AM UTC 24 |
| Peak memory | 287632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364633403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2364633403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.2601705706 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 47134100 ps |
| CPU time | 25.04 seconds |
| Started | Aug 29 10:39:39 AM UTC 24 |
| Finished | Aug 29 10:40:05 AM UTC 24 |
| Peak memory | 269300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601705706 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.2601705706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1789196835 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 16750900 ps |
| CPU time | 21.51 seconds |
| Started | Aug 29 10:39:39 AM UTC 24 |
| Finished | Aug 29 10:40:01 AM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789196835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1789196835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1189140606 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 10633400 ps |
| CPU time | 43.14 seconds |
| Started | Aug 29 10:39:26 AM UTC 24 |
| Finished | Aug 29 10:40:10 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1189140606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.1189140606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.1536444230 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 6430242400 ps |
| CPU time | 263.83 seconds |
| Started | Aug 29 10:38:57 AM UTC 24 |
| Finished | Aug 29 10:43:25 AM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536444230 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.1536444230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.645963208 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 69802175300 ps |
| CPU time | 439.61 seconds |
| Started | Aug 29 10:39:17 AM UTC 24 |
| Finished | Aug 29 10:46:42 AM UTC 24 |
| Peak memory | 293804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=645963208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 21.flash_ctrl_intr_rd_slow_flash.645963208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.1345826218 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 36511700 ps |
| CPU time | 189.24 seconds |
| Started | Aug 29 10:39:05 AM UTC 24 |
| Finished | Aug 29 10:42:17 AM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345826218 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.1345826218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.4001772954 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 63721500 ps |
| CPU time | 26.67 seconds |
| Started | Aug 29 10:39:18 AM UTC 24 |
| Finished | Aug 29 10:39:46 AM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001772954 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.4001772954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.55645407 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 395729300 ps |
| CPU time | 48.15 seconds |
| Started | Aug 29 10:39:18 AM UTC 24 |
| Finished | Aug 29 10:40:08 AM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55645407 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.55645407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.2939432165 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 181121900 ps |
| CPU time | 35.82 seconds |
| Started | Aug 29 10:39:21 AM UTC 24 |
| Finished | Aug 29 10:39:59 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2939432165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c trl_rw_evict_all_en.2939432165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3896473321 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2097476700 ps |
| CPU time | 80.59 seconds |
| Started | Aug 29 10:39:38 AM UTC 24 |
| Finished | Aug 29 10:41:00 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896473321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3896473321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2967258008 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 98168200 ps |
| CPU time | 172.02 seconds |
| Started | Aug 29 10:38:55 AM UTC 24 |
| Finished | Aug 29 10:41:50 AM UTC 24 |
| Peak memory | 287828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967258008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2967258008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3975340384 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 115841100 ps |
| CPU time | 23.4 seconds |
| Started | Aug 29 10:40:14 AM UTC 24 |
| Finished | Aug 29 10:40:39 AM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975340384 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.3975340384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.2716215104 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 14516200 ps |
| CPU time | 25.39 seconds |
| Started | Aug 29 10:40:11 AM UTC 24 |
| Finished | Aug 29 10:40:38 AM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716215104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2716215104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.4291004467 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 15577600 ps |
| CPU time | 44.04 seconds |
| Started | Aug 29 10:40:08 AM UTC 24 |
| Finished | Aug 29 10:40:54 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4291004467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ ctrl_disable.4291004467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.1618886992 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5807712100 ps |
| CPU time | 68.15 seconds |
| Started | Aug 29 10:39:47 AM UTC 24 |
| Finished | Aug 29 10:40:57 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618886992 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.1618886992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.4052326027 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2517901200 ps |
| CPU time | 254.52 seconds |
| Started | Aug 29 10:39:56 AM UTC 24 |
| Finished | Aug 29 10:44:15 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052326027 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.4052326027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.274006923 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 52603561200 ps |
| CPU time | 340.04 seconds |
| Started | Aug 29 10:39:57 AM UTC 24 |
| Finished | Aug 29 10:45:42 AM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=274006923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 22.flash_ctrl_intr_rd_slow_flash.274006923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2586616125 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 41208700 ps |
| CPU time | 193.92 seconds |
| Started | Aug 29 10:39:50 AM UTC 24 |
| Finished | Aug 29 10:43:07 AM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586616125 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.2586616125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.985742632 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 39433200 ps |
| CPU time | 28.28 seconds |
| Started | Aug 29 10:39:59 AM UTC 24 |
| Finished | Aug 29 10:40:29 AM UTC 24 |
| Peak memory | 269172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985742632 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.985742632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3540918621 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 74535600 ps |
| CPU time | 32.7 seconds |
| Started | Aug 29 10:40:02 AM UTC 24 |
| Finished | Aug 29 10:40:36 AM UTC 24 |
| Peak memory | 283888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540918621 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.3540918621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.469866561 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 79604100 ps |
| CPU time | 36.2 seconds |
| Started | Aug 29 10:40:05 AM UTC 24 |
| Finished | Aug 29 10:40:43 AM UTC 24 |
| Peak memory | 287736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=469866561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ct rl_rw_evict_all_en.469866561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.4113100718 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2050716100 ps |
| CPU time | 83.36 seconds |
| Started | Aug 29 10:40:11 AM UTC 24 |
| Finished | Aug 29 10:41:36 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113100718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.4113100718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.2078977488 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 29484700 ps |
| CPU time | 224.62 seconds |
| Started | Aug 29 10:39:46 AM UTC 24 |
| Finished | Aug 29 10:43:34 AM UTC 24 |
| Peak memory | 287624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078977488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2078977488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.2095593195 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 90213500 ps |
| CPU time | 26.04 seconds |
| Started | Aug 29 10:40:55 AM UTC 24 |
| Finished | Aug 29 10:41:23 AM UTC 24 |
| Peak memory | 269500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095593195 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.2095593195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.4238571443 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 49237000 ps |
| CPU time | 23.01 seconds |
| Started | Aug 29 10:40:52 AM UTC 24 |
| Finished | Aug 29 10:41:17 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238571443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.4238571443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.106941808 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 20867700 ps |
| CPU time | 24.83 seconds |
| Started | Aug 29 10:40:50 AM UTC 24 |
| Finished | Aug 29 10:41:16 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=106941808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_disable.106941808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.1638132381 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3537315300 ps |
| CPU time | 106.24 seconds |
| Started | Aug 29 10:40:30 AM UTC 24 |
| Finished | Aug 29 10:42:18 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638132381 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.1638132381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.4176313270 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 588820200 ps |
| CPU time | 129.51 seconds |
| Started | Aug 29 10:40:37 AM UTC 24 |
| Finished | Aug 29 10:42:49 AM UTC 24 |
| Peak memory | 302264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176313270 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.4176313270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.4187601960 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 25447695400 ps |
| CPU time | 322.65 seconds |
| Started | Aug 29 10:40:38 AM UTC 24 |
| Finished | Aug 29 10:46:06 AM UTC 24 |
| Peak memory | 301984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4187601960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.flash_ctrl_intr_rd_slow_flash.4187601960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.1300319265 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 74703500 ps |
| CPU time | 208.72 seconds |
| Started | Aug 29 10:40:33 AM UTC 24 |
| Finished | Aug 29 10:44:06 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300319265 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.1300319265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.1302115354 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2579320200 ps |
| CPU time | 179.36 seconds |
| Started | Aug 29 10:40:40 AM UTC 24 |
| Finished | Aug 29 10:43:42 AM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302115354 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.1302115354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.2483627460 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 44180500 ps |
| CPU time | 50.38 seconds |
| Started | Aug 29 10:40:40 AM UTC 24 |
| Finished | Aug 29 10:41:32 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483627460 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.2483627460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.3511692376 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4430033500 ps |
| CPU time | 85.23 seconds |
| Started | Aug 29 10:40:50 AM UTC 24 |
| Finished | Aug 29 10:42:17 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511692376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3511692376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.1264670591 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 678338600 ps |
| CPU time | 142.02 seconds |
| Started | Aug 29 10:40:14 AM UTC 24 |
| Finished | Aug 29 10:42:38 AM UTC 24 |
| Peak memory | 291732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264670591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1264670591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.1507661591 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 27216100 ps |
| CPU time | 24.86 seconds |
| Started | Aug 29 10:41:23 AM UTC 24 |
| Finished | Aug 29 10:41:49 AM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507661591 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.1507661591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.347523124 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 27353200 ps |
| CPU time | 27.03 seconds |
| Started | Aug 29 10:41:23 AM UTC 24 |
| Finished | Aug 29 10:41:52 AM UTC 24 |
| Peak memory | 295316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347523124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.347523124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.405504792 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 33972300 ps |
| CPU time | 42.85 seconds |
| Started | Aug 29 10:41:17 AM UTC 24 |
| Finished | Aug 29 10:42:01 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=405504792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_disable.405504792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.3760419418 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 7558216300 ps |
| CPU time | 150.47 seconds |
| Started | Aug 29 10:40:58 AM UTC 24 |
| Finished | Aug 29 10:43:31 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760419418 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.3760419418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.1821375245 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 5302572500 ps |
| CPU time | 174.96 seconds |
| Started | Aug 29 10:41:02 AM UTC 24 |
| Finished | Aug 29 10:44:00 AM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821375245 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.1821375245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2668648566 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5908043500 ps |
| CPU time | 135.64 seconds |
| Started | Aug 29 10:41:04 AM UTC 24 |
| Finished | Aug 29 10:43:22 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2668648566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.flash_ctrl_intr_rd_slow_flash.2668648566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.2310385800 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 42230400 ps |
| CPU time | 217.13 seconds |
| Started | Aug 29 10:41:01 AM UTC 24 |
| Finished | Aug 29 10:44:41 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310385800 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.2310385800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.708999879 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 51049400 ps |
| CPU time | 25.71 seconds |
| Started | Aug 29 10:41:13 AM UTC 24 |
| Finished | Aug 29 10:41:40 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708999879 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.708999879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.681838288 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 31442900 ps |
| CPU time | 45.78 seconds |
| Started | Aug 29 10:41:14 AM UTC 24 |
| Finished | Aug 29 10:42:01 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681838288 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.681838288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3140433602 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 40457300 ps |
| CPU time | 52.12 seconds |
| Started | Aug 29 10:41:15 AM UTC 24 |
| Finished | Aug 29 10:42:09 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3140433602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_rw_evict_all_en.3140433602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.365151950 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 15084240200 ps |
| CPU time | 137.12 seconds |
| Started | Aug 29 10:41:17 AM UTC 24 |
| Finished | Aug 29 10:43:37 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365151950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.365151950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.115830705 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 48456400 ps |
| CPU time | 183.31 seconds |
| Started | Aug 29 10:40:55 AM UTC 24 |
| Finished | Aug 29 10:44:02 AM UTC 24 |
| Peak memory | 287624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115830705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.115830705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.291813261 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 150770500 ps |
| CPU time | 23.55 seconds |
| Started | Aug 29 10:42:10 AM UTC 24 |
| Finished | Aug 29 10:42:34 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291813261 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.291813261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.190802977 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 29301000 ps |
| CPU time | 24.83 seconds |
| Started | Aug 29 10:42:09 AM UTC 24 |
| Finished | Aug 29 10:42:35 AM UTC 24 |
| Peak memory | 295188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190802977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.190802977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.2434796136 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 16164000 ps |
| CPU time | 25.69 seconds |
| Started | Aug 29 10:42:02 AM UTC 24 |
| Finished | Aug 29 10:42:29 AM UTC 24 |
| Peak memory | 285724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2434796136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ ctrl_disable.2434796136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3874797083 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 13901316400 ps |
| CPU time | 240.19 seconds |
| Started | Aug 29 10:41:37 AM UTC 24 |
| Finished | Aug 29 10:45:41 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874797083 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3874797083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.514050935 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 8381153200 ps |
| CPU time | 188 seconds |
| Started | Aug 29 10:41:42 AM UTC 24 |
| Finished | Aug 29 10:44:53 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514050935 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.514050935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2315710796 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 28038372400 ps |
| CPU time | 156.72 seconds |
| Started | Aug 29 10:41:48 AM UTC 24 |
| Finished | Aug 29 10:44:27 AM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2315710796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_intr_rd_slow_flash.2315710796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.4002441417 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 138668600 ps |
| CPU time | 204.89 seconds |
| Started | Aug 29 10:41:41 AM UTC 24 |
| Finished | Aug 29 10:45:09 AM UTC 24 |
| Peak memory | 271524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002441417 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.4002441417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.2654114300 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 56617800 ps |
| CPU time | 23.62 seconds |
| Started | Aug 29 10:41:50 AM UTC 24 |
| Finished | Aug 29 10:42:15 AM UTC 24 |
| Peak memory | 269156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654114300 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.2654114300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2382199692 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 60242200 ps |
| CPU time | 41.83 seconds |
| Started | Aug 29 10:41:51 AM UTC 24 |
| Finished | Aug 29 10:42:34 AM UTC 24 |
| Peak memory | 287984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382199692 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.2382199692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.171649348 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 75324200 ps |
| CPU time | 54.62 seconds |
| Started | Aug 29 10:41:52 AM UTC 24 |
| Finished | Aug 29 10:42:48 AM UTC 24 |
| Peak memory | 281620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=171649348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ct rl_rw_evict_all_en.171649348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1050947461 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5424638900 ps |
| CPU time | 96.96 seconds |
| Started | Aug 29 10:42:02 AM UTC 24 |
| Finished | Aug 29 10:43:41 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050947461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1050947461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.2727379183 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 267690600 ps |
| CPU time | 212.32 seconds |
| Started | Aug 29 10:41:32 AM UTC 24 |
| Finished | Aug 29 10:45:08 AM UTC 24 |
| Peak memory | 287632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727379183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2727379183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.4265702621 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 52944300 ps |
| CPU time | 23.6 seconds |
| Started | Aug 29 10:42:55 AM UTC 24 |
| Finished | Aug 29 10:43:20 AM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265702621 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.4265702621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.3884145452 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 17188000 ps |
| CPU time | 18.14 seconds |
| Started | Aug 29 10:42:50 AM UTC 24 |
| Finished | Aug 29 10:43:10 AM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884145452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3884145452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1237815971 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 32627700 ps |
| CPU time | 37.34 seconds |
| Started | Aug 29 10:42:39 AM UTC 24 |
| Finished | Aug 29 10:43:18 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1237815971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ ctrl_disable.1237815971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1202968964 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2299340200 ps |
| CPU time | 49.12 seconds |
| Started | Aug 29 10:42:18 AM UTC 24 |
| Finished | Aug 29 10:43:09 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202968964 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.1202968964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.508241219 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1785246700 ps |
| CPU time | 237.62 seconds |
| Started | Aug 29 10:42:19 AM UTC 24 |
| Finished | Aug 29 10:46:20 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508241219 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.508241219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1497982205 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7811233100 ps |
| CPU time | 168.34 seconds |
| Started | Aug 29 10:42:30 AM UTC 24 |
| Finished | Aug 29 10:45:21 AM UTC 24 |
| Peak memory | 304044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1497982205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.flash_ctrl_intr_rd_slow_flash.1497982205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.2303004932 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 158073500 ps |
| CPU time | 198.42 seconds |
| Started | Aug 29 10:42:18 AM UTC 24 |
| Finished | Aug 29 10:45:40 AM UTC 24 |
| Peak memory | 271292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303004932 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.2303004932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.1757671813 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3409373300 ps |
| CPU time | 172.5 seconds |
| Started | Aug 29 10:42:36 AM UTC 24 |
| Finished | Aug 29 10:45:31 AM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757671813 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.1757671813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.1813740263 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 48248100 ps |
| CPU time | 49.4 seconds |
| Started | Aug 29 10:42:36 AM UTC 24 |
| Finished | Aug 29 10:43:27 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813740263 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.1813740263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.2592845785 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 211954700 ps |
| CPU time | 56.26 seconds |
| Started | Aug 29 10:42:36 AM UTC 24 |
| Finished | Aug 29 10:43:34 AM UTC 24 |
| Peak memory | 287956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2592845785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_rw_evict_all_en.2592845785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.2348757084 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4574831900 ps |
| CPU time | 112.64 seconds |
| Started | Aug 29 10:42:49 AM UTC 24 |
| Finished | Aug 29 10:44:44 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348757084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2348757084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.3031686462 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 32563600 ps |
| CPU time | 158.38 seconds |
| Started | Aug 29 10:42:16 AM UTC 24 |
| Finished | Aug 29 10:44:57 AM UTC 24 |
| Peak memory | 287632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031686462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3031686462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1946789132 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 60243000 ps |
| CPU time | 28.14 seconds |
| Started | Aug 29 10:43:32 AM UTC 24 |
| Finished | Aug 29 10:44:01 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946789132 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.1946789132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.78416618 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 37724000 ps |
| CPU time | 22.51 seconds |
| Started | Aug 29 10:43:28 AM UTC 24 |
| Finished | Aug 29 10:43:51 AM UTC 24 |
| Peak memory | 295112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78416618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.78416618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.487183980 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 13735300 ps |
| CPU time | 39.3 seconds |
| Started | Aug 29 10:43:25 AM UTC 24 |
| Finished | Aug 29 10:44:06 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=487183980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_disable.487183980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.3573674012 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2915389900 ps |
| CPU time | 202.81 seconds |
| Started | Aug 29 10:43:05 AM UTC 24 |
| Finished | Aug 29 10:46:31 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573674012 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.3573674012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.3963527549 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 1426015900 ps |
| CPU time | 145 seconds |
| Started | Aug 29 10:43:10 AM UTC 24 |
| Finished | Aug 29 10:45:37 AM UTC 24 |
| Peak memory | 302264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963527549 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.3963527549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2042219089 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 53726633000 ps |
| CPU time | 320.04 seconds |
| Started | Aug 29 10:43:11 AM UTC 24 |
| Finished | Aug 29 10:48:36 AM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2042219089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.flash_ctrl_intr_rd_slow_flash.2042219089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.1061341653 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2939335300 ps |
| CPU time | 244.01 seconds |
| Started | Aug 29 10:43:19 AM UTC 24 |
| Finished | Aug 29 10:47:27 AM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061341653 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.1061341653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.3889474702 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 27996000 ps |
| CPU time | 38.56 seconds |
| Started | Aug 29 10:43:21 AM UTC 24 |
| Finished | Aug 29 10:44:01 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889474702 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.3889474702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.491003285 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 31892300 ps |
| CPU time | 48.05 seconds |
| Started | Aug 29 10:43:23 AM UTC 24 |
| Finished | Aug 29 10:44:13 AM UTC 24 |
| Peak memory | 287928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=491003285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ct rl_rw_evict_all_en.491003285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.1647695607 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 516337000 ps |
| CPU time | 47.58 seconds |
| Started | Aug 29 10:43:28 AM UTC 24 |
| Finished | Aug 29 10:44:17 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647695607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1647695607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.727882142 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 22671400 ps |
| CPU time | 183.03 seconds |
| Started | Aug 29 10:42:57 AM UTC 24 |
| Finished | Aug 29 10:46:03 AM UTC 24 |
| Peak memory | 289672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727882142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.727882142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.2151033536 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 93722200 ps |
| CPU time | 24.68 seconds |
| Started | Aug 29 10:44:02 AM UTC 24 |
| Finished | Aug 29 10:44:28 AM UTC 24 |
| Peak memory | 271376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151033536 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.2151033536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.182687679 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 22361000 ps |
| CPU time | 26.96 seconds |
| Started | Aug 29 10:44:01 AM UTC 24 |
| Finished | Aug 29 10:44:29 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182687679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.182687679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.223071599 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 10538300 ps |
| CPU time | 27.11 seconds |
| Started | Aug 29 10:43:55 AM UTC 24 |
| Finished | Aug 29 10:44:23 AM UTC 24 |
| Peak memory | 285912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=223071599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_disable.223071599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.922753954 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1616794700 ps |
| CPU time | 75.2 seconds |
| Started | Aug 29 10:43:35 AM UTC 24 |
| Finished | Aug 29 10:44:52 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922753954 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.922753954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.1043166899 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 641166600 ps |
| CPU time | 156.86 seconds |
| Started | Aug 29 10:43:42 AM UTC 24 |
| Finished | Aug 29 10:46:22 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043166899 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.1043166899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3355198974 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 41280026600 ps |
| CPU time | 253.99 seconds |
| Started | Aug 29 10:43:43 AM UTC 24 |
| Finished | Aug 29 10:48:01 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3355198974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.flash_ctrl_intr_rd_slow_flash.3355198974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.1725233993 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 41067800 ps |
| CPU time | 225.84 seconds |
| Started | Aug 29 10:43:37 AM UTC 24 |
| Finished | Aug 29 10:47:26 AM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725233993 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.1725233993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.3598738216 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1360264800 ps |
| CPU time | 46.84 seconds |
| Started | Aug 29 10:43:43 AM UTC 24 |
| Finished | Aug 29 10:44:32 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598738216 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.3598738216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.97200094 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 153352300 ps |
| CPU time | 59.94 seconds |
| Started | Aug 29 10:43:53 AM UTC 24 |
| Finished | Aug 29 10:44:54 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=97200094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctr l_rw_evict_all_en.97200094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.1289119342 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2078593800 ps |
| CPU time | 78.74 seconds |
| Started | Aug 29 10:44:01 AM UTC 24 |
| Finished | Aug 29 10:45:22 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289119342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1289119342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.3096995846 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 94213700 ps |
| CPU time | 334.53 seconds |
| Started | Aug 29 10:43:35 AM UTC 24 |
| Finished | Aug 29 10:49:14 AM UTC 24 |
| Peak memory | 291720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096995846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3096995846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1026540907 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 139927500 ps |
| CPU time | 23.74 seconds |
| Started | Aug 29 10:44:28 AM UTC 24 |
| Finished | Aug 29 10:44:54 AM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026540907 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.1026540907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1095151826 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 19758100 ps |
| CPU time | 28.64 seconds |
| Started | Aug 29 10:44:24 AM UTC 24 |
| Finished | Aug 29 10:44:54 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095151826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1095151826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2777566583 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 18966100 ps |
| CPU time | 34.78 seconds |
| Started | Aug 29 10:44:18 AM UTC 24 |
| Finished | Aug 29 10:44:54 AM UTC 24 |
| Peak memory | 285880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2777566583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ ctrl_disable.2777566583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.1224014160 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1124611600 ps |
| CPU time | 106.08 seconds |
| Started | Aug 29 10:44:02 AM UTC 24 |
| Finished | Aug 29 10:45:50 AM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224014160 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.1224014160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.990063554 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2168908500 ps |
| CPU time | 169.29 seconds |
| Started | Aug 29 10:44:05 AM UTC 24 |
| Finished | Aug 29 10:46:57 AM UTC 24 |
| Peak memory | 306164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990063554 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.990063554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.264571977 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 52740272900 ps |
| CPU time | 355.26 seconds |
| Started | Aug 29 10:44:07 AM UTC 24 |
| Finished | Aug 29 10:50:07 AM UTC 24 |
| Peak memory | 302028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=264571977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 29.flash_ctrl_intr_rd_slow_flash.264571977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.3043460579 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 107274600 ps |
| CPU time | 179.11 seconds |
| Started | Aug 29 10:44:03 AM UTC 24 |
| Finished | Aug 29 10:47:05 AM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043460579 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.3043460579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.144345085 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 19584000 ps |
| CPU time | 22.14 seconds |
| Started | Aug 29 10:44:07 AM UTC 24 |
| Finished | Aug 29 10:44:30 AM UTC 24 |
| Peak memory | 275512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144345085 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.144345085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.1316885583 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 71711900 ps |
| CPU time | 45.53 seconds |
| Started | Aug 29 10:44:14 AM UTC 24 |
| Finished | Aug 29 10:45:01 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316885583 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.1316885583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.2747535468 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 54719700 ps |
| CPU time | 32.37 seconds |
| Started | Aug 29 10:44:15 AM UTC 24 |
| Finished | Aug 29 10:44:49 AM UTC 24 |
| Peak memory | 281616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2747535468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c trl_rw_evict_all_en.2747535468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.2509582367 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 573500900 ps |
| CPU time | 72.5 seconds |
| Started | Aug 29 10:44:18 AM UTC 24 |
| Finished | Aug 29 10:45:32 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509582367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2509582367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.3509496560 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 143209200 ps |
| CPU time | 204.43 seconds |
| Started | Aug 29 10:44:02 AM UTC 24 |
| Finished | Aug 29 10:47:30 AM UTC 24 |
| Peak memory | 287832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509496560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3509496560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3724158038 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 33211700 ps |
| CPU time | 27.31 seconds |
| Started | Aug 29 09:57:09 AM UTC 24 |
| Finished | Aug 29 09:57:38 AM UTC 24 |
| Peak memory | 269524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724158038 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3724158038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2638152758 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 186562800 ps |
| CPU time | 23.66 seconds |
| Started | Aug 29 09:56:50 AM UTC 24 |
| Finished | Aug 29 09:57:15 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638152758 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2638152758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2337257138 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 17342100 ps |
| CPU time | 24.4 seconds |
| Started | Aug 29 09:56:33 AM UTC 24 |
| Finished | Aug 29 09:56:59 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337257138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2337257138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1768803089 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2728562600 ps |
| CPU time | 240.7 seconds |
| Started | Aug 29 09:54:44 AM UTC 24 |
| Finished | Aug 29 09:58:49 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1768803089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.1768803089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3868341403 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 16346300 ps |
| CPU time | 36.53 seconds |
| Started | Aug 29 09:55:51 AM UTC 24 |
| Finished | Aug 29 09:56:29 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3868341403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_disable.3868341403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.1447869934 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 3082328400 ps |
| CPU time | 634.65 seconds |
| Started | Aug 29 09:51:33 AM UTC 24 |
| Finished | Aug 29 10:02:16 AM UTC 24 |
| Peak memory | 275536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447869934 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1447869934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1121050947 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4989296200 ps |
| CPU time | 3133.08 seconds |
| Started | Aug 29 09:52:35 AM UTC 24 |
| Finished | Aug 29 10:45:21 AM UTC 24 |
| Peak memory | 276008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121050947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1121050947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3573817722 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 349070000 ps |
| CPU time | 1202.37 seconds |
| Started | Aug 29 09:52:31 AM UTC 24 |
| Finished | Aug 29 10:12:47 AM UTC 24 |
| Peak memory | 283464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573817722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3573817722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.1764253509 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 664536200 ps |
| CPU time | 52.99 seconds |
| Started | Aug 29 09:56:34 AM UTC 24 |
| Finished | Aug 29 09:57:28 AM UTC 24 |
| Peak memory | 273320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764253 509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.1764253509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.3916721297 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 81038600200 ps |
| CPU time | 2809.82 seconds |
| Started | Aug 29 09:52:08 AM UTC 24 |
| Finished | Aug 29 10:39:29 AM UTC 24 |
| Peak memory | 277920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916721297 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.3916721297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.3883604787 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 87260500 ps |
| CPU time | 71.58 seconds |
| Started | Aug 29 09:51:21 AM UTC 24 |
| Finished | Aug 29 09:52:34 AM UTC 24 |
| Peak memory | 275540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883604787 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3883604787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3075454182 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 10012426900 ps |
| CPU time | 100.02 seconds |
| Started | Aug 29 09:57:07 AM UTC 24 |
| Finished | Aug 29 09:58:49 AM UTC 24 |
| Peak memory | 302084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3075454182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3075454182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.1944144170 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 25511600 ps |
| CPU time | 21.82 seconds |
| Started | Aug 29 09:57:00 AM UTC 24 |
| Finished | Aug 29 09:57:23 AM UTC 24 |
| Peak memory | 271336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1944144170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1944144170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1086806603 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 40122201400 ps |
| CPU time | 910.55 seconds |
| Started | Aug 29 09:51:38 AM UTC 24 |
| Finished | Aug 29 10:07:00 AM UTC 24 |
| Peak memory | 275432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086806603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.1086806603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.373827168 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 25390636300 ps |
| CPU time | 643.66 seconds |
| Started | Aug 29 09:54:53 AM UTC 24 |
| Finished | Aug 29 10:05:45 AM UTC 24 |
| Peak memory | 345108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=373827168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integrity.373827168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1663277987 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4524406000 ps |
| CPU time | 170.95 seconds |
| Started | Aug 29 09:54:54 AM UTC 24 |
| Finished | Aug 29 09:57:48 AM UTC 24 |
| Peak memory | 304148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663277987 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.1663277987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3464560047 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 13337307100 ps |
| CPU time | 331.16 seconds |
| Started | Aug 29 09:55:00 AM UTC 24 |
| Finished | Aug 29 10:00:36 AM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3464560047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.3464560047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1410796181 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 10678779100 ps |
| CPU time | 113.85 seconds |
| Started | Aug 29 09:54:58 AM UTC 24 |
| Finished | Aug 29 09:56:54 AM UTC 24 |
| Peak memory | 275528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410796181 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.1410796181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3688049875 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 98490430500 ps |
| CPU time | 390.93 seconds |
| Started | Aug 29 09:55:28 AM UTC 24 |
| Finished | Aug 29 10:02:04 AM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688049875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3688049875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.432656992 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1624787500 ps |
| CPU time | 96.53 seconds |
| Started | Aug 29 09:52:38 AM UTC 24 |
| Finished | Aug 29 09:54:16 AM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432656992 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.432656992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2553254726 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 14912100 ps |
| CPU time | 26.79 seconds |
| Started | Aug 29 09:56:55 AM UTC 24 |
| Finished | Aug 29 09:57:23 AM UTC 24 |
| Peak memory | 271408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2553254726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_lcmgr_intg.2553254726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.3651579659 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 67072143100 ps |
| CPU time | 478.09 seconds |
| Started | Aug 29 09:51:59 AM UTC 24 |
| Finished | Aug 29 10:00:04 AM UTC 24 |
| Peak memory | 283532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3651579659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.3651579659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.4158012883 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5023139100 ps |
| CPU time | 203.41 seconds |
| Started | Aug 29 09:54:47 AM UTC 24 |
| Finished | Aug 29 09:58:14 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4158012883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.4158012883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.4072622939 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 7190274800 ps |
| CPU time | 539.71 seconds |
| Started | Aug 29 09:51:27 AM UTC 24 |
| Finished | Aug 29 10:00:33 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072622939 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.4072622939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3265520139 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 829667700 ps |
| CPU time | 27.37 seconds |
| Started | Aug 29 09:56:38 AM UTC 24 |
| Finished | Aug 29 09:57:06 AM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3265520139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3265520139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.3522545633 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 57362200 ps |
| CPU time | 24.73 seconds |
| Started | Aug 29 09:55:29 AM UTC 24 |
| Finished | Aug 29 09:55:55 AM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522545633 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.3522545633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2905885385 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3244608200 ps |
| CPU time | 444.24 seconds |
| Started | Aug 29 09:51:17 AM UTC 24 |
| Finished | Aug 29 09:58:46 AM UTC 24 |
| Peak memory | 291920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905885385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2905885385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1147843281 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1492382300 ps |
| CPU time | 194.21 seconds |
| Started | Aug 29 09:51:21 AM UTC 24 |
| Finished | Aug 29 09:54:38 AM UTC 24 |
| Peak memory | 273284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147843281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1147843281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.379467361 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 72432400 ps |
| CPU time | 66.93 seconds |
| Started | Aug 29 09:55:40 AM UTC 24 |
| Finished | Aug 29 09:56:49 AM UTC 24 |
| Peak memory | 283896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379467361 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.379467361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.4251157126 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 30982900 ps |
| CPU time | 38.27 seconds |
| Started | Aug 29 09:54:19 AM UTC 24 |
| Finished | Aug 29 09:54:59 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4251157126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_read_word_sweep_derr.4251157126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.4277343392 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 22632100 ps |
| CPU time | 38.06 seconds |
| Started | Aug 29 09:53:07 AM UTC 24 |
| Finished | Aug 29 09:53:47 AM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277343392 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.4277343392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.68656208 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1165880800 ps |
| CPU time | 111.63 seconds |
| Started | Aug 29 09:52:58 AM UTC 24 |
| Finished | Aug 29 09:54:52 AM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=68656208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.68656208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.395177821 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2691266200 ps |
| CPU time | 156.03 seconds |
| Started | Aug 29 09:54:37 AM UTC 24 |
| Finished | Aug 29 09:57:16 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395177821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.395177821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.259466905 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 728792400 ps |
| CPU time | 158.65 seconds |
| Started | Aug 29 09:53:45 AM UTC 24 |
| Finished | Aug 29 09:56:27 AM UTC 24 |
| Peak memory | 306260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=259466905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ ctrl_ro_serr.259466905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.2578099710 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 6202872600 ps |
| CPU time | 401.5 seconds |
| Started | Aug 29 09:53:04 AM UTC 24 |
| Finished | Aug 29 09:59:51 AM UTC 24 |
| Peak memory | 322572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578099710 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.2578099710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.157973972 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29186300 ps |
| CPU time | 61.39 seconds |
| Started | Aug 29 09:55:29 AM UTC 24 |
| Finished | Aug 29 09:56:32 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157973972 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.157973972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.2552854034 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2283559100 ps |
| CPU time | 212.97 seconds |
| Started | Aug 29 09:53:48 AM UTC 24 |
| Finished | Aug 29 09:57:24 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2552854034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.2552854034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2063598168 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2598378500 ps |
| CPU time | 87.75 seconds |
| Started | Aug 29 09:56:28 AM UTC 24 |
| Finished | Aug 29 09:57:58 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063598168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2063598168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.5739797 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 9570957500 ps |
| CPU time | 88.33 seconds |
| Started | Aug 29 09:54:19 AM UTC 24 |
| Finished | Aug 29 09:55:50 AM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573 9797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr_a ddress.5739797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3588080972 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1333171900 ps |
| CPU time | 102.75 seconds |
| Started | Aug 29 09:53:54 AM UTC 24 |
| Finished | Aug 29 09:55:39 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 88080972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se rr_counter.3588080972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.4035222634 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 157745400 ps |
| CPU time | 216.65 seconds |
| Started | Aug 29 09:51:12 AM UTC 24 |
| Finished | Aug 29 09:54:53 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035222634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.4035222634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.4039477941 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 110920800 ps |
| CPU time | 48.06 seconds |
| Started | Aug 29 09:51:16 AM UTC 24 |
| Finished | Aug 29 09:52:06 AM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039477941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.4039477941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2687062062 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 333350600 ps |
| CPU time | 1553.09 seconds |
| Started | Aug 29 09:56:30 AM UTC 24 |
| Finished | Aug 29 10:22:39 AM UTC 24 |
| Peak memory | 293896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687062062 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.2687062062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3164381593 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 43142300 ps |
| CPU time | 48.61 seconds |
| Started | Aug 29 09:51:17 AM UTC 24 |
| Finished | Aug 29 09:52:07 AM UTC 24 |
| Peak memory | 271308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164381593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3164381593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.762310701 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6573681900 ps |
| CPU time | 147.38 seconds |
| Started | Aug 29 09:52:58 AM UTC 24 |
| Finished | Aug 29 09:55:28 AM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =762310701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.762310701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.3880611133 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 129093600 ps |
| CPU time | 27.91 seconds |
| Started | Aug 29 10:44:55 AM UTC 24 |
| Finished | Aug 29 10:45:24 AM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880611133 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.3880611133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.2738499730 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 42682900 ps |
| CPU time | 24.81 seconds |
| Started | Aug 29 10:44:54 AM UTC 24 |
| Finished | Aug 29 10:45:20 AM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738499730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2738499730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.2827698608 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 10659800 ps |
| CPU time | 34.22 seconds |
| Started | Aug 29 10:44:49 AM UTC 24 |
| Finished | Aug 29 10:45:25 AM UTC 24 |
| Peak memory | 285788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2827698608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ ctrl_disable.2827698608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.4272133470 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 965780200 ps |
| CPU time | 84.74 seconds |
| Started | Aug 29 10:44:30 AM UTC 24 |
| Finished | Aug 29 10:45:56 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272133470 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.4272133470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.711698907 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 644570600 ps |
| CPU time | 145.34 seconds |
| Started | Aug 29 10:44:33 AM UTC 24 |
| Finished | Aug 29 10:47:01 AM UTC 24 |
| Peak memory | 304148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711698907 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.711698907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.292812953 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 5763494900 ps |
| CPU time | 148.38 seconds |
| Started | Aug 29 10:44:42 AM UTC 24 |
| Finished | Aug 29 10:47:13 AM UTC 24 |
| Peak memory | 304044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=292812953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 30.flash_ctrl_intr_rd_slow_flash.292812953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.3510956770 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 41203100 ps |
| CPU time | 229.78 seconds |
| Started | Aug 29 10:44:31 AM UTC 24 |
| Finished | Aug 29 10:48:24 AM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510956770 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.3510956770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.1099395369 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 41041900 ps |
| CPU time | 33.52 seconds |
| Started | Aug 29 10:44:44 AM UTC 24 |
| Finished | Aug 29 10:45:19 AM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099395369 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.1099395369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.2321410952 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 28582000 ps |
| CPU time | 51.44 seconds |
| Started | Aug 29 10:44:45 AM UTC 24 |
| Finished | Aug 29 10:45:39 AM UTC 24 |
| Peak memory | 285676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2321410952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_rw_evict_all_en.2321410952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.2564360397 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1339145400 ps |
| CPU time | 62.54 seconds |
| Started | Aug 29 10:44:53 AM UTC 24 |
| Finished | Aug 29 10:45:57 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564360397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2564360397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.757266508 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 142055800 ps |
| CPU time | 139.92 seconds |
| Started | Aug 29 10:44:29 AM UTC 24 |
| Finished | Aug 29 10:46:51 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757266508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.757266508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.1261369132 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 84179700 ps |
| CPU time | 22.02 seconds |
| Started | Aug 29 10:45:21 AM UTC 24 |
| Finished | Aug 29 10:45:44 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261369132 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.1261369132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.2494738448 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 111535800 ps |
| CPU time | 24.67 seconds |
| Started | Aug 29 10:45:20 AM UTC 24 |
| Finished | Aug 29 10:45:46 AM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494738448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2494738448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.506462355 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21988900 ps |
| CPU time | 36.65 seconds |
| Started | Aug 29 10:45:10 AM UTC 24 |
| Finished | Aug 29 10:45:48 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=506462355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_disable.506462355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.1296779975 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5605725700 ps |
| CPU time | 222.44 seconds |
| Started | Aug 29 10:44:55 AM UTC 24 |
| Finished | Aug 29 10:48:41 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296779975 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.1296779975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.2157002143 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1041405500 ps |
| CPU time | 142.3 seconds |
| Started | Aug 29 10:44:58 AM UTC 24 |
| Finished | Aug 29 10:47:23 AM UTC 24 |
| Peak memory | 306196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157002143 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.2157002143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3474550124 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 48940694000 ps |
| CPU time | 389.89 seconds |
| Started | Aug 29 10:45:02 AM UTC 24 |
| Finished | Aug 29 10:51:38 AM UTC 24 |
| Peak memory | 306216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3474550124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.flash_ctrl_intr_rd_slow_flash.3474550124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2024979495 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 60413300 ps |
| CPU time | 178.03 seconds |
| Started | Aug 29 10:44:55 AM UTC 24 |
| Finished | Aug 29 10:47:56 AM UTC 24 |
| Peak memory | 271268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024979495 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2024979495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.3109777519 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 76293200 ps |
| CPU time | 35.66 seconds |
| Started | Aug 29 10:45:05 AM UTC 24 |
| Finished | Aug 29 10:45:42 AM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109777519 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.3109777519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.3499227724 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 28426400 ps |
| CPU time | 38.98 seconds |
| Started | Aug 29 10:45:08 AM UTC 24 |
| Finished | Aug 29 10:45:49 AM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3499227724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_rw_evict_all_en.3499227724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.3007299729 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 645649500 ps |
| CPU time | 89.09 seconds |
| Started | Aug 29 10:45:10 AM UTC 24 |
| Finished | Aug 29 10:46:41 AM UTC 24 |
| Peak memory | 275480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007299729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3007299729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.2045802933 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 29428200 ps |
| CPU time | 86.86 seconds |
| Started | Aug 29 10:44:55 AM UTC 24 |
| Finished | Aug 29 10:46:24 AM UTC 24 |
| Peak memory | 287664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045802933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2045802933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2145849777 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 19412600 ps |
| CPU time | 24.72 seconds |
| Started | Aug 29 10:45:40 AM UTC 24 |
| Finished | Aug 29 10:46:06 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145849777 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.2145849777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.2941030818 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 15732700 ps |
| CPU time | 28.28 seconds |
| Started | Aug 29 10:45:39 AM UTC 24 |
| Finished | Aug 29 10:46:09 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941030818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2941030818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.785287564 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 24044500 ps |
| CPU time | 36.27 seconds |
| Started | Aug 29 10:45:33 AM UTC 24 |
| Finished | Aug 29 10:46:11 AM UTC 24 |
| Peak memory | 285724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=785287564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_disable.785287564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.1332766388 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 706344300 ps |
| CPU time | 72.13 seconds |
| Started | Aug 29 10:45:22 AM UTC 24 |
| Finished | Aug 29 10:46:36 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332766388 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.1332766388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2026792332 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 12899909600 ps |
| CPU time | 315.16 seconds |
| Started | Aug 29 10:45:25 AM UTC 24 |
| Finished | Aug 29 10:50:45 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2026792332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.flash_ctrl_intr_rd_slow_flash.2026792332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.3979836373 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 50849300 ps |
| CPU time | 215.12 seconds |
| Started | Aug 29 10:45:22 AM UTC 24 |
| Finished | Aug 29 10:49:01 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979836373 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.3979836373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.2681095207 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 145790300 ps |
| CPU time | 50.91 seconds |
| Started | Aug 29 10:45:27 AM UTC 24 |
| Finished | Aug 29 10:46:19 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681095207 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.2681095207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2870154523 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 27050700 ps |
| CPU time | 46.42 seconds |
| Started | Aug 29 10:45:32 AM UTC 24 |
| Finished | Aug 29 10:46:20 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2870154523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_rw_evict_all_en.2870154523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.753856360 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1693879900 ps |
| CPU time | 72.32 seconds |
| Started | Aug 29 10:45:38 AM UTC 24 |
| Finished | Aug 29 10:46:52 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753856360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.753856360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.2308318060 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 75885300 ps |
| CPU time | 109.09 seconds |
| Started | Aug 29 10:45:22 AM UTC 24 |
| Finished | Aug 29 10:47:13 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308318060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2308318060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.523859121 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 51086600 ps |
| CPU time | 23.71 seconds |
| Started | Aug 29 10:45:58 AM UTC 24 |
| Finished | Aug 29 10:46:22 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523859121 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.523859121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.2022814839 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 17006100 ps |
| CPU time | 31.56 seconds |
| Started | Aug 29 10:45:57 AM UTC 24 |
| Finished | Aug 29 10:46:30 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022814839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2022814839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.3323638484 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 48645992200 ps |
| CPU time | 204.85 seconds |
| Started | Aug 29 10:45:42 AM UTC 24 |
| Finished | Aug 29 10:49:10 AM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323638484 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.3323638484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3705111108 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 3905444700 ps |
| CPU time | 237.5 seconds |
| Started | Aug 29 10:45:45 AM UTC 24 |
| Finished | Aug 29 10:49:46 AM UTC 24 |
| Peak memory | 293904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705111108 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.3705111108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.408996452 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 24973041300 ps |
| CPU time | 267.67 seconds |
| Started | Aug 29 10:45:47 AM UTC 24 |
| Finished | Aug 29 10:50:18 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=408996452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 33.flash_ctrl_intr_rd_slow_flash.408996452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.1186257574 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 146095800 ps |
| CPU time | 171.29 seconds |
| Started | Aug 29 10:45:43 AM UTC 24 |
| Finished | Aug 29 10:48:37 AM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186257574 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.1186257574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.3673251920 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 31957200 ps |
| CPU time | 52.76 seconds |
| Started | Aug 29 10:45:49 AM UTC 24 |
| Finished | Aug 29 10:46:43 AM UTC 24 |
| Peak memory | 287984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673251920 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.3673251920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.689193804 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 58752400 ps |
| CPU time | 33.13 seconds |
| Started | Aug 29 10:45:50 AM UTC 24 |
| Finished | Aug 29 10:46:24 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=689193804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ct rl_rw_evict_all_en.689193804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.2887443128 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 590509300 ps |
| CPU time | 65.22 seconds |
| Started | Aug 29 10:45:56 AM UTC 24 |
| Finished | Aug 29 10:47:03 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887443128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2887443128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3150111830 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 6765564800 ps |
| CPU time | 230.27 seconds |
| Started | Aug 29 10:45:41 AM UTC 24 |
| Finished | Aug 29 10:49:35 AM UTC 24 |
| Peak memory | 291660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150111830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3150111830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.1526737450 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 56703900 ps |
| CPU time | 26.69 seconds |
| Started | Aug 29 10:46:23 AM UTC 24 |
| Finished | Aug 29 10:46:51 AM UTC 24 |
| Peak memory | 269500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526737450 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.1526737450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.2987257259 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 96956500 ps |
| CPU time | 19.13 seconds |
| Started | Aug 29 10:46:21 AM UTC 24 |
| Finished | Aug 29 10:46:42 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987257259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2987257259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.2884171038 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 24585100 ps |
| CPU time | 37.07 seconds |
| Started | Aug 29 10:46:20 AM UTC 24 |
| Finished | Aug 29 10:46:59 AM UTC 24 |
| Peak memory | 285892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2884171038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ ctrl_disable.2884171038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.4143210482 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2402084700 ps |
| CPU time | 77.57 seconds |
| Started | Aug 29 10:46:07 AM UTC 24 |
| Finished | Aug 29 10:47:26 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143210482 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.4143210482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2875406265 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 628865500 ps |
| CPU time | 130.32 seconds |
| Started | Aug 29 10:46:10 AM UTC 24 |
| Finished | Aug 29 10:48:23 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875406265 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2875406265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3324646161 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 23752678500 ps |
| CPU time | 155.35 seconds |
| Started | Aug 29 10:46:12 AM UTC 24 |
| Finished | Aug 29 10:48:50 AM UTC 24 |
| Peak memory | 301988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3324646161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.3324646161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.316181298 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 36946300 ps |
| CPU time | 179.92 seconds |
| Started | Aug 29 10:46:07 AM UTC 24 |
| Finished | Aug 29 10:49:10 AM UTC 24 |
| Peak memory | 275484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316181298 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.316181298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.2144409994 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 42033700 ps |
| CPU time | 55.11 seconds |
| Started | Aug 29 10:46:17 AM UTC 24 |
| Finished | Aug 29 10:47:14 AM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144409994 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.2144409994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.1393705483 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 49618100 ps |
| CPU time | 53.37 seconds |
| Started | Aug 29 10:46:18 AM UTC 24 |
| Finished | Aug 29 10:47:13 AM UTC 24 |
| Peak memory | 287720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1393705483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.1393705483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.3221210569 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1873290200 ps |
| CPU time | 79.14 seconds |
| Started | Aug 29 10:46:20 AM UTC 24 |
| Finished | Aug 29 10:47:42 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221210569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3221210569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1856506778 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 27723700 ps |
| CPU time | 84.02 seconds |
| Started | Aug 29 10:46:04 AM UTC 24 |
| Finished | Aug 29 10:47:30 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856506778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1856506778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.2138751224 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 89955400 ps |
| CPU time | 16.11 seconds |
| Started | Aug 29 10:46:51 AM UTC 24 |
| Finished | Aug 29 10:47:08 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138751224 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.2138751224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2029905946 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 51631900 ps |
| CPU time | 32.22 seconds |
| Started | Aug 29 10:46:44 AM UTC 24 |
| Finished | Aug 29 10:47:17 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029905946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2029905946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.1531366770 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 28256900 ps |
| CPU time | 44.84 seconds |
| Started | Aug 29 10:46:43 AM UTC 24 |
| Finished | Aug 29 10:47:29 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1531366770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ ctrl_disable.1531366770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.584380721 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 11238521500 ps |
| CPU time | 169.79 seconds |
| Started | Aug 29 10:46:25 AM UTC 24 |
| Finished | Aug 29 10:49:18 AM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584380721 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.584380721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.356635871 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 5892163400 ps |
| CPU time | 234.39 seconds |
| Started | Aug 29 10:46:31 AM UTC 24 |
| Finished | Aug 29 10:50:29 AM UTC 24 |
| Peak memory | 302260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356635871 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.356635871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3548575450 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 18447319700 ps |
| CPU time | 308.47 seconds |
| Started | Aug 29 10:46:32 AM UTC 24 |
| Finished | Aug 29 10:51:45 AM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3548575450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.flash_ctrl_intr_rd_slow_flash.3548575450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.3696727239 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 81646700 ps |
| CPU time | 201.49 seconds |
| Started | Aug 29 10:46:25 AM UTC 24 |
| Finished | Aug 29 10:49:50 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696727239 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.3696727239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3771681559 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 49646100 ps |
| CPU time | 42.28 seconds |
| Started | Aug 29 10:46:37 AM UTC 24 |
| Finished | Aug 29 10:47:21 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771681559 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.3771681559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3024769165 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 29244500 ps |
| CPU time | 47.57 seconds |
| Started | Aug 29 10:46:41 AM UTC 24 |
| Finished | Aug 29 10:47:30 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3024769165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_rw_evict_all_en.3024769165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.3455088613 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 33209800 ps |
| CPU time | 123.11 seconds |
| Started | Aug 29 10:46:24 AM UTC 24 |
| Finished | Aug 29 10:48:29 AM UTC 24 |
| Peak memory | 287632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455088613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3455088613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.513364973 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 61079000 ps |
| CPU time | 24.91 seconds |
| Started | Aug 29 10:47:14 AM UTC 24 |
| Finished | Aug 29 10:47:40 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513364973 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.513364973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2488962266 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 15950700 ps |
| CPU time | 22.07 seconds |
| Started | Aug 29 10:47:09 AM UTC 24 |
| Finished | Aug 29 10:47:32 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488962266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2488962266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.2469192006 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 12648100 ps |
| CPU time | 40.04 seconds |
| Started | Aug 29 10:47:04 AM UTC 24 |
| Finished | Aug 29 10:47:45 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2469192006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ ctrl_disable.2469192006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.815651286 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4296877300 ps |
| CPU time | 120.79 seconds |
| Started | Aug 29 10:46:52 AM UTC 24 |
| Finished | Aug 29 10:48:55 AM UTC 24 |
| Peak memory | 273152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815651286 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.815651286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.3491519841 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 624761300 ps |
| CPU time | 157.2 seconds |
| Started | Aug 29 10:46:55 AM UTC 24 |
| Finished | Aug 29 10:49:35 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491519841 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.3491519841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3813855840 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 29571801800 ps |
| CPU time | 315.42 seconds |
| Started | Aug 29 10:46:57 AM UTC 24 |
| Finished | Aug 29 10:52:17 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3813855840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.flash_ctrl_intr_rd_slow_flash.3813855840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.1029322358 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 181072500 ps |
| CPU time | 206.73 seconds |
| Started | Aug 29 10:46:53 AM UTC 24 |
| Finished | Aug 29 10:50:23 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029322358 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.1029322358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.2912475156 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 29204000 ps |
| CPU time | 35.96 seconds |
| Started | Aug 29 10:46:59 AM UTC 24 |
| Finished | Aug 29 10:47:37 AM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912475156 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.2912475156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.2149986871 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 31097800 ps |
| CPU time | 58.04 seconds |
| Started | Aug 29 10:47:02 AM UTC 24 |
| Finished | Aug 29 10:48:01 AM UTC 24 |
| Peak memory | 285872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2149986871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_rw_evict_all_en.2149986871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.2083760392 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1571824000 ps |
| CPU time | 65.06 seconds |
| Started | Aug 29 10:47:06 AM UTC 24 |
| Finished | Aug 29 10:48:12 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083760392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2083760392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.3053234831 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 26755100 ps |
| CPU time | 262.09 seconds |
| Started | Aug 29 10:46:52 AM UTC 24 |
| Finished | Aug 29 10:51:18 AM UTC 24 |
| Peak memory | 291724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053234831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3053234831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1061969609 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 45324700 ps |
| CPU time | 15.31 seconds |
| Started | Aug 29 10:47:29 AM UTC 24 |
| Finished | Aug 29 10:47:46 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061969609 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.1061969609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.2551648684 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 16259300 ps |
| CPU time | 26.12 seconds |
| Started | Aug 29 10:47:27 AM UTC 24 |
| Finished | Aug 29 10:47:55 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551648684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2551648684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.1574029090 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 10211800 ps |
| CPU time | 41.69 seconds |
| Started | Aug 29 10:47:27 AM UTC 24 |
| Finished | Aug 29 10:48:10 AM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1574029090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ ctrl_disable.1574029090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1881417525 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 4552745400 ps |
| CPU time | 70.91 seconds |
| Started | Aug 29 10:47:14 AM UTC 24 |
| Finished | Aug 29 10:48:27 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881417525 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.1881417525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.3858057407 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 19679672800 ps |
| CPU time | 205.62 seconds |
| Started | Aug 29 10:47:19 AM UTC 24 |
| Finished | Aug 29 10:50:48 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858057407 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.3858057407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3917630513 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 24185188700 ps |
| CPU time | 132.47 seconds |
| Started | Aug 29 10:47:19 AM UTC 24 |
| Finished | Aug 29 10:49:33 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3917630513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.flash_ctrl_intr_rd_slow_flash.3917630513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.3794801385 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 72207900 ps |
| CPU time | 187.24 seconds |
| Started | Aug 29 10:47:15 AM UTC 24 |
| Finished | Aug 29 10:50:25 AM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794801385 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.3794801385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.3478088328 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 65097800 ps |
| CPU time | 46.02 seconds |
| Started | Aug 29 10:47:22 AM UTC 24 |
| Finished | Aug 29 10:48:09 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478088328 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.3478088328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.3340346948 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 75620000 ps |
| CPU time | 52.38 seconds |
| Started | Aug 29 10:47:24 AM UTC 24 |
| Finished | Aug 29 10:48:18 AM UTC 24 |
| Peak memory | 281576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3340346948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c trl_rw_evict_all_en.3340346948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.948501143 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 6600325000 ps |
| CPU time | 66.61 seconds |
| Started | Aug 29 10:47:27 AM UTC 24 |
| Finished | Aug 29 10:48:35 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948501143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.948501143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.2359816986 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 34303000 ps |
| CPU time | 196.63 seconds |
| Started | Aug 29 10:47:14 AM UTC 24 |
| Finished | Aug 29 10:50:34 AM UTC 24 |
| Peak memory | 279432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359816986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2359816986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.110840422 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 96232500 ps |
| CPU time | 23.27 seconds |
| Started | Aug 29 10:47:56 AM UTC 24 |
| Finished | Aug 29 10:48:21 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110840422 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.110840422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2985156734 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 16995900 ps |
| CPU time | 20.07 seconds |
| Started | Aug 29 10:47:55 AM UTC 24 |
| Finished | Aug 29 10:48:17 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985156734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2985156734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.1071079475 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 23537671300 ps |
| CPU time | 187.35 seconds |
| Started | Aug 29 10:47:31 AM UTC 24 |
| Finished | Aug 29 10:50:41 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071079475 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.1071079475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.2719950605 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 739694400 ps |
| CPU time | 160.49 seconds |
| Started | Aug 29 10:47:33 AM UTC 24 |
| Finished | Aug 29 10:50:16 AM UTC 24 |
| Peak memory | 302100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719950605 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.2719950605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.209596096 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 49529796900 ps |
| CPU time | 310.41 seconds |
| Started | Aug 29 10:47:38 AM UTC 24 |
| Finished | Aug 29 10:52:53 AM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=209596096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 38.flash_ctrl_intr_rd_slow_flash.209596096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.451994345 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 39757500 ps |
| CPU time | 194.58 seconds |
| Started | Aug 29 10:47:32 AM UTC 24 |
| Finished | Aug 29 10:50:49 AM UTC 24 |
| Peak memory | 271280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451994345 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.451994345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.2147141314 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 32027400 ps |
| CPU time | 51.29 seconds |
| Started | Aug 29 10:47:41 AM UTC 24 |
| Finished | Aug 29 10:48:34 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147141314 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.2147141314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.1271455256 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 97878800 ps |
| CPU time | 60.03 seconds |
| Started | Aug 29 10:47:43 AM UTC 24 |
| Finished | Aug 29 10:48:45 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1271455256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c trl_rw_evict_all_en.1271455256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.1538369437 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2044510200 ps |
| CPU time | 91.47 seconds |
| Started | Aug 29 10:47:46 AM UTC 24 |
| Finished | Aug 29 10:49:20 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538369437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1538369437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.3854588294 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 30497500 ps |
| CPU time | 84.21 seconds |
| Started | Aug 29 10:47:31 AM UTC 24 |
| Finished | Aug 29 10:48:57 AM UTC 24 |
| Peak memory | 283540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854588294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3854588294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.2380882605 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 155779600 ps |
| CPU time | 24.13 seconds |
| Started | Aug 29 10:48:24 AM UTC 24 |
| Finished | Aug 29 10:48:49 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380882605 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.2380882605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2825286478 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 42256500 ps |
| CPU time | 29.32 seconds |
| Started | Aug 29 10:48:22 AM UTC 24 |
| Finished | Aug 29 10:48:53 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825286478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2825286478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.56756571 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 10234300 ps |
| CPU time | 31.06 seconds |
| Started | Aug 29 10:48:18 AM UTC 24 |
| Finished | Aug 29 10:48:51 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=56756571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ct rl_disable.56756571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.731828063 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4561605300 ps |
| CPU time | 170.65 seconds |
| Started | Aug 29 10:48:02 AM UTC 24 |
| Finished | Aug 29 10:50:55 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731828063 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.731828063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.4137074348 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 8318490800 ps |
| CPU time | 212.22 seconds |
| Started | Aug 29 10:48:11 AM UTC 24 |
| Finished | Aug 29 10:51:47 AM UTC 24 |
| Peak memory | 302104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137074348 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.4137074348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4000572163 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 23482993700 ps |
| CPU time | 330.29 seconds |
| Started | Aug 29 10:48:11 AM UTC 24 |
| Finished | Aug 29 10:53:46 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4000572163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.4000572163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.1380509435 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 134812000 ps |
| CPU time | 211.14 seconds |
| Started | Aug 29 10:48:10 AM UTC 24 |
| Finished | Aug 29 10:51:45 AM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380509435 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.1380509435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.961692421 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 27416500 ps |
| CPU time | 37.36 seconds |
| Started | Aug 29 10:48:13 AM UTC 24 |
| Finished | Aug 29 10:48:52 AM UTC 24 |
| Peak memory | 283636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961692421 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.961692421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.436233509 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 27301700 ps |
| CPU time | 48.75 seconds |
| Started | Aug 29 10:48:17 AM UTC 24 |
| Finished | Aug 29 10:49:07 AM UTC 24 |
| Peak memory | 281592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=436233509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ct rl_rw_evict_all_en.436233509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.1532162548 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2059769400 ps |
| CPU time | 109.83 seconds |
| Started | Aug 29 10:48:21 AM UTC 24 |
| Finished | Aug 29 10:50:13 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532162548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1532162548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.3396255974 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 39858500 ps |
| CPU time | 84.96 seconds |
| Started | Aug 29 10:48:02 AM UTC 24 |
| Finished | Aug 29 10:49:29 AM UTC 24 |
| Peak memory | 285768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396255974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3396255974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1816359885 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 113069300 ps |
| CPU time | 22.24 seconds |
| Started | Aug 29 10:02:52 AM UTC 24 |
| Finished | Aug 29 10:03:15 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816359885 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1816359885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1881798932 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 20047700 ps |
| CPU time | 29.04 seconds |
| Started | Aug 29 10:02:40 AM UTC 24 |
| Finished | Aug 29 10:03:10 AM UTC 24 |
| Peak memory | 273248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881798932 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.1881798932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2909161462 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 56672000 ps |
| CPU time | 26.89 seconds |
| Started | Aug 29 10:02:14 AM UTC 24 |
| Finished | Aug 29 10:02:42 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909161462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2909161462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3035669082 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3210999200 ps |
| CPU time | 274.61 seconds |
| Started | Aug 29 10:00:37 AM UTC 24 |
| Finished | Aug 29 10:05:16 AM UTC 24 |
| Peak memory | 292048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3035669082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.3035669082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.50872241 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 17829500 ps |
| CPU time | 30.61 seconds |
| Started | Aug 29 10:01:52 AM UTC 24 |
| Finished | Aug 29 10:02:24 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=50872241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr l_disable.50872241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.3657183361 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4174663200 ps |
| CPU time | 598.98 seconds |
| Started | Aug 29 09:57:48 AM UTC 24 |
| Finished | Aug 29 10:07:54 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657183361 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3657183361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.1058874174 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4680835300 ps |
| CPU time | 2769.16 seconds |
| Started | Aug 29 09:58:48 AM UTC 24 |
| Finished | Aug 29 10:45:25 AM UTC 24 |
| Peak memory | 278048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058874174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1058874174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.1179933155 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3288109000 ps |
| CPU time | 3354.33 seconds |
| Started | Aug 29 09:58:15 AM UTC 24 |
| Finished | Aug 29 10:54:45 AM UTC 24 |
| Peak memory | 278140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 79933155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _error_prog_type.1179933155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.273715222 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1070949200 ps |
| CPU time | 1108.06 seconds |
| Started | Aug 29 09:58:47 AM UTC 24 |
| Finished | Aug 29 10:17:26 AM UTC 24 |
| Peak memory | 283464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273715222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.273715222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3752643322 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 512259800 ps |
| CPU time | 37.46 seconds |
| Started | Aug 29 09:58:07 AM UTC 24 |
| Finished | Aug 29 09:58:46 AM UTC 24 |
| Peak memory | 275540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 52643322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.3752643322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.3698332197 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 108589004700 ps |
| CPU time | 4132 seconds |
| Started | Aug 29 09:58:15 AM UTC 24 |
| Finished | Aug 29 11:07:53 AM UTC 24 |
| Peak memory | 277948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698332197 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.3698332197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1301342764 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 57168900 ps |
| CPU time | 195.07 seconds |
| Started | Aug 29 09:57:25 AM UTC 24 |
| Finished | Aug 29 10:00:43 AM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301342764 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1301342764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.330960710 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 10019428800 ps |
| CPU time | 210.53 seconds |
| Started | Aug 29 10:02:51 AM UTC 24 |
| Finished | Aug 29 10:06:24 AM UTC 24 |
| Peak memory | 308180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=330960710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.330960710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2822221603 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 15911000 ps |
| CPU time | 19.92 seconds |
| Started | Aug 29 10:02:43 AM UTC 24 |
| Finished | Aug 29 10:03:04 AM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2822221603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2822221603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.500905584 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 160173872400 ps |
| CPU time | 949.32 seconds |
| Started | Aug 29 09:57:59 AM UTC 24 |
| Finished | Aug 29 10:14:00 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500905584 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.500905584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.2617841221 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5664689500 ps |
| CPU time | 227.46 seconds |
| Started | Aug 29 09:57:39 AM UTC 24 |
| Finished | Aug 29 10:01:30 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617841221 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.2617841221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2130456381 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7721842100 ps |
| CPU time | 442.44 seconds |
| Started | Aug 29 10:00:44 AM UTC 24 |
| Finished | Aug 29 10:08:12 AM UTC 24 |
| Peak memory | 343056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2130456381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr ity.2130456381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1850684010 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3184621000 ps |
| CPU time | 218.61 seconds |
| Started | Aug 29 10:01:08 AM UTC 24 |
| Finished | Aug 29 10:04:50 AM UTC 24 |
| Peak memory | 293900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850684010 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.1850684010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.4016254371 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 33820332800 ps |
| CPU time | 294.18 seconds |
| Started | Aug 29 10:01:11 AM UTC 24 |
| Finished | Aug 29 10:06:09 AM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4016254371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_intr_rd_slow_flash.4016254371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3519031728 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1949527900 ps |
| CPU time | 90.88 seconds |
| Started | Aug 29 10:01:09 AM UTC 24 |
| Finished | Aug 29 10:02:42 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519031728 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.3519031728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3350301008 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 23451056300 ps |
| CPU time | 222.93 seconds |
| Started | Aug 29 10:01:14 AM UTC 24 |
| Finished | Aug 29 10:05:00 AM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350301008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3350301008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.4268827394 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4039484300 ps |
| CPU time | 108.38 seconds |
| Started | Aug 29 09:58:52 AM UTC 24 |
| Finished | Aug 29 10:00:43 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268827394 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.4268827394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3280229784 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 24677800 ps |
| CPU time | 24.95 seconds |
| Started | Aug 29 10:02:43 AM UTC 24 |
| Finished | Aug 29 10:03:09 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3280229784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_lcmgr_intg.3280229784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.4211780490 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1237010300 ps |
| CPU time | 99.75 seconds |
| Started | Aug 29 09:58:52 AM UTC 24 |
| Finished | Aug 29 10:00:34 AM UTC 24 |
| Peak memory | 271332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211780490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4211780490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.3693377026 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9688546900 ps |
| CPU time | 181.19 seconds |
| Started | Aug 29 09:58:04 AM UTC 24 |
| Finished | Aug 29 10:01:08 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3693377026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.3693377026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1859233411 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 349188600 ps |
| CPU time | 208.21 seconds |
| Started | Aug 29 09:58:00 AM UTC 24 |
| Finished | Aug 29 10:01:32 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859233411 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1859233411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.610853302 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2233865400 ps |
| CPU time | 170.29 seconds |
| Started | Aug 29 10:00:44 AM UTC 24 |
| Finished | Aug 29 10:03:37 AM UTC 24 |
| Peak memory | 292024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=610853302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_oversize_error.610853302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1596807341 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1401076200 ps |
| CPU time | 430.48 seconds |
| Started | Aug 29 09:57:29 AM UTC 24 |
| Finished | Aug 29 10:04:45 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596807341 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1596807341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1034776176 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 45719500 ps |
| CPU time | 24.13 seconds |
| Started | Aug 29 10:02:23 AM UTC 24 |
| Finished | Aug 29 10:02:48 AM UTC 24 |
| Peak memory | 275792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1034776176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1034776176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1658303383 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 40948700 ps |
| CPU time | 28.65 seconds |
| Started | Aug 29 10:01:22 AM UTC 24 |
| Finished | Aug 29 10:01:52 AM UTC 24 |
| Peak memory | 271428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658303383 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.1658303383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.3593174724 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 77161400 ps |
| CPU time | 405.1 seconds |
| Started | Aug 29 09:57:16 AM UTC 24 |
| Finished | Aug 29 10:04:06 AM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593174724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3593174724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.2544583095 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 802355100 ps |
| CPU time | 152.65 seconds |
| Started | Aug 29 09:57:25 AM UTC 24 |
| Finished | Aug 29 10:00:00 AM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544583095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2544583095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.3455882948 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 291562400 ps |
| CPU time | 65.17 seconds |
| Started | Aug 29 10:01:32 AM UTC 24 |
| Finished | Aug 29 10:02:39 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455882948 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.3455882948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.268119352 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 57939100 ps |
| CPU time | 43.36 seconds |
| Started | Aug 29 10:00:27 AM UTC 24 |
| Finished | Aug 29 10:01:12 AM UTC 24 |
| Peak memory | 275668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=268119352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_read_word_sweep_derr.268119352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.463580763 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 52503800 ps |
| CPU time | 33.05 seconds |
| Started | Aug 29 09:59:41 AM UTC 24 |
| Finished | Aug 29 10:00:16 AM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463580763 -assert nopostproc +U VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.463580763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.2444350793 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1106422400 ps |
| CPU time | 116.47 seconds |
| Started | Aug 29 09:59:22 AM UTC 24 |
| Finished | Aug 29 10:01:21 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2444350793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.2444350793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1692194319 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 587366900 ps |
| CPU time | 152.14 seconds |
| Started | Aug 29 10:00:33 AM UTC 24 |
| Finished | Aug 29 10:03:08 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692194319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1692194319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.257222309 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 580024100 ps |
| CPU time | 126.71 seconds |
| Started | Aug 29 09:59:51 AM UTC 24 |
| Finished | Aug 29 10:02:00 AM UTC 24 |
| Peak memory | 292048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=257222309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ ctrl_ro_serr.257222309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.156792479 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6049435100 ps |
| CPU time | 454.91 seconds |
| Started | Aug 29 09:59:31 AM UTC 24 |
| Finished | Aug 29 10:07:12 AM UTC 24 |
| Peak memory | 330924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156792479 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.156792479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2878845254 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3742689600 ps |
| CPU time | 271.63 seconds |
| Started | Aug 29 10:00:34 AM UTC 24 |
| Finished | Aug 29 10:05:10 AM UTC 24 |
| Peak memory | 300220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2878845254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_rw_derr.2878845254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3005998190 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 70557300 ps |
| CPU time | 51.1 seconds |
| Started | Aug 29 10:01:22 AM UTC 24 |
| Finished | Aug 29 10:02:14 AM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005998190 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.3005998190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1917112975 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 42893500 ps |
| CPU time | 40.52 seconds |
| Started | Aug 29 10:01:31 AM UTC 24 |
| Finished | Aug 29 10:02:13 AM UTC 24 |
| Peak memory | 287764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1917112975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_rw_evict_all_en.1917112975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.255829874 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2902621900 ps |
| CPU time | 201.16 seconds |
| Started | Aug 29 10:00:00 AM UTC 24 |
| Finished | Aug 29 10:03:29 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=255829874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.255829874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.3210042232 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 14341294500 ps |
| CPU time | 82.33 seconds |
| Started | Aug 29 10:02:05 AM UTC 24 |
| Finished | Aug 29 10:03:30 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210042232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3210042232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3906114218 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 541744600 ps |
| CPU time | 63.15 seconds |
| Started | Aug 29 10:00:16 AM UTC 24 |
| Finished | Aug 29 10:01:21 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390 6114218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.3906114218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1355955798 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1857388800 ps |
| CPU time | 59.88 seconds |
| Started | Aug 29 10:00:07 AM UTC 24 |
| Finished | Aug 29 10:01:09 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 55955798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se rr_counter.1355955798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2224765400 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 140452900 ps |
| CPU time | 144.65 seconds |
| Started | Aug 29 09:57:12 AM UTC 24 |
| Finished | Aug 29 09:59:40 AM UTC 24 |
| Peak memory | 287828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224765400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2224765400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3996959196 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 49087000 ps |
| CPU time | 49.49 seconds |
| Started | Aug 29 09:57:15 AM UTC 24 |
| Finished | Aug 29 09:58:07 AM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996959196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3996959196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.2587602784 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 185425700 ps |
| CPU time | 253.09 seconds |
| Started | Aug 29 10:02:05 AM UTC 24 |
| Finished | Aug 29 10:06:22 AM UTC 24 |
| Peak memory | 289800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587602784 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.2587602784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.511695404 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 30497900 ps |
| CPU time | 35.95 seconds |
| Started | Aug 29 09:57:23 AM UTC 24 |
| Finished | Aug 29 09:58:01 AM UTC 24 |
| Peak memory | 271240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511695404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.511695404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1857979093 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2086420700 ps |
| CPU time | 205.93 seconds |
| Started | Aug 29 09:58:52 AM UTC 24 |
| Finished | Aug 29 10:02:22 AM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1857979093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.1857979093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.495092089 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 162446600 ps |
| CPU time | 26.64 seconds |
| Started | Aug 29 10:48:36 AM UTC 24 |
| Finished | Aug 29 10:49:04 AM UTC 24 |
| Peak memory | 269296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495092089 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.495092089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.3341026259 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 19502000 ps |
| CPU time | 18.13 seconds |
| Started | Aug 29 10:48:36 AM UTC 24 |
| Finished | Aug 29 10:48:56 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341026259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3341026259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.2873658949 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 31250700 ps |
| CPU time | 32.08 seconds |
| Started | Aug 29 10:48:32 AM UTC 24 |
| Finished | Aug 29 10:49:06 AM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2873658949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ ctrl_disable.2873658949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.351846592 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 5590866800 ps |
| CPU time | 247.04 seconds |
| Started | Aug 29 10:48:28 AM UTC 24 |
| Finished | Aug 29 10:52:39 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351846592 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.351846592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.2271241144 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 42070500 ps |
| CPU time | 177.09 seconds |
| Started | Aug 29 10:48:30 AM UTC 24 |
| Finished | Aug 29 10:51:30 AM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271241144 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.2271241144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2121337823 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 1235829500 ps |
| CPU time | 78.76 seconds |
| Started | Aug 29 10:48:34 AM UTC 24 |
| Finished | Aug 29 10:49:55 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121337823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2121337823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.3732581964 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 104130900 ps |
| CPU time | 142.95 seconds |
| Started | Aug 29 10:48:26 AM UTC 24 |
| Finished | Aug 29 10:50:51 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732581964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3732581964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3341075245 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 380848400 ps |
| CPU time | 21.31 seconds |
| Started | Aug 29 10:48:53 AM UTC 24 |
| Finished | Aug 29 10:49:16 AM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341075245 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3341075245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.918655276 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 27083400 ps |
| CPU time | 24.44 seconds |
| Started | Aug 29 10:48:51 AM UTC 24 |
| Finished | Aug 29 10:49:17 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918655276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.918655276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.3256709239 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 36479300 ps |
| CPU time | 26.21 seconds |
| Started | Aug 29 10:48:50 AM UTC 24 |
| Finished | Aug 29 10:49:17 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3256709239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ ctrl_disable.3256709239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.2500925625 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4527212100 ps |
| CPU time | 130.11 seconds |
| Started | Aug 29 10:48:42 AM UTC 24 |
| Finished | Aug 29 10:50:54 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500925625 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.2500925625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.1824011521 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 36109000 ps |
| CPU time | 230.5 seconds |
| Started | Aug 29 10:48:46 AM UTC 24 |
| Finished | Aug 29 10:52:40 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824011521 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.1824011521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.3083098423 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2243890900 ps |
| CPU time | 76.76 seconds |
| Started | Aug 29 10:48:51 AM UTC 24 |
| Finished | Aug 29 10:50:10 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083098423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3083098423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.445278183 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 117784100 ps |
| CPU time | 147.64 seconds |
| Started | Aug 29 10:48:38 AM UTC 24 |
| Finished | Aug 29 10:51:09 AM UTC 24 |
| Peak memory | 277584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445278183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.445278183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.1818464066 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 16618200 ps |
| CPU time | 19.13 seconds |
| Started | Aug 29 10:49:07 AM UTC 24 |
| Finished | Aug 29 10:49:27 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818464066 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.1818464066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.1882638948 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 17123000 ps |
| CPU time | 21.07 seconds |
| Started | Aug 29 10:49:05 AM UTC 24 |
| Finished | Aug 29 10:49:27 AM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882638948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1882638948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.576717617 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 25133900 ps |
| CPU time | 38.21 seconds |
| Started | Aug 29 10:48:58 AM UTC 24 |
| Finished | Aug 29 10:49:37 AM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=576717617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_c trl_disable.576717617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.3574527753 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1719880700 ps |
| CPU time | 85.98 seconds |
| Started | Aug 29 10:48:55 AM UTC 24 |
| Finished | Aug 29 10:50:23 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574527753 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.3574527753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.2926140777 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 34857900 ps |
| CPU time | 190.93 seconds |
| Started | Aug 29 10:48:57 AM UTC 24 |
| Finished | Aug 29 10:52:11 AM UTC 24 |
| Peak memory | 271588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926140777 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.2926140777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.3728916013 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 374155600 ps |
| CPU time | 63.46 seconds |
| Started | Aug 29 10:49:02 AM UTC 24 |
| Finished | Aug 29 10:50:07 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728916013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3728916013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.2908963583 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 28016200 ps |
| CPU time | 148.37 seconds |
| Started | Aug 29 10:48:54 AM UTC 24 |
| Finished | Aug 29 10:51:25 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908963583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2908963583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.3365243478 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 79591700 ps |
| CPU time | 19.41 seconds |
| Started | Aug 29 10:49:18 AM UTC 24 |
| Finished | Aug 29 10:49:38 AM UTC 24 |
| Peak memory | 269520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365243478 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.3365243478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.2266545988 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 16135700 ps |
| CPU time | 22.16 seconds |
| Started | Aug 29 10:49:17 AM UTC 24 |
| Finished | Aug 29 10:49:40 AM UTC 24 |
| Peak memory | 284940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266545988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2266545988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.4242264521 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 6992903600 ps |
| CPU time | 109.49 seconds |
| Started | Aug 29 10:49:08 AM UTC 24 |
| Finished | Aug 29 10:51:00 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242264521 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.4242264521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.2687997935 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 126494300 ps |
| CPU time | 221.83 seconds |
| Started | Aug 29 10:49:10 AM UTC 24 |
| Finished | Aug 29 10:52:56 AM UTC 24 |
| Peak memory | 271280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687997935 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.2687997935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.4283512215 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 8570351900 ps |
| CPU time | 82.15 seconds |
| Started | Aug 29 10:49:15 AM UTC 24 |
| Finished | Aug 29 10:50:39 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283512215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.4283512215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2384249107 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 39368800 ps |
| CPU time | 81.14 seconds |
| Started | Aug 29 10:49:08 AM UTC 24 |
| Finished | Aug 29 10:50:31 AM UTC 24 |
| Peak memory | 283464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384249107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2384249107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1302575310 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 109539000 ps |
| CPU time | 23.7 seconds |
| Started | Aug 29 10:49:35 AM UTC 24 |
| Finished | Aug 29 10:50:00 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302575310 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1302575310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.2649861609 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 16009000 ps |
| CPU time | 26.34 seconds |
| Started | Aug 29 10:49:29 AM UTC 24 |
| Finished | Aug 29 10:49:58 AM UTC 24 |
| Peak memory | 285068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649861609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2649861609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.892232337 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 15513100 ps |
| CPU time | 30.63 seconds |
| Started | Aug 29 10:49:28 AM UTC 24 |
| Finished | Aug 29 10:50:01 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=892232337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_c trl_disable.892232337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.2443419408 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2289211900 ps |
| CPU time | 165.03 seconds |
| Started | Aug 29 10:49:19 AM UTC 24 |
| Finished | Aug 29 10:52:07 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443419408 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.2443419408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.1191367302 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 40383900 ps |
| CPU time | 139.73 seconds |
| Started | Aug 29 10:49:21 AM UTC 24 |
| Finished | Aug 29 10:51:43 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191367302 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.1191367302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.1494152291 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6236219600 ps |
| CPU time | 85.16 seconds |
| Started | Aug 29 10:49:28 AM UTC 24 |
| Finished | Aug 29 10:50:56 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494152291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1494152291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.27335096 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 24002800 ps |
| CPU time | 213.02 seconds |
| Started | Aug 29 10:49:18 AM UTC 24 |
| Finished | Aug 29 10:52:54 AM UTC 24 |
| Peak memory | 291732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27335096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.27335096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.1507455846 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 26964300 ps |
| CPU time | 23.65 seconds |
| Started | Aug 29 10:49:48 AM UTC 24 |
| Finished | Aug 29 10:50:13 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507455846 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.1507455846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.622007347 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 43193100 ps |
| CPU time | 18.03 seconds |
| Started | Aug 29 10:49:46 AM UTC 24 |
| Finished | Aug 29 10:50:06 AM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622007347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.622007347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.3252787617 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 12992500 ps |
| CPU time | 33.33 seconds |
| Started | Aug 29 10:49:39 AM UTC 24 |
| Finished | Aug 29 10:50:14 AM UTC 24 |
| Peak memory | 275676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3252787617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ ctrl_disable.3252787617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.1406251068 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 5907102500 ps |
| CPU time | 241.72 seconds |
| Started | Aug 29 10:49:36 AM UTC 24 |
| Finished | Aug 29 10:53:41 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406251068 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.1406251068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.1983054640 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 44743600 ps |
| CPU time | 182.48 seconds |
| Started | Aug 29 10:49:38 AM UTC 24 |
| Finished | Aug 29 10:52:43 AM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983054640 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.1983054640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.3911960152 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 1452649100 ps |
| CPU time | 89.97 seconds |
| Started | Aug 29 10:49:41 AM UTC 24 |
| Finished | Aug 29 10:51:13 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911960152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3911960152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1292063224 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 121227200 ps |
| CPU time | 159.46 seconds |
| Started | Aug 29 10:49:36 AM UTC 24 |
| Finished | Aug 29 10:52:18 AM UTC 24 |
| Peak memory | 287628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292063224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1292063224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.3000417741 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 56193100 ps |
| CPU time | 26.07 seconds |
| Started | Aug 29 10:50:06 AM UTC 24 |
| Finished | Aug 29 10:50:33 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000417741 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.3000417741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.2487326329 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 38937300 ps |
| CPU time | 27.03 seconds |
| Started | Aug 29 10:50:02 AM UTC 24 |
| Finished | Aug 29 10:50:30 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487326329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2487326329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.665197687 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 15203300 ps |
| CPU time | 27.89 seconds |
| Started | Aug 29 10:49:59 AM UTC 24 |
| Finished | Aug 29 10:50:28 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=665197687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_c trl_disable.665197687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3397427166 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 4849037000 ps |
| CPU time | 75.69 seconds |
| Started | Aug 29 10:49:55 AM UTC 24 |
| Finished | Aug 29 10:51:12 AM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397427166 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.3397427166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.808270206 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 75056500 ps |
| CPU time | 240.75 seconds |
| Started | Aug 29 10:49:56 AM UTC 24 |
| Finished | Aug 29 10:54:00 AM UTC 24 |
| Peak memory | 271276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808270206 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.808270206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1772448449 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 133859700 ps |
| CPU time | 206.06 seconds |
| Started | Aug 29 10:49:50 AM UTC 24 |
| Finished | Aug 29 10:53:20 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772448449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1772448449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.2816072508 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 52983300 ps |
| CPU time | 29.54 seconds |
| Started | Aug 29 10:50:17 AM UTC 24 |
| Finished | Aug 29 10:50:48 AM UTC 24 |
| Peak memory | 269328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816072508 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.2816072508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.2515402229 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 27386400 ps |
| CPU time | 20.8 seconds |
| Started | Aug 29 10:50:15 AM UTC 24 |
| Finished | Aug 29 10:50:37 AM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515402229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2515402229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.569623518 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 22746900 ps |
| CPU time | 36.38 seconds |
| Started | Aug 29 10:50:15 AM UTC 24 |
| Finished | Aug 29 10:50:52 AM UTC 24 |
| Peak memory | 285752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=569623518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_c trl_disable.569623518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.4068511450 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2049482900 ps |
| CPU time | 106.49 seconds |
| Started | Aug 29 10:50:08 AM UTC 24 |
| Finished | Aug 29 10:51:57 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068511450 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.4068511450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3883882315 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 127363500 ps |
| CPU time | 201.45 seconds |
| Started | Aug 29 10:50:10 AM UTC 24 |
| Finished | Aug 29 10:53:36 AM UTC 24 |
| Peak memory | 271136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883882315 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.3883882315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.1931847202 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 1352248000 ps |
| CPU time | 66.49 seconds |
| Started | Aug 29 10:50:15 AM UTC 24 |
| Finished | Aug 29 10:51:23 AM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931847202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1931847202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1145134112 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 37694900 ps |
| CPU time | 187.97 seconds |
| Started | Aug 29 10:50:07 AM UTC 24 |
| Finished | Aug 29 10:53:18 AM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145134112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.1145134112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.3186233738 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 34621300 ps |
| CPU time | 22.84 seconds |
| Started | Aug 29 10:50:32 AM UTC 24 |
| Finished | Aug 29 10:50:56 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186233738 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.3186233738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.4162745973 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 23989500 ps |
| CPU time | 19.61 seconds |
| Started | Aug 29 10:50:31 AM UTC 24 |
| Finished | Aug 29 10:50:51 AM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162745973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.4162745973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.2278842009 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 28472100 ps |
| CPU time | 27.21 seconds |
| Started | Aug 29 10:50:26 AM UTC 24 |
| Finished | Aug 29 10:50:55 AM UTC 24 |
| Peak memory | 285764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2278842009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.2278842009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.551853630 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 7721849800 ps |
| CPU time | 88.7 seconds |
| Started | Aug 29 10:50:24 AM UTC 24 |
| Finished | Aug 29 10:51:55 AM UTC 24 |
| Peak memory | 271108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551853630 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.551853630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3686439331 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 147009200 ps |
| CPU time | 156.35 seconds |
| Started | Aug 29 10:50:24 AM UTC 24 |
| Finished | Aug 29 10:53:03 AM UTC 24 |
| Peak memory | 275576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686439331 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.3686439331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.49897060 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 1676590600 ps |
| CPU time | 101.78 seconds |
| Started | Aug 29 10:50:28 AM UTC 24 |
| Finished | Aug 29 10:52:12 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49897060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.49897060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3020807572 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 113463100 ps |
| CPU time | 273.73 seconds |
| Started | Aug 29 10:50:19 AM UTC 24 |
| Finished | Aug 29 10:54:57 AM UTC 24 |
| Peak memory | 291732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020807572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3020807572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.2653970929 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 38926900 ps |
| CPU time | 18.41 seconds |
| Started | Aug 29 10:50:46 AM UTC 24 |
| Finished | Aug 29 10:51:06 AM UTC 24 |
| Peak memory | 269500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653970929 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.2653970929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.576623329 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 22484600 ps |
| CPU time | 22.01 seconds |
| Started | Aug 29 10:50:42 AM UTC 24 |
| Finished | Aug 29 10:51:06 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576623329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.576623329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1625265852 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 44489400 ps |
| CPU time | 28.63 seconds |
| Started | Aug 29 10:50:38 AM UTC 24 |
| Finished | Aug 29 10:51:08 AM UTC 24 |
| Peak memory | 285916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1625265852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ ctrl_disable.1625265852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.266126769 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 818075400 ps |
| CPU time | 71.31 seconds |
| Started | Aug 29 10:50:34 AM UTC 24 |
| Finished | Aug 29 10:51:47 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266126769 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.266126769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2711914796 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 36201500 ps |
| CPU time | 209.69 seconds |
| Started | Aug 29 10:50:35 AM UTC 24 |
| Finished | Aug 29 10:54:08 AM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711914796 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.2711914796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3214683558 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 26065600 ps |
| CPU time | 249.47 seconds |
| Started | Aug 29 10:50:32 AM UTC 24 |
| Finished | Aug 29 10:54:45 AM UTC 24 |
| Peak memory | 291912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214683558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3214683558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.4006844671 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 18152300 ps |
| CPU time | 22.96 seconds |
| Started | Aug 29 10:06:10 AM UTC 24 |
| Finished | Aug 29 10:06:35 AM UTC 24 |
| Peak memory | 275456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006844671 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.4006844671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1214243666 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 47497200 ps |
| CPU time | 29.77 seconds |
| Started | Aug 29 10:05:50 AM UTC 24 |
| Finished | Aug 29 10:06:21 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214243666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1214243666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.3172674486 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 78789300 ps |
| CPU time | 39.37 seconds |
| Started | Aug 29 10:05:47 AM UTC 24 |
| Finished | Aug 29 10:06:27 AM UTC 24 |
| Peak memory | 285880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3172674486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c trl_disable.3172674486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.557447581 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 1882418000 ps |
| CPU time | 3057.88 seconds |
| Started | Aug 29 10:03:19 AM UTC 24 |
| Finished | Aug 29 10:54:50 AM UTC 24 |
| Peak memory | 278120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557447581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.557447581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2791252472 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1012024200 ps |
| CPU time | 1260.3 seconds |
| Started | Aug 29 10:03:17 AM UTC 24 |
| Finished | Aug 29 10:24:32 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791252472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2791252472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.3058391763 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 198798200 ps |
| CPU time | 24.08 seconds |
| Started | Aug 29 10:03:11 AM UTC 24 |
| Finished | Aug 29 10:03:37 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 58391763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc h_code.3058391763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3493345715 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 10144691500 ps |
| CPU time | 58.74 seconds |
| Started | Aug 29 10:06:03 AM UTC 24 |
| Finished | Aug 29 10:07:03 AM UTC 24 |
| Peak memory | 275724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3493345715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3493345715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.810249052 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 48433400 ps |
| CPU time | 26.4 seconds |
| Started | Aug 29 10:06:01 AM UTC 24 |
| Finished | Aug 29 10:06:29 AM UTC 24 |
| Peak memory | 275432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=810249052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5 .flash_ctrl_hw_read_seed_err.810249052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.738701348 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 160173070500 ps |
| CPU time | 957.95 seconds |
| Started | Aug 29 10:03:06 AM UTC 24 |
| Finished | Aug 29 10:19:16 AM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738701348 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.738701348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.247120938 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2889122400 ps |
| CPU time | 149.94 seconds |
| Started | Aug 29 10:03:05 AM UTC 24 |
| Finished | Aug 29 10:05:37 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247120938 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.247120938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.2388812371 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1903629600 ps |
| CPU time | 248.1 seconds |
| Started | Aug 29 10:04:31 AM UTC 24 |
| Finished | Aug 29 10:08:42 AM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388812371 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.2388812371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1792693506 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 60779451100 ps |
| CPU time | 328.25 seconds |
| Started | Aug 29 10:04:47 AM UTC 24 |
| Finished | Aug 29 10:10:19 AM UTC 24 |
| Peak memory | 302252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1792693506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_intr_rd_slow_flash.1792693506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.2258117439 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5785607400 ps |
| CPU time | 116.54 seconds |
| Started | Aug 29 10:04:46 AM UTC 24 |
| Finished | Aug 29 10:06:45 AM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258117439 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.2258117439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2132236815 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 111840387100 ps |
| CPU time | 393.84 seconds |
| Started | Aug 29 10:04:51 AM UTC 24 |
| Finished | Aug 29 10:11:30 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132236815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2132236815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2547753626 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3359556900 ps |
| CPU time | 84.67 seconds |
| Started | Aug 29 10:03:19 AM UTC 24 |
| Finished | Aug 29 10:04:45 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547753626 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2547753626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1788201414 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 88690200 ps |
| CPU time | 23.52 seconds |
| Started | Aug 29 10:05:59 AM UTC 24 |
| Finished | Aug 29 10:06:24 AM UTC 24 |
| Peak memory | 271664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1788201414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.1788201414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2710779301 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 25433231400 ps |
| CPU time | 935.85 seconds |
| Started | Aug 29 10:03:10 AM UTC 24 |
| Finished | Aug 29 10:18:57 AM UTC 24 |
| Peak memory | 283536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2710779301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.2710779301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1254730681 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 43021600 ps |
| CPU time | 181.38 seconds |
| Started | Aug 29 10:03:09 AM UTC 24 |
| Finished | Aug 29 10:06:13 AM UTC 24 |
| Peak memory | 271736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254730681 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.1254730681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.1284389254 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 33497700 ps |
| CPU time | 214.58 seconds |
| Started | Aug 29 10:02:56 AM UTC 24 |
| Finished | Aug 29 10:06:34 AM UTC 24 |
| Peak memory | 275528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284389254 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1284389254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.403255554 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4418142700 ps |
| CPU time | 207.52 seconds |
| Started | Aug 29 10:05:01 AM UTC 24 |
| Finished | Aug 29 10:08:32 AM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403255554 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.403255554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1970487338 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 130964000 ps |
| CPU time | 610.84 seconds |
| Started | Aug 29 10:02:55 AM UTC 24 |
| Finished | Aug 29 10:13:13 AM UTC 24 |
| Peak memory | 291728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970487338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1970487338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.3470852358 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 121851600 ps |
| CPU time | 66.26 seconds |
| Started | Aug 29 10:05:38 AM UTC 24 |
| Finished | Aug 29 10:06:46 AM UTC 24 |
| Peak memory | 283636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470852358 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.3470852358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3916786570 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1090703100 ps |
| CPU time | 133.02 seconds |
| Started | Aug 29 10:03:31 AM UTC 24 |
| Finished | Aug 29 10:05:47 AM UTC 24 |
| Peak memory | 292028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3916786570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.3916786570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.12935849 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2431729100 ps |
| CPU time | 160.16 seconds |
| Started | Aug 29 10:04:06 AM UTC 24 |
| Finished | Aug 29 10:06:49 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12935849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.12935849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3115719077 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 621287900 ps |
| CPU time | 137.96 seconds |
| Started | Aug 29 10:03:38 AM UTC 24 |
| Finished | Aug 29 10:05:58 AM UTC 24 |
| Peak memory | 292024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3115719077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_ro_serr.3115719077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2019471493 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 51533037900 ps |
| CPU time | 586.48 seconds |
| Started | Aug 29 10:03:38 AM UTC 24 |
| Finished | Aug 29 10:13:32 AM UTC 24 |
| Peak memory | 330764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019471493 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.2019471493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.331066114 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1751825600 ps |
| CPU time | 263.27 seconds |
| Started | Aug 29 10:04:07 AM UTC 24 |
| Finished | Aug 29 10:08:35 AM UTC 24 |
| Peak memory | 291864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=331066114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_rw_derr.331066114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2381909170 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 70426600 ps |
| CPU time | 56.3 seconds |
| Started | Aug 29 10:05:17 AM UTC 24 |
| Finished | Aug 29 10:06:15 AM UTC 24 |
| Peak memory | 285876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2381909170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct rl_rw_evict_all_en.2381909170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.3326772639 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1750839900 ps |
| CPU time | 129.05 seconds |
| Started | Aug 29 10:03:49 AM UTC 24 |
| Finished | Aug 29 10:06:00 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3326772639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.3326772639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.4253278172 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3652992000 ps |
| CPU time | 90.89 seconds |
| Started | Aug 29 10:05:48 AM UTC 24 |
| Finished | Aug 29 10:07:21 AM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253278172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.4253278172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.959731597 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 21294800 ps |
| CPU time | 94.96 seconds |
| Started | Aug 29 10:02:53 AM UTC 24 |
| Finished | Aug 29 10:04:30 AM UTC 24 |
| Peak memory | 283792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959731597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.959731597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.630717682 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1828265700 ps |
| CPU time | 199.29 seconds |
| Started | Aug 29 10:03:30 AM UTC 24 |
| Finished | Aug 29 10:06:52 AM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =630717682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.630717682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.149908558 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 46949600 ps |
| CPU time | 24.08 seconds |
| Started | Aug 29 10:50:49 AM UTC 24 |
| Finished | Aug 29 10:51:14 AM UTC 24 |
| Peak memory | 295188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149908558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.149908558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.3417177173 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 49502800 ps |
| CPU time | 27.9 seconds |
| Started | Aug 29 10:50:52 AM UTC 24 |
| Finished | Aug 29 10:51:21 AM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417177173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3417177173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1845952243 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 36479100 ps |
| CPU time | 162.03 seconds |
| Started | Aug 29 10:50:50 AM UTC 24 |
| Finished | Aug 29 10:53:35 AM UTC 24 |
| Peak memory | 271280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845952243 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.1845952243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.1099338288 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 16310800 ps |
| CPU time | 28.17 seconds |
| Started | Aug 29 10:50:53 AM UTC 24 |
| Finished | Aug 29 10:51:23 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099338288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1099338288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1334903439 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 71965300 ps |
| CPU time | 181.53 seconds |
| Started | Aug 29 10:50:52 AM UTC 24 |
| Finished | Aug 29 10:53:56 AM UTC 24 |
| Peak memory | 275644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334903439 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.1334903439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.4179101370 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 101914900 ps |
| CPU time | 26.12 seconds |
| Started | Aug 29 10:50:56 AM UTC 24 |
| Finished | Aug 29 10:51:24 AM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179101370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.4179101370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3771731432 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 77399800 ps |
| CPU time | 159.6 seconds |
| Started | Aug 29 10:50:55 AM UTC 24 |
| Finished | Aug 29 10:53:37 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771731432 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.3771731432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.3053316770 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 68051900 ps |
| CPU time | 17.84 seconds |
| Started | Aug 29 10:50:56 AM UTC 24 |
| Finished | Aug 29 10:51:16 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053316770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3053316770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1389508452 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 40141600 ps |
| CPU time | 169.63 seconds |
| Started | Aug 29 10:50:56 AM UTC 24 |
| Finished | Aug 29 10:53:49 AM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389508452 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.1389508452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.2906074737 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 35872400 ps |
| CPU time | 25.71 seconds |
| Started | Aug 29 10:51:01 AM UTC 24 |
| Finished | Aug 29 10:51:28 AM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906074737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2906074737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.316455022 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 39356800 ps |
| CPU time | 181.79 seconds |
| Started | Aug 29 10:50:57 AM UTC 24 |
| Finished | Aug 29 10:54:02 AM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316455022 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.316455022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1817470523 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 27624900 ps |
| CPU time | 23.43 seconds |
| Started | Aug 29 10:51:07 AM UTC 24 |
| Finished | Aug 29 10:51:32 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817470523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1817470523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3192289125 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 48267800 ps |
| CPU time | 173.34 seconds |
| Started | Aug 29 10:51:06 AM UTC 24 |
| Finished | Aug 29 10:54:02 AM UTC 24 |
| Peak memory | 275488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192289125 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.3192289125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.486267185 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 13576500 ps |
| CPU time | 26.89 seconds |
| Started | Aug 29 10:51:09 AM UTC 24 |
| Finished | Aug 29 10:51:37 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486267185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.486267185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1509133718 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 38509500 ps |
| CPU time | 157.5 seconds |
| Started | Aug 29 10:51:07 AM UTC 24 |
| Finished | Aug 29 10:53:47 AM UTC 24 |
| Peak memory | 275832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509133718 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1509133718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.212077811 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 53087100 ps |
| CPU time | 25.64 seconds |
| Started | Aug 29 10:51:11 AM UTC 24 |
| Finished | Aug 29 10:51:38 AM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212077811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.212077811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2049802533 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 44459000 ps |
| CPU time | 185.57 seconds |
| Started | Aug 29 10:51:09 AM UTC 24 |
| Finished | Aug 29 10:54:18 AM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049802533 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.2049802533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.3088081276 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 15249300 ps |
| CPU time | 17.67 seconds |
| Started | Aug 29 10:51:15 AM UTC 24 |
| Finished | Aug 29 10:51:33 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088081276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3088081276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3319871552 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 128778200 ps |
| CPU time | 196.68 seconds |
| Started | Aug 29 10:51:13 AM UTC 24 |
| Finished | Aug 29 10:54:33 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319871552 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.3319871552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.2069060247 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 58756300 ps |
| CPU time | 27.54 seconds |
| Started | Aug 29 10:08:59 AM UTC 24 |
| Finished | Aug 29 10:09:28 AM UTC 24 |
| Peak memory | 269568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069060247 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2069060247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.4148401728 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 22390300 ps |
| CPU time | 30.1 seconds |
| Started | Aug 29 10:08:43 AM UTC 24 |
| Finished | Aug 29 10:09:15 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148401728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4148401728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.3110896465 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 52667600 ps |
| CPU time | 40.09 seconds |
| Started | Aug 29 10:08:33 AM UTC 24 |
| Finished | Aug 29 10:09:15 AM UTC 24 |
| Peak memory | 285720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3110896465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c trl_disable.3110896465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3737723063 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 4958191200 ps |
| CPU time | 3124.42 seconds |
| Started | Aug 29 10:06:36 AM UTC 24 |
| Finished | Aug 29 10:59:13 AM UTC 24 |
| Peak memory | 275928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737723063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3737723063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.4210832747 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4100761500 ps |
| CPU time | 1597.39 seconds |
| Started | Aug 29 10:06:35 AM UTC 24 |
| Finished | Aug 29 10:33:31 AM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210832747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.4210832747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2101875867 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1923548900 ps |
| CPU time | 23.27 seconds |
| Started | Aug 29 10:06:30 AM UTC 24 |
| Finished | Aug 29 10:06:54 AM UTC 24 |
| Peak memory | 273556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 01875867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc h_code.2101875867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2430092800 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 10019612900 ps |
| CPU time | 108.85 seconds |
| Started | Aug 29 10:08:59 AM UTC 24 |
| Finished | Aug 29 10:10:50 AM UTC 24 |
| Peak memory | 332808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2430092800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2430092800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1704293642 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 48478000 ps |
| CPU time | 28.46 seconds |
| Started | Aug 29 10:08:49 AM UTC 24 |
| Finished | Aug 29 10:09:19 AM UTC 24 |
| Peak memory | 271336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1704293642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1704293642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.424978123 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 40124977600 ps |
| CPU time | 809.69 seconds |
| Started | Aug 29 10:06:24 AM UTC 24 |
| Finished | Aug 29 10:20:04 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424978123 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.424978123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.3565238773 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1899578300 ps |
| CPU time | 188.81 seconds |
| Started | Aug 29 10:06:23 AM UTC 24 |
| Finished | Aug 29 10:09:36 AM UTC 24 |
| Peak memory | 273156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565238773 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.3565238773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.600814139 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 10383105300 ps |
| CPU time | 198.14 seconds |
| Started | Aug 29 10:07:13 AM UTC 24 |
| Finished | Aug 29 10:10:34 AM UTC 24 |
| Peak memory | 302092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600814139 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.600814139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3622851714 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 24118248300 ps |
| CPU time | 553.91 seconds |
| Started | Aug 29 10:07:22 AM UTC 24 |
| Finished | Aug 29 10:16:43 AM UTC 24 |
| Peak memory | 304080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3622851714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_intr_rd_slow_flash.3622851714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.417755494 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 7728219100 ps |
| CPU time | 83.9 seconds |
| Started | Aug 29 10:07:22 AM UTC 24 |
| Finished | Aug 29 10:08:48 AM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417755494 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.417755494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2154239401 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 63833964400 ps |
| CPU time | 175.34 seconds |
| Started | Aug 29 10:07:53 AM UTC 24 |
| Finished | Aug 29 10:10:51 AM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154239401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2154239401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.353767136 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2169561400 ps |
| CPU time | 63.94 seconds |
| Started | Aug 29 10:06:46 AM UTC 24 |
| Finished | Aug 29 10:07:52 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353767136 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.353767136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2538468483 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 44541500 ps |
| CPU time | 23.26 seconds |
| Started | Aug 29 10:08:44 AM UTC 24 |
| Finished | Aug 29 10:09:08 AM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2538468483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.2538468483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3304284825 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 27525131600 ps |
| CPU time | 209.5 seconds |
| Started | Aug 29 10:06:29 AM UTC 24 |
| Finished | Aug 29 10:10:02 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3304284825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3304284825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2490428600 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 74722000 ps |
| CPU time | 213.66 seconds |
| Started | Aug 29 10:06:26 AM UTC 24 |
| Finished | Aug 29 10:10:03 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490428600 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.2490428600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3638010306 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 63717500 ps |
| CPU time | 599.89 seconds |
| Started | Aug 29 10:06:22 AM UTC 24 |
| Finished | Aug 29 10:16:30 AM UTC 24 |
| Peak memory | 275536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638010306 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3638010306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.4022252946 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 18202400 ps |
| CPU time | 24.22 seconds |
| Started | Aug 29 10:07:55 AM UTC 24 |
| Finished | Aug 29 10:08:20 AM UTC 24 |
| Peak memory | 269160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022252946 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.4022252946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4073410506 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 167438900 ps |
| CPU time | 389.97 seconds |
| Started | Aug 29 10:06:16 AM UTC 24 |
| Finished | Aug 29 10:12:51 AM UTC 24 |
| Peak memory | 287628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073410506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.4073410506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3722272047 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 628256200 ps |
| CPU time | 110.16 seconds |
| Started | Aug 29 10:06:50 AM UTC 24 |
| Finished | Aug 29 10:08:42 AM UTC 24 |
| Peak memory | 291964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3722272047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.3722272047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2294254781 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 689440700 ps |
| CPU time | 183.6 seconds |
| Started | Aug 29 10:07:01 AM UTC 24 |
| Finished | Aug 29 10:10:07 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294254781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2294254781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.3655199340 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4532513200 ps |
| CPU time | 126.24 seconds |
| Started | Aug 29 10:06:53 AM UTC 24 |
| Finished | Aug 29 10:09:02 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3655199340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_ro_serr.3655199340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.1779789482 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 36332030200 ps |
| CPU time | 645.65 seconds |
| Started | Aug 29 10:06:51 AM UTC 24 |
| Finished | Aug 29 10:17:46 AM UTC 24 |
| Peak memory | 330996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779789482 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.1779789482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1554325348 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1984180200 ps |
| CPU time | 291.14 seconds |
| Started | Aug 29 10:07:04 AM UTC 24 |
| Finished | Aug 29 10:11:59 AM UTC 24 |
| Peak memory | 300028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1554325348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_rw_derr.1554325348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3257101403 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 69978300 ps |
| CPU time | 56.35 seconds |
| Started | Aug 29 10:08:00 AM UTC 24 |
| Finished | Aug 29 10:08:58 AM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257101403 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.3257101403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1048572913 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 26242900 ps |
| CPU time | 61.47 seconds |
| Started | Aug 29 10:08:13 AM UTC 24 |
| Finished | Aug 29 10:09:16 AM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1048572913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct rl_rw_evict_all_en.1048572913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1221826391 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 7587350400 ps |
| CPU time | 184.21 seconds |
| Started | Aug 29 10:06:55 AM UTC 24 |
| Finished | Aug 29 10:10:03 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1221826391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1221826391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.2503353208 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 10631579700 ps |
| CPU time | 127 seconds |
| Started | Aug 29 10:08:35 AM UTC 24 |
| Finished | Aug 29 10:10:45 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503353208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2503353208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2477117300 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 49300500 ps |
| CPU time | 172.62 seconds |
| Started | Aug 29 10:06:14 AM UTC 24 |
| Finished | Aug 29 10:09:10 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477117300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2477117300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1687472719 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 7976393100 ps |
| CPU time | 128.06 seconds |
| Started | Aug 29 10:06:47 AM UTC 24 |
| Finished | Aug 29 10:08:58 AM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1687472719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.1687472719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.173348968 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 24002600 ps |
| CPU time | 15.23 seconds |
| Started | Aug 29 10:51:17 AM UTC 24 |
| Finished | Aug 29 10:51:33 AM UTC 24 |
| Peak memory | 295380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173348968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.173348968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3088149242 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 57836100 ps |
| CPU time | 171.32 seconds |
| Started | Aug 29 10:51:15 AM UTC 24 |
| Finished | Aug 29 10:54:09 AM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088149242 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.3088149242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1839108766 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 14187300 ps |
| CPU time | 22.7 seconds |
| Started | Aug 29 10:51:22 AM UTC 24 |
| Finished | Aug 29 10:51:46 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839108766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1839108766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.761650275 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 36498100 ps |
| CPU time | 199.06 seconds |
| Started | Aug 29 10:51:19 AM UTC 24 |
| Finished | Aug 29 10:54:41 AM UTC 24 |
| Peak memory | 275424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761650275 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.761650275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3515659570 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 25368800 ps |
| CPU time | 26.64 seconds |
| Started | Aug 29 10:51:24 AM UTC 24 |
| Finished | Aug 29 10:51:52 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515659570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3515659570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.966048716 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 145440700 ps |
| CPU time | 171.84 seconds |
| Started | Aug 29 10:51:24 AM UTC 24 |
| Finished | Aug 29 10:54:19 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966048716 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.966048716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.3584060250 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 54208000 ps |
| CPU time | 22.6 seconds |
| Started | Aug 29 10:51:26 AM UTC 24 |
| Finished | Aug 29 10:51:50 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584060250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3584060250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2433416603 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 38644000 ps |
| CPU time | 187.19 seconds |
| Started | Aug 29 10:51:25 AM UTC 24 |
| Finished | Aug 29 10:54:35 AM UTC 24 |
| Peak memory | 271268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433416603 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.2433416603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.2375902247 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 44217800 ps |
| CPU time | 18.16 seconds |
| Started | Aug 29 10:51:30 AM UTC 24 |
| Finished | Aug 29 10:51:50 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375902247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2375902247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1016513331 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 149030800 ps |
| CPU time | 159.96 seconds |
| Started | Aug 29 10:51:28 AM UTC 24 |
| Finished | Aug 29 10:54:11 AM UTC 24 |
| Peak memory | 271536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016513331 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.1016513331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.3953121093 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 13366300 ps |
| CPU time | 27.8 seconds |
| Started | Aug 29 10:51:34 AM UTC 24 |
| Finished | Aug 29 10:52:03 AM UTC 24 |
| Peak memory | 284944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953121093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3953121093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2420702409 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 81367700 ps |
| CPU time | 159.03 seconds |
| Started | Aug 29 10:51:33 AM UTC 24 |
| Finished | Aug 29 10:54:14 AM UTC 24 |
| Peak memory | 271416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420702409 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.2420702409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.2635159141 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 61958200 ps |
| CPU time | 16.27 seconds |
| Started | Aug 29 10:51:38 AM UTC 24 |
| Finished | Aug 29 10:51:55 AM UTC 24 |
| Peak memory | 295372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635159141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2635159141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1197938038 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 149208700 ps |
| CPU time | 154.03 seconds |
| Started | Aug 29 10:51:35 AM UTC 24 |
| Finished | Aug 29 10:54:12 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197938038 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.1197938038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.2596693091 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 17380000 ps |
| CPU time | 20.32 seconds |
| Started | Aug 29 10:51:39 AM UTC 24 |
| Finished | Aug 29 10:52:00 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596693091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2596693091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3198079799 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 37361200 ps |
| CPU time | 176.56 seconds |
| Started | Aug 29 10:51:39 AM UTC 24 |
| Finished | Aug 29 10:54:38 AM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198079799 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.3198079799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3387461653 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 13520800 ps |
| CPU time | 21.04 seconds |
| Started | Aug 29 10:51:45 AM UTC 24 |
| Finished | Aug 29 10:52:08 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387461653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3387461653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1673656122 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 80526800 ps |
| CPU time | 180.43 seconds |
| Started | Aug 29 10:51:44 AM UTC 24 |
| Finished | Aug 29 10:54:48 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673656122 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.1673656122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.3844700653 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 20440000 ps |
| CPU time | 21.81 seconds |
| Started | Aug 29 10:51:47 AM UTC 24 |
| Finished | Aug 29 10:52:10 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844700653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3844700653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1776011042 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 42556900 ps |
| CPU time | 172.66 seconds |
| Started | Aug 29 10:51:46 AM UTC 24 |
| Finished | Aug 29 10:54:42 AM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776011042 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.1776011042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1852285165 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 22667100 ps |
| CPU time | 25.73 seconds |
| Started | Aug 29 10:12:52 AM UTC 24 |
| Finished | Aug 29 10:13:19 AM UTC 24 |
| Peak memory | 275476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852285165 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1852285165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3722675877 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 37261800 ps |
| CPU time | 37.27 seconds |
| Started | Aug 29 10:12:16 AM UTC 24 |
| Finished | Aug 29 10:12:55 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3722675877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.3722675877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3413456138 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 18892738600 ps |
| CPU time | 2955.91 seconds |
| Started | Aug 29 10:09:37 AM UTC 24 |
| Finished | Aug 29 10:59:23 AM UTC 24 |
| Peak memory | 278128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413456138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3413456138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3136728395 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 693328900 ps |
| CPU time | 951.35 seconds |
| Started | Aug 29 10:09:29 AM UTC 24 |
| Finished | Aug 29 10:25:30 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136728395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3136728395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3585049399 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 273677200 ps |
| CPU time | 37.36 seconds |
| Started | Aug 29 10:09:22 AM UTC 24 |
| Finished | Aug 29 10:10:01 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 85049399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc h_code.3585049399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3031196949 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 10011932200 ps |
| CPU time | 131.44 seconds |
| Started | Aug 29 10:12:51 AM UTC 24 |
| Finished | Aug 29 10:15:04 AM UTC 24 |
| Peak memory | 382188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3031196949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3031196949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2021101261 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 15521500 ps |
| CPU time | 19.36 seconds |
| Started | Aug 29 10:12:51 AM UTC 24 |
| Finished | Aug 29 10:13:11 AM UTC 24 |
| Peak memory | 271336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2021101261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2021101261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3440579189 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 80136560600 ps |
| CPU time | 884.17 seconds |
| Started | Aug 29 10:09:16 AM UTC 24 |
| Finished | Aug 29 10:24:11 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440579189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.3440579189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3405407122 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 29052387600 ps |
| CPU time | 298.93 seconds |
| Started | Aug 29 10:09:16 AM UTC 24 |
| Finished | Aug 29 10:14:20 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405407122 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.3405407122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.594995787 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 23233579000 ps |
| CPU time | 161.73 seconds |
| Started | Aug 29 10:11:24 AM UTC 24 |
| Finished | Aug 29 10:14:08 AM UTC 24 |
| Peak memory | 304044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=594995787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_rd_slow_flash.594995787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2645106650 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6440080900 ps |
| CPU time | 82.65 seconds |
| Started | Aug 29 10:10:51 AM UTC 24 |
| Finished | Aug 29 10:12:16 AM UTC 24 |
| Peak memory | 271424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645106650 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.2645106650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3661190994 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 30182404400 ps |
| CPU time | 348.3 seconds |
| Started | Aug 29 10:11:29 AM UTC 24 |
| Finished | Aug 29 10:17:22 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661190994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3661190994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.4148994399 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2084343300 ps |
| CPU time | 78.54 seconds |
| Started | Aug 29 10:10:02 AM UTC 24 |
| Finished | Aug 29 10:11:23 AM UTC 24 |
| Peak memory | 271108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148994399 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.4148994399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1165340634 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 58672786900 ps |
| CPU time | 499.76 seconds |
| Started | Aug 29 10:09:19 AM UTC 24 |
| Finished | Aug 29 10:17:45 AM UTC 24 |
| Peak memory | 283528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1165340634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.1165340634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3349857931 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 40382200 ps |
| CPU time | 245.91 seconds |
| Started | Aug 29 10:09:17 AM UTC 24 |
| Finished | Aug 29 10:13:27 AM UTC 24 |
| Peak memory | 273588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349857931 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.3349857931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.2661267991 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 45478300 ps |
| CPU time | 409.13 seconds |
| Started | Aug 29 10:09:11 AM UTC 24 |
| Finished | Aug 29 10:16:06 AM UTC 24 |
| Peak memory | 273224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661267991 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2661267991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.2440470729 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 108833500 ps |
| CPU time | 23.32 seconds |
| Started | Aug 29 10:11:31 AM UTC 24 |
| Finished | Aug 29 10:11:55 AM UTC 24 |
| Peak memory | 275500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440470729 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.2440470729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.885761674 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1386291700 ps |
| CPU time | 785.89 seconds |
| Started | Aug 29 10:09:09 AM UTC 24 |
| Finished | Aug 29 10:22:24 AM UTC 24 |
| Peak memory | 293776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885761674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.885761674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.509777860 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 91085600 ps |
| CPU time | 48.11 seconds |
| Started | Aug 29 10:12:00 AM UTC 24 |
| Finished | Aug 29 10:12:50 AM UTC 24 |
| Peak memory | 283832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509777860 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.509777860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1235871577 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 517156400 ps |
| CPU time | 135.3 seconds |
| Started | Aug 29 10:10:03 AM UTC 24 |
| Finished | Aug 29 10:12:22 AM UTC 24 |
| Peak memory | 291580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1235871577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.1235871577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2165264312 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3568304200 ps |
| CPU time | 132.83 seconds |
| Started | Aug 29 10:10:35 AM UTC 24 |
| Finished | Aug 29 10:12:50 AM UTC 24 |
| Peak memory | 292024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165264312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2165264312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.3827449251 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 5374893900 ps |
| CPU time | 171.04 seconds |
| Started | Aug 29 10:10:09 AM UTC 24 |
| Finished | Aug 29 10:13:03 AM UTC 24 |
| Peak memory | 306360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3827449251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_ro_serr.3827449251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1354453010 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3737189300 ps |
| CPU time | 496.83 seconds |
| Started | Aug 29 10:10:04 AM UTC 24 |
| Finished | Aug 29 10:18:27 AM UTC 24 |
| Peak memory | 324604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354453010 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.1354453010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.1056661391 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3682681200 ps |
| CPU time | 197.5 seconds |
| Started | Aug 29 10:10:46 AM UTC 24 |
| Finished | Aug 29 10:14:07 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1056661391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_rw_derr.1056661391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2552221941 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 166321300 ps |
| CPU time | 43.82 seconds |
| Started | Aug 29 10:11:55 AM UTC 24 |
| Finished | Aug 29 10:12:40 AM UTC 24 |
| Peak memory | 287752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552221941 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.2552221941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2484750425 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 59125300 ps |
| CPU time | 58.09 seconds |
| Started | Aug 29 10:11:56 AM UTC 24 |
| Finished | Aug 29 10:12:56 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2484750425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct rl_rw_evict_all_en.2484750425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.153587378 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4186671700 ps |
| CPU time | 212.55 seconds |
| Started | Aug 29 10:10:21 AM UTC 24 |
| Finished | Aug 29 10:13:57 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=153587378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.153587378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3671282385 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1883059500 ps |
| CPU time | 105.09 seconds |
| Started | Aug 29 10:12:22 AM UTC 24 |
| Finished | Aug 29 10:14:10 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671282385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3671282385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1012060452 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 40486100 ps |
| CPU time | 249.82 seconds |
| Started | Aug 29 10:09:03 AM UTC 24 |
| Finished | Aug 29 10:13:17 AM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012060452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1012060452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.3030909599 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2499465000 ps |
| CPU time | 167.87 seconds |
| Started | Aug 29 10:10:03 AM UTC 24 |
| Finished | Aug 29 10:12:54 AM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3030909599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.3030909599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.2945887935 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 14591600 ps |
| CPU time | 23.69 seconds |
| Started | Aug 29 10:51:48 AM UTC 24 |
| Finished | Aug 29 10:52:13 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945887935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2945887935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.4126266032 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 76937100 ps |
| CPU time | 179.98 seconds |
| Started | Aug 29 10:51:48 AM UTC 24 |
| Finished | Aug 29 10:54:51 AM UTC 24 |
| Peak memory | 271268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126266032 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.4126266032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.2822522287 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 41137800 ps |
| CPU time | 24.42 seconds |
| Started | Aug 29 10:51:51 AM UTC 24 |
| Finished | Aug 29 10:52:17 AM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822522287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2822522287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1332195377 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 146782400 ps |
| CPU time | 154.01 seconds |
| Started | Aug 29 10:51:51 AM UTC 24 |
| Finished | Aug 29 10:54:28 AM UTC 24 |
| Peak memory | 275364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332195377 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.1332195377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1821368969 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 27134300 ps |
| CPU time | 26.68 seconds |
| Started | Aug 29 10:51:56 AM UTC 24 |
| Finished | Aug 29 10:52:24 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821368969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1821368969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1236607269 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 145586500 ps |
| CPU time | 173.16 seconds |
| Started | Aug 29 10:51:53 AM UTC 24 |
| Finished | Aug 29 10:54:49 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236607269 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.1236607269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.3738753701 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 15610300 ps |
| CPU time | 20.66 seconds |
| Started | Aug 29 10:51:57 AM UTC 24 |
| Finished | Aug 29 10:52:19 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738753701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3738753701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.502964723 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 40396000 ps |
| CPU time | 140.64 seconds |
| Started | Aug 29 10:51:56 AM UTC 24 |
| Finished | Aug 29 10:54:19 AM UTC 24 |
| Peak memory | 275632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502964723 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.502964723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.811190420 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 44882300 ps |
| CPU time | 26.41 seconds |
| Started | Aug 29 10:52:02 AM UTC 24 |
| Finished | Aug 29 10:52:29 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811190420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.811190420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.150807844 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 73433600 ps |
| CPU time | 167.52 seconds |
| Started | Aug 29 10:51:59 AM UTC 24 |
| Finished | Aug 29 10:54:50 AM UTC 24 |
| Peak memory | 271384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150807844 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.150807844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.68745669 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 26750100 ps |
| CPU time | 29.11 seconds |
| Started | Aug 29 10:52:08 AM UTC 24 |
| Finished | Aug 29 10:52:38 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68745669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.68745669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2243063297 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 81596100 ps |
| CPU time | 167.36 seconds |
| Started | Aug 29 10:52:04 AM UTC 24 |
| Finished | Aug 29 10:54:54 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243063297 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.2243063297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3833271738 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 15721500 ps |
| CPU time | 20.57 seconds |
| Started | Aug 29 10:52:10 AM UTC 24 |
| Finished | Aug 29 10:52:32 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833271738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3833271738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3353061909 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 202828200 ps |
| CPU time | 159.68 seconds |
| Started | Aug 29 10:52:09 AM UTC 24 |
| Finished | Aug 29 10:54:51 AM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353061909 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.3353061909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.401033375 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 47041000 ps |
| CPU time | 18.72 seconds |
| Started | Aug 29 10:52:13 AM UTC 24 |
| Finished | Aug 29 10:52:33 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401033375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.401033375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.4203949908 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 40791400 ps |
| CPU time | 168.99 seconds |
| Started | Aug 29 10:52:12 AM UTC 24 |
| Finished | Aug 29 10:55:04 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203949908 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.4203949908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1025077750 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 27993500 ps |
| CPU time | 23.2 seconds |
| Started | Aug 29 10:52:18 AM UTC 24 |
| Finished | Aug 29 10:52:42 AM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025077750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1025077750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2412772195 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 60273100 ps |
| CPU time | 168.95 seconds |
| Started | Aug 29 10:52:13 AM UTC 24 |
| Finished | Aug 29 10:55:05 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412772195 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.2412772195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.512994434 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 15988000 ps |
| CPU time | 15.62 seconds |
| Started | Aug 29 10:52:19 AM UTC 24 |
| Finished | Aug 29 10:52:35 AM UTC 24 |
| Peak memory | 295120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512994434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.512994434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3586224395 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 147429300 ps |
| CPU time | 166.87 seconds |
| Started | Aug 29 10:52:19 AM UTC 24 |
| Finished | Aug 29 10:55:08 AM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586224395 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.3586224395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.418462973 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 496881000 ps |
| CPU time | 25.91 seconds |
| Started | Aug 29 10:16:31 AM UTC 24 |
| Finished | Aug 29 10:16:58 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418462973 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.418462973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.94600621 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 14228400 ps |
| CPU time | 14.95 seconds |
| Started | Aug 29 10:16:04 AM UTC 24 |
| Finished | Aug 29 10:16:21 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94600621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.94600621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.353497151 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 40340100 ps |
| CPU time | 34.55 seconds |
| Started | Aug 29 10:16:00 AM UTC 24 |
| Finished | Aug 29 10:16:36 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=353497151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_disable.353497151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.323051942 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4554765500 ps |
| CPU time | 1170.82 seconds |
| Started | Aug 29 10:13:17 AM UTC 24 |
| Finished | Aug 29 10:33:01 AM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323051942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.323051942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3607399919 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 413323500 ps |
| CPU time | 36.8 seconds |
| Started | Aug 29 10:13:13 AM UTC 24 |
| Finished | Aug 29 10:13:52 AM UTC 24 |
| Peak memory | 275604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 07399919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc h_code.3607399919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2222443408 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 10054263900 ps |
| CPU time | 78.98 seconds |
| Started | Aug 29 10:16:26 AM UTC 24 |
| Finished | Aug 29 10:17:47 AM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2222443408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2222443408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2259911225 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 160191007700 ps |
| CPU time | 775.97 seconds |
| Started | Aug 29 10:13:07 AM UTC 24 |
| Finished | Aug 29 10:26:12 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259911225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2259911225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1328495206 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2560849100 ps |
| CPU time | 234.48 seconds |
| Started | Aug 29 10:13:03 AM UTC 24 |
| Finished | Aug 29 10:17:01 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328495206 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.1328495206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.443094938 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3671031900 ps |
| CPU time | 207.3 seconds |
| Started | Aug 29 10:14:08 AM UTC 24 |
| Finished | Aug 29 10:17:39 AM UTC 24 |
| Peak memory | 302096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443094938 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.443094938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2057140688 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 26379747900 ps |
| CPU time | 371.6 seconds |
| Started | Aug 29 10:14:21 AM UTC 24 |
| Finished | Aug 29 10:20:37 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2057140688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_intr_rd_slow_flash.2057140688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3368701902 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4073007800 ps |
| CPU time | 90.94 seconds |
| Started | Aug 29 10:14:11 AM UTC 24 |
| Finished | Aug 29 10:15:44 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368701902 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.3368701902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2576480551 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 24092186600 ps |
| CPU time | 271.11 seconds |
| Started | Aug 29 10:15:05 AM UTC 24 |
| Finished | Aug 29 10:19:40 AM UTC 24 |
| Peak memory | 271300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576480551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2576480551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2052179253 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 40821600 ps |
| CPU time | 28.87 seconds |
| Started | Aug 29 10:16:07 AM UTC 24 |
| Finished | Aug 29 10:16:37 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2052179253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_lcmgr_intg.2052179253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2242617977 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4588266800 ps |
| CPU time | 166.96 seconds |
| Started | Aug 29 10:13:12 AM UTC 24 |
| Finished | Aug 29 10:16:02 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2242617977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.2242617977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.2735893610 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 47641000 ps |
| CPU time | 194.05 seconds |
| Started | Aug 29 10:13:08 AM UTC 24 |
| Finished | Aug 29 10:16:25 AM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735893610 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.2735893610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1486942879 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 893032300 ps |
| CPU time | 237.05 seconds |
| Started | Aug 29 10:12:57 AM UTC 24 |
| Finished | Aug 29 10:16:58 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486942879 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1486942879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3529995153 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 64647600 ps |
| CPU time | 27.91 seconds |
| Started | Aug 29 10:15:24 AM UTC 24 |
| Finished | Aug 29 10:15:54 AM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529995153 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.3529995153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3020868855 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 84422000 ps |
| CPU time | 171.3 seconds |
| Started | Aug 29 10:12:56 AM UTC 24 |
| Finished | Aug 29 10:15:50 AM UTC 24 |
| Peak memory | 289872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020868855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3020868855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.900175061 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 141672500 ps |
| CPU time | 57.53 seconds |
| Started | Aug 29 10:15:55 AM UTC 24 |
| Finished | Aug 29 10:16:54 AM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900175061 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.900175061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.2113723009 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 952151800 ps |
| CPU time | 136.13 seconds |
| Started | Aug 29 10:13:45 AM UTC 24 |
| Finished | Aug 29 10:16:04 AM UTC 24 |
| Peak memory | 304180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2113723009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.2113723009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2369222341 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2800862300 ps |
| CPU time | 188.29 seconds |
| Started | Aug 29 10:14:01 AM UTC 24 |
| Finished | Aug 29 10:17:13 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369222341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2369222341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3594904229 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 4038340400 ps |
| CPU time | 175 seconds |
| Started | Aug 29 10:13:58 AM UTC 24 |
| Finished | Aug 29 10:16:56 AM UTC 24 |
| Peak memory | 292024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3594904229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.3594904229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.2172788172 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 8397896200 ps |
| CPU time | 225.84 seconds |
| Started | Aug 29 10:14:07 AM UTC 24 |
| Finished | Aug 29 10:17:57 AM UTC 24 |
| Peak memory | 300220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2172788172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.2172788172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.2565079307 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 70735700 ps |
| CPU time | 51.42 seconds |
| Started | Aug 29 10:15:44 AM UTC 24 |
| Finished | Aug 29 10:16:38 AM UTC 24 |
| Peak memory | 283632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565079307 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.2565079307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3312744962 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 31453200 ps |
| CPU time | 50.14 seconds |
| Started | Aug 29 10:15:51 AM UTC 24 |
| Finished | Aug 29 10:16:42 AM UTC 24 |
| Peak memory | 287924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3312744962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_rw_evict_all_en.3312744962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.272629683 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1616706900 ps |
| CPU time | 177.4 seconds |
| Started | Aug 29 10:13:58 AM UTC 24 |
| Finished | Aug 29 10:16:58 AM UTC 24 |
| Peak memory | 306364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=272629683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.272629683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.1719068861 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 668428800 ps |
| CPU time | 67.11 seconds |
| Started | Aug 29 10:16:03 AM UTC 24 |
| Finished | Aug 29 10:17:12 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719068861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1719068861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2077129106 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 218314900 ps |
| CPU time | 291.82 seconds |
| Started | Aug 29 10:12:55 AM UTC 24 |
| Finished | Aug 29 10:17:50 AM UTC 24 |
| Peak memory | 289680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077129106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2077129106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1213465164 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 4731284600 ps |
| CPU time | 223.09 seconds |
| Started | Aug 29 10:13:33 AM UTC 24 |
| Finished | Aug 29 10:17:19 AM UTC 24 |
| Peak memory | 271220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1213465164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.1213465164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1067264834 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 50040900 ps |
| CPU time | 25.4 seconds |
| Started | Aug 29 10:18:55 AM UTC 24 |
| Finished | Aug 29 10:19:21 AM UTC 24 |
| Peak memory | 269312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067264834 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1067264834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3887863891 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 39853700 ps |
| CPU time | 23.68 seconds |
| Started | Aug 29 10:18:40 AM UTC 24 |
| Finished | Aug 29 10:19:05 AM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887863891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3887863891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.1327875090 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 15445800 ps |
| CPU time | 45.06 seconds |
| Started | Aug 29 10:18:09 AM UTC 24 |
| Finished | Aug 29 10:18:55 AM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1327875090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c trl_disable.1327875090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1595695356 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4591378400 ps |
| CPU time | 2993.12 seconds |
| Started | Aug 29 10:16:59 AM UTC 24 |
| Finished | Aug 29 11:07:24 AM UTC 24 |
| Peak memory | 275940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595695356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1595695356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.1243663903 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2067593800 ps |
| CPU time | 1033.08 seconds |
| Started | Aug 29 10:16:59 AM UTC 24 |
| Finished | Aug 29 10:34:22 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243663903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1243663903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2179741210 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1578719100 ps |
| CPU time | 41.36 seconds |
| Started | Aug 29 10:16:56 AM UTC 24 |
| Finished | Aug 29 10:17:39 AM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 79741210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.2179741210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3038504923 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 10018817300 ps |
| CPU time | 119.94 seconds |
| Started | Aug 29 10:18:52 AM UTC 24 |
| Finished | Aug 29 10:20:55 AM UTC 24 |
| Peak memory | 333004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3038504923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3038504923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.4263132670 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 15950700 ps |
| CPU time | 23.42 seconds |
| Started | Aug 29 10:18:44 AM UTC 24 |
| Finished | Aug 29 10:19:09 AM UTC 24 |
| Peak memory | 275456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4263132670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.4263132670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.352786982 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 260233216900 ps |
| CPU time | 1042.74 seconds |
| Started | Aug 29 10:16:44 AM UTC 24 |
| Finished | Aug 29 10:34:19 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352786982 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.352786982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3887621311 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4057905300 ps |
| CPU time | 63.53 seconds |
| Started | Aug 29 10:16:43 AM UTC 24 |
| Finished | Aug 29 10:17:48 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887621311 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.3887621311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.434210610 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 789074700 ps |
| CPU time | 168.86 seconds |
| Started | Aug 29 10:17:39 AM UTC 24 |
| Finished | Aug 29 10:20:31 AM UTC 24 |
| Peak memory | 306188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434210610 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.434210610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3589971063 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 35363471500 ps |
| CPU time | 160.67 seconds |
| Started | Aug 29 10:17:47 AM UTC 24 |
| Finished | Aug 29 10:20:31 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3589971063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_intr_rd_slow_flash.3589971063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.3393780222 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3115142800 ps |
| CPU time | 69.66 seconds |
| Started | Aug 29 10:17:41 AM UTC 24 |
| Finished | Aug 29 10:18:52 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393780222 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.3393780222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3734177025 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 21235996200 ps |
| CPU time | 321.69 seconds |
| Started | Aug 29 10:17:47 AM UTC 24 |
| Finished | Aug 29 10:23:14 AM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734177025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3734177025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3374455795 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3911199100 ps |
| CPU time | 97.89 seconds |
| Started | Aug 29 10:17:00 AM UTC 24 |
| Finished | Aug 29 10:18:40 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374455795 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3374455795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1747226027 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 82792100 ps |
| CPU time | 23.7 seconds |
| Started | Aug 29 10:18:43 AM UTC 24 |
| Finished | Aug 29 10:19:08 AM UTC 24 |
| Peak memory | 271564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1747226027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.1747226027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2371322290 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5128109700 ps |
| CPU time | 192.52 seconds |
| Started | Aug 29 10:16:54 AM UTC 24 |
| Finished | Aug 29 10:20:10 AM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2371322290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.2371322290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2281646254 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 68545100 ps |
| CPU time | 198.54 seconds |
| Started | Aug 29 10:16:46 AM UTC 24 |
| Finished | Aug 29 10:20:08 AM UTC 24 |
| Peak memory | 271652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281646254 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.2281646254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.4249140216 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1440432900 ps |
| CPU time | 313.69 seconds |
| Started | Aug 29 10:16:39 AM UTC 24 |
| Finished | Aug 29 10:21:57 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249140216 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.4249140216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3879896461 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 9454746400 ps |
| CPU time | 242.5 seconds |
| Started | Aug 29 10:17:47 AM UTC 24 |
| Finished | Aug 29 10:21:54 AM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879896461 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.3879896461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1832384671 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 303176200 ps |
| CPU time | 918.81 seconds |
| Started | Aug 29 10:16:38 AM UTC 24 |
| Finished | Aug 29 10:32:07 AM UTC 24 |
| Peak memory | 291920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832384671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1832384671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3115066975 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 111657100 ps |
| CPU time | 54.37 seconds |
| Started | Aug 29 10:17:58 AM UTC 24 |
| Finished | Aug 29 10:18:54 AM UTC 24 |
| Peak memory | 285708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115066975 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.3115066975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2473510860 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 482530700 ps |
| CPU time | 133.02 seconds |
| Started | Aug 29 10:17:13 AM UTC 24 |
| Finished | Aug 29 10:19:29 AM UTC 24 |
| Peak memory | 291720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2473510860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.2473510860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2409175913 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1528220600 ps |
| CPU time | 174.64 seconds |
| Started | Aug 29 10:17:27 AM UTC 24 |
| Finished | Aug 29 10:20:25 AM UTC 24 |
| Peak memory | 291816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409175913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2409175913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3252577059 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 777741400 ps |
| CPU time | 166.77 seconds |
| Started | Aug 29 10:17:20 AM UTC 24 |
| Finished | Aug 29 10:20:10 AM UTC 24 |
| Peak memory | 304312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3252577059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_ro_serr.3252577059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1404990072 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 8081340200 ps |
| CPU time | 582.61 seconds |
| Started | Aug 29 10:17:14 AM UTC 24 |
| Finished | Aug 29 10:27:05 AM UTC 24 |
| Peak memory | 330664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404990072 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.1404990072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.677227506 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1347307900 ps |
| CPU time | 208.14 seconds |
| Started | Aug 29 10:17:27 AM UTC 24 |
| Finished | Aug 29 10:20:59 AM UTC 24 |
| Peak memory | 297940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=677227506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_rw_derr.677227506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1599393965 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 30221200 ps |
| CPU time | 52.02 seconds |
| Started | Aug 29 10:17:50 AM UTC 24 |
| Finished | Aug 29 10:18:43 AM UTC 24 |
| Peak memory | 287924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599393965 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.1599393965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2855061380 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 72594300 ps |
| CPU time | 49.49 seconds |
| Started | Aug 29 10:17:52 AM UTC 24 |
| Finished | Aug 29 10:18:43 AM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2855061380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_rw_evict_all_en.2855061380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2405325907 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4579767300 ps |
| CPU time | 187.85 seconds |
| Started | Aug 29 10:17:23 AM UTC 24 |
| Finished | Aug 29 10:20:34 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2405325907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.2405325907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2892477934 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 22620400 ps |
| CPU time | 88.87 seconds |
| Started | Aug 29 10:16:37 AM UTC 24 |
| Finished | Aug 29 10:18:08 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892477934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2892477934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3321416172 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 5001925900 ps |
| CPU time | 236.55 seconds |
| Started | Aug 29 10:17:02 AM UTC 24 |
| Finished | Aug 29 10:21:02 AM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3321416172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.3321416172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |