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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.73 93.97 98.31 91.84 98.25 96.89 98.24


Total test records in report: 1271
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T88 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1662847066 Sep 01 07:12:43 PM UTC 24 Sep 01 07:31:44 PM UTC 24 82225816200 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2861104675 Sep 01 07:30:25 PM UTC 24 Sep 01 07:31:56 PM UTC 24 4049413400 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.469944165 Sep 01 07:28:17 PM UTC 24 Sep 01 07:31:56 PM UTC 24 11623067000 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1649482318 Sep 01 07:24:30 PM UTC 24 Sep 01 07:31:58 PM UTC 24 112233900 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2009051231 Sep 01 07:28:27 PM UTC 24 Sep 01 07:32:06 PM UTC 24 21611674000 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2755052961 Sep 01 07:07:57 PM UTC 24 Sep 01 07:32:10 PM UTC 24 185686800 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.2339740685 Sep 01 07:30:34 PM UTC 24 Sep 01 07:32:18 PM UTC 24 538705200 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1007684479 Sep 01 07:30:18 PM UTC 24 Sep 01 07:32:29 PM UTC 24 37673100 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2900913831 Sep 01 07:30:16 PM UTC 24 Sep 01 07:32:53 PM UTC 24 3897726200 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2103855412 Sep 01 07:18:14 PM UTC 24 Sep 01 07:32:56 PM UTC 24 110018100 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.661407940 Sep 01 07:31:58 PM UTC 24 Sep 01 07:32:57 PM UTC 24 94533900 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1513381598 Sep 01 07:32:19 PM UTC 24 Sep 01 07:32:59 PM UTC 24 13350800 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1521198499 Sep 01 07:31:28 PM UTC 24 Sep 01 07:33:05 PM UTC 24 2585960400 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3715216842 Sep 01 07:32:07 PM UTC 24 Sep 01 07:33:10 PM UTC 24 66694300 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.1826244937 Sep 01 07:31:09 PM UTC 24 Sep 01 07:33:11 PM UTC 24 619205700 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.1688543218 Sep 01 07:17:49 PM UTC 24 Sep 01 07:33:13 PM UTC 24 163831378200 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.592060305 Sep 01 07:32:11 PM UTC 24 Sep 01 07:33:17 PM UTC 24 111248400 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.342279868 Sep 01 07:30:54 PM UTC 24 Sep 01 07:33:20 PM UTC 24 770639900 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3632563532 Sep 01 07:32:58 PM UTC 24 Sep 01 07:33:23 PM UTC 24 120495200 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.2230109231 Sep 01 07:32:57 PM UTC 24 Sep 01 07:33:23 PM UTC 24 46593700 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2719112182 Sep 01 07:33:06 PM UTC 24 Sep 01 07:33:25 PM UTC 24 244402700 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.3863769078 Sep 01 07:32:54 PM UTC 24 Sep 01 07:33:26 PM UTC 24 14588500 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.3506884334 Sep 01 07:30:29 PM UTC 24 Sep 01 07:33:55 PM UTC 24 1987848600 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2180254787 Sep 01 07:24:41 PM UTC 24 Sep 01 07:33:55 PM UTC 24 772914500 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.1817993775 Sep 01 07:33:26 PM UTC 24 Sep 01 07:33:59 PM UTC 24 368813100 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2822325754 Sep 01 07:18:40 PM UTC 24 Sep 01 07:34:11 PM UTC 24 40122646800 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.727198808 Sep 01 07:30:08 PM UTC 24 Sep 01 07:34:15 PM UTC 24 2843638100 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3146291607 Sep 01 07:32:30 PM UTC 24 Sep 01 07:34:21 PM UTC 24 3151459000 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3669906702 Sep 01 07:33:00 PM UTC 24 Sep 01 07:34:24 PM UTC 24 10042511800 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1774440271 Sep 01 07:33:18 PM UTC 24 Sep 01 07:34:31 PM UTC 24 1242665300 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.908116610 Sep 01 07:06:08 PM UTC 24 Sep 01 07:34:38 PM UTC 24 11911558800 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1286457738 Sep 01 07:13:15 PM UTC 24 Sep 01 07:34:46 PM UTC 24 778081900 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3445695434 Sep 01 07:31:18 PM UTC 24 Sep 01 07:34:57 PM UTC 24 9318869000 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.1047046990 Sep 01 07:30:58 PM UTC 24 Sep 01 07:34:59 PM UTC 24 2014614100 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3843742084 Sep 01 07:26:33 PM UTC 24 Sep 01 07:35:08 PM UTC 24 13880938700 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2130076146 Sep 01 07:33:11 PM UTC 24 Sep 01 07:35:16 PM UTC 24 25462100 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3406671094 Sep 01 07:33:55 PM UTC 24 Sep 01 07:35:37 PM UTC 24 8297130700 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3950138395 Sep 01 07:31:46 PM UTC 24 Sep 01 07:35:38 PM UTC 24 11792849100 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.3513786336 Sep 01 07:35:12 PM UTC 24 Sep 01 07:35:39 PM UTC 24 32666700 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.2235105671 Sep 01 07:31:57 PM UTC 24 Sep 01 07:35:59 PM UTC 24 11849219900 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2358239231 Sep 01 07:35:17 PM UTC 24 Sep 01 07:36:18 PM UTC 24 66693000 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.736974555 Sep 01 07:35:40 PM UTC 24 Sep 01 07:36:18 PM UTC 24 35256200 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.956926298 Sep 01 07:34:58 PM UTC 24 Sep 01 07:36:25 PM UTC 24 7231934100 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2408562290 Sep 01 07:35:39 PM UTC 24 Sep 01 07:36:33 PM UTC 24 75625000 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1296637176 Sep 01 07:35:38 PM UTC 24 Sep 01 07:36:38 PM UTC 24 67634900 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3153150248 Sep 01 07:36:19 PM UTC 24 Sep 01 07:36:44 PM UTC 24 24353400 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1893684258 Sep 01 07:36:26 PM UTC 24 Sep 01 07:36:47 PM UTC 24 150398900 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3713881173 Sep 01 07:34:13 PM UTC 24 Sep 01 07:36:47 PM UTC 24 4555092500 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2787236949 Sep 01 07:36:19 PM UTC 24 Sep 01 07:36:50 PM UTC 24 18638500 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.2933396533 Sep 01 07:34:22 PM UTC 24 Sep 01 07:36:50 PM UTC 24 1964454800 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3752431899 Sep 01 07:36:39 PM UTC 24 Sep 01 07:37:07 PM UTC 24 104003700 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.120565752 Sep 01 07:27:55 PM UTC 24 Sep 01 07:37:08 PM UTC 24 15003105500 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3919968493 Sep 01 07:34:32 PM UTC 24 Sep 01 07:37:22 PM UTC 24 574282500 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3291283745 Sep 01 07:33:24 PM UTC 24 Sep 01 07:37:33 PM UTC 24 648436100 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.45474974 Sep 01 07:34:01 PM UTC 24 Sep 01 07:37:38 PM UTC 24 4297916500 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1080567530 Sep 01 07:35:59 PM UTC 24 Sep 01 07:37:43 PM UTC 24 2576442700 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.378775299 Sep 01 07:36:34 PM UTC 24 Sep 01 07:37:50 PM UTC 24 10127855400 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.686588837 Sep 01 07:35:01 PM UTC 24 Sep 01 07:37:56 PM UTC 24 5935661100 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.3109197808 Sep 01 07:34:47 PM UTC 24 Sep 01 07:38:10 PM UTC 24 8812029900 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3828488589 Sep 01 07:37:23 PM UTC 24 Sep 01 07:38:12 PM UTC 24 2332828200 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4088681126 Sep 01 07:31:57 PM UTC 24 Sep 01 07:38:13 PM UTC 24 46989347900 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3370033302 Sep 01 07:33:15 PM UTC 24 Sep 01 07:38:31 PM UTC 24 49619400 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1046762980 Sep 01 07:29:24 PM UTC 24 Sep 01 07:38:37 PM UTC 24 370955300 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.767745785 Sep 01 07:34:25 PM UTC 24 Sep 01 07:38:54 PM UTC 24 7328168000 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2940768171 Sep 01 07:37:43 PM UTC 24 Sep 01 07:39:12 PM UTC 24 12002074300 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.596338991 Sep 01 07:14:17 PM UTC 24 Sep 01 07:39:29 PM UTC 24 5770218200 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.1109155532 Sep 01 07:33:11 PM UTC 24 Sep 01 07:39:33 PM UTC 24 38067800 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.2793568477 Sep 01 07:24:46 PM UTC 24 Sep 01 07:39:52 PM UTC 24 50126396900 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2815169800 Sep 01 07:34:39 PM UTC 24 Sep 01 07:40:00 PM UTC 24 2000971500 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2633939150 Sep 01 07:36:45 PM UTC 24 Sep 01 07:40:11 PM UTC 24 38970200 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3182295800 Sep 01 07:37:07 PM UTC 24 Sep 01 07:40:26 PM UTC 24 37951900 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3406076625 Sep 01 07:35:09 PM UTC 24 Sep 01 07:40:29 PM UTC 24 40785263700 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.710062424 Sep 01 07:37:57 PM UTC 24 Sep 01 07:40:30 PM UTC 24 577105300 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.852387191 Sep 01 07:37:09 PM UTC 24 Sep 01 07:40:32 PM UTC 24 10868952200 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1707083977 Sep 01 07:38:13 PM UTC 24 Sep 01 07:40:36 PM UTC 24 1293957000 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2033735614 Sep 01 07:36:50 PM UTC 24 Sep 01 07:40:45 PM UTC 24 5374692300 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2599113699 Sep 01 07:40:01 PM UTC 24 Sep 01 07:40:55 PM UTC 24 49562700 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2582403673 Sep 01 07:38:32 PM UTC 24 Sep 01 07:40:55 PM UTC 24 4184382500 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2956040018 Sep 01 07:37:51 PM UTC 24 Sep 01 07:40:59 PM UTC 24 17669143700 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2308351075 Sep 01 07:40:37 PM UTC 24 Sep 01 07:41:01 PM UTC 24 29120300 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1790683594 Sep 01 07:40:30 PM UTC 24 Sep 01 07:41:02 PM UTC 24 13775700 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2862685463 Sep 01 07:40:12 PM UTC 24 Sep 01 07:41:03 PM UTC 24 31686400 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1600898458 Sep 01 07:40:27 PM UTC 24 Sep 01 07:41:04 PM UTC 24 892659100 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3365096719 Sep 01 07:40:34 PM UTC 24 Sep 01 07:41:07 PM UTC 24 136532700 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.3361908518 Sep 01 07:40:46 PM UTC 24 Sep 01 07:41:13 PM UTC 24 29013600 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.3196572527 Sep 01 07:40:56 PM UTC 24 Sep 01 07:41:23 PM UTC 24 59542800 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3420930241 Sep 01 07:39:13 PM UTC 24 Sep 01 07:41:25 PM UTC 24 21412395500 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.1388656049 Sep 01 07:33:24 PM UTC 24 Sep 01 07:41:44 PM UTC 24 19893624100 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1695489517 Sep 01 07:30:19 PM UTC 24 Sep 01 07:41:48 PM UTC 24 30304258800 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.626494219 Sep 01 07:41:24 PM UTC 24 Sep 01 07:41:50 PM UTC 24 1184662900 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.1734454245 Sep 01 07:17:20 PM UTC 24 Sep 01 07:42:08 PM UTC 24 1590188500 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1597584623 Sep 01 07:36:48 PM UTC 24 Sep 01 07:42:21 PM UTC 24 62600000 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.895070571 Sep 01 07:34:16 PM UTC 24 Sep 01 07:42:25 PM UTC 24 3731470400 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2568469000 Sep 01 07:40:31 PM UTC 24 Sep 01 07:42:31 PM UTC 24 2136273200 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.2092257344 Sep 01 07:38:13 PM UTC 24 Sep 01 07:42:38 PM UTC 24 2866090200 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2598677483 Sep 01 07:38:55 PM UTC 24 Sep 01 07:42:45 PM UTC 24 5417276100 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1215371635 Sep 01 07:39:29 PM UTC 24 Sep 01 07:42:47 PM UTC 24 5841628200 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.1143390978 Sep 01 07:39:52 PM UTC 24 Sep 01 07:43:02 PM UTC 24 4477804600 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1954267925 Sep 01 07:41:03 PM UTC 24 Sep 01 07:43:05 PM UTC 24 5091385500 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.19713201 Sep 01 07:41:00 PM UTC 24 Sep 01 07:43:08 PM UTC 24 20834400 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.867926735 Sep 01 07:40:56 PM UTC 24 Sep 01 07:43:08 PM UTC 24 10019643900 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2707746571 Sep 01 07:39:34 PM UTC 24 Sep 01 07:43:15 PM UTC 24 70038636000 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.937426341 Sep 01 07:41:49 PM UTC 24 Sep 01 07:43:30 PM UTC 24 2132468000 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4133376342 Sep 01 07:38:38 PM UTC 24 Sep 01 07:43:49 PM UTC 24 19740532600 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.4199030885 Sep 01 07:43:15 PM UTC 24 Sep 01 07:44:20 PM UTC 24 30934600 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1690941747 Sep 01 07:43:32 PM UTC 24 Sep 01 07:44:21 PM UTC 24 105313300 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3969086974 Sep 01 07:43:50 PM UTC 24 Sep 01 07:44:28 PM UTC 24 79287000 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1018312005 Sep 01 07:42:08 PM UTC 24 Sep 01 07:44:37 PM UTC 24 578473800 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2309976927 Sep 01 07:43:03 PM UTC 24 Sep 01 07:44:41 PM UTC 24 8698575500 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3905727676 Sep 01 07:41:08 PM UTC 24 Sep 01 07:44:51 PM UTC 24 55653100 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.663164461 Sep 01 07:44:29 PM UTC 24 Sep 01 07:44:54 PM UTC 24 16634900 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2969199555 Sep 01 07:44:38 PM UTC 24 Sep 01 07:45:03 PM UTC 24 76918200 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.2678946005 Sep 01 07:44:41 PM UTC 24 Sep 01 07:45:03 PM UTC 24 26890600 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3447406320 Sep 01 07:44:20 PM UTC 24 Sep 01 07:45:06 PM UTC 24 18955600 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1037792245 Sep 01 07:42:26 PM UTC 24 Sep 01 07:45:11 PM UTC 24 2033546100 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1089134212 Sep 01 07:06:05 PM UTC 24 Sep 01 07:45:12 PM UTC 24 167369325200 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.108723417 Sep 01 07:30:17 PM UTC 24 Sep 01 07:45:16 PM UTC 24 100145119800 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3678383710 Sep 01 07:44:55 PM UTC 24 Sep 01 07:45:18 PM UTC 24 37323400 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.4181669583 Sep 01 07:42:48 PM UTC 24 Sep 01 07:45:19 PM UTC 24 580532300 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2328803368 Sep 01 07:23:36 PM UTC 24 Sep 01 07:45:26 PM UTC 24 276368400 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.26133191 Sep 01 07:42:39 PM UTC 24 Sep 01 07:45:37 PM UTC 24 3146213100 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.49058790 Sep 01 07:43:09 PM UTC 24 Sep 01 07:45:59 PM UTC 24 4031515100 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.696383439 Sep 01 07:45:11 PM UTC 24 Sep 01 07:46:02 PM UTC 24 581254900 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.1395172124 Sep 01 07:08:20 PM UTC 24 Sep 01 07:46:03 PM UTC 24 168655464400 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1823734076 Sep 01 07:41:51 PM UTC 24 Sep 01 07:46:04 PM UTC 24 3524770600 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1708791376 Sep 01 07:45:19 PM UTC 24 Sep 01 07:46:07 PM UTC 24 799139900 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3035682262 Sep 01 07:43:05 PM UTC 24 Sep 01 07:46:07 PM UTC 24 6054342900 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.855698615 Sep 01 07:19:06 PM UTC 24 Sep 01 07:46:09 PM UTC 24 2905548200 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3404741529 Sep 01 07:44:22 PM UTC 24 Sep 01 07:46:13 PM UTC 24 2757577800 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1018235929 Sep 01 07:13:42 PM UTC 24 Sep 01 07:46:40 PM UTC 24 340568721800 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.695862794 Sep 01 07:42:32 PM UTC 24 Sep 01 07:46:44 PM UTC 24 6185369400 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1914215240 Sep 01 07:41:03 PM UTC 24 Sep 01 07:46:54 PM UTC 24 2735260700 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1407740752 Sep 01 07:38:11 PM UTC 24 Sep 01 07:46:55 PM UTC 24 2908192800 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2983842597 Sep 01 07:45:07 PM UTC 24 Sep 01 07:46:57 PM UTC 24 88837300 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.4122829500 Sep 01 07:44:52 PM UTC 24 Sep 01 07:46:59 PM UTC 24 10011865800 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2168426794 Sep 01 07:46:00 PM UTC 24 Sep 01 07:47:00 PM UTC 24 9399836800 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2768844100 Sep 01 07:41:14 PM UTC 24 Sep 01 07:47:26 PM UTC 24 45727891100 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.178586172 Sep 01 07:36:48 PM UTC 24 Sep 01 07:47:38 PM UTC 24 5483378600 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2211657745 Sep 01 07:46:59 PM UTC 24 Sep 01 07:47:49 PM UTC 24 101634800 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1185807102 Sep 01 07:47:01 PM UTC 24 Sep 01 07:47:50 PM UTC 24 36450800 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1675938142 Sep 01 07:42:46 PM UTC 24 Sep 01 07:47:53 PM UTC 24 1613357300 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.455584507 Sep 01 07:43:08 PM UTC 24 Sep 01 07:47:58 PM UTC 24 44844267800 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3910387191 Sep 01 07:45:04 PM UTC 24 Sep 01 07:48:00 PM UTC 24 91346700 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1443031744 Sep 01 07:33:21 PM UTC 24 Sep 01 07:48:01 PM UTC 24 130174298300 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1123408298 Sep 01 07:46:04 PM UTC 24 Sep 01 07:48:04 PM UTC 24 538285100 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2622024707 Sep 01 07:47:39 PM UTC 24 Sep 01 07:48:15 PM UTC 24 16444700 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.46952372 Sep 01 07:46:45 PM UTC 24 Sep 01 07:48:17 PM UTC 24 1809099500 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3575117627 Sep 01 07:47:27 PM UTC 24 Sep 01 07:48:18 PM UTC 24 145793300 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1358756153 Sep 01 07:47:53 PM UTC 24 Sep 01 07:48:22 PM UTC 24 15554100 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.2683500074 Sep 01 07:47:58 PM UTC 24 Sep 01 07:48:23 PM UTC 24 47125300 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3824155176 Sep 01 07:47:50 PM UTC 24 Sep 01 07:48:23 PM UTC 24 21452100 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1224609077 Sep 01 07:48:03 PM UTC 24 Sep 01 07:48:28 PM UTC 24 99453800 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3434037442 Sep 01 07:45:16 PM UTC 24 Sep 01 07:48:31 PM UTC 24 36760000 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.412608701 Sep 01 07:46:07 PM UTC 24 Sep 01 07:48:32 PM UTC 24 1143006900 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1242084376 Sep 01 07:46:03 PM UTC 24 Sep 01 07:49:26 PM UTC 24 8432312200 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.346341287 Sep 01 07:24:22 PM UTC 24 Sep 01 07:48:49 PM UTC 24 517787200 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2941438181 Sep 01 07:47:50 PM UTC 24 Sep 01 07:48:55 PM UTC 24 1125825100 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1747980438 Sep 01 07:48:01 PM UTC 24 Sep 01 07:49:10 PM UTC 24 10034503900 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1480941123 Sep 01 07:46:08 PM UTC 24 Sep 01 07:49:21 PM UTC 24 1718110300 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2062496336 Sep 01 07:46:09 PM UTC 24 Sep 01 07:49:25 PM UTC 24 4895499100 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1758255602 Sep 01 07:46:58 PM UTC 24 Sep 01 07:49:30 PM UTC 24 8227824800 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1307203243 Sep 01 07:49:22 PM UTC 24 Sep 01 07:49:51 PM UTC 24 82543500 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.880768031 Sep 01 07:25:51 PM UTC 24 Sep 01 07:49:53 PM UTC 24 1522410500 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.4262059378 Sep 01 07:49:52 PM UTC 24 Sep 01 07:50:16 PM UTC 24 16450800 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3887524145 Sep 01 07:49:27 PM UTC 24 Sep 01 07:50:20 PM UTC 24 67733400 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3537728736 Sep 01 07:49:26 PM UTC 24 Sep 01 07:50:25 PM UTC 24 66919400 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.29767666 Sep 01 07:48:19 PM UTC 24 Sep 01 07:50:26 PM UTC 24 14134469000 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.999165314 Sep 01 07:48:29 PM UTC 24 Sep 01 07:50:26 PM UTC 24 1011495400 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2705510058 Sep 01 07:46:14 PM UTC 24 Sep 01 07:50:36 PM UTC 24 3071284800 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1609181695 Sep 01 07:50:17 PM UTC 24 Sep 01 07:50:38 PM UTC 24 15928100 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3599788237 Sep 01 07:49:32 PM UTC 24 Sep 01 07:50:39 PM UTC 24 238319600 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1735279583 Sep 01 07:06:06 PM UTC 24 Sep 01 07:50:47 PM UTC 24 460525249700 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.398419519 Sep 01 07:50:21 PM UTC 24 Sep 01 07:50:48 PM UTC 24 15535900 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2592430416 Sep 01 07:50:26 PM UTC 24 Sep 01 07:50:51 PM UTC 24 25750000 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2838412929 Sep 01 07:48:34 PM UTC 24 Sep 01 07:50:55 PM UTC 24 940008100 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.3216062243 Sep 01 07:50:28 PM UTC 24 Sep 01 07:50:58 PM UTC 24 136576200 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3446241790 Sep 01 07:48:56 PM UTC 24 Sep 01 07:50:59 PM UTC 24 482945600 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.4121142170 Sep 01 07:30:21 PM UTC 24 Sep 01 07:51:04 PM UTC 24 1519408200 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2323379759 Sep 01 07:48:05 PM UTC 24 Sep 01 07:51:06 PM UTC 24 191923500 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2879277645 Sep 01 07:45:18 PM UTC 24 Sep 01 07:51:14 PM UTC 24 26342112800 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.1275314469 Sep 01 07:49:55 PM UTC 24 Sep 01 07:51:20 PM UTC 24 14573680100 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3644253402 Sep 01 07:46:41 PM UTC 24 Sep 01 07:51:22 PM UTC 24 18132788900 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.662147020 Sep 01 07:42:22 PM UTC 24 Sep 01 07:51:46 PM UTC 24 3572449500 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.295257597 Sep 01 07:48:31 PM UTC 24 Sep 01 07:51:50 PM UTC 24 2564434300 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2085736859 Sep 01 07:50:59 PM UTC 24 Sep 01 07:52:12 PM UTC 24 1698589500 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.4041204790 Sep 01 07:48:18 PM UTC 24 Sep 01 07:52:16 PM UTC 24 154911000 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.531386104 Sep 01 07:51:47 PM UTC 24 Sep 01 07:52:25 PM UTC 24 34058200 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.144128637 Sep 01 07:46:56 PM UTC 24 Sep 01 07:52:41 PM UTC 24 90830269300 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1608566459 Sep 01 07:50:26 PM UTC 24 Sep 01 07:52:43 PM UTC 24 10034086000 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.586509834 Sep 01 07:51:52 PM UTC 24 Sep 01 07:52:46 PM UTC 24 91730800 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2755698245 Sep 01 07:52:17 PM UTC 24 Sep 01 07:52:46 PM UTC 24 13236000 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3674311556 Sep 01 07:49:11 PM UTC 24 Sep 01 07:52:55 PM UTC 24 5988839700 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3977070629 Sep 01 07:52:13 PM UTC 24 Sep 01 07:52:56 PM UTC 24 74072200 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2342869536 Sep 01 07:48:24 PM UTC 24 Sep 01 07:52:56 PM UTC 24 714938900 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.377681009 Sep 01 07:46:55 PM UTC 24 Sep 01 07:53:01 PM UTC 24 110863848100 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.257488113 Sep 01 07:52:43 PM UTC 24 Sep 01 07:53:10 PM UTC 24 15254400 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2989485379 Sep 01 07:51:05 PM UTC 24 Sep 01 07:53:10 PM UTC 24 2132880800 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.131317690 Sep 01 07:52:42 PM UTC 24 Sep 01 07:53:12 PM UTC 24 19137500 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4022609179 Sep 01 07:52:46 PM UTC 24 Sep 01 07:53:16 PM UTC 24 25330600 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1173037021 Sep 01 07:50:48 PM UTC 24 Sep 01 07:53:23 PM UTC 24 6305100100 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3715142384 Sep 01 07:52:57 PM UTC 24 Sep 01 07:53:23 PM UTC 24 98630700 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.74072177 Sep 01 07:50:52 PM UTC 24 Sep 01 07:53:27 PM UTC 24 106967400 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1121076707 Sep 01 07:45:04 PM UTC 24 Sep 01 07:53:29 PM UTC 24 294982700 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.336901646 Sep 01 07:36:51 PM UTC 24 Sep 01 07:53:43 PM UTC 24 100147980600 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.3920043186 Sep 01 07:46:05 PM UTC 24 Sep 01 07:53:48 PM UTC 24 6136035400 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.4220356322 Sep 01 07:52:26 PM UTC 24 Sep 01 07:53:49 PM UTC 24 1179921800 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3175825090 Sep 01 07:51:15 PM UTC 24 Sep 01 07:53:51 PM UTC 24 3318367800 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2942026470 Sep 01 07:53:50 PM UTC 24 Sep 01 07:54:19 PM UTC 24 34591400 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3752806787 Sep 01 07:52:48 PM UTC 24 Sep 01 07:54:33 PM UTC 24 10019158000 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1120388803 Sep 01 07:53:52 PM UTC 24 Sep 01 07:54:48 PM UTC 24 84567800 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.87537400 Sep 01 07:53:23 PM UTC 24 Sep 01 07:55:18 PM UTC 24 992197600 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.4149027337 Sep 01 07:54:20 PM UTC 24 Sep 01 07:55:20 PM UTC 24 65174100 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.4288949977 Sep 01 07:50:59 PM UTC 24 Sep 01 07:55:25 PM UTC 24 5176079200 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.1872081461 Sep 01 07:50:55 PM UTC 24 Sep 01 07:55:27 PM UTC 24 19737402400 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.3908235767 Sep 01 07:50:37 PM UTC 24 Sep 01 07:55:30 PM UTC 24 93440200 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.4289495398 Sep 01 07:54:50 PM UTC 24 Sep 01 07:55:34 PM UTC 24 10414100 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.2410526644 Sep 01 07:51:22 PM UTC 24 Sep 01 07:55:38 PM UTC 24 2639564000 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2366833897 Sep 01 07:54:35 PM UTC 24 Sep 01 07:55:42 PM UTC 24 408818000 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.360173277 Sep 01 07:08:53 PM UTC 24 Sep 01 07:55:43 PM UTC 24 159754802100 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.199546865 Sep 01 07:55:21 PM UTC 24 Sep 01 07:55:48 PM UTC 24 152323700 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3126879638 Sep 01 07:53:11 PM UTC 24 Sep 01 07:55:50 PM UTC 24 1907455700 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3606496029 Sep 01 07:52:57 PM UTC 24 Sep 01 07:55:52 PM UTC 24 23985200 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1638118893 Sep 01 07:55:28 PM UTC 24 Sep 01 07:55:54 PM UTC 24 20311700 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.914766554 Sep 01 07:55:26 PM UTC 24 Sep 01 07:55:55 PM UTC 24 17759600 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.363728391 Sep 01 07:55:35 PM UTC 24 Sep 01 07:56:00 PM UTC 24 33074400 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2518356698 Sep 01 07:48:24 PM UTC 24 Sep 01 07:56:02 PM UTC 24 16951409500 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.2779658829 Sep 01 07:14:04 PM UTC 24 Sep 01 07:56:02 PM UTC 24 183120320100 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4189941998 Sep 01 07:53:27 PM UTC 24 Sep 01 07:56:04 PM UTC 24 918452800 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.4086417385 Sep 01 07:06:08 PM UTC 24 Sep 01 07:56:29 PM UTC 24 936181700 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.188296837 Sep 01 07:55:19 PM UTC 24 Sep 01 07:56:51 PM UTC 24 1642936100 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.407184131 Sep 01 07:53:23 PM UTC 24 Sep 01 07:57:03 PM UTC 24 3767253400 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3433916823 Sep 01 07:53:44 PM UTC 24 Sep 01 07:57:06 PM UTC 24 1647879000 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.743812061 Sep 01 07:53:02 PM UTC 24 Sep 01 07:57:07 PM UTC 24 802567400 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.101511404 Sep 01 07:37:34 PM UTC 24 Sep 01 07:57:13 PM UTC 24 1325430600 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3433743769 Sep 01 07:55:31 PM UTC 24 Sep 01 07:57:16 PM UTC 24 10033761800 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.2302945392 Sep 01 07:48:50 PM UTC 24 Sep 01 07:57:45 PM UTC 24 7700906400 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2828851541 Sep 01 07:53:12 PM UTC 24 Sep 01 07:57:33 PM UTC 24 67556100 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3771666203 Sep 01 07:55:56 PM UTC 24 Sep 01 07:57:37 PM UTC 24 3277113800 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1984724211 Sep 01 07:57:14 PM UTC 24 Sep 01 07:57:42 PM UTC 24 16285100 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2566590538 Sep 01 07:41:05 PM UTC 24 Sep 01 07:57:48 PM UTC 24 170172445500 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.219502842 Sep 01 07:57:07 PM UTC 24 Sep 01 07:57:55 PM UTC 24 30437300 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.908340300 Sep 01 07:57:33 PM UTC 24 Sep 01 07:57:57 PM UTC 24 27139600 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2157514047 Sep 01 07:57:39 PM UTC 24 Sep 01 07:58:02 PM UTC 24 94760200 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.3807645685 Sep 01 07:53:16 PM UTC 24 Sep 01 07:58:04 PM UTC 24 11310557100 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3987865026 Sep 01 07:57:43 PM UTC 24 Sep 01 07:58:04 PM UTC 24 26351200 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2467354221 Sep 01 07:57:04 PM UTC 24 Sep 01 07:58:05 PM UTC 24 28852700 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2042283894 Sep 01 07:53:49 PM UTC 24 Sep 01 07:58:05 PM UTC 24 24466456400 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2268420833 Sep 01 07:57:49 PM UTC 24 Sep 01 07:58:07 PM UTC 24 157603500 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.4282482095 Sep 01 07:57:08 PM UTC 24 Sep 01 07:58:11 PM UTC 24 123634900 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2374085511 Sep 01 07:18:49 PM UTC 24 Sep 01 07:58:15 PM UTC 24 534157369000 ps
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