| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.18 | 95.73 | 93.97 | 98.31 | 91.84 | 98.25 | 96.89 | 98.24 |
| T1270 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3699274539 | Sep 01 07:05:39 PM UTC 24 | Sep 01 07:06:26 PM UTC 24 | 287177500 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2757188035 | Sep 01 07:05:14 PM UTC 24 | Sep 01 07:14:15 PM UTC 24 | 753522300 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.227924327 | Sep 01 07:04:54 PM UTC 24 | Sep 01 07:14:45 PM UTC 24 | 707427500 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3940567771 | Sep 01 07:05:28 PM UTC 24 | Sep 01 07:15:01 PM UTC 24 | 2520391000 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3635445491 | Sep 01 07:05:07 PM UTC 24 | Sep 01 07:15:26 PM UTC 24 | 1729318000 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.284006558 | Sep 01 07:05:03 PM UTC 24 | Sep 01 07:16:11 PM UTC 24 | 1287871500 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1440623666 | Sep 01 07:04:01 PM UTC 24 | Sep 01 07:16:19 PM UTC 24 | 596904400 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.245572561 | Sep 01 07:04:20 PM UTC 24 | Sep 01 07:16:33 PM UTC 24 | 474414300 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1899284655 | Sep 01 07:05:01 PM UTC 24 | Sep 01 07:16:35 PM UTC 24 | 1909519400 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.540702656 | Sep 01 07:05:20 PM UTC 24 | Sep 01 07:16:47 PM UTC 24 | 359101200 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2966405308 | Sep 01 07:04:40 PM UTC 24 | Sep 01 07:17:04 PM UTC 24 | 678809900 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4135196255 | Sep 01 07:04:08 PM UTC 24 | Sep 01 07:17:23 PM UTC 24 | 420787000 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1208797996 | Sep 01 07:05:34 PM UTC 24 | Sep 01 07:17:24 PM UTC 24 | 346287300 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2477614708 | Sep 01 07:05:23 PM UTC 24 | Sep 01 07:24:23 PM UTC 24 | 338057500 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2971479646 | Sep 01 07:04:30 PM UTC 24 | Sep 01 07:25:24 PM UTC 24 | 790254900 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3018718119 | Sep 01 07:04:36 PM UTC 24 | Sep 01 07:26:02 PM UTC 24 | 1278487300 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.937398490 | Sep 01 07:04:04 PM UTC 24 | Sep 01 07:27:21 PM UTC 24 | 3538339600 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.719555499 | Sep 01 07:03:58 PM UTC 24 | Sep 01 07:28:31 PM UTC 24 | 605808100 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3919989839 | Sep 01 07:04:48 PM UTC 24 | Sep 01 07:28:34 PM UTC 24 | 726883400 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1902508304 | Sep 01 07:05:38 PM UTC 24 | Sep 01 07:29:56 PM UTC 24 | 1937039000 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2768590573 | Sep 01 07:04:26 PM UTC 24 | Sep 01 07:30:17 PM UTC 24 | 1746313300 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1245367172 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2299053300 ps |
| CPU time | 48 seconds |
| Started | Sep 01 07:06:06 PM UTC 24 |
| Finished | Sep 01 07:06:56 PM UTC 24 |
| Peak memory | 273472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12 45367172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc h_code.1245367172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1852287540 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1791695100 ps |
| CPU time | 73.1 seconds |
| Started | Sep 01 07:06:09 PM UTC 24 |
| Finished | Sep 01 07:07:24 PM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852287540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1852287540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3405049058 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 692252900 ps |
| CPU time | 31.16 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:31 PM UTC 24 |
| Peak memory | 284632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3405049058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3405049058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3788076440 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 65598600 ps |
| CPU time | 42.49 seconds |
| Started | Sep 01 07:07:10 PM UTC 24 |
| Finished | Sep 01 07:07:55 PM UTC 24 |
| Peak memory | 287916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378807644 0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.3788076440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3773048166 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 46517000 ps |
| CPU time | 30.76 seconds |
| Started | Sep 01 07:07:11 PM UTC 24 |
| Finished | Sep 01 07:07:44 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773048166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_wr_intg.3773048166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3243531056 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 79918181100 ps |
| CPU time | 901.75 seconds |
| Started | Sep 01 07:07:38 PM UTC 24 |
| Finished | Sep 01 07:22:50 PM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3243531056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. flash_ctrl_rma_err.3243531056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2486711963 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1813517300 ps |
| CPU time | 189.35 seconds |
| Started | Sep 01 07:06:06 PM UTC 24 |
| Finished | Sep 01 07:09:19 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2486711963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.2486711963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1655971697 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1228138400 ps |
| CPU time | 210.46 seconds |
| Started | Sep 01 07:06:12 PM UTC 24 |
| Finished | Sep 01 07:09:46 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1655971697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.1655971697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.2143082470 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1660311700 ps |
| CPU time | 7048.96 seconds |
| Started | Sep 01 07:11:45 PM UTC 24 |
| Finished | Sep 01 09:10:33 PM UTC 24 |
| Peak memory | 316504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143082470 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2143082470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2422436396 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 126877900 ps |
| CPU time | 24.22 seconds |
| Started | Sep 01 07:04:16 PM UTC 24 |
| Finished | Sep 01 07:04:42 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2422436396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2422436396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1157768852 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 157257000 ps |
| CPU time | 60.07 seconds |
| Started | Sep 01 07:06:35 PM UTC 24 |
| Finished | Sep 01 07:07:37 PM UTC 24 |
| Peak memory | 283816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1157768852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_rw_evict_all_en.1157768852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.56671216 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2483273900 ps |
| CPU time | 437.77 seconds |
| Started | Sep 01 07:06:04 PM UTC 24 |
| Finished | Sep 01 07:13:27 PM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56671216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.56671216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.838726023 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 92452600 ps |
| CPU time | 186.49 seconds |
| Started | Sep 01 07:18:43 PM UTC 24 |
| Finished | Sep 01 07:21:53 PM UTC 24 |
| Peak memory | 271548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838726023 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.838726023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2396724494 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1321048500 ps |
| CPU time | 64.32 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:05:04 PM UTC 24 |
| Peak memory | 272204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396724494 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2396724494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2121124538 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 26846100 ps |
| CPU time | 25.84 seconds |
| Started | Sep 01 07:07:29 PM UTC 24 |
| Finished | Sep 01 07:07:57 PM UTC 24 |
| Peak memory | 273460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2121124538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2121124538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2818055784 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 31619100 ps |
| CPU time | 39.98 seconds |
| Started | Sep 01 07:06:38 PM UTC 24 |
| Finished | Sep 01 07:07:20 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2818055784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_disable.2818055784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2708883075 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6446414000 ps |
| CPU time | 130.67 seconds |
| Started | Sep 01 07:06:04 PM UTC 24 |
| Finished | Sep 01 07:08:17 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708883075 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.2708883075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.680587488 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 944098600 ps |
| CPU time | 154.59 seconds |
| Started | Sep 01 07:06:16 PM UTC 24 |
| Finished | Sep 01 07:08:53 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=680587488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_oversize_error.680587488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2828851541 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 67556100 ps |
| CPU time | 256.79 seconds |
| Started | Sep 01 07:53:12 PM UTC 24 |
| Finished | Sep 01 07:57:33 PM UTC 24 |
| Peak memory | 275572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828851541 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.2828851541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.1395172124 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 168655464400 ps |
| CPU time | 2235.56 seconds |
| Started | Sep 01 07:08:20 PM UTC 24 |
| Finished | Sep 01 07:46:03 PM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395172124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.1395172124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.4265432068 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 15801900 ps |
| CPU time | 16.5 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:22 PM UTC 24 |
| Peak memory | 272184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265432068 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.4265432068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2832613415 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12128080700 ps |
| CPU time | 389.17 seconds |
| Started | Sep 01 07:10:44 PM UTC 24 |
| Finished | Sep 01 07:17:18 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2832613415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_intr_rd_slow_flash.2832613415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.537179742 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 278485800 ps |
| CPU time | 155.32 seconds |
| Started | Sep 01 07:08:35 PM UTC 24 |
| Finished | Sep 01 07:11:14 PM UTC 24 |
| Peak memory | 271336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537179742 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.537179742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.245572561 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 474414300 ps |
| CPU time | 723.92 seconds |
| Started | Sep 01 07:04:20 PM UTC 24 |
| Finished | Sep 01 07:16:33 PM UTC 24 |
| Peak memory | 274600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245572561 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.245572561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1582360550 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7540909700 ps |
| CPU time | 120.32 seconds |
| Started | Sep 01 07:06:57 PM UTC 24 |
| Finished | Sep 01 07:08:59 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582360550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1582360550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3425820536 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 329651400 ps |
| CPU time | 23.43 seconds |
| Started | Sep 01 07:04:16 PM UTC 24 |
| Finished | Sep 01 07:04:41 PM UTC 24 |
| Peak memory | 274296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425820536 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3425820536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3262273266 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 15779100 ps |
| CPU time | 29.87 seconds |
| Started | Sep 01 07:07:30 PM UTC 24 |
| Finished | Sep 01 07:08:02 PM UTC 24 |
| Peak memory | 273800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262273266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3262273266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3789532683 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 31818300 ps |
| CPU time | 28.41 seconds |
| Started | Sep 01 07:07:51 PM UTC 24 |
| Finished | Sep 01 07:08:21 PM UTC 24 |
| Peak memory | 271604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789532683 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3789532683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2656720214 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 76426500 ps |
| CPU time | 186.91 seconds |
| Started | Sep 01 08:15:35 PM UTC 24 |
| Finished | Sep 01 08:18:46 PM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656720214 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.2656720214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1435068247 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2558049900 ps |
| CPU time | 129.84 seconds |
| Started | Sep 01 07:09:05 PM UTC 24 |
| Finished | Sep 01 07:11:17 PM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435068247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1435068247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3860943627 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 369761556000 ps |
| CPU time | 3474.95 seconds |
| Started | Sep 01 07:24:55 PM UTC 24 |
| Finished | Sep 01 08:23:32 PM UTC 24 |
| Peak memory | 278232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860943627 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3860943627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3446624236 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 117540000 ps |
| CPU time | 22.82 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:22 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446624236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.3446624236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1182932304 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 75779038000 ps |
| CPU time | 302.66 seconds |
| Started | Sep 01 07:13:59 PM UTC 24 |
| Finished | Sep 01 07:19:06 PM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1182932304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.1182932304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3702104373 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1505663500 ps |
| CPU time | 229.16 seconds |
| Started | Sep 01 07:06:18 PM UTC 24 |
| Finished | Sep 01 07:10:11 PM UTC 24 |
| Peak memory | 293888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702104373 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.3702104373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1128268273 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 6132590700 ps |
| CPU time | 204.77 seconds |
| Started | Sep 01 07:10:06 PM UTC 24 |
| Finished | Sep 01 07:13:34 PM UTC 24 |
| Peak memory | 300044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1128268273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_rw_derr.1128268273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.574899890 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 263319500 ps |
| CPU time | 58.03 seconds |
| Started | Sep 01 07:11:24 PM UTC 24 |
| Finished | Sep 01 07:12:24 PM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574899890 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.574899890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2913433739 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 15681700 ps |
| CPU time | 19.93 seconds |
| Started | Sep 01 07:24:08 PM UTC 24 |
| Finished | Sep 01 07:24:29 PM UTC 24 |
| Peak memory | 275636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2913433739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_lcmgr_intg.2913433739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1812631968 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 108791600 ps |
| CPU time | 24.05 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:23 PM UTC 24 |
| Peak memory | 274296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812631968 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1812631968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2492571416 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 55455400 ps |
| CPU time | 22.78 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:28 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492571416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.2492571416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.937426341 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2132468000 ps |
| CPU time | 99.32 seconds |
| Started | Sep 01 07:41:49 PM UTC 24 |
| Finished | Sep 01 07:43:30 PM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937426341 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.937426341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.516954996 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 10019077500 ps |
| CPU time | 90.02 seconds |
| Started | Sep 01 07:07:49 PM UTC 24 |
| Finished | Sep 01 07:09:21 PM UTC 24 |
| Peak memory | 320548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=516954996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.516954996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2971479646 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 790254900 ps |
| CPU time | 1240.3 seconds |
| Started | Sep 01 07:04:30 PM UTC 24 |
| Finished | Sep 01 07:25:24 PM UTC 24 |
| Peak memory | 276620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971479646 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.2971479646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3881036565 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 646111700 ps |
| CPU time | 41.15 seconds |
| Started | Sep 01 07:07:24 PM UTC 24 |
| Finished | Sep 01 07:08:07 PM UTC 24 |
| Peak memory | 275852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3881036565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3881036565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2815169800 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2000971500 ps |
| CPU time | 315.78 seconds |
| Started | Sep 01 07:34:39 PM UTC 24 |
| Finished | Sep 01 07:40:00 PM UTC 24 |
| Peak memory | 300044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2815169800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_rw_derr.2815169800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.1025673416 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15117600 ps |
| CPU time | 25.6 seconds |
| Started | Sep 01 07:23:48 PM UTC 24 |
| Finished | Sep 01 07:24:15 PM UTC 24 |
| Peak memory | 275572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1025673416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1025673416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2515096550 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 11858933800 ps |
| CPU time | 199.69 seconds |
| Started | Sep 01 08:11:37 PM UTC 24 |
| Finished | Sep 01 08:15:00 PM UTC 24 |
| Peak memory | 273360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515096550 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.2515096550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.3864131298 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2412887500 ps |
| CPU time | 176.74 seconds |
| Started | Sep 01 07:21:53 PM UTC 24 |
| Finished | Sep 01 07:24:53 PM UTC 24 |
| Peak memory | 293856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864131298 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.3864131298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3919989839 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 726883400 ps |
| CPU time | 1409.69 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:28:34 PM UTC 24 |
| Peak memory | 276488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919989839 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.3919989839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.1101464534 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5087297700 ps |
| CPU time | 59.34 seconds |
| Started | Sep 01 07:12:13 PM UTC 24 |
| Finished | Sep 01 07:13:14 PM UTC 24 |
| Peak memory | 273496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101464 534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f s_sup.1101464534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1171286874 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 109800820100 ps |
| CPU time | 426.22 seconds |
| Started | Sep 01 07:08:42 PM UTC 24 |
| Finished | Sep 01 07:15:55 PM UTC 24 |
| Peak memory | 283528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1171286874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.1171286874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2183352419 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1191177300 ps |
| CPU time | 71.58 seconds |
| Started | Sep 01 07:29:14 PM UTC 24 |
| Finished | Sep 01 07:30:28 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183352419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2183352419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.124514430 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 17059500 ps |
| CPU time | 26.44 seconds |
| Started | Sep 01 07:07:22 PM UTC 24 |
| Finished | Sep 01 07:07:50 PM UTC 24 |
| Peak memory | 275600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=124514430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.124514430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.3198537033 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 112581700 ps |
| CPU time | 39.99 seconds |
| Started | Sep 01 07:22:53 PM UTC 24 |
| Finished | Sep 01 07:23:34 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198537033 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.3198537033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.4086417385 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 936181700 ps |
| CPU time | 2991.28 seconds |
| Started | Sep 01 07:06:08 PM UTC 24 |
| Finished | Sep 01 07:56:29 PM UTC 24 |
| Peak memory | 278108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 86417385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _error_prog_type.4086417385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.661407940 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 94533900 ps |
| CPU time | 57.28 seconds |
| Started | Sep 01 07:31:58 PM UTC 24 |
| Finished | Sep 01 07:32:57 PM UTC 24 |
| Peak memory | 287752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661407940 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.661407940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3788172522 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 45158200 ps |
| CPU time | 18.62 seconds |
| Started | Sep 01 07:17:53 PM UTC 24 |
| Finished | Sep 01 07:18:13 PM UTC 24 |
| Peak memory | 269616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3788172522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3788172522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.1573425710 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 40035000 ps |
| CPU time | 17.14 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:04:20 PM UTC 24 |
| Peak memory | 272052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573425710 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1573425710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3365096719 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 136532700 ps |
| CPU time | 32.48 seconds |
| Started | Sep 01 07:40:34 PM UTC 24 |
| Finished | Sep 01 07:41:07 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365096719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3365096719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.417175401 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 559305700 ps |
| CPU time | 140.25 seconds |
| Started | Sep 01 07:06:11 PM UTC 24 |
| Finished | Sep 01 07:08:34 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=417175401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ ctrl_ro_serr.417175401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.28383463 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 885175600 ps |
| CPU time | 41.52 seconds |
| Started | Sep 01 07:17:40 PM UTC 24 |
| Finished | Sep 01 07:18:24 PM UTC 24 |
| Peak memory | 275556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=28383463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.28383463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.908116610 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 11911558800 ps |
| CPU time | 1691.64 seconds |
| Started | Sep 01 07:06:08 PM UTC 24 |
| Finished | Sep 01 07:34:38 PM UTC 24 |
| Peak memory | 288304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908116610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.908116610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.481049890 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 507335400 ps |
| CPU time | 62 seconds |
| Started | Sep 01 07:17:38 PM UTC 24 |
| Finished | Sep 01 07:18:42 PM UTC 24 |
| Peak memory | 275392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4810498 90 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fs _sup.481049890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1295972276 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3906642600 ps |
| CPU time | 29.27 seconds |
| Started | Sep 01 07:08:50 PM UTC 24 |
| Finished | Sep 01 07:09:21 PM UTC 24 |
| Peak memory | 273268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12 95972276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc h_code.1295972276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1578457493 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 45586300 ps |
| CPU time | 24.32 seconds |
| Started | Sep 01 07:12:25 PM UTC 24 |
| Finished | Sep 01 07:12:51 PM UTC 24 |
| Peak memory | 293240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578457493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1578457493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.202907875 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1587070700 ps |
| CPU time | 6529.38 seconds |
| Started | Sep 01 07:06:52 PM UTC 24 |
| Finished | Sep 01 08:56:51 PM UTC 24 |
| Peak memory | 316504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202907875 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.202907875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.398419519 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 15535900 ps |
| CPU time | 25.11 seconds |
| Started | Sep 01 07:50:21 PM UTC 24 |
| Finished | Sep 01 07:50:48 PM UTC 24 |
| Peak memory | 275436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=398419519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas h_ctrl_lcmgr_intg.398419519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1168810530 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 23987700 ps |
| CPU time | 38.66 seconds |
| Started | Sep 01 08:11:22 PM UTC 24 |
| Finished | Sep 01 08:12:03 PM UTC 24 |
| Peak memory | 285860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1168810530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.1168810530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.336901646 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 100147980600 ps |
| CPU time | 999.71 seconds |
| Started | Sep 01 07:36:51 PM UTC 24 |
| Finished | Sep 01 07:53:43 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336901646 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.336901646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1608566459 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 10034086000 ps |
| CPU time | 133.95 seconds |
| Started | Sep 01 07:50:26 PM UTC 24 |
| Finished | Sep 01 07:52:43 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1608566459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1608566459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3752806787 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 10019158000 ps |
| CPU time | 103.6 seconds |
| Started | Sep 01 07:52:48 PM UTC 24 |
| Finished | Sep 01 07:54:33 PM UTC 24 |
| Peak memory | 281760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3752806787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3752806787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.672951566 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 29687000 ps |
| CPU time | 28.36 seconds |
| Started | Sep 01 07:12:57 PM UTC 24 |
| Finished | Sep 01 07:13:26 PM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=672951566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_hw_read_seed_err.672951566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.1275314469 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 14573680100 ps |
| CPU time | 83.2 seconds |
| Started | Sep 01 07:49:55 PM UTC 24 |
| Finished | Sep 01 07:51:20 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275314469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1275314469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.3374621691 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 3005841700 ps |
| CPU time | 98.76 seconds |
| Started | Sep 01 07:59:53 PM UTC 24 |
| Finished | Sep 01 08:01:34 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374621691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3374621691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.713249043 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 33036900 ps |
| CPU time | 63.82 seconds |
| Started | Sep 01 08:10:29 PM UTC 24 |
| Finished | Sep 01 08:11:35 PM UTC 24 |
| Peak memory | 285704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=713249043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ct rl_rw_evict_all_en.713249043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3146291607 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3151459000 ps |
| CPU time | 108.76 seconds |
| Started | Sep 01 07:32:30 PM UTC 24 |
| Finished | Sep 01 07:34:21 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146291607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3146291607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2862685463 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 31686400 ps |
| CPU time | 49.26 seconds |
| Started | Sep 01 07:40:12 PM UTC 24 |
| Finished | Sep 01 07:41:03 PM UTC 24 |
| Peak memory | 281508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2862685463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct rl_rw_evict_all_en.2862685463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.2979197125 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 224055700 ps |
| CPU time | 54.24 seconds |
| Started | Sep 01 07:06:36 PM UTC 24 |
| Finished | Sep 01 07:07:32 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979197125 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.2979197125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4038398663 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 237961400 ps |
| CPU time | 25.4 seconds |
| Started | Sep 01 07:05:19 PM UTC 24 |
| Finished | Sep 01 07:05:46 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038398663 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.4038398663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.848918927 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 20170700 ps |
| CPU time | 26.19 seconds |
| Started | Sep 01 07:07:34 PM UTC 24 |
| Finished | Sep 01 07:08:01 PM UTC 24 |
| Peak memory | 273288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848918927 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.848918927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.527754097 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 827144000 ps |
| CPU time | 31.44 seconds |
| Started | Sep 01 07:12:24 PM UTC 24 |
| Finished | Sep 01 07:12:57 PM UTC 24 |
| Peak memory | 273516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=527754097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.527754097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2269505140 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 163688000 ps |
| CPU time | 30.63 seconds |
| Started | Sep 01 07:17:26 PM UTC 24 |
| Finished | Sep 01 07:17:58 PM UTC 24 |
| Peak memory | 273420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269505140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_wr_intg.2269505140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4094418826 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8101735800 ps |
| CPU time | 53.22 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:53 PM UTC 24 |
| Peak memory | 272356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094418826 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.4094418826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.2831479127 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1726889400 ps |
| CPU time | 156.7 seconds |
| Started | Sep 01 08:01:33 PM UTC 24 |
| Finished | Sep 01 08:04:13 PM UTC 24 |
| Peak memory | 306364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831479127 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.2831479127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.355875616 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 168723900 ps |
| CPU time | 20.63 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:06:00 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355875616 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.355875616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.227924327 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 707427500 ps |
| CPU time | 583.92 seconds |
| Started | Sep 01 07:04:54 PM UTC 24 |
| Finished | Sep 01 07:14:45 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227924327 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.227924327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1773633405 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 57115600 ps |
| CPU time | 21.7 seconds |
| Started | Sep 01 07:05:05 PM UTC 24 |
| Finished | Sep 01 07:05:28 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773633405 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.1773633405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.284006558 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1287871500 ps |
| CPU time | 658.84 seconds |
| Started | Sep 01 07:05:03 PM UTC 24 |
| Finished | Sep 01 07:16:11 PM UTC 24 |
| Peak memory | 284588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284006558 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.284006558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2757188035 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 753522300 ps |
| CPU time | 535.33 seconds |
| Started | Sep 01 07:05:14 PM UTC 24 |
| Finished | Sep 01 07:14:15 PM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757188035 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2757188035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2966405308 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 678809900 ps |
| CPU time | 734.96 seconds |
| Started | Sep 01 07:04:40 PM UTC 24 |
| Finished | Sep 01 07:17:04 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966405308 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.2966405308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.842360119 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 10550300 ps |
| CPU time | 33.24 seconds |
| Started | Sep 01 07:11:33 PM UTC 24 |
| Finished | Sep 01 07:12:08 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=842360119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_disable.842360119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2755698245 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 13236000 ps |
| CPU time | 27.85 seconds |
| Started | Sep 01 07:52:17 PM UTC 24 |
| Finished | Sep 01 07:52:46 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2755698245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ ctrl_disable.2755698245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.3791739978 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 69444200 ps |
| CPU time | 58.06 seconds |
| Started | Sep 01 08:05:57 PM UTC 24 |
| Finished | Sep 01 08:06:57 PM UTC 24 |
| Peak memory | 287984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791739978 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.3791739978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.297376750 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 13107500 ps |
| CPU time | 36.39 seconds |
| Started | Sep 01 08:08:00 PM UTC 24 |
| Finished | Sep 01 08:08:38 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=297376750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c trl_disable.297376750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.1756948466 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 644133200 ps |
| CPU time | 88.83 seconds |
| Started | Sep 01 08:08:10 PM UTC 24 |
| Finished | Sep 01 08:09:41 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756948466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1756948466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.2780611655 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 51522600 ps |
| CPU time | 37.24 seconds |
| Started | Sep 01 08:13:19 PM UTC 24 |
| Finished | Sep 01 08:13:57 PM UTC 24 |
| Peak memory | 275620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2780611655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ ctrl_disable.2780611655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.2993923524 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 31261100 ps |
| CPU time | 30.91 seconds |
| Started | Sep 01 08:15:20 PM UTC 24 |
| Finished | Sep 01 08:15:52 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2993923524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ ctrl_disable.2993923524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2739413937 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6531416900 ps |
| CPU time | 117.59 seconds |
| Started | Sep 01 08:19:44 PM UTC 24 |
| Finished | Sep 01 08:21:43 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739413937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2739413937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1209128107 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4196954300 ps |
| CPU time | 82.9 seconds |
| Started | Sep 01 07:06:19 PM UTC 24 |
| Finished | Sep 01 07:07:44 PM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209128107 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.1209128107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1375981173 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 40122450700 ps |
| CPU time | 953.46 seconds |
| Started | Sep 01 08:00:36 PM UTC 24 |
| Finished | Sep 01 08:16:44 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375981173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.1375981173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2880127589 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2288756700 ps |
| CPU time | 166.59 seconds |
| Started | Sep 01 07:10:13 PM UTC 24 |
| Finished | Sep 01 07:13:03 PM UTC 24 |
| Peak memory | 302240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2880127589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2880127589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3978165967 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 38257627900 ps |
| CPU time | 422.81 seconds |
| Started | Sep 01 08:07:18 PM UTC 24 |
| Finished | Sep 01 08:14:27 PM UTC 24 |
| Peak memory | 304220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3978165967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_intr_rd_slow_flash.3978165967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3872329142 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2318186800 ps |
| CPU time | 204.5 seconds |
| Started | Sep 01 07:21:19 PM UTC 24 |
| Finished | Sep 01 07:24:47 PM UTC 24 |
| Peak memory | 296124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3872329142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.3872329142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2582403673 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4184382500 ps |
| CPU time | 140.74 seconds |
| Started | Sep 01 07:38:32 PM UTC 24 |
| Finished | Sep 01 07:40:55 PM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582403673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2582403673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3500279747 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 218518100 ps |
| CPU time | 36.11 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:36 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500279747 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.3500279747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1412595736 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 175159600 ps |
| CPU time | 24.26 seconds |
| Started | Sep 01 07:05:02 PM UTC 24 |
| Finished | Sep 01 07:05:27 PM UTC 24 |
| Peak memory | 284708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1412595736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1412595736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2379910741 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 114459500 ps |
| CPU time | 30.42 seconds |
| Started | Sep 01 07:05:07 PM UTC 24 |
| Finished | Sep 01 07:05:38 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379910741 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.2379910741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1902508304 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1937039000 ps |
| CPU time | 1441.71 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:29:56 PM UTC 24 |
| Peak memory | 276492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902508304 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.1902508304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.1829515827 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 20893762600 ps |
| CPU time | 3307 seconds |
| Started | Sep 01 07:06:08 PM UTC 24 |
| Finished | Sep 01 08:01:50 PM UTC 24 |
| Peak memory | 276208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829515827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.1829515827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4130259514 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 232816464000 ps |
| CPU time | 4090.92 seconds |
| Started | Sep 01 07:06:07 PM UTC 24 |
| Finished | Sep 01 08:15:09 PM UTC 24 |
| Peak memory | 288372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130259514 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.4130259514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3320393015 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2146178300 ps |
| CPU time | 97.36 seconds |
| Started | Sep 01 07:06:09 PM UTC 24 |
| Finished | Sep 01 07:07:48 PM UTC 24 |
| Peak memory | 271084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320393015 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3320393015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.2530613106 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 14413100 ps |
| CPU time | 20.17 seconds |
| Started | Sep 01 07:17:30 PM UTC 24 |
| Finished | Sep 01 07:17:52 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2530613106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2530613106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1495608782 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2130205200 ps |
| CPU time | 258.09 seconds |
| Started | Sep 01 07:15:44 PM UTC 24 |
| Finished | Sep 01 07:20:06 PM UTC 24 |
| Peak memory | 294140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1495608782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rw_derr.1495608782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2609750584 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 17495900 ps |
| CPU time | 16.22 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:15 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609750584 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2609750584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2080185500 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 96070100 ps |
| CPU time | 15.68 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:15 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080185500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.2080185500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.495599376 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 47317700 ps |
| CPU time | 21.15 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:20 PM UTC 24 |
| Peak memory | 272228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495599376 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.495599376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1038629747 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 112267200 ps |
| CPU time | 37.91 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:38 PM UTC 24 |
| Peak memory | 272232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1038629747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ same_csr_outstanding.1038629747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.315842050 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 15071400 ps |
| CPU time | 21.57 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:21 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315 842050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shad ow_reg_errors.315842050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.941425912 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 21303700 ps |
| CPU time | 15.54 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:04:15 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=941425912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_shadow_reg_errors_with_csr_rw.941425912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.719555499 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 605808100 ps |
| CPU time | 1456.14 seconds |
| Started | Sep 01 07:03:58 PM UTC 24 |
| Finished | Sep 01 07:28:31 PM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719555499 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.719555499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4236769203 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5438713800 ps |
| CPU time | 49.54 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:55 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236769203 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.4236769203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1169318586 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2640392500 ps |
| CPU time | 73.45 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:05:19 PM UTC 24 |
| Peak memory | 272292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169318586 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.1169318586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1701077385 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 99920800 ps |
| CPU time | 51.98 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:57 PM UTC 24 |
| Peak memory | 272292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701077385 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.1701077385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.68109369 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 390438400 ps |
| CPU time | 20.36 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:26 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=68109369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.68109369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.209371500 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 70433400 ps |
| CPU time | 25.83 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:31 PM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209371500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.209371500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2866067514 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 23424700 ps |
| CPU time | 16.79 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:04:19 PM UTC 24 |
| Peak memory | 272296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866067514 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2866067514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.211053221 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 127623600 ps |
| CPU time | 22.07 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:27 PM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 211053221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_s ame_csr_outstanding.211053221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.936956806 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 15371300 ps |
| CPU time | 23.14 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:04:26 PM UTC 24 |
| Peak memory | 261548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936 956806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shad ow_reg_errors.936956806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3276257371 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 38947600 ps |
| CPU time | 18.27 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:04:21 PM UTC 24 |
| Peak memory | 261276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3276257371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3276257371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1612287518 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 119466700 ps |
| CPU time | 19.76 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:04:22 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612287518 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1612287518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1440623666 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 596904400 ps |
| CPU time | 729.03 seconds |
| Started | Sep 01 07:04:01 PM UTC 24 |
| Finished | Sep 01 07:16:19 PM UTC 24 |
| Peak memory | 274444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440623666 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.1440623666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.598934148 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 163218500 ps |
| CPU time | 27.41 seconds |
| Started | Sep 01 07:04:58 PM UTC 24 |
| Finished | Sep 01 07:05:26 PM UTC 24 |
| Peak memory | 284636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=598934148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.598934148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3051418210 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 65976500 ps |
| CPU time | 21.64 seconds |
| Started | Sep 01 07:04:57 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051418210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.3051418210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.4082408829 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 37724700 ps |
| CPU time | 22.88 seconds |
| Started | Sep 01 07:04:54 PM UTC 24 |
| Finished | Sep 01 07:05:18 PM UTC 24 |
| Peak memory | 272176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082408829 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.4082408829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3684139719 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 137650500 ps |
| CPU time | 21.22 seconds |
| Started | Sep 01 07:04:58 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 274268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3684139719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _same_csr_outstanding.3684139719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1330386688 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 12787000 ps |
| CPU time | 21.21 seconds |
| Started | Sep 01 07:04:54 PM UTC 24 |
| Finished | Sep 01 07:05:16 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133 0386688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.1330386688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2145089713 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 23343600 ps |
| CPU time | 26.74 seconds |
| Started | Sep 01 07:04:54 PM UTC 24 |
| Finished | Sep 01 07:05:22 PM UTC 24 |
| Peak memory | 261988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2145089713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f lash_ctrl_shadow_reg_errors_with_csr_rw.2145089713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.869772656 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 351345300 ps |
| CPU time | 30.34 seconds |
| Started | Sep 01 07:04:53 PM UTC 24 |
| Finished | Sep 01 07:05:24 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869772656 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.869772656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2417133674 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 66605500 ps |
| CPU time | 17.94 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417133674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.2417133674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3154748799 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 19346200 ps |
| CPU time | 21.14 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:05:23 PM UTC 24 |
| Peak memory | 272180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154748799 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.3154748799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4028281509 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 354405700 ps |
| CPU time | 25.12 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:05:27 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4028281509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.4028281509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1663712166 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 24627800 ps |
| CPU time | 18.02 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 261896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166 3712166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh adow_reg_errors.1663712166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3702168210 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 18383700 ps |
| CPU time | 22.77 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:05:25 PM UTC 24 |
| Peak memory | 261988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3702168210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f lash_ctrl_shadow_reg_errors_with_csr_rw.3702168210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3000171910 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 61676600 ps |
| CPU time | 26.36 seconds |
| Started | Sep 01 07:05:00 PM UTC 24 |
| Finished | Sep 01 07:05:28 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000171910 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.3000171910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1899284655 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1909519400 ps |
| CPU time | 686.1 seconds |
| Started | Sep 01 07:05:01 PM UTC 24 |
| Finished | Sep 01 07:16:35 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899284655 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.1899284655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2380820535 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 60214500 ps |
| CPU time | 21.78 seconds |
| Started | Sep 01 07:05:05 PM UTC 24 |
| Finished | Sep 01 07:05:28 PM UTC 24 |
| Peak memory | 284708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2380820535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2380820535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.75381920 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 19274600 ps |
| CPU time | 22.74 seconds |
| Started | Sep 01 07:05:05 PM UTC 24 |
| Finished | Sep 01 07:05:29 PM UTC 24 |
| Peak memory | 274268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75381920 -assert n opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.75381920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2693620529 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 291155000 ps |
| CPU time | 40.51 seconds |
| Started | Sep 01 07:05:05 PM UTC 24 |
| Finished | Sep 01 07:05:47 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2693620529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl _same_csr_outstanding.2693620529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.893645877 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 68939400 ps |
| CPU time | 22.22 seconds |
| Started | Sep 01 07:05:03 PM UTC 24 |
| Finished | Sep 01 07:05:26 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893 645877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sha dow_reg_errors.893645877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1024842086 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 13402300 ps |
| CPU time | 18.62 seconds |
| Started | Sep 01 07:05:04 PM UTC 24 |
| Finished | Sep 01 07:05:24 PM UTC 24 |
| Peak memory | 261988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1024842086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.1024842086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4126573371 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 61526100 ps |
| CPU time | 26.85 seconds |
| Started | Sep 01 07:05:02 PM UTC 24 |
| Finished | Sep 01 07:05:30 PM UTC 24 |
| Peak memory | 274356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126573371 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.4126573371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2715361146 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 130488700 ps |
| CPU time | 22.66 seconds |
| Started | Sep 01 07:05:13 PM UTC 24 |
| Finished | Sep 01 07:05:37 PM UTC 24 |
| Peak memory | 274400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2715361146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2715361146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1964978571 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 200559000 ps |
| CPU time | 21.49 seconds |
| Started | Sep 01 07:05:13 PM UTC 24 |
| Finished | Sep 01 07:05:35 PM UTC 24 |
| Peak memory | 272288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964978571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.1964978571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.171806931 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 16115100 ps |
| CPU time | 17.89 seconds |
| Started | Sep 01 07:05:12 PM UTC 24 |
| Finished | Sep 01 07:05:32 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171806931 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.171806931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1060223798 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 442965800 ps |
| CPU time | 24.71 seconds |
| Started | Sep 01 07:05:13 PM UTC 24 |
| Finished | Sep 01 07:05:39 PM UTC 24 |
| Peak memory | 274268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1060223798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _same_csr_outstanding.1060223798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2628464866 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 11479700 ps |
| CPU time | 23.82 seconds |
| Started | Sep 01 07:05:08 PM UTC 24 |
| Finished | Sep 01 07:05:33 PM UTC 24 |
| Peak memory | 261912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262 8464866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh adow_reg_errors.2628464866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3620027693 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 34785200 ps |
| CPU time | 19.94 seconds |
| Started | Sep 01 07:05:12 PM UTC 24 |
| Finished | Sep 01 07:05:34 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3620027693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f lash_ctrl_shadow_reg_errors_with_csr_rw.3620027693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3635445491 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1729318000 ps |
| CPU time | 611.65 seconds |
| Started | Sep 01 07:05:07 PM UTC 24 |
| Finished | Sep 01 07:15:26 PM UTC 24 |
| Peak memory | 274344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635445491 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.3635445491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.254688256 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 331641200 ps |
| CPU time | 24.96 seconds |
| Started | Sep 01 07:05:19 PM UTC 24 |
| Finished | Sep 01 07:05:45 PM UTC 24 |
| Peak memory | 284768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=254688256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.254688256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4287213995 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 43882300 ps |
| CPU time | 23.19 seconds |
| Started | Sep 01 07:05:18 PM UTC 24 |
| Finished | Sep 01 07:05:42 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287213995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.4287213995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2119109202 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 16086200 ps |
| CPU time | 16.41 seconds |
| Started | Sep 01 07:05:17 PM UTC 24 |
| Finished | Sep 01 07:05:35 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119109202 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.2119109202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2699825789 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 877406300 ps |
| CPU time | 23.62 seconds |
| Started | Sep 01 07:05:19 PM UTC 24 |
| Finished | Sep 01 07:05:44 PM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2699825789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _same_csr_outstanding.2699825789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3125883988 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 18224400 ps |
| CPU time | 17.09 seconds |
| Started | Sep 01 07:05:14 PM UTC 24 |
| Finished | Sep 01 07:05:32 PM UTC 24 |
| Peak memory | 262048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312 5883988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.3125883988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1640676350 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 97526600 ps |
| CPU time | 27.5 seconds |
| Started | Sep 01 07:05:15 PM UTC 24 |
| Finished | Sep 01 07:05:44 PM UTC 24 |
| Peak memory | 261988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1640676350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f lash_ctrl_shadow_reg_errors_with_csr_rw.1640676350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2191004318 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 72884600 ps |
| CPU time | 32.13 seconds |
| Started | Sep 01 07:05:13 PM UTC 24 |
| Finished | Sep 01 07:05:46 PM UTC 24 |
| Peak memory | 274356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191004318 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.2191004318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3407929052 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 89192700 ps |
| CPU time | 21.61 seconds |
| Started | Sep 01 07:05:22 PM UTC 24 |
| Finished | Sep 01 07:05:45 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3407929052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3407929052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4077975128 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 306353400 ps |
| CPU time | 21.2 seconds |
| Started | Sep 01 07:05:22 PM UTC 24 |
| Finished | Sep 01 07:05:44 PM UTC 24 |
| Peak memory | 274268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077975128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.4077975128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.211865118 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 153944200 ps |
| CPU time | 23.52 seconds |
| Started | Sep 01 07:05:21 PM UTC 24 |
| Finished | Sep 01 07:05:45 PM UTC 24 |
| Peak memory | 272176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211865118 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.211865118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.133603760 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 106137300 ps |
| CPU time | 20.23 seconds |
| Started | Sep 01 07:05:22 PM UTC 24 |
| Finished | Sep 01 07:05:43 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 133603760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ same_csr_outstanding.133603760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.396666187 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 12629300 ps |
| CPU time | 21.14 seconds |
| Started | Sep 01 07:05:21 PM UTC 24 |
| Finished | Sep 01 07:05:43 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396 666187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sha dow_reg_errors.396666187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1377190009 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 31225000 ps |
| CPU time | 21.33 seconds |
| Started | Sep 01 07:05:21 PM UTC 24 |
| Finished | Sep 01 07:05:43 PM UTC 24 |
| Peak memory | 262052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1377190009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f lash_ctrl_shadow_reg_errors_with_csr_rw.1377190009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.540702656 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 359101200 ps |
| CPU time | 678.65 seconds |
| Started | Sep 01 07:05:20 PM UTC 24 |
| Finished | Sep 01 07:16:47 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540702656 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.540702656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4101613723 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 383281400 ps |
| CPU time | 22.08 seconds |
| Started | Sep 01 07:05:25 PM UTC 24 |
| Finished | Sep 01 07:05:49 PM UTC 24 |
| Peak memory | 284712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4101613723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4101613723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.910866538 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 62869300 ps |
| CPU time | 19.84 seconds |
| Started | Sep 01 07:05:25 PM UTC 24 |
| Finished | Sep 01 07:05:46 PM UTC 24 |
| Peak memory | 274264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910866538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.910866538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1824779501 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 17869500 ps |
| CPU time | 22.27 seconds |
| Started | Sep 01 07:05:25 PM UTC 24 |
| Finished | Sep 01 07:05:49 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824779501 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.1824779501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2777811164 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 229394700 ps |
| CPU time | 20.82 seconds |
| Started | Sep 01 07:05:25 PM UTC 24 |
| Finished | Sep 01 07:05:47 PM UTC 24 |
| Peak memory | 272220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2777811164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _same_csr_outstanding.2777811164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1459339558 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 36566600 ps |
| CPU time | 22.17 seconds |
| Started | Sep 01 07:05:24 PM UTC 24 |
| Finished | Sep 01 07:05:47 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145 9339558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh adow_reg_errors.1459339558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.57723822 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 13268100 ps |
| CPU time | 24.9 seconds |
| Started | Sep 01 07:05:25 PM UTC 24 |
| Finished | Sep 01 07:05:51 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=57723822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_shadow_reg_errors_with_csr_rw.57723822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1223655472 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 52620400 ps |
| CPU time | 23.92 seconds |
| Started | Sep 01 07:05:22 PM UTC 24 |
| Finished | Sep 01 07:05:47 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223655472 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.1223655472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2477614708 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 338057500 ps |
| CPU time | 1127.75 seconds |
| Started | Sep 01 07:05:23 PM UTC 24 |
| Finished | Sep 01 07:24:23 PM UTC 24 |
| Peak memory | 276484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477614708 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.2477614708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.402519111 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 112167600 ps |
| CPU time | 24.95 seconds |
| Started | Sep 01 07:05:29 PM UTC 24 |
| Finished | Sep 01 07:05:55 PM UTC 24 |
| Peak memory | 284704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=402519111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.402519111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1823560167 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 17804900 ps |
| CPU time | 19.24 seconds |
| Started | Sep 01 07:05:29 PM UTC 24 |
| Finished | Sep 01 07:05:49 PM UTC 24 |
| Peak memory | 272216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823560167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.1823560167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1284969149 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 111351300 ps |
| CPU time | 16.19 seconds |
| Started | Sep 01 07:05:29 PM UTC 24 |
| Finished | Sep 01 07:05:46 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284969149 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.1284969149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3807762964 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 534380900 ps |
| CPU time | 23.13 seconds |
| Started | Sep 01 07:05:29 PM UTC 24 |
| Finished | Sep 01 07:05:53 PM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3807762964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl _same_csr_outstanding.3807762964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.249805170 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 12160300 ps |
| CPU time | 27.63 seconds |
| Started | Sep 01 07:05:28 PM UTC 24 |
| Finished | Sep 01 07:05:57 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249 805170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sha dow_reg_errors.249805170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1819674067 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 19450600 ps |
| CPU time | 17.1 seconds |
| Started | Sep 01 07:05:29 PM UTC 24 |
| Finished | Sep 01 07:05:47 PM UTC 24 |
| Peak memory | 262052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1819674067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f lash_ctrl_shadow_reg_errors_with_csr_rw.1819674067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1439977 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 109478400 ps |
| CPU time | 25.64 seconds |
| Started | Sep 01 07:05:28 PM UTC 24 |
| Finished | Sep 01 07:05:54 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439977 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.1439977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3940567771 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2520391000 ps |
| CPU time | 565.76 seconds |
| Started | Sep 01 07:05:28 PM UTC 24 |
| Finished | Sep 01 07:15:01 PM UTC 24 |
| Peak memory | 274348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940567771 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.3940567771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3453309308 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 331379500 ps |
| CPU time | 27.03 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:06:03 PM UTC 24 |
| Peak memory | 284644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3453309308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3453309308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.910446854 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 248194000 ps |
| CPU time | 21.08 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:05:56 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910446854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.910446854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1887340321 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 28218100 ps |
| CPU time | 18.99 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:05:54 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887340321 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.1887340321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.377375420 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 106261200 ps |
| CPU time | 27.93 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:06:03 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 377375420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ same_csr_outstanding.377375420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.938514416 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 12297400 ps |
| CPU time | 30.12 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:06:05 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938 514416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sha dow_reg_errors.938514416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3972673667 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 14276800 ps |
| CPU time | 22.87 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:05:58 PM UTC 24 |
| Peak memory | 261916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3972673667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f lash_ctrl_shadow_reg_errors_with_csr_rw.3972673667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3854193085 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 97367500 ps |
| CPU time | 34.15 seconds |
| Started | Sep 01 07:05:30 PM UTC 24 |
| Finished | Sep 01 07:06:06 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854193085 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.3854193085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1208797996 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 346287300 ps |
| CPU time | 701.94 seconds |
| Started | Sep 01 07:05:34 PM UTC 24 |
| Finished | Sep 01 07:17:24 PM UTC 24 |
| Peak memory | 274348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208797996 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.1208797996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.358328072 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 334273400 ps |
| CPU time | 25.87 seconds |
| Started | Sep 01 07:05:40 PM UTC 24 |
| Finished | Sep 01 07:06:07 PM UTC 24 |
| Peak memory | 284704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=358328072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.358328072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2623400669 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 118266900 ps |
| CPU time | 27.13 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:06:06 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623400669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.2623400669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3620870949 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 47415400 ps |
| CPU time | 20.75 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:06:00 PM UTC 24 |
| Peak memory | 272240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620870949 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3620870949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3699274539 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 287177500 ps |
| CPU time | 45.96 seconds |
| Started | Sep 01 07:05:39 PM UTC 24 |
| Finished | Sep 01 07:06:26 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3699274539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl _same_csr_outstanding.3699274539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3323792856 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 35396000 ps |
| CPU time | 21.79 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:06:01 PM UTC 24 |
| Peak memory | 261912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332 3792856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.3323792856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.232729949 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 24582300 ps |
| CPU time | 18.68 seconds |
| Started | Sep 01 07:05:38 PM UTC 24 |
| Finished | Sep 01 07:05:58 PM UTC 24 |
| Peak memory | 261980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=232729949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_shadow_reg_errors_with_csr_rw.232729949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3175298195 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 3077254200 ps |
| CPU time | 77.99 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:05:28 PM UTC 24 |
| Peak memory | 272292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175298195 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.3175298195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1601957863 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 6196999100 ps |
| CPU time | 80.27 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:05:30 PM UTC 24 |
| Peak memory | 272140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601957863 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.1601957863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3053613884 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 98379000 ps |
| CPU time | 67.67 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:05:17 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053613884 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.3053613884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.463315866 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 163424100 ps |
| CPU time | 28.74 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:38 PM UTC 24 |
| Peak memory | 284636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=463315866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.463315866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1511245328 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 42495000 ps |
| CPU time | 25.02 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:34 PM UTC 24 |
| Peak memory | 273984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511245328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1511245328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2772367586 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 86766900 ps |
| CPU time | 17.72 seconds |
| Started | Sep 01 07:04:07 PM UTC 24 |
| Finished | Sep 01 07:04:26 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772367586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.2772367586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.27881549 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 14799200 ps |
| CPU time | 27.39 seconds |
| Started | Sep 01 07:04:07 PM UTC 24 |
| Finished | Sep 01 07:04:36 PM UTC 24 |
| Peak memory | 272304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27881549 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.27881549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3718532087 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 162289000 ps |
| CPU time | 28.86 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:38 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3718532087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.3718532087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1905108274 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 44688500 ps |
| CPU time | 19.3 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:25 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190 5108274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.1905108274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2682580807 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 13665600 ps |
| CPU time | 21.69 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:27 PM UTC 24 |
| Peak memory | 261916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2682580807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2682580807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3196488486 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 59800000 ps |
| CPU time | 23.07 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:04:29 PM UTC 24 |
| Peak memory | 274296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196488486 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3196488486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.937398490 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 3538339600 ps |
| CPU time | 1380.88 seconds |
| Started | Sep 01 07:04:04 PM UTC 24 |
| Finished | Sep 01 07:27:21 PM UTC 24 |
| Peak memory | 276488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937398490 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.937398490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1602121579 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 42184700 ps |
| CPU time | 18.92 seconds |
| Started | Sep 01 07:05:43 PM UTC 24 |
| Finished | Sep 01 07:06:03 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602121579 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.1602121579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2015143838 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 47129300 ps |
| CPU time | 18.42 seconds |
| Started | Sep 01 07:05:44 PM UTC 24 |
| Finished | Sep 01 07:06:04 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015143838 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.2015143838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3619256793 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 50541700 ps |
| CPU time | 18.5 seconds |
| Started | Sep 01 07:05:44 PM UTC 24 |
| Finished | Sep 01 07:06:04 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619256793 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.3619256793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.480734535 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 17115400 ps |
| CPU time | 17.93 seconds |
| Started | Sep 01 07:05:44 PM UTC 24 |
| Finished | Sep 01 07:06:03 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480734535 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.480734535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2903752901 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 30583800 ps |
| CPU time | 18.29 seconds |
| Started | Sep 01 07:05:44 PM UTC 24 |
| Finished | Sep 01 07:06:04 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903752901 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.2903752901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2286331498 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 44265200 ps |
| CPU time | 23.66 seconds |
| Started | Sep 01 07:05:45 PM UTC 24 |
| Finished | Sep 01 07:06:10 PM UTC 24 |
| Peak memory | 272040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286331498 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.2286331498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.3549097281 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 30497900 ps |
| CPU time | 22.92 seconds |
| Started | Sep 01 07:05:45 PM UTC 24 |
| Finished | Sep 01 07:06:10 PM UTC 24 |
| Peak memory | 272240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549097281 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.3549097281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3581256823 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 72127400 ps |
| CPU time | 18.54 seconds |
| Started | Sep 01 07:05:45 PM UTC 24 |
| Finished | Sep 01 07:06:05 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581256823 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.3581256823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.923995878 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 31022700 ps |
| CPU time | 21.95 seconds |
| Started | Sep 01 07:05:47 PM UTC 24 |
| Finished | Sep 01 07:06:10 PM UTC 24 |
| Peak memory | 272176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923995878 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.923995878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.1965334862 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 44732800 ps |
| CPU time | 18.29 seconds |
| Started | Sep 01 07:05:47 PM UTC 24 |
| Finished | Sep 01 07:06:06 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965334862 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.1965334862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1415854029 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1484526300 ps |
| CPU time | 62.92 seconds |
| Started | Sep 01 07:04:16 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 272228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415854029 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1415854029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.87914622 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 7482322500 ps |
| CPU time | 55.31 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:05:05 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87914622 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.87914622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1464895294 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 91983200 ps |
| CPU time | 39.74 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:49 PM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464895294 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.1464895294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1631491773 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 57562500 ps |
| CPU time | 23.95 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:34 PM UTC 24 |
| Peak memory | 272352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631491773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1631491773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1790610984 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 66369400 ps |
| CPU time | 20.36 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:30 PM UTC 24 |
| Peak memory | 272184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790610984 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1790610984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3017474492 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 14834300 ps |
| CPU time | 17.03 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:26 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017474492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.3017474492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2729471078 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 66695800 ps |
| CPU time | 25.51 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:35 PM UTC 24 |
| Peak memory | 272232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729471078 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.2729471078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.840036739 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 69805300 ps |
| CPU time | 21.9 seconds |
| Started | Sep 01 07:04:16 PM UTC 24 |
| Finished | Sep 01 07:04:39 PM UTC 24 |
| Peak memory | 272092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 840036739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_s ame_csr_outstanding.840036739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.300981876 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 18789400 ps |
| CPU time | 21.1 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:30 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300 981876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shad ow_reg_errors.300981876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.167121052 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 14609500 ps |
| CPU time | 22.74 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:32 PM UTC 24 |
| Peak memory | 261916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=167121052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_shadow_reg_errors_with_csr_rw.167121052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3004556068 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 143454400 ps |
| CPU time | 25.68 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:04:35 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004556068 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3004556068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4135196255 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 420787000 ps |
| CPU time | 785.27 seconds |
| Started | Sep 01 07:04:08 PM UTC 24 |
| Finished | Sep 01 07:17:23 PM UTC 24 |
| Peak memory | 276400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135196255 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.4135196255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1341875868 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 71390700 ps |
| CPU time | 20.35 seconds |
| Started | Sep 01 07:05:47 PM UTC 24 |
| Finished | Sep 01 07:06:08 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341875868 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1341875868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2002800669 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 74206600 ps |
| CPU time | 20.25 seconds |
| Started | Sep 01 07:05:47 PM UTC 24 |
| Finished | Sep 01 07:06:08 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002800669 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.2002800669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.304394634 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 31665000 ps |
| CPU time | 20.49 seconds |
| Started | Sep 01 07:05:47 PM UTC 24 |
| Finished | Sep 01 07:06:08 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304394634 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.304394634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3388589449 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 43079900 ps |
| CPU time | 22.36 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:11 PM UTC 24 |
| Peak memory | 272040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388589449 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.3388589449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1324046264 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 28331900 ps |
| CPU time | 18.21 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:07 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324046264 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.1324046264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2326081158 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 42298800 ps |
| CPU time | 19.85 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:09 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326081158 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2326081158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.784373640 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 24981700 ps |
| CPU time | 17.4 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:06 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784373640 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.784373640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.838227618 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 15062100 ps |
| CPU time | 20.33 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:10 PM UTC 24 |
| Peak memory | 272176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838227618 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.838227618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3522409441 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 22741400 ps |
| CPU time | 25.76 seconds |
| Started | Sep 01 07:05:48 PM UTC 24 |
| Finished | Sep 01 07:06:15 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522409441 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.3522409441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.209655012 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 31493100 ps |
| CPU time | 21.45 seconds |
| Started | Sep 01 07:05:52 PM UTC 24 |
| Finished | Sep 01 07:06:15 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209655012 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.209655012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2388069631 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 226396800 ps |
| CPU time | 34.12 seconds |
| Started | Sep 01 07:04:24 PM UTC 24 |
| Finished | Sep 01 07:04:59 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388069631 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.2388069631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2401554907 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1583300700 ps |
| CPU time | 52.93 seconds |
| Started | Sep 01 07:04:24 PM UTC 24 |
| Finished | Sep 01 07:05:18 PM UTC 24 |
| Peak memory | 272268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401554907 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.2401554907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1904944776 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 84963400 ps |
| CPU time | 68.76 seconds |
| Started | Sep 01 07:04:24 PM UTC 24 |
| Finished | Sep 01 07:05:35 PM UTC 24 |
| Peak memory | 274340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904944776 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.1904944776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1007717444 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 37526500 ps |
| CPU time | 25.87 seconds |
| Started | Sep 01 07:04:25 PM UTC 24 |
| Finished | Sep 01 07:04:53 PM UTC 24 |
| Peak memory | 290776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1007717444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1007717444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3524542190 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 43675200 ps |
| CPU time | 20.48 seconds |
| Started | Sep 01 07:04:24 PM UTC 24 |
| Finished | Sep 01 07:04:46 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524542190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.3524542190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2354332494 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 29832400 ps |
| CPU time | 17.33 seconds |
| Started | Sep 01 07:04:21 PM UTC 24 |
| Finished | Sep 01 07:04:40 PM UTC 24 |
| Peak memory | 272080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354332494 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2354332494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1956787214 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 44675500 ps |
| CPU time | 23.52 seconds |
| Started | Sep 01 07:04:22 PM UTC 24 |
| Finished | Sep 01 07:04:48 PM UTC 24 |
| Peak memory | 274348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956787214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.1956787214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3099740639 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 47880600 ps |
| CPU time | 16.13 seconds |
| Started | Sep 01 07:04:22 PM UTC 24 |
| Finished | Sep 01 07:04:40 PM UTC 24 |
| Peak memory | 272296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099740639 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.3099740639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1348576382 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 204704200 ps |
| CPU time | 26.73 seconds |
| Started | Sep 01 07:04:24 PM UTC 24 |
| Finished | Sep 01 07:04:52 PM UTC 24 |
| Peak memory | 272232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1348576382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ same_csr_outstanding.1348576382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1992579335 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 18296300 ps |
| CPU time | 24.62 seconds |
| Started | Sep 01 07:04:20 PM UTC 24 |
| Finished | Sep 01 07:04:46 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199 2579335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha dow_reg_errors.1992579335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1282732188 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 13914900 ps |
| CPU time | 17.92 seconds |
| Started | Sep 01 07:04:21 PM UTC 24 |
| Finished | Sep 01 07:04:40 PM UTC 24 |
| Peak memory | 261972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1282732188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1282732188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2290374603 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 55196900 ps |
| CPU time | 19.49 seconds |
| Started | Sep 01 07:05:52 PM UTC 24 |
| Finished | Sep 01 07:06:12 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290374603 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.2290374603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3089343989 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 92869800 ps |
| CPU time | 19.78 seconds |
| Started | Sep 01 07:05:52 PM UTC 24 |
| Finished | Sep 01 07:06:13 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089343989 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.3089343989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3990951599 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 43302100 ps |
| CPU time | 19.32 seconds |
| Started | Sep 01 07:05:53 PM UTC 24 |
| Finished | Sep 01 07:06:14 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990951599 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.3990951599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.571458487 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 52230900 ps |
| CPU time | 18.07 seconds |
| Started | Sep 01 07:05:53 PM UTC 24 |
| Finished | Sep 01 07:06:13 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571458487 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.571458487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3943053449 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 52862800 ps |
| CPU time | 21.29 seconds |
| Started | Sep 01 07:05:55 PM UTC 24 |
| Finished | Sep 01 07:06:18 PM UTC 24 |
| Peak memory | 272176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943053449 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.3943053449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.715940756 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 58465400 ps |
| CPU time | 26.8 seconds |
| Started | Sep 01 07:05:55 PM UTC 24 |
| Finished | Sep 01 07:06:23 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715940756 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.715940756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2542447645 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 91236000 ps |
| CPU time | 18.74 seconds |
| Started | Sep 01 07:05:55 PM UTC 24 |
| Finished | Sep 01 07:06:15 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542447645 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.2542447645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.4040575751 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 18253200 ps |
| CPU time | 18.36 seconds |
| Started | Sep 01 07:05:56 PM UTC 24 |
| Finished | Sep 01 07:06:16 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040575751 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.4040575751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1059162558 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 29643500 ps |
| CPU time | 20.28 seconds |
| Started | Sep 01 07:05:57 PM UTC 24 |
| Finished | Sep 01 07:06:20 PM UTC 24 |
| Peak memory | 272108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059162558 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.1059162558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.4056584422 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 76203600 ps |
| CPU time | 17.82 seconds |
| Started | Sep 01 07:05:57 PM UTC 24 |
| Finished | Sep 01 07:06:17 PM UTC 24 |
| Peak memory | 272104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056584422 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.4056584422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3990744090 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 754040500 ps |
| CPU time | 34.31 seconds |
| Started | Sep 01 07:04:30 PM UTC 24 |
| Finished | Sep 01 07:05:06 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3990744090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3990744090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2354333904 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 124415200 ps |
| CPU time | 27.85 seconds |
| Started | Sep 01 07:04:28 PM UTC 24 |
| Finished | Sep 01 07:04:58 PM UTC 24 |
| Peak memory | 272288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354333904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.2354333904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.3475394921 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 24411500 ps |
| CPU time | 17.86 seconds |
| Started | Sep 01 07:04:28 PM UTC 24 |
| Finished | Sep 01 07:04:48 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475394921 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3475394921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3514704999 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 125159800 ps |
| CPU time | 48.32 seconds |
| Started | Sep 01 07:04:30 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 272296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3514704999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ same_csr_outstanding.3514704999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2252053249 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 11775700 ps |
| CPU time | 24.43 seconds |
| Started | Sep 01 07:04:27 PM UTC 24 |
| Finished | Sep 01 07:04:53 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225 2053249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha dow_reg_errors.2252053249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2244883655 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 14594400 ps |
| CPU time | 20.22 seconds |
| Started | Sep 01 07:04:28 PM UTC 24 |
| Finished | Sep 01 07:04:50 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2244883655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2244883655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3828347602 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 63616800 ps |
| CPU time | 19.11 seconds |
| Started | Sep 01 07:04:25 PM UTC 24 |
| Finished | Sep 01 07:04:46 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828347602 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3828347602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2768590573 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1746313300 ps |
| CPU time | 1531.11 seconds |
| Started | Sep 01 07:04:26 PM UTC 24 |
| Finished | Sep 01 07:30:17 PM UTC 24 |
| Peak memory | 276484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768590573 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2768590573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1567153164 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 170374300 ps |
| CPU time | 22.94 seconds |
| Started | Sep 01 07:04:34 PM UTC 24 |
| Finished | Sep 01 07:04:59 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1567153164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1567153164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2989643208 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 52972200 ps |
| CPU time | 21.03 seconds |
| Started | Sep 01 07:04:32 PM UTC 24 |
| Finished | Sep 01 07:04:55 PM UTC 24 |
| Peak memory | 272220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989643208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.2989643208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1868396843 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 16405400 ps |
| CPU time | 16.28 seconds |
| Started | Sep 01 07:04:31 PM UTC 24 |
| Finished | Sep 01 07:04:49 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868396843 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1868396843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2952838202 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 1529406700 ps |
| CPU time | 24.02 seconds |
| Started | Sep 01 07:04:33 PM UTC 24 |
| Finished | Sep 01 07:04:59 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2952838202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ same_csr_outstanding.2952838202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4210184426 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 41651000 ps |
| CPU time | 28.18 seconds |
| Started | Sep 01 07:04:30 PM UTC 24 |
| Finished | Sep 01 07:05:00 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421 0184426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha dow_reg_errors.4210184426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2760852852 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 15120600 ps |
| CPU time | 20.28 seconds |
| Started | Sep 01 07:04:31 PM UTC 24 |
| Finished | Sep 01 07:04:53 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2760852852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2760852852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2602174023 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 43692000 ps |
| CPU time | 19.87 seconds |
| Started | Sep 01 07:04:30 PM UTC 24 |
| Finished | Sep 01 07:04:52 PM UTC 24 |
| Peak memory | 274296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602174023 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2602174023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2197578861 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 117657700 ps |
| CPU time | 24.13 seconds |
| Started | Sep 01 07:04:39 PM UTC 24 |
| Finished | Sep 01 07:05:05 PM UTC 24 |
| Peak memory | 274188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2197578861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2197578861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3304296283 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 67477500 ps |
| CPU time | 28.32 seconds |
| Started | Sep 01 07:04:38 PM UTC 24 |
| Finished | Sep 01 07:05:08 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304296283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.3304296283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.653571949 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 14551200 ps |
| CPU time | 24.26 seconds |
| Started | Sep 01 07:04:37 PM UTC 24 |
| Finished | Sep 01 07:05:02 PM UTC 24 |
| Peak memory | 272100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653571949 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.653571949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.118889237 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 256721100 ps |
| CPU time | 44.18 seconds |
| Started | Sep 01 07:04:39 PM UTC 24 |
| Finished | Sep 01 07:05:25 PM UTC 24 |
| Peak memory | 271920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 118889237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_s ame_csr_outstanding.118889237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2636481349 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 21271600 ps |
| CPU time | 27.98 seconds |
| Started | Sep 01 07:04:36 PM UTC 24 |
| Finished | Sep 01 07:05:05 PM UTC 24 |
| Peak memory | 261928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263 6481349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha dow_reg_errors.2636481349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.549718753 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 33473900 ps |
| CPU time | 19.59 seconds |
| Started | Sep 01 07:04:37 PM UTC 24 |
| Finished | Sep 01 07:04:58 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=549718753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_shadow_reg_errors_with_csr_rw.549718753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.561761852 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 57380400 ps |
| CPU time | 23.3 seconds |
| Started | Sep 01 07:04:36 PM UTC 24 |
| Finished | Sep 01 07:05:00 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561761852 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.561761852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3018718119 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1278487300 ps |
| CPU time | 1271.5 seconds |
| Started | Sep 01 07:04:36 PM UTC 24 |
| Finished | Sep 01 07:26:02 PM UTC 24 |
| Peak memory | 276484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018718119 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.3018718119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2698246455 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 89712300 ps |
| CPU time | 22.18 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:05:12 PM UTC 24 |
| Peak memory | 290576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2698246455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2698246455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3223579469 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 37613800 ps |
| CPU time | 18.24 seconds |
| Started | Sep 01 07:04:42 PM UTC 24 |
| Finished | Sep 01 07:05:02 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223579469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.3223579469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1757501466 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 17686000 ps |
| CPU time | 20.33 seconds |
| Started | Sep 01 07:04:41 PM UTC 24 |
| Finished | Sep 01 07:05:03 PM UTC 24 |
| Peak memory | 272116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757501466 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1757501466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1375767328 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 303336400 ps |
| CPU time | 34.6 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:05:24 PM UTC 24 |
| Peak memory | 273956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1375767328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.1375767328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2724270625 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 46100300 ps |
| CPU time | 21.87 seconds |
| Started | Sep 01 07:04:41 PM UTC 24 |
| Finished | Sep 01 07:05:05 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272 4270625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha dow_reg_errors.2724270625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.774845177 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 18882400 ps |
| CPU time | 22.04 seconds |
| Started | Sep 01 07:04:41 PM UTC 24 |
| Finished | Sep 01 07:05:05 PM UTC 24 |
| Peak memory | 261916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=774845177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_shadow_reg_errors_with_csr_rw.774845177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3425157794 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 57012300 ps |
| CPU time | 27.88 seconds |
| Started | Sep 01 07:04:40 PM UTC 24 |
| Finished | Sep 01 07:05:09 PM UTC 24 |
| Peak memory | 274292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425157794 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3425157794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2943076445 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 672155400 ps |
| CPU time | 24.77 seconds |
| Started | Sep 01 07:04:53 PM UTC 24 |
| Finished | Sep 01 07:05:19 PM UTC 24 |
| Peak memory | 284632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2943076445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2943076445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1825947468 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 72700800 ps |
| CPU time | 28.16 seconds |
| Started | Sep 01 07:04:51 PM UTC 24 |
| Finished | Sep 01 07:05:20 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825947468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.1825947468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1962063324 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 116623400 ps |
| CPU time | 23.57 seconds |
| Started | Sep 01 07:04:50 PM UTC 24 |
| Finished | Sep 01 07:05:14 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962063324 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1962063324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2129735427 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 242095700 ps |
| CPU time | 40.63 seconds |
| Started | Sep 01 07:04:51 PM UTC 24 |
| Finished | Sep 01 07:05:33 PM UTC 24 |
| Peak memory | 272232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2129735427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ same_csr_outstanding.2129735427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2249327342 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 31331500 ps |
| CPU time | 22.24 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:05:12 PM UTC 24 |
| Peak memory | 261932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224 9327342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.2249327342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1081758796 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 11586700 ps |
| CPU time | 20.94 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:05:11 PM UTC 24 |
| Peak memory | 261984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1081758796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1081758796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3251766600 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 213248100 ps |
| CPU time | 23.26 seconds |
| Started | Sep 01 07:04:48 PM UTC 24 |
| Finished | Sep 01 07:05:13 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251766600 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3251766600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2267030587 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 16279400 ps |
| CPU time | 30.39 seconds |
| Started | Sep 01 07:06:58 PM UTC 24 |
| Finished | Sep 01 07:07:29 PM UTC 24 |
| Peak memory | 295244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267030587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2267030587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3953739029 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1407856200 ps |
| CPU time | 247.91 seconds |
| Started | Sep 01 07:06:16 PM UTC 24 |
| Finished | Sep 01 07:10:27 PM UTC 24 |
| Peak memory | 289760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3953739029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3953739029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2785459664 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1183466600 ps |
| CPU time | 53.98 seconds |
| Started | Sep 01 07:07:23 PM UTC 24 |
| Finished | Sep 01 07:08:19 PM UTC 24 |
| Peak memory | 273496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785459 664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f s_sup.2785459664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1636767405 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 26711800 ps |
| CPU time | 49.54 seconds |
| Started | Sep 01 07:07:50 PM UTC 24 |
| Finished | Sep 01 07:08:41 PM UTC 24 |
| Peak memory | 285812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163676740 5 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.1636767405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1735279583 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 460525249700 ps |
| CPU time | 2652 seconds |
| Started | Sep 01 07:06:06 PM UTC 24 |
| Finished | Sep 01 07:50:47 PM UTC 24 |
| Peak memory | 278232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735279583 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.1735279583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3456595561 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 28361600 ps |
| CPU time | 66.35 seconds |
| Started | Sep 01 07:06:02 PM UTC 24 |
| Finished | Sep 01 07:07:10 PM UTC 24 |
| Peak memory | 273264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456595561 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3456595561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.4061981071 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 15531300 ps |
| CPU time | 28.3 seconds |
| Started | Sep 01 07:07:45 PM UTC 24 |
| Finished | Sep 01 07:08:14 PM UTC 24 |
| Peak memory | 269240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4061981071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.4061981071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1089134212 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 167369325200 ps |
| CPU time | 2318.18 seconds |
| Started | Sep 01 07:06:05 PM UTC 24 |
| Finished | Sep 01 07:45:12 PM UTC 24 |
| Peak memory | 277956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089134212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.1089134212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.2851063380 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 70135658300 ps |
| CPU time | 1016.16 seconds |
| Started | Sep 01 07:06:05 PM UTC 24 |
| Finished | Sep 01 07:23:14 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851063380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.2851063380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3532135676 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 18171332400 ps |
| CPU time | 551.21 seconds |
| Started | Sep 01 07:06:17 PM UTC 24 |
| Finished | Sep 01 07:15:35 PM UTC 24 |
| Peak memory | 347304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3532135676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr ity.3532135676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2406231051 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6128969400 ps |
| CPU time | 178.57 seconds |
| Started | Sep 01 07:06:21 PM UTC 24 |
| Finished | Sep 01 07:09:22 PM UTC 24 |
| Peak memory | 304220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2406231051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.2406231051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2290807417 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 33983912500 ps |
| CPU time | 225.04 seconds |
| Started | Sep 01 07:06:24 PM UTC 24 |
| Finished | Sep 01 07:10:13 PM UTC 24 |
| Peak memory | 271444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290807417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2290807417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1521773243 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 15272100 ps |
| CPU time | 28.15 seconds |
| Started | Sep 01 07:07:45 PM UTC 24 |
| Finished | Sep 01 07:08:14 PM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1521773243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.1521773243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.942158530 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 69577900 ps |
| CPU time | 260.05 seconds |
| Started | Sep 01 07:06:05 PM UTC 24 |
| Finished | Sep 01 07:10:29 PM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942158530 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.942158530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.546129083 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 96557600 ps |
| CPU time | 466.4 seconds |
| Started | Sep 01 07:06:04 PM UTC 24 |
| Finished | Sep 01 07:13:56 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546129083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.546129083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2068816240 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 63792000 ps |
| CPU time | 28.43 seconds |
| Started | Sep 01 07:06:27 PM UTC 24 |
| Finished | Sep 01 07:06:57 PM UTC 24 |
| Peak memory | 275540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068816240 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.2068816240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2023007982 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 395263700 ps |
| CPU time | 491.13 seconds |
| Started | Sep 01 07:06:01 PM UTC 24 |
| Finished | Sep 01 07:14:17 PM UTC 24 |
| Peak memory | 291704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023007982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2023007982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3879897807 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 268888900 ps |
| CPU time | 149.29 seconds |
| Started | Sep 01 07:06:04 PM UTC 24 |
| Finished | Sep 01 07:08:36 PM UTC 24 |
| Peak memory | 273528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879897807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3879897807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.37886208 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 156643200 ps |
| CPU time | 68.24 seconds |
| Started | Sep 01 07:07:49 PM UTC 24 |
| Finished | Sep 01 07:08:59 PM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37886208 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.37886208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1980133755 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 24843800 ps |
| CPU time | 17.47 seconds |
| Started | Sep 01 07:06:10 PM UTC 24 |
| Finished | Sep 01 07:06:29 PM UTC 24 |
| Peak memory | 269520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980133755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1980133755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2762499555 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 58174800 ps |
| CPU time | 35.28 seconds |
| Started | Sep 01 07:06:14 PM UTC 24 |
| Finished | Sep 01 07:06:51 PM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2762499555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_read_word_sweep_derr.2762499555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2014761342 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 76285800 ps |
| CPU time | 44.32 seconds |
| Started | Sep 01 07:06:11 PM UTC 24 |
| Finished | Sep 01 07:06:57 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014761342 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.2014761342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2016294393 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3543622400 ps |
| CPU time | 103.71 seconds |
| Started | Sep 01 07:06:10 PM UTC 24 |
| Finished | Sep 01 07:07:56 PM UTC 24 |
| Peak memory | 291912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2016294393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.2016294393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3984560594 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 706187800 ps |
| CPU time | 179.19 seconds |
| Started | Sep 01 07:06:14 PM UTC 24 |
| Finished | Sep 01 07:09:17 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984560594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3984560594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.2973270819 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5573983200 ps |
| CPU time | 165.18 seconds |
| Started | Sep 01 07:06:16 PM UTC 24 |
| Finished | Sep 01 07:09:04 PM UTC 24 |
| Peak memory | 298168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2973270819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rw_derr.2973270819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.3924526223 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 27115600 ps |
| CPU time | 57.61 seconds |
| Started | Sep 01 07:06:29 PM UTC 24 |
| Finished | Sep 01 07:07:28 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924526223 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.3924526223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2899778561 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 701923700 ps |
| CPU time | 91.93 seconds |
| Started | Sep 01 07:06:13 PM UTC 24 |
| Finished | Sep 01 07:07:48 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289 9778561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.2899778561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3084276353 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4752099300 ps |
| CPU time | 93.08 seconds |
| Started | Sep 01 07:06:13 PM UTC 24 |
| Finished | Sep 01 07:07:49 PM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 84276353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se rr_counter.3084276353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2938213175 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 168372900 ps |
| CPU time | 342.63 seconds |
| Started | Sep 01 07:05:59 PM UTC 24 |
| Finished | Sep 01 07:11:46 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938213175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2938213175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.1115754573 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 16536500 ps |
| CPU time | 34.24 seconds |
| Started | Sep 01 07:05:59 PM UTC 24 |
| Finished | Sep 01 07:06:35 PM UTC 24 |
| Peak memory | 271152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115754573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1115754573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1876007336 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2391268100 ps |
| CPU time | 1371.01 seconds |
| Started | Sep 01 07:06:58 PM UTC 24 |
| Finished | Sep 01 07:30:04 PM UTC 24 |
| Peak memory | 295752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876007336 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.1876007336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.569740575 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 54609300 ps |
| CPU time | 33.66 seconds |
| Started | Sep 01 07:06:01 PM UTC 24 |
| Finished | Sep 01 07:06:36 PM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569740575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.569740575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2685804694 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1995191000 ps |
| CPU time | 212.43 seconds |
| Started | Sep 01 07:06:09 PM UTC 24 |
| Finished | Sep 01 07:09:45 PM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2685804694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.2685804694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.615821292 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 278789200 ps |
| CPU time | 26.57 seconds |
| Started | Sep 01 07:06:10 PM UTC 24 |
| Finished | Sep 01 07:06:38 PM UTC 24 |
| Peak memory | 268948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615821292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.615821292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1740600244 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 23437200 ps |
| CPU time | 28.64 seconds |
| Started | Sep 01 07:12:12 PM UTC 24 |
| Finished | Sep 01 07:12:42 PM UTC 24 |
| Peak memory | 273492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1740600244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1740600244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.3971678115 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 31187700 ps |
| CPU time | 19.58 seconds |
| Started | Sep 01 07:13:04 PM UTC 24 |
| Finished | Sep 01 07:13:25 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971678115 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3971678115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.1846562162 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 40752200 ps |
| CPU time | 29 seconds |
| Started | Sep 01 07:12:37 PM UTC 24 |
| Finished | Sep 01 07:13:08 PM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846562162 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.1846562162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.3942943527 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 25024900 ps |
| CPU time | 21.92 seconds |
| Started | Sep 01 07:12:00 PM UTC 24 |
| Finished | Sep 01 07:12:23 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942943527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3942943527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3550123684 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 772652100 ps |
| CPU time | 305.65 seconds |
| Started | Sep 01 07:10:11 PM UTC 24 |
| Finished | Sep 01 07:15:22 PM UTC 24 |
| Peak memory | 292068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3550123684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_derr_detect.3550123684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.862610532 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6423073600 ps |
| CPU time | 752.26 seconds |
| Started | Sep 01 07:08:18 PM UTC 24 |
| Finished | Sep 01 07:21:00 PM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862610532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.862610532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.4105422041 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15688782600 ps |
| CPU time | 3277.77 seconds |
| Started | Sep 01 07:09:00 PM UTC 24 |
| Finished | Sep 01 08:04:14 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105422041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.4105422041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2119052010 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1640092000 ps |
| CPU time | 3124.6 seconds |
| Started | Sep 01 07:08:54 PM UTC 24 |
| Finished | Sep 01 08:01:32 PM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 19052010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _error_prog_type.2119052010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.4143899973 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 621609600 ps |
| CPU time | 1243.15 seconds |
| Started | Sep 01 07:08:54 PM UTC 24 |
| Finished | Sep 01 07:29:51 PM UTC 24 |
| Peak memory | 283480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143899973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.4143899973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.360173277 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 159754802100 ps |
| CPU time | 2777.96 seconds |
| Started | Sep 01 07:08:53 PM UTC 24 |
| Finished | Sep 01 07:55:43 PM UTC 24 |
| Peak memory | 285404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360173277 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.360173277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1299315417 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 27403800 ps |
| CPU time | 46.03 seconds |
| Started | Sep 01 07:12:58 PM UTC 24 |
| Finished | Sep 01 07:13:45 PM UTC 24 |
| Peak memory | 281524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129931541 7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho st_addr_infection.1299315417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2965179583 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 239376370500 ps |
| CPU time | 3402.62 seconds |
| Started | Sep 01 07:08:36 PM UTC 24 |
| Finished | Sep 01 08:05:59 PM UTC 24 |
| Peak memory | 275704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965179583 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.2965179583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4268025580 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 21238600 ps |
| CPU time | 47.3 seconds |
| Started | Sep 01 07:08:03 PM UTC 24 |
| Finished | Sep 01 07:08:51 PM UTC 24 |
| Peak memory | 273260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268025580 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4268025580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2612688733 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 10048945500 ps |
| CPU time | 86.31 seconds |
| Started | Sep 01 07:12:58 PM UTC 24 |
| Finished | Sep 01 07:14:26 PM UTC 24 |
| Peak memory | 287944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2612688733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2612688733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.837773640 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 80133591000 ps |
| CPU time | 1151.06 seconds |
| Started | Sep 01 07:08:22 PM UTC 24 |
| Finished | Sep 01 07:27:47 PM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837773640 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.837773640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2340635089 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3133630600 ps |
| CPU time | 81.77 seconds |
| Started | Sep 01 07:08:15 PM UTC 24 |
| Finished | Sep 01 07:09:38 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340635089 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.2340635089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.3608419100 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 772177400 ps |
| CPU time | 187.01 seconds |
| Started | Sep 01 07:10:30 PM UTC 24 |
| Finished | Sep 01 07:13:40 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608419100 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.3608419100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.265039820 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1983392200 ps |
| CPU time | 98.92 seconds |
| Started | Sep 01 07:10:43 PM UTC 24 |
| Finished | Sep 01 07:12:24 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265039820 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.265039820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2932621744 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 155533680600 ps |
| CPU time | 397 seconds |
| Started | Sep 01 07:10:47 PM UTC 24 |
| Finished | Sep 01 07:17:29 PM UTC 24 |
| Peak memory | 271524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932621744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2932621744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2878449410 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3351916000 ps |
| CPU time | 63.94 seconds |
| Started | Sep 01 07:09:00 PM UTC 24 |
| Finished | Sep 01 07:10:05 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878449410 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2878449410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3480575997 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 16088800 ps |
| CPU time | 26.45 seconds |
| Started | Sep 01 07:12:52 PM UTC 24 |
| Finished | Sep 01 07:13:19 PM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3480575997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_lcmgr_intg.3480575997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2842915854 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 308815800 ps |
| CPU time | 421.34 seconds |
| Started | Sep 01 07:08:15 PM UTC 24 |
| Finished | Sep 01 07:15:21 PM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842915854 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2842915854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2839691246 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 45125600 ps |
| CPU time | 28.43 seconds |
| Started | Sep 01 07:12:25 PM UTC 24 |
| Finished | Sep 01 07:12:55 PM UTC 24 |
| Peak memory | 275604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2839691246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2839691246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1457395017 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 58241900 ps |
| CPU time | 19.89 seconds |
| Started | Sep 01 07:11:02 PM UTC 24 |
| Finished | Sep 01 07:11:23 PM UTC 24 |
| Peak memory | 269196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457395017 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.1457395017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2755052961 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 185686800 ps |
| CPU time | 1436.83 seconds |
| Started | Sep 01 07:07:57 PM UTC 24 |
| Finished | Sep 01 07:32:10 PM UTC 24 |
| Peak memory | 298056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755052961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2755052961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3964112490 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3685139900 ps |
| CPU time | 171.03 seconds |
| Started | Sep 01 07:08:08 PM UTC 24 |
| Finished | Sep 01 07:11:02 PM UTC 24 |
| Peak memory | 273276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964112490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3964112490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1450015012 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 63788700 ps |
| CPU time | 61.48 seconds |
| Started | Sep 01 07:12:05 PM UTC 24 |
| Finished | Sep 01 07:13:08 PM UTC 24 |
| Peak memory | 287752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145001501 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.1450015012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3297602196 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 31427000 ps |
| CPU time | 45.94 seconds |
| Started | Sep 01 07:09:53 PM UTC 24 |
| Finished | Sep 01 07:10:40 PM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3297602196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_read_word_sweep_derr.3297602196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2489468393 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 44028200 ps |
| CPU time | 36.41 seconds |
| Started | Sep 01 07:09:22 PM UTC 24 |
| Finished | Sep 01 07:10:00 PM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489468393 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.2489468393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1662847066 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 82225816200 ps |
| CPU time | 1127.48 seconds |
| Started | Sep 01 07:12:43 PM UTC 24 |
| Finished | Sep 01 07:31:44 PM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1662847066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.1662847066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2347954281 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 664223100 ps |
| CPU time | 141.28 seconds |
| Started | Sep 01 07:09:21 PM UTC 24 |
| Finished | Sep 01 07:11:45 PM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2347954281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.2347954281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1727885629 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 507818100 ps |
| CPU time | 173.56 seconds |
| Started | Sep 01 07:10:00 PM UTC 24 |
| Finished | Sep 01 07:12:57 PM UTC 24 |
| Peak memory | 291804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727885629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1727885629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.2321583850 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 615477100 ps |
| CPU time | 164.98 seconds |
| Started | Sep 01 07:09:23 PM UTC 24 |
| Finished | Sep 01 07:12:11 PM UTC 24 |
| Peak memory | 302248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2321583850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_ro_serr.2321583850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.1789117581 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 29288600 ps |
| CPU time | 56.77 seconds |
| Started | Sep 01 07:11:14 PM UTC 24 |
| Finished | Sep 01 07:12:12 PM UTC 24 |
| Peak memory | 288016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789117581 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.1789117581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1828615734 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 28530700 ps |
| CPU time | 35.66 seconds |
| Started | Sep 01 07:11:18 PM UTC 24 |
| Finished | Sep 01 07:11:55 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1828615734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.1828615734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1570661117 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2809961200 ps |
| CPU time | 256.04 seconds |
| Started | Sep 01 07:09:39 PM UTC 24 |
| Finished | Sep 01 07:13:59 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1570661117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.1570661117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1813591589 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1548086400 ps |
| CPU time | 104.34 seconds |
| Started | Sep 01 07:11:48 PM UTC 24 |
| Finished | Sep 01 07:13:35 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813591589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1813591589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.287745952 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2480486600 ps |
| CPU time | 129.46 seconds |
| Started | Sep 01 07:09:47 PM UTC 24 |
| Finished | Sep 01 07:11:59 PM UTC 24 |
| Peak memory | 275644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287 745952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_serr _address.287745952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1194412889 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1438287100 ps |
| CPU time | 59.74 seconds |
| Started | Sep 01 07:09:45 PM UTC 24 |
| Finished | Sep 01 07:10:46 PM UTC 24 |
| Peak memory | 275552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 94412889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.1194412889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.4241156459 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 20795300 ps |
| CPU time | 213.58 seconds |
| Started | Sep 01 07:07:55 PM UTC 24 |
| Finished | Sep 01 07:11:32 PM UTC 24 |
| Peak memory | 289656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241156459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.4241156459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3043935165 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 17456100 ps |
| CPU time | 54.89 seconds |
| Started | Sep 01 07:07:56 PM UTC 24 |
| Finished | Sep 01 07:08:53 PM UTC 24 |
| Peak memory | 271308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043935165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3043935165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.3221382111 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 33074700 ps |
| CPU time | 137.42 seconds |
| Started | Sep 01 07:11:56 PM UTC 24 |
| Finished | Sep 01 07:14:15 PM UTC 24 |
| Peak memory | 289608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221382111 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.3221382111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3338765541 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 33286900 ps |
| CPU time | 45.46 seconds |
| Started | Sep 01 07:08:03 PM UTC 24 |
| Finished | Sep 01 07:08:50 PM UTC 24 |
| Peak memory | 273104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338765541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3338765541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.998354074 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4186409600 ps |
| CPU time | 163.74 seconds |
| Started | Sep 01 07:09:18 PM UTC 24 |
| Finished | Sep 01 07:12:04 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =998354074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.998354074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.1447345664 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 85435400 ps |
| CPU time | 26.34 seconds |
| Started | Sep 01 07:12:09 PM UTC 24 |
| Finished | Sep 01 07:12:37 PM UTC 24 |
| Peak memory | 271572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447345664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.1447345664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.3216062243 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 136576200 ps |
| CPU time | 29.48 seconds |
| Started | Sep 01 07:50:28 PM UTC 24 |
| Finished | Sep 01 07:50:58 PM UTC 24 |
| Peak memory | 275620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216062243 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.3216062243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1609181695 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 15928100 ps |
| CPU time | 19.84 seconds |
| Started | Sep 01 07:50:17 PM UTC 24 |
| Finished | Sep 01 07:50:38 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609181695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1609181695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.4262059378 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 16450800 ps |
| CPU time | 23.15 seconds |
| Started | Sep 01 07:49:52 PM UTC 24 |
| Finished | Sep 01 07:50:16 PM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4262059378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ ctrl_disable.4262059378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2592430416 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 25750000 ps |
| CPU time | 23.31 seconds |
| Started | Sep 01 07:50:26 PM UTC 24 |
| Finished | Sep 01 07:50:51 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2592430416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2592430416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.2401460083 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 80137857900 ps |
| CPU time | 951.38 seconds |
| Started | Sep 01 07:48:23 PM UTC 24 |
| Finished | Sep 01 08:04:26 PM UTC 24 |
| Peak memory | 275356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401460083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res et.2401460083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.29767666 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 14134469000 ps |
| CPU time | 124.28 seconds |
| Started | Sep 01 07:48:19 PM UTC 24 |
| Finished | Sep 01 07:50:26 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29767666 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.29767666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3446241790 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 482945600 ps |
| CPU time | 120.52 seconds |
| Started | Sep 01 07:48:56 PM UTC 24 |
| Finished | Sep 01 07:50:59 PM UTC 24 |
| Peak memory | 306176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446241790 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.3446241790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3674311556 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 5988839700 ps |
| CPU time | 220.67 seconds |
| Started | Sep 01 07:49:11 PM UTC 24 |
| Finished | Sep 01 07:52:55 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3674311556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_intr_rd_slow_flash.3674311556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.999165314 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1011495400 ps |
| CPU time | 114.43 seconds |
| Started | Sep 01 07:48:29 PM UTC 24 |
| Finished | Sep 01 07:50:26 PM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999165314 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.999165314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2518356698 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 16951409500 ps |
| CPU time | 451.51 seconds |
| Started | Sep 01 07:48:24 PM UTC 24 |
| Finished | Sep 01 07:56:02 PM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2518356698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2518356698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2342869536 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 714938900 ps |
| CPU time | 267.34 seconds |
| Started | Sep 01 07:48:24 PM UTC 24 |
| Finished | Sep 01 07:52:56 PM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342869536 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.2342869536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.4041204790 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 154911000 ps |
| CPU time | 235.01 seconds |
| Started | Sep 01 07:48:18 PM UTC 24 |
| Finished | Sep 01 07:52:16 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041204790 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.4041204790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1307203243 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 82543500 ps |
| CPU time | 26.89 seconds |
| Started | Sep 01 07:49:22 PM UTC 24 |
| Finished | Sep 01 07:49:51 PM UTC 24 |
| Peak memory | 269184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307203243 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.1307203243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2549358437 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 217991100 ps |
| CPU time | 1554.72 seconds |
| Started | Sep 01 07:48:16 PM UTC 24 |
| Finished | Sep 01 08:14:31 PM UTC 24 |
| Peak memory | 295800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549358437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2549358437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3599788237 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 238319600 ps |
| CPU time | 65.66 seconds |
| Started | Sep 01 07:49:32 PM UTC 24 |
| Finished | Sep 01 07:50:39 PM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599788237 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.3599788237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2838412929 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 940008100 ps |
| CPU time | 138.12 seconds |
| Started | Sep 01 07:48:34 PM UTC 24 |
| Finished | Sep 01 07:50:55 PM UTC 24 |
| Peak memory | 291760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2838412929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.2838412929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.2302945392 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 7700906400 ps |
| CPU time | 527.95 seconds |
| Started | Sep 01 07:48:50 PM UTC 24 |
| Finished | Sep 01 07:57:45 PM UTC 24 |
| Peak memory | 322672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302945392 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.2302945392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3537728736 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 66919400 ps |
| CPU time | 56.95 seconds |
| Started | Sep 01 07:49:26 PM UTC 24 |
| Finished | Sep 01 07:50:25 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537728736 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.3537728736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3887524145 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 67733400 ps |
| CPU time | 51.36 seconds |
| Started | Sep 01 07:49:27 PM UTC 24 |
| Finished | Sep 01 07:50:20 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3887524145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_rw_evict_all_en.3887524145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2323379759 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 191923500 ps |
| CPU time | 178.6 seconds |
| Started | Sep 01 07:48:05 PM UTC 24 |
| Finished | Sep 01 07:51:06 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323379759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2323379759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.295257597 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2564434300 ps |
| CPU time | 195.7 seconds |
| Started | Sep 01 07:48:31 PM UTC 24 |
| Finished | Sep 01 07:51:50 PM UTC 24 |
| Peak memory | 271244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =295257597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.295257597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3715142384 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 98630700 ps |
| CPU time | 24.94 seconds |
| Started | Sep 01 07:52:57 PM UTC 24 |
| Finished | Sep 01 07:53:23 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715142384 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.3715142384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.131317690 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 19137500 ps |
| CPU time | 28.06 seconds |
| Started | Sep 01 07:52:42 PM UTC 24 |
| Finished | Sep 01 07:53:12 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131317690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.131317690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4022609179 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 25330600 ps |
| CPU time | 27.9 seconds |
| Started | Sep 01 07:52:46 PM UTC 24 |
| Finished | Sep 01 07:53:16 PM UTC 24 |
| Peak memory | 269616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4022609179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.4022609179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1910996112 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 160179163200 ps |
| CPU time | 809.62 seconds |
| Started | Sep 01 07:50:48 PM UTC 24 |
| Finished | Sep 01 08:04:27 PM UTC 24 |
| Peak memory | 273376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910996112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res et.1910996112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1173037021 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 6305100100 ps |
| CPU time | 151.84 seconds |
| Started | Sep 01 07:50:48 PM UTC 24 |
| Finished | Sep 01 07:53:23 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173037021 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.1173037021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3175825090 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3318367800 ps |
| CPU time | 153.11 seconds |
| Started | Sep 01 07:51:15 PM UTC 24 |
| Finished | Sep 01 07:53:51 PM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175825090 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.3175825090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.4013546142 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 51912426000 ps |
| CPU time | 547.39 seconds |
| Started | Sep 01 07:51:20 PM UTC 24 |
| Finished | Sep 01 08:00:35 PM UTC 24 |
| Peak memory | 293780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4013546142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_intr_rd_slow_flash.4013546142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2085736859 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1698589500 ps |
| CPU time | 70.6 seconds |
| Started | Sep 01 07:50:59 PM UTC 24 |
| Finished | Sep 01 07:52:12 PM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085736859 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2085736859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.257488113 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 15254400 ps |
| CPU time | 25.25 seconds |
| Started | Sep 01 07:52:43 PM UTC 24 |
| Finished | Sep 01 07:53:10 PM UTC 24 |
| Peak memory | 271632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=257488113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_lcmgr_intg.257488113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.1872081461 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 19737402400 ps |
| CPU time | 267.45 seconds |
| Started | Sep 01 07:50:55 PM UTC 24 |
| Finished | Sep 01 07:55:27 PM UTC 24 |
| Peak memory | 281452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1872081461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.1872081461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.74072177 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 106967400 ps |
| CPU time | 151.99 seconds |
| Started | Sep 01 07:50:52 PM UTC 24 |
| Finished | Sep 01 07:53:27 PM UTC 24 |
| Peak memory | 271536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74072177 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.74072177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.619979988 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 131441200 ps |
| CPU time | 846 seconds |
| Started | Sep 01 07:50:40 PM UTC 24 |
| Finished | Sep 01 08:04:58 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619979988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.619979988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.2410526644 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2639564000 ps |
| CPU time | 252 seconds |
| Started | Sep 01 07:51:22 PM UTC 24 |
| Finished | Sep 01 07:55:38 PM UTC 24 |
| Peak memory | 271468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410526644 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.2410526644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.2087351536 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 279025800 ps |
| CPU time | 992.24 seconds |
| Started | Sep 01 07:50:39 PM UTC 24 |
| Finished | Sep 01 08:07:24 PM UTC 24 |
| Peak memory | 293708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087351536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2087351536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3977070629 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 74072200 ps |
| CPU time | 41.37 seconds |
| Started | Sep 01 07:52:13 PM UTC 24 |
| Finished | Sep 01 07:52:56 PM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977070629 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.3977070629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2989485379 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2132880800 ps |
| CPU time | 123.29 seconds |
| Started | Sep 01 07:51:05 PM UTC 24 |
| Finished | Sep 01 07:53:10 PM UTC 24 |
| Peak memory | 308168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2989485379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.2989485379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3459393338 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3775205500 ps |
| CPU time | 517.67 seconds |
| Started | Sep 01 07:51:08 PM UTC 24 |
| Finished | Sep 01 07:59:52 PM UTC 24 |
| Peak memory | 320672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459393338 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.3459393338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.531386104 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 34058200 ps |
| CPU time | 37.32 seconds |
| Started | Sep 01 07:51:47 PM UTC 24 |
| Finished | Sep 01 07:52:25 PM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531386104 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.531386104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.586509834 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 91730800 ps |
| CPU time | 51.98 seconds |
| Started | Sep 01 07:51:52 PM UTC 24 |
| Finished | Sep 01 07:52:46 PM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=586509834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ct rl_rw_evict_all_en.586509834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.4220356322 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1179921800 ps |
| CPU time | 80.69 seconds |
| Started | Sep 01 07:52:26 PM UTC 24 |
| Finished | Sep 01 07:53:49 PM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220356322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.4220356322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.3908235767 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 93440200 ps |
| CPU time | 288.92 seconds |
| Started | Sep 01 07:50:37 PM UTC 24 |
| Finished | Sep 01 07:55:30 PM UTC 24 |
| Peak memory | 291696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908235767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3908235767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.4288949977 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 5176079200 ps |
| CPU time | 261.42 seconds |
| Started | Sep 01 07:50:59 PM UTC 24 |
| Finished | Sep 01 07:55:25 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4288949977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.4288949977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.363728391 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 33074400 ps |
| CPU time | 23.85 seconds |
| Started | Sep 01 07:55:35 PM UTC 24 |
| Finished | Sep 01 07:56:00 PM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363728391 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.363728391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.199546865 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 152323700 ps |
| CPU time | 25.65 seconds |
| Started | Sep 01 07:55:21 PM UTC 24 |
| Finished | Sep 01 07:55:48 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199546865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.199546865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.4289495398 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 10414100 ps |
| CPU time | 43.34 seconds |
| Started | Sep 01 07:54:50 PM UTC 24 |
| Finished | Sep 01 07:55:34 PM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4289495398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.4289495398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3433743769 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 10033761800 ps |
| CPU time | 103.21 seconds |
| Started | Sep 01 07:55:31 PM UTC 24 |
| Finished | Sep 01 07:57:16 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3433743769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3433743769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1638118893 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 20311700 ps |
| CPU time | 24.41 seconds |
| Started | Sep 01 07:55:28 PM UTC 24 |
| Finished | Sep 01 07:55:54 PM UTC 24 |
| Peak memory | 275420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1638118893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1638118893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.315871885 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 160178534400 ps |
| CPU time | 977.07 seconds |
| Started | Sep 01 07:53:11 PM UTC 24 |
| Finished | Sep 01 08:09:42 PM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315871885 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_reset.315871885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3126879638 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1907455700 ps |
| CPU time | 155.87 seconds |
| Started | Sep 01 07:53:11 PM UTC 24 |
| Finished | Sep 01 07:55:50 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126879638 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.3126879638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3433916823 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1647879000 ps |
| CPU time | 198.71 seconds |
| Started | Sep 01 07:53:44 PM UTC 24 |
| Finished | Sep 01 07:57:06 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433916823 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.3433916823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2042283894 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 24466456400 ps |
| CPU time | 252.78 seconds |
| Started | Sep 01 07:53:49 PM UTC 24 |
| Finished | Sep 01 07:58:05 PM UTC 24 |
| Peak memory | 302192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2042283894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_intr_rd_slow_flash.2042283894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.87537400 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 992197600 ps |
| CPU time | 112.67 seconds |
| Started | Sep 01 07:53:23 PM UTC 24 |
| Finished | Sep 01 07:55:18 PM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87537400 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.87537400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.914766554 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 17759600 ps |
| CPU time | 26.92 seconds |
| Started | Sep 01 07:55:26 PM UTC 24 |
| Finished | Sep 01 07:55:55 PM UTC 24 |
| Peak memory | 275436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=914766554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas h_ctrl_lcmgr_intg.914766554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.3807645685 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 11310557100 ps |
| CPU time | 283.19 seconds |
| Started | Sep 01 07:53:16 PM UTC 24 |
| Finished | Sep 01 07:58:04 PM UTC 24 |
| Peak memory | 283500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3807645685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3807645685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.743812061 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 802567400 ps |
| CPU time | 241.52 seconds |
| Started | Sep 01 07:53:02 PM UTC 24 |
| Finished | Sep 01 07:57:07 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743812061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.743812061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2942026470 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 34591400 ps |
| CPU time | 27.84 seconds |
| Started | Sep 01 07:53:50 PM UTC 24 |
| Finished | Sep 01 07:54:19 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942026470 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.2942026470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3042374092 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 128324100 ps |
| CPU time | 735.89 seconds |
| Started | Sep 01 07:52:57 PM UTC 24 |
| Finished | Sep 01 08:05:23 PM UTC 24 |
| Peak memory | 291708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042374092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3042374092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2366833897 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 408818000 ps |
| CPU time | 65.56 seconds |
| Started | Sep 01 07:54:35 PM UTC 24 |
| Finished | Sep 01 07:55:42 PM UTC 24 |
| Peak memory | 289772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366833897 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2366833897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4189941998 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 918452800 ps |
| CPU time | 153.19 seconds |
| Started | Sep 01 07:53:27 PM UTC 24 |
| Finished | Sep 01 07:56:04 PM UTC 24 |
| Peak memory | 304056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4189941998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.4189941998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.735052218 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3622710100 ps |
| CPU time | 653.88 seconds |
| Started | Sep 01 07:53:30 PM UTC 24 |
| Finished | Sep 01 08:04:32 PM UTC 24 |
| Peak memory | 330708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735052218 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.735052218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1120388803 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 84567800 ps |
| CPU time | 54.66 seconds |
| Started | Sep 01 07:53:52 PM UTC 24 |
| Finished | Sep 01 07:54:48 PM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120388803 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.1120388803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.4149027337 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 65174100 ps |
| CPU time | 58.12 seconds |
| Started | Sep 01 07:54:20 PM UTC 24 |
| Finished | Sep 01 07:55:20 PM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4149027337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c trl_rw_evict_all_en.4149027337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.188296837 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1642936100 ps |
| CPU time | 90.38 seconds |
| Started | Sep 01 07:55:19 PM UTC 24 |
| Finished | Sep 01 07:56:51 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188296837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.188296837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.3606496029 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 23985200 ps |
| CPU time | 172.72 seconds |
| Started | Sep 01 07:52:57 PM UTC 24 |
| Finished | Sep 01 07:55:52 PM UTC 24 |
| Peak memory | 289656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606496029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.3606496029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.407184131 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3767253400 ps |
| CPU time | 215.96 seconds |
| Started | Sep 01 07:53:23 PM UTC 24 |
| Finished | Sep 01 07:57:03 PM UTC 24 |
| Peak memory | 275508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =407184131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.407184131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2268420833 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 157603500 ps |
| CPU time | 16.21 seconds |
| Started | Sep 01 07:57:49 PM UTC 24 |
| Finished | Sep 01 07:58:07 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268420833 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.2268420833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.908340300 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 27139600 ps |
| CPU time | 20.86 seconds |
| Started | Sep 01 07:57:33 PM UTC 24 |
| Finished | Sep 01 07:57:57 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908340300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.908340300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1984724211 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 16285100 ps |
| CPU time | 26.08 seconds |
| Started | Sep 01 07:57:14 PM UTC 24 |
| Finished | Sep 01 07:57:42 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1984724211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ ctrl_disable.1984724211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1186839970 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10036265200 ps |
| CPU time | 94.76 seconds |
| Started | Sep 01 07:57:46 PM UTC 24 |
| Finished | Sep 01 07:59:23 PM UTC 24 |
| Peak memory | 293920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1186839970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1186839970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3987865026 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 26351200 ps |
| CPU time | 19.67 seconds |
| Started | Sep 01 07:57:43 PM UTC 24 |
| Finished | Sep 01 07:58:04 PM UTC 24 |
| Peak memory | 269616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3987865026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3987865026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.371414894 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 240192705200 ps |
| CPU time | 990.53 seconds |
| Started | Sep 01 07:55:54 PM UTC 24 |
| Finished | Sep 01 08:12:39 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371414894 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_reset.371414894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.904200306 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 4101213700 ps |
| CPU time | 208.24 seconds |
| Started | Sep 01 07:55:53 PM UTC 24 |
| Finished | Sep 01 07:59:25 PM UTC 24 |
| Peak memory | 273352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904200306 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.904200306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.4199754112 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4003586300 ps |
| CPU time | 265.84 seconds |
| Started | Sep 01 07:56:12 PM UTC 24 |
| Finished | Sep 01 08:00:43 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199754112 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.4199754112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.553335090 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 14584154100 ps |
| CPU time | 396.83 seconds |
| Started | Sep 01 07:56:31 PM UTC 24 |
| Finished | Sep 01 08:03:13 PM UTC 24 |
| Peak memory | 301980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=553335090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 13.flash_ctrl_intr_rd_slow_flash.553335090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3771666203 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3277113800 ps |
| CPU time | 99.25 seconds |
| Started | Sep 01 07:55:56 PM UTC 24 |
| Finished | Sep 01 07:57:37 PM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771666203 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3771666203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2157514047 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 94760200 ps |
| CPU time | 22.09 seconds |
| Started | Sep 01 07:57:39 PM UTC 24 |
| Finished | Sep 01 07:58:02 PM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2157514047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.2157514047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.2644756870 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9290149600 ps |
| CPU time | 540.22 seconds |
| Started | Sep 01 07:55:55 PM UTC 24 |
| Finished | Sep 01 08:05:03 PM UTC 24 |
| Peak memory | 283696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2644756870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.2644756870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.3951079994 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 35315600 ps |
| CPU time | 200.79 seconds |
| Started | Sep 01 07:55:54 PM UTC 24 |
| Finished | Sep 01 07:59:18 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951079994 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.3951079994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3356224889 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 210765100 ps |
| CPU time | 468.25 seconds |
| Started | Sep 01 07:55:52 PM UTC 24 |
| Finished | Sep 01 08:03:46 PM UTC 24 |
| Peak memory | 273220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356224889 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3356224889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2516165337 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 9675693500 ps |
| CPU time | 228.49 seconds |
| Started | Sep 01 07:56:52 PM UTC 24 |
| Finished | Sep 01 08:00:44 PM UTC 24 |
| Peak memory | 271236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516165337 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.2516165337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.189592478 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3096753000 ps |
| CPU time | 1563.86 seconds |
| Started | Sep 01 07:55:43 PM UTC 24 |
| Finished | Sep 01 08:22:07 PM UTC 24 |
| Peak memory | 293756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189592478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.189592478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.4282482095 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 123634900 ps |
| CPU time | 61.25 seconds |
| Started | Sep 01 07:57:08 PM UTC 24 |
| Finished | Sep 01 07:58:11 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282482095 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.4282482095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1264749211 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2152785500 ps |
| CPU time | 144.61 seconds |
| Started | Sep 01 07:56:11 PM UTC 24 |
| Finished | Sep 01 07:58:39 PM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1264749211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1264749211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.1574666152 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 9938557700 ps |
| CPU time | 623.06 seconds |
| Started | Sep 01 07:56:11 PM UTC 24 |
| Finished | Sep 01 08:06:45 PM UTC 24 |
| Peak memory | 332852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574666152 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.1574666152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2467354221 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 28852700 ps |
| CPU time | 59.35 seconds |
| Started | Sep 01 07:57:04 PM UTC 24 |
| Finished | Sep 01 07:58:05 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467354221 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.2467354221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.219502842 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 30437300 ps |
| CPU time | 46.17 seconds |
| Started | Sep 01 07:57:07 PM UTC 24 |
| Finished | Sep 01 07:57:55 PM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=219502842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ct rl_rw_evict_all_en.219502842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2868481856 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 39491127500 ps |
| CPU time | 92.16 seconds |
| Started | Sep 01 07:57:17 PM UTC 24 |
| Finished | Sep 01 07:58:51 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868481856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2868481856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3846645303 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 27071800 ps |
| CPU time | 187.39 seconds |
| Started | Sep 01 07:55:39 PM UTC 24 |
| Finished | Sep 01 07:58:50 PM UTC 24 |
| Peak memory | 287564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846645303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3846645303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.3569647359 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 67941700 ps |
| CPU time | 28.16 seconds |
| Started | Sep 01 08:00:12 PM UTC 24 |
| Finished | Sep 01 08:00:41 PM UTC 24 |
| Peak memory | 275420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569647359 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.3569647359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.3933422311 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 87979800 ps |
| CPU time | 33.66 seconds |
| Started | Sep 01 08:00:00 PM UTC 24 |
| Finished | Sep 01 08:00:35 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933422311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3933422311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.3747064966 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 10656100 ps |
| CPU time | 44.56 seconds |
| Started | Sep 01 07:59:26 PM UTC 24 |
| Finished | Sep 01 08:00:12 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3747064966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.3747064966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.609979673 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10012782400 ps |
| CPU time | 193.99 seconds |
| Started | Sep 01 08:00:08 PM UTC 24 |
| Finished | Sep 01 08:03:26 PM UTC 24 |
| Peak memory | 381956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=609979673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.609979673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.99335683 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 25478700 ps |
| CPU time | 28.98 seconds |
| Started | Sep 01 08:00:08 PM UTC 24 |
| Finished | Sep 01 08:00:39 PM UTC 24 |
| Peak memory | 269424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=99335683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .flash_ctrl_hw_read_seed_err.99335683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.2116590442 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 160179583700 ps |
| CPU time | 960.84 seconds |
| Started | Sep 01 07:58:05 PM UTC 24 |
| Finished | Sep 01 08:14:19 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116590442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res et.2116590442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.916757937 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2436671300 ps |
| CPU time | 111.45 seconds |
| Started | Sep 01 07:58:05 PM UTC 24 |
| Finished | Sep 01 07:59:59 PM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916757937 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.916757937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1964640295 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1831235900 ps |
| CPU time | 275.15 seconds |
| Started | Sep 01 07:58:40 PM UTC 24 |
| Finished | Sep 01 08:03:19 PM UTC 24 |
| Peak memory | 302240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964640295 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.1964640295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1149842358 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 35132045200 ps |
| CPU time | 295.4 seconds |
| Started | Sep 01 07:58:51 PM UTC 24 |
| Finished | Sep 01 08:03:51 PM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1149842358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.1149842358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.2728043309 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1928219700 ps |
| CPU time | 120.15 seconds |
| Started | Sep 01 07:58:07 PM UTC 24 |
| Finished | Sep 01 08:00:10 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728043309 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2728043309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.540583893 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 92754900 ps |
| CPU time | 24.73 seconds |
| Started | Sep 01 08:00:01 PM UTC 24 |
| Finished | Sep 01 08:00:31 PM UTC 24 |
| Peak memory | 271568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=540583893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_lcmgr_intg.540583893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.2752709463 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 32573565100 ps |
| CPU time | 322.38 seconds |
| Started | Sep 01 07:58:06 PM UTC 24 |
| Finished | Sep 01 08:03:34 PM UTC 24 |
| Peak memory | 283500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2752709463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2752709463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1097025124 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 323302600 ps |
| CPU time | 206.48 seconds |
| Started | Sep 01 07:58:06 PM UTC 24 |
| Finished | Sep 01 08:01:36 PM UTC 24 |
| Peak memory | 271064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097025124 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.1097025124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.4045228543 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 55364600 ps |
| CPU time | 269.83 seconds |
| Started | Sep 01 07:58:03 PM UTC 24 |
| Finished | Sep 01 08:02:38 PM UTC 24 |
| Peak memory | 275508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045228543 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.4045228543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3339772584 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 99811600 ps |
| CPU time | 15.59 seconds |
| Started | Sep 01 07:58:52 PM UTC 24 |
| Finished | Sep 01 07:59:09 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339772584 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.3339772584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.1862353564 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 825597000 ps |
| CPU time | 1382.91 seconds |
| Started | Sep 01 07:57:57 PM UTC 24 |
| Finished | Sep 01 08:21:20 PM UTC 24 |
| Peak memory | 293756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862353564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1862353564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3161189888 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 79696400 ps |
| CPU time | 65.02 seconds |
| Started | Sep 01 07:59:24 PM UTC 24 |
| Finished | Sep 01 08:00:30 PM UTC 24 |
| Peak memory | 283632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161189888 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.3161189888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.2431172469 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 9735928600 ps |
| CPU time | 163.95 seconds |
| Started | Sep 01 07:58:16 PM UTC 24 |
| Finished | Sep 01 08:01:03 PM UTC 24 |
| Peak memory | 304116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2431172469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.2431172469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2160103644 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 19105723800 ps |
| CPU time | 683.79 seconds |
| Started | Sep 01 07:58:39 PM UTC 24 |
| Finished | Sep 01 08:10:14 PM UTC 24 |
| Peak memory | 320464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160103644 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.2160103644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.1969461420 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 29914200 ps |
| CPU time | 48.85 seconds |
| Started | Sep 01 07:59:09 PM UTC 24 |
| Finished | Sep 01 08:00:00 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969461420 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.1969461420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.2936371970 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 28893600 ps |
| CPU time | 47.72 seconds |
| Started | Sep 01 07:59:18 PM UTC 24 |
| Finished | Sep 01 08:00:08 PM UTC 24 |
| Peak memory | 281576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2936371970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.2936371970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.2291047215 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 23841100 ps |
| CPU time | 184.91 seconds |
| Started | Sep 01 07:57:55 PM UTC 24 |
| Finished | Sep 01 08:01:03 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291047215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2291047215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3470921477 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2780935400 ps |
| CPU time | 288.09 seconds |
| Started | Sep 01 07:58:12 PM UTC 24 |
| Finished | Sep 01 08:03:04 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3470921477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.3470921477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.1014600651 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 52636400 ps |
| CPU time | 28.69 seconds |
| Started | Sep 01 08:03:14 PM UTC 24 |
| Finished | Sep 01 08:03:44 PM UTC 24 |
| Peak memory | 271332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014600651 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.1014600651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.665982693 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 16015500 ps |
| CPU time | 29 seconds |
| Started | Sep 01 08:02:47 PM UTC 24 |
| Finished | Sep 01 08:03:18 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665982693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.665982693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.3478690891 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 34809200 ps |
| CPU time | 41.04 seconds |
| Started | Sep 01 08:02:22 PM UTC 24 |
| Finished | Sep 01 08:03:05 PM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3478690891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ ctrl_disable.3478690891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3843601326 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 10036597500 ps |
| CPU time | 61.69 seconds |
| Started | Sep 01 08:03:06 PM UTC 24 |
| Finished | Sep 01 08:04:09 PM UTC 24 |
| Peak memory | 298016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3843601326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3843601326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.766666062 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 19484900 ps |
| CPU time | 27.51 seconds |
| Started | Sep 01 08:03:05 PM UTC 24 |
| Finished | Sep 01 08:03:34 PM UTC 24 |
| Peak memory | 269144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=766666062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.flash_ctrl_hw_read_seed_err.766666062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.2608540046 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1467603700 ps |
| CPU time | 97.23 seconds |
| Started | Sep 01 08:00:36 PM UTC 24 |
| Finished | Sep 01 08:02:16 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608540046 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.2608540046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3884014357 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 26502524800 ps |
| CPU time | 246.38 seconds |
| Started | Sep 01 08:01:35 PM UTC 24 |
| Finished | Sep 01 08:05:48 PM UTC 24 |
| Peak memory | 304020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3884014357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_intr_rd_slow_flash.3884014357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1694375334 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2106937100 ps |
| CPU time | 95.98 seconds |
| Started | Sep 01 08:00:43 PM UTC 24 |
| Finished | Sep 01 08:02:22 PM UTC 24 |
| Peak memory | 273140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694375334 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1694375334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1916061727 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 26168600 ps |
| CPU time | 17.96 seconds |
| Started | Sep 01 08:02:57 PM UTC 24 |
| Finished | Sep 01 08:03:16 PM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1916061727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_lcmgr_intg.1916061727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1167143985 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 18709352000 ps |
| CPU time | 522 seconds |
| Started | Sep 01 08:00:42 PM UTC 24 |
| Finished | Sep 01 08:09:35 PM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1167143985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1167143985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.1854261641 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 86257000 ps |
| CPU time | 162.25 seconds |
| Started | Sep 01 08:00:39 PM UTC 24 |
| Finished | Sep 01 08:03:24 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854261641 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.1854261641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2061054875 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 507976100 ps |
| CPU time | 607.96 seconds |
| Started | Sep 01 08:00:32 PM UTC 24 |
| Finished | Sep 01 08:10:50 PM UTC 24 |
| Peak memory | 273260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061054875 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2061054875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.670405742 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2215548900 ps |
| CPU time | 203.24 seconds |
| Started | Sep 01 08:01:37 PM UTC 24 |
| Finished | Sep 01 08:05:05 PM UTC 24 |
| Peak memory | 275512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670405742 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.670405742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.112743533 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 54819500 ps |
| CPU time | 697.93 seconds |
| Started | Sep 01 08:00:31 PM UTC 24 |
| Finished | Sep 01 08:12:19 PM UTC 24 |
| Peak memory | 291708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112743533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.112743533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.3126828203 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 80100100 ps |
| CPU time | 57.54 seconds |
| Started | Sep 01 08:02:17 PM UTC 24 |
| Finished | Sep 01 08:03:16 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126828203 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.3126828203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2833470223 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 998184200 ps |
| CPU time | 142.51 seconds |
| Started | Sep 01 08:01:04 PM UTC 24 |
| Finished | Sep 01 08:03:29 PM UTC 24 |
| Peak memory | 291756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2833470223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.2833470223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1196647771 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 6297752000 ps |
| CPU time | 480.03 seconds |
| Started | Sep 01 08:01:05 PM UTC 24 |
| Finished | Sep 01 08:09:13 PM UTC 24 |
| Peak memory | 324688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196647771 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.1196647771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3749810018 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 84560200 ps |
| CPU time | 63.6 seconds |
| Started | Sep 01 08:01:51 PM UTC 24 |
| Finished | Sep 01 08:02:56 PM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749810018 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.3749810018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1196009790 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 44304600 ps |
| CPU time | 54.23 seconds |
| Started | Sep 01 08:01:51 PM UTC 24 |
| Finished | Sep 01 08:02:47 PM UTC 24 |
| Peak memory | 281576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1196009790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_rw_evict_all_en.1196009790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.146179447 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 8798076300 ps |
| CPU time | 98.5 seconds |
| Started | Sep 01 08:02:38 PM UTC 24 |
| Finished | Sep 01 08:04:19 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146179447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.146179447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2028266582 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 79360700 ps |
| CPU time | 230.68 seconds |
| Started | Sep 01 08:00:13 PM UTC 24 |
| Finished | Sep 01 08:04:07 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028266582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2028266582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.3728542214 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 10463142100 ps |
| CPU time | 177.84 seconds |
| Started | Sep 01 08:00:45 PM UTC 24 |
| Finished | Sep 01 08:03:46 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3728542214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.3728542214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.2744018491 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 51068800 ps |
| CPU time | 24.52 seconds |
| Started | Sep 01 08:04:42 PM UTC 24 |
| Finished | Sep 01 08:05:10 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744018491 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.2744018491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1759959180 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 39549200 ps |
| CPU time | 31.14 seconds |
| Started | Sep 01 08:04:20 PM UTC 24 |
| Finished | Sep 01 08:04:53 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759959180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1759959180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2680922953 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 29258800 ps |
| CPU time | 25.72 seconds |
| Started | Sep 01 08:04:14 PM UTC 24 |
| Finished | Sep 01 08:04:41 PM UTC 24 |
| Peak memory | 285696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2680922953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.2680922953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.993445955 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 10018745100 ps |
| CPU time | 149.27 seconds |
| Started | Sep 01 08:04:33 PM UTC 24 |
| Finished | Sep 01 08:07:07 PM UTC 24 |
| Peak memory | 332804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=993445955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.993445955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3652034851 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 26651600 ps |
| CPU time | 24.3 seconds |
| Started | Sep 01 08:04:28 PM UTC 24 |
| Finished | Sep 01 08:04:54 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3652034851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3652034851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.1123351829 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 50130062000 ps |
| CPU time | 1047.2 seconds |
| Started | Sep 01 08:03:20 PM UTC 24 |
| Finished | Sep 01 08:21:03 PM UTC 24 |
| Peak memory | 273112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123351829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res et.1123351829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3779934430 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 9901175300 ps |
| CPU time | 199.15 seconds |
| Started | Sep 01 08:03:18 PM UTC 24 |
| Finished | Sep 01 08:06:43 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779934430 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.3779934430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3842881660 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1953693300 ps |
| CPU time | 184.59 seconds |
| Started | Sep 01 08:03:47 PM UTC 24 |
| Finished | Sep 01 08:06:56 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842881660 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.3842881660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1104379065 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 23928843000 ps |
| CPU time | 279.35 seconds |
| Started | Sep 01 08:03:48 PM UTC 24 |
| Finished | Sep 01 08:08:33 PM UTC 24 |
| Peak memory | 293772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1104379065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_intr_rd_slow_flash.1104379065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3039984622 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4166762700 ps |
| CPU time | 95.19 seconds |
| Started | Sep 01 08:03:30 PM UTC 24 |
| Finished | Sep 01 08:05:10 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039984622 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3039984622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.3985668720 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 42544700 ps |
| CPU time | 24.91 seconds |
| Started | Sep 01 08:04:27 PM UTC 24 |
| Finished | Sep 01 08:04:53 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3985668720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.3985668720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1975057467 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 16856150700 ps |
| CPU time | 222.34 seconds |
| Started | Sep 01 08:03:27 PM UTC 24 |
| Finished | Sep 01 08:07:17 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1975057467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1975057467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.853067633 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 77170100 ps |
| CPU time | 263.94 seconds |
| Started | Sep 01 08:03:25 PM UTC 24 |
| Finished | Sep 01 08:07:55 PM UTC 24 |
| Peak memory | 271732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853067633 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.853067633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.1383936953 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 53454200 ps |
| CPU time | 302.57 seconds |
| Started | Sep 01 08:03:17 PM UTC 24 |
| Finished | Sep 01 08:08:27 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383936953 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1383936953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.938989516 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 32060800 ps |
| CPU time | 24.72 seconds |
| Started | Sep 01 08:03:51 PM UTC 24 |
| Finished | Sep 01 08:04:17 PM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938989516 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.938989516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.1626978559 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 205790100 ps |
| CPU time | 401.16 seconds |
| Started | Sep 01 08:03:17 PM UTC 24 |
| Finished | Sep 01 08:10:06 PM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626978559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1626978559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.96181969 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 378101200 ps |
| CPU time | 56.98 seconds |
| Started | Sep 01 08:04:13 PM UTC 24 |
| Finished | Sep 01 08:05:13 PM UTC 24 |
| Peak memory | 283652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96181969 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.96181969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3166010591 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 998943100 ps |
| CPU time | 119.23 seconds |
| Started | Sep 01 08:03:36 PM UTC 24 |
| Finished | Sep 01 08:05:39 PM UTC 24 |
| Peak memory | 302264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3166010591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.3166010591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1994241488 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4293909500 ps |
| CPU time | 518.48 seconds |
| Started | Sep 01 08:03:45 PM UTC 24 |
| Finished | Sep 01 08:12:33 PM UTC 24 |
| Peak memory | 324592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994241488 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.1994241488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1839881068 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 142143600 ps |
| CPU time | 48.8 seconds |
| Started | Sep 01 08:04:08 PM UTC 24 |
| Finished | Sep 01 08:04:59 PM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839881068 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.1839881068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2743529139 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 28492300 ps |
| CPU time | 53.82 seconds |
| Started | Sep 01 08:04:10 PM UTC 24 |
| Finished | Sep 01 08:05:07 PM UTC 24 |
| Peak memory | 281772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2743529139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c trl_rw_evict_all_en.2743529139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3907626868 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 377668400 ps |
| CPU time | 76.93 seconds |
| Started | Sep 01 08:04:18 PM UTC 24 |
| Finished | Sep 01 08:05:38 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907626868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3907626868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3083733487 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 236437700 ps |
| CPU time | 154.87 seconds |
| Started | Sep 01 08:03:16 PM UTC 24 |
| Finished | Sep 01 08:05:56 PM UTC 24 |
| Peak memory | 287600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083733487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3083733487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1393942664 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 14321028200 ps |
| CPU time | 201.69 seconds |
| Started | Sep 01 08:03:35 PM UTC 24 |
| Finished | Sep 01 08:07:02 PM UTC 24 |
| Peak memory | 275332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1393942664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.1393942664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.3137575479 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 27756100 ps |
| CPU time | 23.72 seconds |
| Started | Sep 01 08:06:44 PM UTC 24 |
| Finished | Sep 01 08:07:09 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137575479 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.3137575479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2830418541 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 14610000 ps |
| CPU time | 28.84 seconds |
| Started | Sep 01 08:06:12 PM UTC 24 |
| Finished | Sep 01 08:06:42 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830418541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2830418541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1008586073 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 10012500 ps |
| CPU time | 41.45 seconds |
| Started | Sep 01 08:06:00 PM UTC 24 |
| Finished | Sep 01 08:06:43 PM UTC 24 |
| Peak memory | 275460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1008586073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.1008586073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2406872050 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 10013386300 ps |
| CPU time | 180.36 seconds |
| Started | Sep 01 08:06:44 PM UTC 24 |
| Finished | Sep 01 08:09:47 PM UTC 24 |
| Peak memory | 300192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2406872050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2406872050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.3775855379 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 25703500 ps |
| CPU time | 25.13 seconds |
| Started | Sep 01 08:06:17 PM UTC 24 |
| Finished | Sep 01 08:06:44 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3775855379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3775855379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.4200181791 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 40125772400 ps |
| CPU time | 845.32 seconds |
| Started | Sep 01 08:05:00 PM UTC 24 |
| Finished | Sep 01 08:19:17 PM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200181791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res et.4200181791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.3554657656 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 5578159200 ps |
| CPU time | 235.08 seconds |
| Started | Sep 01 08:04:59 PM UTC 24 |
| Finished | Sep 01 08:09:00 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554657656 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.3554657656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.233692715 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1629086100 ps |
| CPU time | 210.87 seconds |
| Started | Sep 01 08:05:24 PM UTC 24 |
| Finished | Sep 01 08:08:59 PM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233692715 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.233692715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1148090522 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 13529960500 ps |
| CPU time | 413.55 seconds |
| Started | Sep 01 08:05:33 PM UTC 24 |
| Finished | Sep 01 08:12:33 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1148090522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_intr_rd_slow_flash.1148090522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.3477347615 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 6475000700 ps |
| CPU time | 65.32 seconds |
| Started | Sep 01 08:05:08 PM UTC 24 |
| Finished | Sep 01 08:06:16 PM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477347615 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3477347615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1500552458 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 25434400 ps |
| CPU time | 27.78 seconds |
| Started | Sep 01 08:06:17 PM UTC 24 |
| Finished | Sep 01 08:06:46 PM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1500552458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_lcmgr_intg.1500552458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.4237167753 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 24385235700 ps |
| CPU time | 363.4 seconds |
| Started | Sep 01 08:05:06 PM UTC 24 |
| Finished | Sep 01 08:11:16 PM UTC 24 |
| Peak memory | 283524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4237167753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.4237167753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1621079494 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 94948100 ps |
| CPU time | 242.89 seconds |
| Started | Sep 01 08:05:05 PM UTC 24 |
| Finished | Sep 01 08:09:13 PM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621079494 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.1621079494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1955494747 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 714373500 ps |
| CPU time | 308.52 seconds |
| Started | Sep 01 08:04:55 PM UTC 24 |
| Finished | Sep 01 08:10:10 PM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955494747 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1955494747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1279117016 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 19953200 ps |
| CPU time | 29.07 seconds |
| Started | Sep 01 08:05:39 PM UTC 24 |
| Finished | Sep 01 08:06:10 PM UTC 24 |
| Peak memory | 271204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279117016 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.1279117016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.1134394547 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 1619022200 ps |
| CPU time | 1109.64 seconds |
| Started | Sep 01 08:04:55 PM UTC 24 |
| Finished | Sep 01 08:23:40 PM UTC 24 |
| Peak memory | 293948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134394547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1134394547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.2776650072 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1030928800 ps |
| CPU time | 101.75 seconds |
| Started | Sep 01 08:05:11 PM UTC 24 |
| Finished | Sep 01 08:06:55 PM UTC 24 |
| Peak memory | 291784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2776650072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.2776650072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.3922176751 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 13639599700 ps |
| CPU time | 524.11 seconds |
| Started | Sep 01 08:05:14 PM UTC 24 |
| Finished | Sep 01 08:14:06 PM UTC 24 |
| Peak memory | 324552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922176751 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.3922176751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.102611586 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 40875100 ps |
| CPU time | 34.04 seconds |
| Started | Sep 01 08:05:40 PM UTC 24 |
| Finished | Sep 01 08:06:16 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102611586 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.102611586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1552375426 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 33069200 ps |
| CPU time | 56.34 seconds |
| Started | Sep 01 08:05:50 PM UTC 24 |
| Finished | Sep 01 08:06:48 PM UTC 24 |
| Peak memory | 287916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1552375426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c trl_rw_evict_all_en.1552375426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.848981969 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 10341429500 ps |
| CPU time | 96.99 seconds |
| Started | Sep 01 08:06:11 PM UTC 24 |
| Finished | Sep 01 08:07:50 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848981969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.848981969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.2481710336 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 60582900 ps |
| CPU time | 192.05 seconds |
| Started | Sep 01 08:04:53 PM UTC 24 |
| Finished | Sep 01 08:08:10 PM UTC 24 |
| Peak memory | 287600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481710336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2481710336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.2966581551 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3414567000 ps |
| CPU time | 165.55 seconds |
| Started | Sep 01 08:05:11 PM UTC 24 |
| Finished | Sep 01 08:08:00 PM UTC 24 |
| Peak memory | 271220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2966581551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.2966581551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.144492226 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 105961600 ps |
| CPU time | 17.21 seconds |
| Started | Sep 01 08:08:39 PM UTC 24 |
| Finished | Sep 01 08:08:57 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144492226 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.144492226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.4249197526 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 50426400 ps |
| CPU time | 27.34 seconds |
| Started | Sep 01 08:08:14 PM UTC 24 |
| Finished | Sep 01 08:08:42 PM UTC 24 |
| Peak memory | 284940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249197526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.4249197526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2123828850 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10105104100 ps |
| CPU time | 81.69 seconds |
| Started | Sep 01 08:08:34 PM UTC 24 |
| Finished | Sep 01 08:09:58 PM UTC 24 |
| Peak memory | 275488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2123828850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2123828850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3269558119 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 16467200 ps |
| CPU time | 23.82 seconds |
| Started | Sep 01 08:08:34 PM UTC 24 |
| Finished | Sep 01 08:08:59 PM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3269558119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3269558119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.2105467624 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 50123812400 ps |
| CPU time | 851.26 seconds |
| Started | Sep 01 08:06:48 PM UTC 24 |
| Finished | Sep 01 08:21:10 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105467624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res et.2105467624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.2334802672 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1042560900 ps |
| CPU time | 103.72 seconds |
| Started | Sep 01 08:06:47 PM UTC 24 |
| Finished | Sep 01 08:08:33 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334802672 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.2334802672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.3669544195 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1633566700 ps |
| CPU time | 182.22 seconds |
| Started | Sep 01 08:07:13 PM UTC 24 |
| Finished | Sep 01 08:10:19 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669544195 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.3669544195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.2549250615 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4650482900 ps |
| CPU time | 104.87 seconds |
| Started | Sep 01 08:06:58 PM UTC 24 |
| Finished | Sep 01 08:08:45 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549250615 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2549250615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.3182979288 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 15518900 ps |
| CPU time | 23.94 seconds |
| Started | Sep 01 08:08:28 PM UTC 24 |
| Finished | Sep 01 08:08:53 PM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3182979288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_lcmgr_intg.3182979288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.384645142 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6760550400 ps |
| CPU time | 490.7 seconds |
| Started | Sep 01 08:06:58 PM UTC 24 |
| Finished | Sep 01 08:15:15 PM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=384645142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_mp_regions.384645142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.1129482365 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 40138600 ps |
| CPU time | 190.98 seconds |
| Started | Sep 01 08:06:56 PM UTC 24 |
| Finished | Sep 01 08:10:11 PM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129482365 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.1129482365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.533992333 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 49581400 ps |
| CPU time | 85.03 seconds |
| Started | Sep 01 08:06:46 PM UTC 24 |
| Finished | Sep 01 08:08:13 PM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533992333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.533992333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.3615137102 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 22541300 ps |
| CPU time | 28.88 seconds |
| Started | Sep 01 08:07:25 PM UTC 24 |
| Finished | Sep 01 08:07:55 PM UTC 24 |
| Peak memory | 271428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615137102 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.3615137102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1814668017 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 1568286400 ps |
| CPU time | 996.43 seconds |
| Started | Sep 01 08:06:45 PM UTC 24 |
| Finished | Sep 01 08:23:33 PM UTC 24 |
| Peak memory | 293756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814668017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1814668017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1416835984 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 405049600 ps |
| CPU time | 64.93 seconds |
| Started | Sep 01 08:07:56 PM UTC 24 |
| Finished | Sep 01 08:09:03 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416835984 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.1416835984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.104556826 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1039813300 ps |
| CPU time | 112.08 seconds |
| Started | Sep 01 08:07:08 PM UTC 24 |
| Finished | Sep 01 08:09:02 PM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=104556826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.104556826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.88689206 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 4191058100 ps |
| CPU time | 594 seconds |
| Started | Sep 01 08:07:10 PM UTC 24 |
| Finished | Sep 01 08:17:12 PM UTC 24 |
| Peak memory | 320752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88689206 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.88689206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.1466020354 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 59939000 ps |
| CPU time | 63.99 seconds |
| Started | Sep 01 08:07:51 PM UTC 24 |
| Finished | Sep 01 08:08:57 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466020354 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.1466020354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.3299045670 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 31863700 ps |
| CPU time | 55.39 seconds |
| Started | Sep 01 08:07:56 PM UTC 24 |
| Finished | Sep 01 08:08:53 PM UTC 24 |
| Peak memory | 287916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3299045670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c trl_rw_evict_all_en.3299045670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.4099821462 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 62450000 ps |
| CPU time | 315.63 seconds |
| Started | Sep 01 08:06:44 PM UTC 24 |
| Finished | Sep 01 08:12:04 PM UTC 24 |
| Peak memory | 289916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099821462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.4099821462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.4029877687 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4802905500 ps |
| CPU time | 231.76 seconds |
| Started | Sep 01 08:07:04 PM UTC 24 |
| Finished | Sep 01 08:11:00 PM UTC 24 |
| Peak memory | 275508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4029877687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.4029877687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.962456430 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 63685800 ps |
| CPU time | 31.53 seconds |
| Started | Sep 01 08:10:11 PM UTC 24 |
| Finished | Sep 01 08:10:44 PM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962456430 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.962456430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.2411514735 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 41711100 ps |
| CPU time | 32.9 seconds |
| Started | Sep 01 08:09:54 PM UTC 24 |
| Finished | Sep 01 08:10:28 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411514735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2411514735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1689460448 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 75844400 ps |
| CPU time | 39.27 seconds |
| Started | Sep 01 08:09:44 PM UTC 24 |
| Finished | Sep 01 08:10:25 PM UTC 24 |
| Peak memory | 285564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1689460448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ ctrl_disable.1689460448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1206627392 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 10012328300 ps |
| CPU time | 133.08 seconds |
| Started | Sep 01 08:10:10 PM UTC 24 |
| Finished | Sep 01 08:12:26 PM UTC 24 |
| Peak memory | 341028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1206627392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1206627392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.1291565044 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 48073500 ps |
| CPU time | 23.34 seconds |
| Started | Sep 01 08:10:06 PM UTC 24 |
| Finished | Sep 01 08:10:31 PM UTC 24 |
| Peak memory | 269216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1291565044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1291565044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3691880159 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 80149717000 ps |
| CPU time | 800.24 seconds |
| Started | Sep 01 08:08:58 PM UTC 24 |
| Finished | Sep 01 08:22:28 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691880159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res et.3691880159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.3015484753 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3703473300 ps |
| CPU time | 118.08 seconds |
| Started | Sep 01 08:08:56 PM UTC 24 |
| Finished | Sep 01 08:10:56 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015484753 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.3015484753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1399955652 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6854101600 ps |
| CPU time | 268.09 seconds |
| Started | Sep 01 08:09:13 PM UTC 24 |
| Finished | Sep 01 08:13:46 PM UTC 24 |
| Peak memory | 302296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399955652 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.1399955652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.830276557 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5883086900 ps |
| CPU time | 204.57 seconds |
| Started | Sep 01 08:09:14 PM UTC 24 |
| Finished | Sep 01 08:12:42 PM UTC 24 |
| Peak memory | 306060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=830276557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.flash_ctrl_intr_rd_slow_flash.830276557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.2919594696 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5376415200 ps |
| CPU time | 132.64 seconds |
| Started | Sep 01 08:09:00 PM UTC 24 |
| Finished | Sep 01 08:11:16 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919594696 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2919594696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3513378704 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 48680600 ps |
| CPU time | 25.78 seconds |
| Started | Sep 01 08:09:59 PM UTC 24 |
| Finished | Sep 01 08:10:26 PM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3513378704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.3513378704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1893291395 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 9245333800 ps |
| CPU time | 229.93 seconds |
| Started | Sep 01 08:09:00 PM UTC 24 |
| Finished | Sep 01 08:12:54 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1893291395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1893291395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.548965000 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 138632300 ps |
| CPU time | 239.67 seconds |
| Started | Sep 01 08:08:58 PM UTC 24 |
| Finished | Sep 01 08:13:02 PM UTC 24 |
| Peak memory | 275636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548965000 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.548965000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1243076287 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 3076139000 ps |
| CPU time | 682.74 seconds |
| Started | Sep 01 08:08:56 PM UTC 24 |
| Finished | Sep 01 08:20:27 PM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243076287 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1243076287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.3823690692 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 28715500 ps |
| CPU time | 27.15 seconds |
| Started | Sep 01 08:09:25 PM UTC 24 |
| Finished | Sep 01 08:09:53 PM UTC 24 |
| Peak memory | 271208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823690692 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.3823690692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.3030602702 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 269633000 ps |
| CPU time | 628.08 seconds |
| Started | Sep 01 08:08:46 PM UTC 24 |
| Finished | Sep 01 08:19:22 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030602702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3030602702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2026187252 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 158572200 ps |
| CPU time | 42.14 seconds |
| Started | Sep 01 08:09:43 PM UTC 24 |
| Finished | Sep 01 08:10:26 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026187252 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.2026187252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.2233627626 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2616465600 ps |
| CPU time | 123.45 seconds |
| Started | Sep 01 08:09:03 PM UTC 24 |
| Finished | Sep 01 08:11:10 PM UTC 24 |
| Peak memory | 308216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2233627626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.2233627626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.3507927522 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 13598604300 ps |
| CPU time | 562.37 seconds |
| Started | Sep 01 08:09:04 PM UTC 24 |
| Finished | Sep 01 08:18:35 PM UTC 24 |
| Peak memory | 320500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507927522 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.3507927522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.4077082701 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 77359400 ps |
| CPU time | 50.69 seconds |
| Started | Sep 01 08:09:26 PM UTC 24 |
| Finished | Sep 01 08:10:18 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077082701 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.4077082701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1116961603 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 42885700 ps |
| CPU time | 39.31 seconds |
| Started | Sep 01 08:09:35 PM UTC 24 |
| Finished | Sep 01 08:10:17 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1116961603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_rw_evict_all_en.1116961603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.991755842 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 6963769000 ps |
| CPU time | 105.82 seconds |
| Started | Sep 01 08:09:48 PM UTC 24 |
| Finished | Sep 01 08:11:36 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991755842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.991755842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1416965731 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 24755700 ps |
| CPU time | 231.31 seconds |
| Started | Sep 01 08:08:43 PM UTC 24 |
| Finished | Sep 01 08:12:38 PM UTC 24 |
| Peak memory | 289656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416965731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1416965731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.3515825569 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 9577722000 ps |
| CPU time | 189.05 seconds |
| Started | Sep 01 08:09:00 PM UTC 24 |
| Finished | Sep 01 08:12:13 PM UTC 24 |
| Peak memory | 271436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3515825569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.3515825569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.3413529693 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 111823000 ps |
| CPU time | 18.11 seconds |
| Started | Sep 01 07:18:03 PM UTC 24 |
| Finished | Sep 01 07:18:23 PM UTC 24 |
| Peak memory | 275700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413529693 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3413529693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.37219457 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 26057700 ps |
| CPU time | 26.06 seconds |
| Started | Sep 01 07:17:47 PM UTC 24 |
| Finished | Sep 01 07:18:14 PM UTC 24 |
| Peak memory | 273276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37219457 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.37219457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.601551033 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 24549900 ps |
| CPU time | 21.16 seconds |
| Started | Sep 01 07:17:20 PM UTC 24 |
| Finished | Sep 01 07:17:42 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601551033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.601551033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2002826287 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3166794300 ps |
| CPU time | 239.6 seconds |
| Started | Sep 01 07:15:45 PM UTC 24 |
| Finished | Sep 01 07:19:48 PM UTC 24 |
| Peak memory | 289764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2002826287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.2002826287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1849946704 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 30387900 ps |
| CPU time | 44.61 seconds |
| Started | Sep 01 07:17:05 PM UTC 24 |
| Finished | Sep 01 07:17:52 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1849946704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_disable.1849946704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.3618342800 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5395217200 ps |
| CPU time | 557.98 seconds |
| Started | Sep 01 07:13:36 PM UTC 24 |
| Finished | Sep 01 07:23:01 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618342800 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3618342800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.4262183163 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 14534375100 ps |
| CPU time | 3390.77 seconds |
| Started | Sep 01 07:14:18 PM UTC 24 |
| Finished | Sep 01 08:11:27 PM UTC 24 |
| Peak memory | 273332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262183163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.4262183163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3463731591 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1106809700 ps |
| CPU time | 3465.73 seconds |
| Started | Sep 01 07:14:16 PM UTC 24 |
| Finished | Sep 01 08:12:43 PM UTC 24 |
| Peak memory | 275424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 63731591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _error_prog_type.3463731591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.596338991 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5770218200 ps |
| CPU time | 1495.13 seconds |
| Started | Sep 01 07:14:17 PM UTC 24 |
| Finished | Sep 01 07:39:29 PM UTC 24 |
| Peak memory | 283660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596338991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.596338991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1649300863 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 975526200 ps |
| CPU time | 37.23 seconds |
| Started | Sep 01 07:14:03 PM UTC 24 |
| Finished | Sep 01 07:14:41 PM UTC 24 |
| Peak memory | 273464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16 49300863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc h_code.1649300863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.2779658829 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 183120320100 ps |
| CPU time | 2490.62 seconds |
| Started | Sep 01 07:14:04 PM UTC 24 |
| Finished | Sep 01 07:56:02 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779658829 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.2779658829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.870132007 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 39989600 ps |
| CPU time | 56.07 seconds |
| Started | Sep 01 07:17:59 PM UTC 24 |
| Finished | Sep 01 07:18:57 PM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870132007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hos t_addr_infection.870132007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.4281052357 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 226521847300 ps |
| CPU time | 3154.59 seconds |
| Started | Sep 01 07:13:57 PM UTC 24 |
| Finished | Sep 01 08:07:12 PM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281052357 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.4281052357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.475179002 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 242202400 ps |
| CPU time | 180.29 seconds |
| Started | Sep 01 07:13:26 PM UTC 24 |
| Finished | Sep 01 07:16:30 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475179002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.475179002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2337635222 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 10011652300 ps |
| CPU time | 199.65 seconds |
| Started | Sep 01 07:17:55 PM UTC 24 |
| Finished | Sep 01 07:21:18 PM UTC 24 |
| Peak memory | 306308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2337635222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2337635222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1018235929 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 340568721800 ps |
| CPU time | 1955.01 seconds |
| Started | Sep 01 07:13:42 PM UTC 24 |
| Finished | Sep 01 07:46:40 PM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018235929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.1018235929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.1596626519 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 50126242700 ps |
| CPU time | 892.9 seconds |
| Started | Sep 01 07:13:43 PM UTC 24 |
| Finished | Sep 01 07:28:47 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596626519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.1596626519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.719666466 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1051461000 ps |
| CPU time | 70.45 seconds |
| Started | Sep 01 07:13:36 PM UTC 24 |
| Finished | Sep 01 07:14:48 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719666466 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.719666466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.862812967 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 15051637600 ps |
| CPU time | 470.23 seconds |
| Started | Sep 01 07:16:11 PM UTC 24 |
| Finished | Sep 01 07:24:08 PM UTC 24 |
| Peak memory | 339196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=862812967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integrity.862812967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.275271014 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 16226143000 ps |
| CPU time | 315.89 seconds |
| Started | Sep 01 07:16:31 PM UTC 24 |
| Finished | Sep 01 07:21:52 PM UTC 24 |
| Peak memory | 293788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=275271014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_rd_slow_flash.275271014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.825299953 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1983222300 ps |
| CPU time | 82.38 seconds |
| Started | Sep 01 07:16:21 PM UTC 24 |
| Finished | Sep 01 07:17:45 PM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825299953 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.825299953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2684168838 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 46222989300 ps |
| CPU time | 244.96 seconds |
| Started | Sep 01 07:16:34 PM UTC 24 |
| Finished | Sep 01 07:20:43 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684168838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2684168838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2705664816 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 8711646800 ps |
| CPU time | 62.54 seconds |
| Started | Sep 01 07:14:29 PM UTC 24 |
| Finished | Sep 01 07:15:34 PM UTC 24 |
| Peak memory | 273140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705664816 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2705664816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.283083038 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 59254100 ps |
| CPU time | 28.58 seconds |
| Started | Sep 01 07:17:53 PM UTC 24 |
| Finished | Sep 01 07:18:23 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=283083038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_lcmgr_intg.283083038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.3976323944 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1653465700 ps |
| CPU time | 125.08 seconds |
| Started | Sep 01 07:14:29 PM UTC 24 |
| Finished | Sep 01 07:16:37 PM UTC 24 |
| Peak memory | 271324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976323944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3976323944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.1607782307 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 139098600 ps |
| CPU time | 209.16 seconds |
| Started | Sep 01 07:13:46 PM UTC 24 |
| Finished | Sep 01 07:17:19 PM UTC 24 |
| Peak memory | 275364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607782307 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.1607782307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3719724637 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1676857900 ps |
| CPU time | 194.69 seconds |
| Started | Sep 01 07:15:55 PM UTC 24 |
| Finished | Sep 01 07:19:14 PM UTC 24 |
| Peak memory | 306140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3719724637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.3719724637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.3146923188 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 24175800 ps |
| CPU time | 22.25 seconds |
| Started | Sep 01 07:17:45 PM UTC 24 |
| Finished | Sep 01 07:18:08 PM UTC 24 |
| Peak memory | 275584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146923188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3146923188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1376194626 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 40981700 ps |
| CPU time | 226.33 seconds |
| Started | Sep 01 07:13:29 PM UTC 24 |
| Finished | Sep 01 07:17:19 PM UTC 24 |
| Peak memory | 273532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376194626 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1376194626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.3849685559 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 111002300 ps |
| CPU time | 26.59 seconds |
| Started | Sep 01 07:17:42 PM UTC 24 |
| Finished | Sep 01 07:18:11 PM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3849685559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3849685559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.533862140 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 9823399900 ps |
| CPU time | 245.34 seconds |
| Started | Sep 01 07:16:36 PM UTC 24 |
| Finished | Sep 01 07:20:46 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533862140 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.533862140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1286457738 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 778081900 ps |
| CPU time | 1275.99 seconds |
| Started | Sep 01 07:13:15 PM UTC 24 |
| Finished | Sep 01 07:34:46 PM UTC 24 |
| Peak memory | 295800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286457738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1286457738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1995984796 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 733096900 ps |
| CPU time | 133.37 seconds |
| Started | Sep 01 07:13:27 PM UTC 24 |
| Finished | Sep 01 07:15:43 PM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995984796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1995984796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.1218989441 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 86630500 ps |
| CPU time | 35.57 seconds |
| Started | Sep 01 07:17:25 PM UTC 24 |
| Finished | Sep 01 07:18:02 PM UTC 24 |
| Peak memory | 287720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121898944 1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.1218989441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.277228069 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 62047200 ps |
| CPU time | 40.61 seconds |
| Started | Sep 01 07:16:57 PM UTC 24 |
| Finished | Sep 01 07:17:39 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277228069 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.277228069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2011407696 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 33520100 ps |
| CPU time | 41.55 seconds |
| Started | Sep 01 07:15:35 PM UTC 24 |
| Finished | Sep 01 07:16:18 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2011407696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_read_word_sweep_derr.2011407696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3150344300 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 80942800 ps |
| CPU time | 39.95 seconds |
| Started | Sep 01 07:15:02 PM UTC 24 |
| Finished | Sep 01 07:15:43 PM UTC 24 |
| Peak memory | 275584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150344300 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.3150344300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.1688543218 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 163831378200 ps |
| CPU time | 913.8 seconds |
| Started | Sep 01 07:17:49 PM UTC 24 |
| Finished | Sep 01 07:33:13 PM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1688543218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. flash_ctrl_rma_err.1688543218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3678733625 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 12172225800 ps |
| CPU time | 184.38 seconds |
| Started | Sep 01 07:14:46 PM UTC 24 |
| Finished | Sep 01 07:17:53 PM UTC 24 |
| Peak memory | 301940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3678733625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.3678733625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.809443689 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 698033600 ps |
| CPU time | 189.4 seconds |
| Started | Sep 01 07:15:36 PM UTC 24 |
| Finished | Sep 01 07:18:48 PM UTC 24 |
| Peak memory | 292000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809443689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.809443689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3736980166 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3417700900 ps |
| CPU time | 108.33 seconds |
| Started | Sep 01 07:15:22 PM UTC 24 |
| Finished | Sep 01 07:17:13 PM UTC 24 |
| Peak memory | 292008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3736980166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_ro_serr.3736980166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.455374234 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 43709857600 ps |
| CPU time | 621.62 seconds |
| Started | Sep 01 07:14:49 PM UTC 24 |
| Finished | Sep 01 07:25:19 PM UTC 24 |
| Peak memory | 324588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455374234 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.455374234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.469835263 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29209200 ps |
| CPU time | 57.78 seconds |
| Started | Sep 01 07:16:38 PM UTC 24 |
| Finished | Sep 01 07:17:38 PM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469835263 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.469835263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1356990407 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 55424300 ps |
| CPU time | 51.82 seconds |
| Started | Sep 01 07:16:48 PM UTC 24 |
| Finished | Sep 01 07:17:42 PM UTC 24 |
| Peak memory | 287716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1356990407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_rw_evict_all_en.1356990407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3989200533 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1872510900 ps |
| CPU time | 209.84 seconds |
| Started | Sep 01 07:15:23 PM UTC 24 |
| Finished | Sep 01 07:18:56 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3989200533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.3989200533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.59855745 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1952442200 ps |
| CPU time | 6810.16 seconds |
| Started | Sep 01 07:17:14 PM UTC 24 |
| Finished | Sep 01 09:11:59 PM UTC 24 |
| Peak memory | 314456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59855745 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.59855745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2743105037 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3413838800 ps |
| CPU time | 104.09 seconds |
| Started | Sep 01 07:17:19 PM UTC 24 |
| Finished | Sep 01 07:19:05 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743105037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2743105037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.626183552 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2990212100 ps |
| CPU time | 137.69 seconds |
| Started | Sep 01 07:15:27 PM UTC 24 |
| Finished | Sep 01 07:17:48 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626 183552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr _address.626183552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3576350271 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1997519900 ps |
| CPU time | 88.4 seconds |
| Started | Sep 01 07:15:26 PM UTC 24 |
| Finished | Sep 01 07:16:57 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 76350271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.3576350271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.4142214768 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 112769700 ps |
| CPU time | 134.04 seconds |
| Started | Sep 01 07:13:09 PM UTC 24 |
| Finished | Sep 01 07:15:26 PM UTC 24 |
| Peak memory | 287860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142214768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.4142214768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1133545095 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 55156300 ps |
| CPU time | 52.04 seconds |
| Started | Sep 01 07:13:09 PM UTC 24 |
| Finished | Sep 01 07:14:03 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133545095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1133545095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.1734454245 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1590188500 ps |
| CPU time | 1469.61 seconds |
| Started | Sep 01 07:17:20 PM UTC 24 |
| Finished | Sep 01 07:42:08 PM UTC 24 |
| Peak memory | 295952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734454245 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.1734454245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.181149271 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 35177000 ps |
| CPU time | 40.54 seconds |
| Started | Sep 01 07:13:20 PM UTC 24 |
| Finished | Sep 01 07:14:02 PM UTC 24 |
| Peak memory | 271240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181149271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.181149271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.2386454635 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3582577100 ps |
| CPU time | 210.93 seconds |
| Started | Sep 01 07:14:43 PM UTC 24 |
| Finished | Sep 01 07:18:17 PM UTC 24 |
| Peak memory | 271480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2386454635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.2386454635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.994557145 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 35417400 ps |
| CPU time | 27.03 seconds |
| Started | Sep 01 08:10:51 PM UTC 24 |
| Finished | Sep 01 08:11:19 PM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994557145 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.994557145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.654824916 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 50211800 ps |
| CPU time | 24.91 seconds |
| Started | Sep 01 08:10:46 PM UTC 24 |
| Finished | Sep 01 08:11:12 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654824916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.654824916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4265493135 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 11265800 ps |
| CPU time | 43.87 seconds |
| Started | Sep 01 08:10:29 PM UTC 24 |
| Finished | Sep 01 08:11:15 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4265493135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.4265493135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.741734758 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 631846200 ps |
| CPU time | 75.07 seconds |
| Started | Sep 01 08:10:18 PM UTC 24 |
| Finished | Sep 01 08:11:35 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741734758 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.741734758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.4265320862 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3864618800 ps |
| CPU time | 160.15 seconds |
| Started | Sep 01 08:10:20 PM UTC 24 |
| Finished | Sep 01 08:13:03 PM UTC 24 |
| Peak memory | 306336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265320862 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.4265320862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4209894932 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 23993303900 ps |
| CPU time | 210.9 seconds |
| Started | Sep 01 08:10:26 PM UTC 24 |
| Finished | Sep 01 08:14:00 PM UTC 24 |
| Peak memory | 304220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4209894932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.flash_ctrl_intr_rd_slow_flash.4209894932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3373295268 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 71417900 ps |
| CPU time | 213.61 seconds |
| Started | Sep 01 08:10:19 PM UTC 24 |
| Finished | Sep 01 08:13:56 PM UTC 24 |
| Peak memory | 275356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373295268 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.3373295268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1540767543 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2247968900 ps |
| CPU time | 228.55 seconds |
| Started | Sep 01 08:10:27 PM UTC 24 |
| Finished | Sep 01 08:14:19 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540767543 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.1540767543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.83697675 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 38514900 ps |
| CPU time | 52.9 seconds |
| Started | Sep 01 08:10:27 PM UTC 24 |
| Finished | Sep 01 08:11:22 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83697675 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.83697675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2444648953 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 914155500 ps |
| CPU time | 60.2 seconds |
| Started | Sep 01 08:10:32 PM UTC 24 |
| Finished | Sep 01 08:11:34 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444648953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2444648953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.116287238 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 32087800 ps |
| CPU time | 178.51 seconds |
| Started | Sep 01 08:10:15 PM UTC 24 |
| Finished | Sep 01 08:13:17 PM UTC 24 |
| Peak memory | 277372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116287238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.116287238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.2351754395 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 162049100 ps |
| CPU time | 29.27 seconds |
| Started | Sep 01 08:11:36 PM UTC 24 |
| Finished | Sep 01 08:12:07 PM UTC 24 |
| Peak memory | 269280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351754395 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.2351754395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.4187524996 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 15454900 ps |
| CPU time | 32.4 seconds |
| Started | Sep 01 08:11:35 PM UTC 24 |
| Finished | Sep 01 08:12:09 PM UTC 24 |
| Peak memory | 295372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187524996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.4187524996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.4133557516 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 7477574300 ps |
| CPU time | 103.18 seconds |
| Started | Sep 01 08:11:00 PM UTC 24 |
| Finished | Sep 01 08:12:46 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133557516 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.4133557516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2438539773 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 3009124800 ps |
| CPU time | 224.6 seconds |
| Started | Sep 01 08:11:12 PM UTC 24 |
| Finished | Sep 01 08:15:01 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438539773 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.2438539773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.611752507 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 18071774400 ps |
| CPU time | 383.39 seconds |
| Started | Sep 01 08:11:15 PM UTC 24 |
| Finished | Sep 01 08:17:44 PM UTC 24 |
| Peak memory | 302112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=611752507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 21.flash_ctrl_intr_rd_slow_flash.611752507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.2583763970 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 37083500 ps |
| CPU time | 194.68 seconds |
| Started | Sep 01 08:11:10 PM UTC 24 |
| Finished | Sep 01 08:14:28 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583763970 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.2583763970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1553784519 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 468229300 ps |
| CPU time | 53.05 seconds |
| Started | Sep 01 08:11:17 PM UTC 24 |
| Finished | Sep 01 08:12:12 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553784519 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.1553784519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.3044586003 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 43291300 ps |
| CPU time | 51.76 seconds |
| Started | Sep 01 08:11:17 PM UTC 24 |
| Finished | Sep 01 08:12:11 PM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044586003 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.3044586003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.1253200535 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 50083200 ps |
| CPU time | 47.82 seconds |
| Started | Sep 01 08:11:20 PM UTC 24 |
| Finished | Sep 01 08:12:10 PM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1253200535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c trl_rw_evict_all_en.1253200535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.1917281688 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 422149500 ps |
| CPU time | 87.11 seconds |
| Started | Sep 01 08:11:28 PM UTC 24 |
| Finished | Sep 01 08:12:57 PM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917281688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.1917281688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.1384143485 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 20951900 ps |
| CPU time | 181.22 seconds |
| Started | Sep 01 08:10:57 PM UTC 24 |
| Finished | Sep 01 08:14:01 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384143485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1384143485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3343667739 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 24912000 ps |
| CPU time | 23.82 seconds |
| Started | Sep 01 08:12:27 PM UTC 24 |
| Finished | Sep 01 08:12:52 PM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343667739 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.3343667739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.1902570907 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 21706300 ps |
| CPU time | 24.89 seconds |
| Started | Sep 01 08:12:20 PM UTC 24 |
| Finished | Sep 01 08:12:47 PM UTC 24 |
| Peak memory | 284940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902570907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1902570907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.3060046439 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 22207300 ps |
| CPU time | 25.28 seconds |
| Started | Sep 01 08:12:13 PM UTC 24 |
| Finished | Sep 01 08:12:39 PM UTC 24 |
| Peak memory | 275460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3060046439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ ctrl_disable.3060046439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.936406263 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1907527600 ps |
| CPU time | 161.6 seconds |
| Started | Sep 01 08:12:05 PM UTC 24 |
| Finished | Sep 01 08:14:50 PM UTC 24 |
| Peak memory | 293852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936406263 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.936406263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4168402970 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5882044200 ps |
| CPU time | 173.99 seconds |
| Started | Sep 01 08:12:07 PM UTC 24 |
| Finished | Sep 01 08:15:04 PM UTC 24 |
| Peak memory | 304012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4168402970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.flash_ctrl_intr_rd_slow_flash.4168402970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2671168783 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 164272500 ps |
| CPU time | 236.02 seconds |
| Started | Sep 01 08:12:03 PM UTC 24 |
| Finished | Sep 01 08:16:03 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671168783 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.2671168783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3384832940 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 37521500 ps |
| CPU time | 26.18 seconds |
| Started | Sep 01 08:12:09 PM UTC 24 |
| Finished | Sep 01 08:12:37 PM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384832940 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3384832940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3046998664 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 45366700 ps |
| CPU time | 38.24 seconds |
| Started | Sep 01 08:12:11 PM UTC 24 |
| Finished | Sep 01 08:12:50 PM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046998664 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.3046998664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.384373296 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4390456500 ps |
| CPU time | 85.65 seconds |
| Started | Sep 01 08:12:14 PM UTC 24 |
| Finished | Sep 01 08:13:41 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384373296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.384373296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.2078902131 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 26727100 ps |
| CPU time | 160.24 seconds |
| Started | Sep 01 08:11:36 PM UTC 24 |
| Finished | Sep 01 08:14:19 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078902131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2078902131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.3733718839 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 61786400 ps |
| CPU time | 23.27 seconds |
| Started | Sep 01 08:12:53 PM UTC 24 |
| Finished | Sep 01 08:13:18 PM UTC 24 |
| Peak memory | 275620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733718839 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.3733718839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.705357043 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 49345600 ps |
| CPU time | 25.35 seconds |
| Started | Sep 01 08:12:51 PM UTC 24 |
| Finished | Sep 01 08:13:18 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705357043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.705357043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3411164757 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 10648600 ps |
| CPU time | 45.2 seconds |
| Started | Sep 01 08:12:47 PM UTC 24 |
| Finished | Sep 01 08:13:34 PM UTC 24 |
| Peak memory | 285924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3411164757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ ctrl_disable.3411164757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3784125045 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3007426000 ps |
| CPU time | 109.77 seconds |
| Started | Sep 01 08:12:33 PM UTC 24 |
| Finished | Sep 01 08:14:26 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784125045 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3784125045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.1386925325 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3706821100 ps |
| CPU time | 164.92 seconds |
| Started | Sep 01 08:12:39 PM UTC 24 |
| Finished | Sep 01 08:15:28 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386925325 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.1386925325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2972198440 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 25300338400 ps |
| CPU time | 397.77 seconds |
| Started | Sep 01 08:12:40 PM UTC 24 |
| Finished | Sep 01 08:19:23 PM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2972198440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.flash_ctrl_intr_rd_slow_flash.2972198440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.904689913 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 74993400 ps |
| CPU time | 187.33 seconds |
| Started | Sep 01 08:12:38 PM UTC 24 |
| Finished | Sep 01 08:15:49 PM UTC 24 |
| Peak memory | 271604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904689913 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.904689913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.3475670840 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 21631600 ps |
| CPU time | 24.83 seconds |
| Started | Sep 01 08:12:41 PM UTC 24 |
| Finished | Sep 01 08:13:07 PM UTC 24 |
| Peak memory | 275572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475670840 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.3475670840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3211047687 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 29464100 ps |
| CPU time | 52.89 seconds |
| Started | Sep 01 08:12:43 PM UTC 24 |
| Finished | Sep 01 08:13:37 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211047687 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.3211047687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.401278236 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 28069000 ps |
| CPU time | 32.25 seconds |
| Started | Sep 01 08:12:44 PM UTC 24 |
| Finished | Sep 01 08:13:18 PM UTC 24 |
| Peak memory | 285680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=401278236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ct rl_rw_evict_all_en.401278236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2682025939 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5681640700 ps |
| CPU time | 64.84 seconds |
| Started | Sep 01 08:12:47 PM UTC 24 |
| Finished | Sep 01 08:13:54 PM UTC 24 |
| Peak memory | 275476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682025939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2682025939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.3367409319 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 196430600 ps |
| CPU time | 252.62 seconds |
| Started | Sep 01 08:12:33 PM UTC 24 |
| Finished | Sep 01 08:16:50 PM UTC 24 |
| Peak memory | 289852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367409319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3367409319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.3992659531 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 37012300 ps |
| CPU time | 17.26 seconds |
| Started | Sep 01 08:13:35 PM UTC 24 |
| Finished | Sep 01 08:13:53 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992659531 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.3992659531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.3267060349 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 84473800 ps |
| CPU time | 27.43 seconds |
| Started | Sep 01 08:13:19 PM UTC 24 |
| Finished | Sep 01 08:13:48 PM UTC 24 |
| Peak memory | 284940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267060349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3267060349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.1170921892 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 10807007900 ps |
| CPU time | 124.68 seconds |
| Started | Sep 01 08:12:58 PM UTC 24 |
| Finished | Sep 01 08:15:05 PM UTC 24 |
| Peak memory | 273172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170921892 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.1170921892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.1802814105 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1375006800 ps |
| CPU time | 174.45 seconds |
| Started | Sep 01 08:13:03 PM UTC 24 |
| Finished | Sep 01 08:16:01 PM UTC 24 |
| Peak memory | 304356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802814105 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.1802814105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1007674736 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 35164181300 ps |
| CPU time | 167.93 seconds |
| Started | Sep 01 08:13:07 PM UTC 24 |
| Finished | Sep 01 08:15:58 PM UTC 24 |
| Peak memory | 301976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1007674736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.flash_ctrl_intr_rd_slow_flash.1007674736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.816532303 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 254639800 ps |
| CPU time | 234.37 seconds |
| Started | Sep 01 08:13:03 PM UTC 24 |
| Finished | Sep 01 08:17:01 PM UTC 24 |
| Peak memory | 271540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816532303 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.816532303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.385644532 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 19990600 ps |
| CPU time | 25.19 seconds |
| Started | Sep 01 08:13:12 PM UTC 24 |
| Finished | Sep 01 08:13:39 PM UTC 24 |
| Peak memory | 269160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385644532 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.385644532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.2111057091 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 28621900 ps |
| CPU time | 51.28 seconds |
| Started | Sep 01 08:13:14 PM UTC 24 |
| Finished | Sep 01 08:14:07 PM UTC 24 |
| Peak memory | 287760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111057091 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.2111057091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.2498524956 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 30138900 ps |
| CPU time | 45.19 seconds |
| Started | Sep 01 08:13:18 PM UTC 24 |
| Finished | Sep 01 08:14:04 PM UTC 24 |
| Peak memory | 285676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2498524956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_rw_evict_all_en.2498524956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.3944052209 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 6025906900 ps |
| CPU time | 81.71 seconds |
| Started | Sep 01 08:13:19 PM UTC 24 |
| Finished | Sep 01 08:14:42 PM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944052209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3944052209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.1253317066 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 37986300 ps |
| CPU time | 281.84 seconds |
| Started | Sep 01 08:12:55 PM UTC 24 |
| Finished | Sep 01 08:17:41 PM UTC 24 |
| Peak memory | 289660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253317066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1253317066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.603841207 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 69833500 ps |
| CPU time | 25.99 seconds |
| Started | Sep 01 08:14:02 PM UTC 24 |
| Finished | Sep 01 08:14:30 PM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603841207 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.603841207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.446277856 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 21259200 ps |
| CPU time | 29.45 seconds |
| Started | Sep 01 08:14:01 PM UTC 24 |
| Finished | Sep 01 08:14:32 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446277856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.446277856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3982620762 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 27767900 ps |
| CPU time | 40.69 seconds |
| Started | Sep 01 08:13:58 PM UTC 24 |
| Finished | Sep 01 08:14:41 PM UTC 24 |
| Peak memory | 285860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3982620762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ ctrl_disable.3982620762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.1613318746 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 39993757600 ps |
| CPU time | 163.5 seconds |
| Started | Sep 01 08:13:40 PM UTC 24 |
| Finished | Sep 01 08:16:26 PM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613318746 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.1613318746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.357975008 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2761127900 ps |
| CPU time | 151.63 seconds |
| Started | Sep 01 08:13:47 PM UTC 24 |
| Finished | Sep 01 08:16:22 PM UTC 24 |
| Peak memory | 306176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357975008 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.357975008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1824703257 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 12947135000 ps |
| CPU time | 273.87 seconds |
| Started | Sep 01 08:13:48 PM UTC 24 |
| Finished | Sep 01 08:18:26 PM UTC 24 |
| Peak memory | 302164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1824703257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_intr_rd_slow_flash.1824703257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.2818323740 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 149226200 ps |
| CPU time | 223.92 seconds |
| Started | Sep 01 08:13:42 PM UTC 24 |
| Finished | Sep 01 08:17:30 PM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818323740 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.2818323740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.266827696 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 296423900 ps |
| CPU time | 16.6 seconds |
| Started | Sep 01 08:13:57 PM UTC 24 |
| Finished | Sep 01 08:14:15 PM UTC 24 |
| Peak memory | 271432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266827696 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.266827696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.4287226301 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 125083100 ps |
| CPU time | 51.96 seconds |
| Started | Sep 01 08:13:58 PM UTC 24 |
| Finished | Sep 01 08:14:52 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287226301 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.4287226301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3852222751 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 27602300 ps |
| CPU time | 40.1 seconds |
| Started | Sep 01 08:13:58 PM UTC 24 |
| Finished | Sep 01 08:14:40 PM UTC 24 |
| Peak memory | 285868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3852222751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c trl_rw_evict_all_en.3852222751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1180219536 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 6199412400 ps |
| CPU time | 76.02 seconds |
| Started | Sep 01 08:13:58 PM UTC 24 |
| Finished | Sep 01 08:15:16 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180219536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1180219536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.457856383 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 30415200 ps |
| CPU time | 76.05 seconds |
| Started | Sep 01 08:13:38 PM UTC 24 |
| Finished | Sep 01 08:14:56 PM UTC 24 |
| Peak memory | 285564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457856383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.457856383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2394888210 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 72500100 ps |
| CPU time | 19.91 seconds |
| Started | Sep 01 08:14:32 PM UTC 24 |
| Finished | Sep 01 08:14:53 PM UTC 24 |
| Peak memory | 271344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394888210 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.2394888210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.3069739354 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 25648200 ps |
| CPU time | 28.29 seconds |
| Started | Sep 01 08:14:30 PM UTC 24 |
| Finished | Sep 01 08:15:00 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069739354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3069739354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.2320942136 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 12021900 ps |
| CPU time | 35.08 seconds |
| Started | Sep 01 08:14:28 PM UTC 24 |
| Finished | Sep 01 08:15:05 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2320942136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ ctrl_disable.2320942136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.485565358 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3116538600 ps |
| CPU time | 80.45 seconds |
| Started | Sep 01 08:14:06 PM UTC 24 |
| Finished | Sep 01 08:15:29 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485565358 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.485565358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.75717544 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2285607300 ps |
| CPU time | 316.3 seconds |
| Started | Sep 01 08:14:16 PM UTC 24 |
| Finished | Sep 01 08:19:37 PM UTC 24 |
| Peak memory | 293852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75717544 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.75717544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2689235643 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5625143500 ps |
| CPU time | 161.62 seconds |
| Started | Sep 01 08:14:20 PM UTC 24 |
| Finished | Sep 01 08:17:04 PM UTC 24 |
| Peak memory | 304020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2689235643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.flash_ctrl_intr_rd_slow_flash.2689235643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.3427270291 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 192165600 ps |
| CPU time | 205.31 seconds |
| Started | Sep 01 08:14:08 PM UTC 24 |
| Finished | Sep 01 08:17:37 PM UTC 24 |
| Peak memory | 271656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427270291 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.3427270291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.3173963926 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 21986100 ps |
| CPU time | 28.28 seconds |
| Started | Sep 01 08:14:21 PM UTC 24 |
| Finished | Sep 01 08:14:50 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173963926 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.3173963926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.4001927073 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 41752200 ps |
| CPU time | 43.9 seconds |
| Started | Sep 01 08:14:21 PM UTC 24 |
| Finished | Sep 01 08:15:06 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001927073 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.4001927073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.3882666584 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 28920800 ps |
| CPU time | 49.62 seconds |
| Started | Sep 01 08:14:26 PM UTC 24 |
| Finished | Sep 01 08:15:17 PM UTC 24 |
| Peak memory | 285672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3882666584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_rw_evict_all_en.3882666584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.596802963 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 497941400 ps |
| CPU time | 94.65 seconds |
| Started | Sep 01 08:14:29 PM UTC 24 |
| Finished | Sep 01 08:16:06 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596802963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.596802963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.2555394933 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 232389000 ps |
| CPU time | 341.9 seconds |
| Started | Sep 01 08:14:05 PM UTC 24 |
| Finished | Sep 01 08:19:52 PM UTC 24 |
| Peak memory | 289648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555394933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2555394933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.182226525 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 105731400 ps |
| CPU time | 22.62 seconds |
| Started | Sep 01 08:15:01 PM UTC 24 |
| Finished | Sep 01 08:15:25 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182226525 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.182226525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3407220178 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 13416900 ps |
| CPU time | 19.25 seconds |
| Started | Sep 01 08:15:01 PM UTC 24 |
| Finished | Sep 01 08:15:21 PM UTC 24 |
| Peak memory | 285068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407220178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3407220178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.4282838382 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 10559100 ps |
| CPU time | 35.68 seconds |
| Started | Sep 01 08:14:54 PM UTC 24 |
| Finished | Sep 01 08:15:31 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4282838382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ ctrl_disable.4282838382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.2159913391 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 8405464600 ps |
| CPU time | 218.88 seconds |
| Started | Sep 01 08:14:40 PM UTC 24 |
| Finished | Sep 01 08:18:22 PM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159913391 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.2159913391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.736142808 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 774233900 ps |
| CPU time | 177.93 seconds |
| Started | Sep 01 08:14:41 PM UTC 24 |
| Finished | Sep 01 08:17:42 PM UTC 24 |
| Peak memory | 293852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736142808 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.736142808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.992172773 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 11547414500 ps |
| CPU time | 362.06 seconds |
| Started | Sep 01 08:14:43 PM UTC 24 |
| Finished | Sep 01 08:20:50 PM UTC 24 |
| Peak memory | 301976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=992172773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 27.flash_ctrl_intr_rd_slow_flash.992172773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.1589216118 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 76420500 ps |
| CPU time | 142.24 seconds |
| Started | Sep 01 08:14:41 PM UTC 24 |
| Finished | Sep 01 08:17:06 PM UTC 24 |
| Peak memory | 271464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589216118 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.1589216118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.1484189355 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 21881435000 ps |
| CPU time | 218.08 seconds |
| Started | Sep 01 08:14:50 PM UTC 24 |
| Finished | Sep 01 08:18:32 PM UTC 24 |
| Peak memory | 275308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484189355 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.1484189355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.4172679796 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 44163600 ps |
| CPU time | 42.12 seconds |
| Started | Sep 01 08:14:51 PM UTC 24 |
| Finished | Sep 01 08:15:35 PM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172679796 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.4172679796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.811642676 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 45330900 ps |
| CPU time | 54.67 seconds |
| Started | Sep 01 08:14:52 PM UTC 24 |
| Finished | Sep 01 08:15:49 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=811642676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ct rl_rw_evict_all_en.811642676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2427139393 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2923749500 ps |
| CPU time | 99.48 seconds |
| Started | Sep 01 08:14:57 PM UTC 24 |
| Finished | Sep 01 08:16:38 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427139393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2427139393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.374634505 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 60092100 ps |
| CPU time | 178.69 seconds |
| Started | Sep 01 08:14:33 PM UTC 24 |
| Finished | Sep 01 08:17:34 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374634505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.374634505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.2947574634 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 112674500 ps |
| CPU time | 17.75 seconds |
| Started | Sep 01 08:15:29 PM UTC 24 |
| Finished | Sep 01 08:15:48 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947574634 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.2947574634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.791810654 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 54694600 ps |
| CPU time | 19 seconds |
| Started | Sep 01 08:15:26 PM UTC 24 |
| Finished | Sep 01 08:15:46 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791810654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.791810654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.3661726371 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 7794319200 ps |
| CPU time | 171.83 seconds |
| Started | Sep 01 08:15:05 PM UTC 24 |
| Finished | Sep 01 08:18:00 PM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661726371 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.3661726371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.3355780823 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 18391032700 ps |
| CPU time | 272 seconds |
| Started | Sep 01 08:15:06 PM UTC 24 |
| Finished | Sep 01 08:19:43 PM UTC 24 |
| Peak memory | 293884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355780823 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.3355780823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.787000904 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 62295030700 ps |
| CPU time | 324.44 seconds |
| Started | Sep 01 08:15:08 PM UTC 24 |
| Finished | Sep 01 08:20:37 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=787000904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 28.flash_ctrl_intr_rd_slow_flash.787000904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.228116619 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 236691900 ps |
| CPU time | 213 seconds |
| Started | Sep 01 08:15:05 PM UTC 24 |
| Finished | Sep 01 08:18:42 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228116619 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.228116619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.617015049 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 26052400 ps |
| CPU time | 18.89 seconds |
| Started | Sep 01 08:15:18 PM UTC 24 |
| Finished | Sep 01 08:15:38 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617015049 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.617015049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.3897965918 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 41567400 ps |
| CPU time | 52.89 seconds |
| Started | Sep 01 08:15:19 PM UTC 24 |
| Finished | Sep 01 08:16:14 PM UTC 24 |
| Peak memory | 285708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897965918 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.3897965918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.3319439533 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 50571400 ps |
| CPU time | 37.58 seconds |
| Started | Sep 01 08:15:20 PM UTC 24 |
| Finished | Sep 01 08:15:58 PM UTC 24 |
| Peak memory | 285676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3319439533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_rw_evict_all_en.3319439533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.2707015220 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 7876181400 ps |
| CPU time | 91.42 seconds |
| Started | Sep 01 08:15:23 PM UTC 24 |
| Finished | Sep 01 08:16:56 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707015220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2707015220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.3854182001 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 46166300 ps |
| CPU time | 140.48 seconds |
| Started | Sep 01 08:15:02 PM UTC 24 |
| Finished | Sep 01 08:17:25 PM UTC 24 |
| Peak memory | 287596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854182001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3854182001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.4153656814 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 277599700 ps |
| CPU time | 21.39 seconds |
| Started | Sep 01 08:16:00 PM UTC 24 |
| Finished | Sep 01 08:16:22 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153656814 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.4153656814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1376430568 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 39213500 ps |
| CPU time | 26.95 seconds |
| Started | Sep 01 08:15:58 PM UTC 24 |
| Finished | Sep 01 08:16:27 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376430568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1376430568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2636637175 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 31366100 ps |
| CPU time | 39.15 seconds |
| Started | Sep 01 08:15:50 PM UTC 24 |
| Finished | Sep 01 08:16:31 PM UTC 24 |
| Peak memory | 285860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2636637175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ ctrl_disable.2636637175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.2074528461 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 25010593500 ps |
| CPU time | 107.65 seconds |
| Started | Sep 01 08:15:31 PM UTC 24 |
| Finished | Sep 01 08:17:21 PM UTC 24 |
| Peak memory | 271312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074528461 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.2074528461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.2144197755 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 5141468800 ps |
| CPU time | 186.15 seconds |
| Started | Sep 01 08:15:38 PM UTC 24 |
| Finished | Sep 01 08:18:48 PM UTC 24 |
| Peak memory | 302044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144197755 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.2144197755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.212873840 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 46338709900 ps |
| CPU time | 193.46 seconds |
| Started | Sep 01 08:15:41 PM UTC 24 |
| Finished | Sep 01 08:18:57 PM UTC 24 |
| Peak memory | 304028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=212873840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 29.flash_ctrl_intr_rd_slow_flash.212873840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.3682788652 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 15699702100 ps |
| CPU time | 197.24 seconds |
| Started | Sep 01 08:15:47 PM UTC 24 |
| Finished | Sep 01 08:19:07 PM UTC 24 |
| Peak memory | 271236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682788652 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.3682788652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.1854559329 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 83094200 ps |
| CPU time | 52.93 seconds |
| Started | Sep 01 08:15:49 PM UTC 24 |
| Finished | Sep 01 08:16:43 PM UTC 24 |
| Peak memory | 287756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854559329 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.1854559329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.1247928196 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 532618600 ps |
| CPU time | 71.51 seconds |
| Started | Sep 01 08:15:52 PM UTC 24 |
| Finished | Sep 01 08:17:06 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247928196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1247928196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.864209379 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 19097700 ps |
| CPU time | 95.53 seconds |
| Started | Sep 01 08:15:30 PM UTC 24 |
| Finished | Sep 01 08:17:08 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864209379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.864209379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3947203780 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 86663900 ps |
| CPU time | 23.5 seconds |
| Started | Sep 01 07:24:15 PM UTC 24 |
| Finished | Sep 01 07:24:40 PM UTC 24 |
| Peak memory | 269280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947203780 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3947203780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.596883167 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 21530900 ps |
| CPU time | 17.06 seconds |
| Started | Sep 01 07:24:02 PM UTC 24 |
| Finished | Sep 01 07:24:20 PM UTC 24 |
| Peak memory | 273440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596883167 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.596883167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.239050533 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 21846100 ps |
| CPU time | 29.71 seconds |
| Started | Sep 01 07:23:37 PM UTC 24 |
| Finished | Sep 01 07:24:08 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239050533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.239050533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.591708921 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 743686400 ps |
| CPU time | 297.79 seconds |
| Started | Sep 01 07:21:33 PM UTC 24 |
| Finished | Sep 01 07:26:35 PM UTC 24 |
| Peak memory | 289764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=591708921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_derr_detect.591708921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3323291054 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 17505200 ps |
| CPU time | 35.77 seconds |
| Started | Sep 01 07:22:59 PM UTC 24 |
| Finished | Sep 01 07:23:36 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3323291054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_disable.3323291054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2251661039 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 102951300 ps |
| CPU time | 336 seconds |
| Started | Sep 01 07:18:27 PM UTC 24 |
| Finished | Sep 01 07:24:08 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251661039 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2251661039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1297975918 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 23488070900 ps |
| CPU time | 3293.07 seconds |
| Started | Sep 01 07:19:07 PM UTC 24 |
| Finished | Sep 01 08:14:38 PM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297975918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1297975918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.3626243678 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 451657900 ps |
| CPU time | 3215.15 seconds |
| Started | Sep 01 07:19:00 PM UTC 24 |
| Finished | Sep 01 08:13:12 PM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 26243678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _error_prog_type.3626243678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.855698615 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2905548200 ps |
| CPU time | 1604.65 seconds |
| Started | Sep 01 07:19:06 PM UTC 24 |
| Finished | Sep 01 07:46:09 PM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855698615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.855698615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.3461676504 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 333895500 ps |
| CPU time | 34.15 seconds |
| Started | Sep 01 07:18:58 PM UTC 24 |
| Finished | Sep 01 07:19:33 PM UTC 24 |
| Peak memory | 273472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34 61676504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc h_code.3461676504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3177461050 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 614195600 ps |
| CPU time | 44.96 seconds |
| Started | Sep 01 07:23:38 PM UTC 24 |
| Finished | Sep 01 07:24:25 PM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177461 050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.3177461050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2516215355 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 325644453500 ps |
| CPU time | 2981.61 seconds |
| Started | Sep 01 07:18:58 PM UTC 24 |
| Finished | Sep 01 08:09:16 PM UTC 24 |
| Peak memory | 273244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516215355 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.2516215355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2374085511 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 534157369000 ps |
| CPU time | 2339.91 seconds |
| Started | Sep 01 07:18:49 PM UTC 24 |
| Finished | Sep 01 07:58:15 PM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374085511 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.2374085511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.4223811434 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 19493200 ps |
| CPU time | 33.43 seconds |
| Started | Sep 01 07:18:18 PM UTC 24 |
| Finished | Sep 01 07:18:52 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223811434 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.4223811434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3692421606 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 10015492300 ps |
| CPU time | 300.07 seconds |
| Started | Sep 01 07:24:09 PM UTC 24 |
| Finished | Sep 01 07:29:14 PM UTC 24 |
| Peak memory | 320468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3692421606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3692421606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.342202367 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 25350500 ps |
| CPU time | 28.5 seconds |
| Started | Sep 01 07:24:09 PM UTC 24 |
| Finished | Sep 01 07:24:39 PM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=342202367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_hw_read_seed_err.342202367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2822325754 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 40122646800 ps |
| CPU time | 919.88 seconds |
| Started | Sep 01 07:18:40 PM UTC 24 |
| Finished | Sep 01 07:34:11 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822325754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.2822325754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.2146257602 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 722786200 ps |
| CPU time | 79.7 seconds |
| Started | Sep 01 07:18:26 PM UTC 24 |
| Finished | Sep 01 07:19:48 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146257602 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.2146257602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2241411455 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3972733700 ps |
| CPU time | 475.09 seconds |
| Started | Sep 01 07:21:52 PM UTC 24 |
| Finished | Sep 01 07:29:54 PM UTC 24 |
| Peak memory | 337148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2241411455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr ity.2241411455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4242669198 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 22428582900 ps |
| CPU time | 204.5 seconds |
| Started | Sep 01 07:22:15 PM UTC 24 |
| Finished | Sep 01 07:25:43 PM UTC 24 |
| Peak memory | 303944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4242669198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.4242669198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.6841370 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4507839000 ps |
| CPU time | 98.36 seconds |
| Started | Sep 01 07:22:03 PM UTC 24 |
| Finished | Sep 01 07:23:44 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6841370 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.6841370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3924345367 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 54677324400 ps |
| CPU time | 317.45 seconds |
| Started | Sep 01 07:22:22 PM UTC 24 |
| Finished | Sep 01 07:27:44 PM UTC 24 |
| Peak memory | 271260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924345367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3924345367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3340944127 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9529610900 ps |
| CPU time | 61 seconds |
| Started | Sep 01 07:19:11 PM UTC 24 |
| Finished | Sep 01 07:20:14 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340944127 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3340944127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.4154564600 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 827299200 ps |
| CPU time | 137.96 seconds |
| Started | Sep 01 07:19:14 PM UTC 24 |
| Finished | Sep 01 07:21:35 PM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154564600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.4154564600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2492408241 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 5834520500 ps |
| CPU time | 452.02 seconds |
| Started | Sep 01 07:18:53 PM UTC 24 |
| Finished | Sep 01 07:26:32 PM UTC 24 |
| Peak memory | 283788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2492408241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2492408241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1753772207 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1320379600 ps |
| CPU time | 250.67 seconds |
| Started | Sep 01 07:21:36 PM UTC 24 |
| Finished | Sep 01 07:25:51 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1753772207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1753772207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1029453214 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 60565900 ps |
| CPU time | 26.09 seconds |
| Started | Sep 01 07:23:56 PM UTC 24 |
| Finished | Sep 01 07:24:23 PM UTC 24 |
| Peak memory | 275588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029453214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1029453214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.932787548 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1433148200 ps |
| CPU time | 270.54 seconds |
| Started | Sep 01 07:18:24 PM UTC 24 |
| Finished | Sep 01 07:22:58 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932787548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.932787548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2435722582 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 765872800 ps |
| CPU time | 34.02 seconds |
| Started | Sep 01 07:23:45 PM UTC 24 |
| Finished | Sep 01 07:24:20 PM UTC 24 |
| Peak memory | 273548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2435722582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2435722582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.1719717493 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 189250500 ps |
| CPU time | 23.55 seconds |
| Started | Sep 01 07:22:25 PM UTC 24 |
| Finished | Sep 01 07:22:50 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719717493 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.1719717493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2103855412 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 110018100 ps |
| CPU time | 872.29 seconds |
| Started | Sep 01 07:18:14 PM UTC 24 |
| Finished | Sep 01 07:32:56 PM UTC 24 |
| Peak memory | 293752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103855412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2103855412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.3408433872 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2074795800 ps |
| CPU time | 264.27 seconds |
| Started | Sep 01 07:18:24 PM UTC 24 |
| Finished | Sep 01 07:22:52 PM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408433872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3408433872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.1842904331 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 32677600 ps |
| CPU time | 37.78 seconds |
| Started | Sep 01 07:20:53 PM UTC 24 |
| Finished | Sep 01 07:21:32 PM UTC 24 |
| Peak memory | 275420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1842904331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_read_word_sweep_derr.1842904331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.1335242751 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 344440400 ps |
| CPU time | 43.36 seconds |
| Started | Sep 01 07:20:07 PM UTC 24 |
| Finished | Sep 01 07:20:52 PM UTC 24 |
| Peak memory | 275684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335242751 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.1335242751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2457465830 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6844056800 ps |
| CPU time | 149.14 seconds |
| Started | Sep 01 07:19:49 PM UTC 24 |
| Finished | Sep 01 07:22:21 PM UTC 24 |
| Peak memory | 302196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2457465830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.2457465830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.363885894 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4460011300 ps |
| CPU time | 171.45 seconds |
| Started | Sep 01 07:21:01 PM UTC 24 |
| Finished | Sep 01 07:23:55 PM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363885894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.363885894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3656557361 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1058601300 ps |
| CPU time | 126.52 seconds |
| Started | Sep 01 07:20:15 PM UTC 24 |
| Finished | Sep 01 07:22:24 PM UTC 24 |
| Peak memory | 306172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3656557361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_ro_serr.3656557361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.517435851 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3710980500 ps |
| CPU time | 580.12 seconds |
| Started | Sep 01 07:19:49 PM UTC 24 |
| Finished | Sep 01 07:29:37 PM UTC 24 |
| Peak memory | 332772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517435851 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.517435851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.1991572807 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 78250800 ps |
| CPU time | 42.85 seconds |
| Started | Sep 01 07:22:51 PM UTC 24 |
| Finished | Sep 01 07:23:35 PM UTC 24 |
| Peak memory | 287952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991572807 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.1991572807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.1905380369 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 30210700 ps |
| CPU time | 54.54 seconds |
| Started | Sep 01 07:22:51 PM UTC 24 |
| Finished | Sep 01 07:23:47 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1905380369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_rw_evict_all_en.1905380369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.3184149638 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1773873000 ps |
| CPU time | 232.16 seconds |
| Started | Sep 01 07:20:19 PM UTC 24 |
| Finished | Sep 01 07:24:15 PM UTC 24 |
| Peak memory | 291812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3184149638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.3184149638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1350794777 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2181032900 ps |
| CPU time | 7470.51 seconds |
| Started | Sep 01 07:23:01 PM UTC 24 |
| Finished | Sep 01 09:28:59 PM UTC 24 |
| Peak memory | 312368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350794777 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1350794777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.599594671 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2971365400 ps |
| CPU time | 88.72 seconds |
| Started | Sep 01 07:23:14 PM UTC 24 |
| Finished | Sep 01 07:24:45 PM UTC 24 |
| Peak memory | 273176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599594671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.599594671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1031090565 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2963383800 ps |
| CPU time | 74 seconds |
| Started | Sep 01 07:20:47 PM UTC 24 |
| Finished | Sep 01 07:22:03 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103 1090565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_address.1031090565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.2300285293 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1901499300 ps |
| CPU time | 87.58 seconds |
| Started | Sep 01 07:20:44 PM UTC 24 |
| Finished | Sep 01 07:22:14 PM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23 00285293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se rr_counter.2300285293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3943065080 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 67109500 ps |
| CPU time | 126.4 seconds |
| Started | Sep 01 07:18:09 PM UTC 24 |
| Finished | Sep 01 07:20:18 PM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943065080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3943065080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.678294957 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 55653100 ps |
| CPU time | 46.21 seconds |
| Started | Sep 01 07:18:11 PM UTC 24 |
| Finished | Sep 01 07:18:59 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678294957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.678294957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2328803368 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 276368400 ps |
| CPU time | 1295.7 seconds |
| Started | Sep 01 07:23:36 PM UTC 24 |
| Finished | Sep 01 07:45:26 PM UTC 24 |
| Peak memory | 295760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328803368 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.2328803368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.2233463230 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 46006900 ps |
| CPU time | 53.35 seconds |
| Started | Sep 01 07:18:16 PM UTC 24 |
| Finished | Sep 01 07:19:11 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233463230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2233463230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3465803660 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 5606503600 ps |
| CPU time | 264.24 seconds |
| Started | Sep 01 07:19:34 PM UTC 24 |
| Finished | Sep 01 07:24:02 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3465803660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.3465803660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.3840331774 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 262575200 ps |
| CPU time | 22.5 seconds |
| Started | Sep 01 08:16:43 PM UTC 24 |
| Finished | Sep 01 08:17:07 PM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840331774 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.3840331774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.1576180174 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 16494500 ps |
| CPU time | 23.77 seconds |
| Started | Sep 01 08:16:40 PM UTC 24 |
| Finished | Sep 01 08:17:05 PM UTC 24 |
| Peak memory | 295112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576180174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1576180174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.2778354670 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 18666000 ps |
| CPU time | 43.24 seconds |
| Started | Sep 01 08:16:28 PM UTC 24 |
| Finished | Sep 01 08:17:12 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2778354670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ ctrl_disable.2778354670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.2194097307 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2655149900 ps |
| CPU time | 258.92 seconds |
| Started | Sep 01 08:16:04 PM UTC 24 |
| Finished | Sep 01 08:20:27 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194097307 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.2194097307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.2512747556 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1078182800 ps |
| CPU time | 201.68 seconds |
| Started | Sep 01 08:16:15 PM UTC 24 |
| Finished | Sep 01 08:19:40 PM UTC 24 |
| Peak memory | 304100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512747556 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.2512747556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3116866043 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 35672314600 ps |
| CPU time | 191.06 seconds |
| Started | Sep 01 08:16:23 PM UTC 24 |
| Finished | Sep 01 08:19:37 PM UTC 24 |
| Peak memory | 304020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3116866043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.flash_ctrl_intr_rd_slow_flash.3116866043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.1829007670 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 148435600 ps |
| CPU time | 174.08 seconds |
| Started | Sep 01 08:16:07 PM UTC 24 |
| Finished | Sep 01 08:19:04 PM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829007670 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.1829007670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.14885124 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 192004400 ps |
| CPU time | 44.27 seconds |
| Started | Sep 01 08:16:23 PM UTC 24 |
| Finished | Sep 01 08:17:09 PM UTC 24 |
| Peak memory | 283820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14885124 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.14885124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.3287133243 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 285706100 ps |
| CPU time | 45.96 seconds |
| Started | Sep 01 08:16:27 PM UTC 24 |
| Finished | Sep 01 08:17:15 PM UTC 24 |
| Peak memory | 287852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3287133243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_rw_evict_all_en.3287133243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.2954631760 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2351410100 ps |
| CPU time | 90.02 seconds |
| Started | Sep 01 08:16:32 PM UTC 24 |
| Finished | Sep 01 08:18:04 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954631760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2954631760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3015410897 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 46135500 ps |
| CPU time | 136.03 seconds |
| Started | Sep 01 08:16:02 PM UTC 24 |
| Finished | Sep 01 08:18:20 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015410897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3015410897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.1221812231 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 170246300 ps |
| CPU time | 20.03 seconds |
| Started | Sep 01 08:17:08 PM UTC 24 |
| Finished | Sep 01 08:17:30 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221812231 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.1221812231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.2501869162 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 13672900 ps |
| CPU time | 16.06 seconds |
| Started | Sep 01 08:17:07 PM UTC 24 |
| Finished | Sep 01 08:17:25 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501869162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2501869162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1289821816 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 21300500 ps |
| CPU time | 29.67 seconds |
| Started | Sep 01 08:17:07 PM UTC 24 |
| Finished | Sep 01 08:17:38 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1289821816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ ctrl_disable.1289821816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.373176096 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1557579700 ps |
| CPU time | 82.01 seconds |
| Started | Sep 01 08:16:45 PM UTC 24 |
| Finished | Sep 01 08:18:09 PM UTC 24 |
| Peak memory | 273352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373176096 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.373176096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.2770502476 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1493477400 ps |
| CPU time | 158.38 seconds |
| Started | Sep 01 08:16:57 PM UTC 24 |
| Finished | Sep 01 08:19:38 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770502476 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.2770502476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3499363439 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 25457717100 ps |
| CPU time | 334.04 seconds |
| Started | Sep 01 08:17:02 PM UTC 24 |
| Finished | Sep 01 08:22:41 PM UTC 24 |
| Peak memory | 304220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3499363439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.flash_ctrl_intr_rd_slow_flash.3499363439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.150511268 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 39031500 ps |
| CPU time | 196.94 seconds |
| Started | Sep 01 08:16:51 PM UTC 24 |
| Finished | Sep 01 08:20:12 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150511268 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.150511268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.4104730914 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 216245600 ps |
| CPU time | 48.1 seconds |
| Started | Sep 01 08:17:05 PM UTC 24 |
| Finished | Sep 01 08:17:55 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104730914 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.4104730914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.2400889397 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 29611400 ps |
| CPU time | 33.96 seconds |
| Started | Sep 01 08:17:06 PM UTC 24 |
| Finished | Sep 01 08:17:42 PM UTC 24 |
| Peak memory | 287916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2400889397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_rw_evict_all_en.2400889397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.3598577897 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 503460100 ps |
| CPU time | 63.91 seconds |
| Started | Sep 01 08:17:07 PM UTC 24 |
| Finished | Sep 01 08:18:13 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598577897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3598577897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.2138221739 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 74610100 ps |
| CPU time | 221.39 seconds |
| Started | Sep 01 08:16:44 PM UTC 24 |
| Finished | Sep 01 08:20:29 PM UTC 24 |
| Peak memory | 289916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138221739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2138221739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2571480716 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 277044300 ps |
| CPU time | 22.39 seconds |
| Started | Sep 01 08:17:38 PM UTC 24 |
| Finished | Sep 01 08:18:02 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571480716 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.2571480716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1293763649 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 21374500 ps |
| CPU time | 26.26 seconds |
| Started | Sep 01 08:17:35 PM UTC 24 |
| Finished | Sep 01 08:18:02 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293763649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1293763649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.4066589076 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 12452900 ps |
| CPU time | 27.97 seconds |
| Started | Sep 01 08:17:30 PM UTC 24 |
| Finished | Sep 01 08:18:00 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4066589076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ ctrl_disable.4066589076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.3370764302 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3625642400 ps |
| CPU time | 108.98 seconds |
| Started | Sep 01 08:17:13 PM UTC 24 |
| Finished | Sep 01 08:19:04 PM UTC 24 |
| Peak memory | 273424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370764302 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.3370764302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.678326473 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 6644641600 ps |
| CPU time | 165.25 seconds |
| Started | Sep 01 08:17:16 PM UTC 24 |
| Finished | Sep 01 08:20:04 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678326473 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.678326473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.398000911 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 24692227800 ps |
| CPU time | 468.35 seconds |
| Started | Sep 01 08:17:22 PM UTC 24 |
| Finished | Sep 01 08:25:16 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=398000911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 32.flash_ctrl_intr_rd_slow_flash.398000911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2844730207 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 39081300 ps |
| CPU time | 192.54 seconds |
| Started | Sep 01 08:17:14 PM UTC 24 |
| Finished | Sep 01 08:20:29 PM UTC 24 |
| Peak memory | 275688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844730207 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.2844730207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.69455565 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 37978800 ps |
| CPU time | 44.78 seconds |
| Started | Sep 01 08:17:25 PM UTC 24 |
| Finished | Sep 01 08:18:12 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69455565 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.69455565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.3567666276 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 182184600 ps |
| CPU time | 46.06 seconds |
| Started | Sep 01 08:17:26 PM UTC 24 |
| Finished | Sep 01 08:18:14 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3567666276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_rw_evict_all_en.3567666276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.2108356638 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 6118797800 ps |
| CPU time | 106.63 seconds |
| Started | Sep 01 08:17:31 PM UTC 24 |
| Finished | Sep 01 08:19:20 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108356638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2108356638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.2416105100 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 61771500 ps |
| CPU time | 100.24 seconds |
| Started | Sep 01 08:17:09 PM UTC 24 |
| Finished | Sep 01 08:18:52 PM UTC 24 |
| Peak memory | 285556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416105100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2416105100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.2188654545 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 34808200 ps |
| CPU time | 27.65 seconds |
| Started | Sep 01 08:18:04 PM UTC 24 |
| Finished | Sep 01 08:18:33 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188654545 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.2188654545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.2191300381 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 72428500 ps |
| CPU time | 22.14 seconds |
| Started | Sep 01 08:18:03 PM UTC 24 |
| Finished | Sep 01 08:18:26 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191300381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2191300381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.1077976062 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 17511000 ps |
| CPU time | 31.51 seconds |
| Started | Sep 01 08:18:01 PM UTC 24 |
| Finished | Sep 01 08:18:34 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1077976062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ ctrl_disable.1077976062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.1634877339 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1116277200 ps |
| CPU time | 118.72 seconds |
| Started | Sep 01 08:17:42 PM UTC 24 |
| Finished | Sep 01 08:19:43 PM UTC 24 |
| Peak memory | 275224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634877339 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.1634877339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.2328203391 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1711358900 ps |
| CPU time | 256.51 seconds |
| Started | Sep 01 08:17:43 PM UTC 24 |
| Finished | Sep 01 08:22:04 PM UTC 24 |
| Peak memory | 293880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328203391 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.2328203391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1607714563 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 45656943300 ps |
| CPU time | 372.86 seconds |
| Started | Sep 01 08:17:45 PM UTC 24 |
| Finished | Sep 01 08:24:04 PM UTC 24 |
| Peak memory | 304028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1607714563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.flash_ctrl_intr_rd_slow_flash.1607714563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.3801716458 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 42121900 ps |
| CPU time | 186.89 seconds |
| Started | Sep 01 08:17:42 PM UTC 24 |
| Finished | Sep 01 08:20:53 PM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801716458 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.3801716458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.1435089499 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 38339200 ps |
| CPU time | 37.71 seconds |
| Started | Sep 01 08:17:56 PM UTC 24 |
| Finished | Sep 01 08:18:35 PM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435089499 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.1435089499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.2741269964 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 265060200 ps |
| CPU time | 53.15 seconds |
| Started | Sep 01 08:18:01 PM UTC 24 |
| Finished | Sep 01 08:18:56 PM UTC 24 |
| Peak memory | 281512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2741269964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c trl_rw_evict_all_en.2741269964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1471774385 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 9312870300 ps |
| CPU time | 91.6 seconds |
| Started | Sep 01 08:18:02 PM UTC 24 |
| Finished | Sep 01 08:19:36 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471774385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1471774385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3769253163 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 97297200 ps |
| CPU time | 178.29 seconds |
| Started | Sep 01 08:17:39 PM UTC 24 |
| Finished | Sep 01 08:20:40 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769253163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3769253163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2798346002 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 21718300 ps |
| CPU time | 26.44 seconds |
| Started | Sep 01 08:18:35 PM UTC 24 |
| Finished | Sep 01 08:19:03 PM UTC 24 |
| Peak memory | 275556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798346002 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.2798346002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.3393192119 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 16668700 ps |
| CPU time | 25.27 seconds |
| Started | Sep 01 08:18:35 PM UTC 24 |
| Finished | Sep 01 08:19:01 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393192119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3393192119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.75689525 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 13775700 ps |
| CPU time | 28.33 seconds |
| Started | Sep 01 08:18:27 PM UTC 24 |
| Finished | Sep 01 08:18:57 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=75689525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ct rl_disable.75689525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.2077296924 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5777299500 ps |
| CPU time | 75.98 seconds |
| Started | Sep 01 08:18:13 PM UTC 24 |
| Finished | Sep 01 08:19:30 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077296924 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.2077296924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.3854765382 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 839499800 ps |
| CPU time | 154.56 seconds |
| Started | Sep 01 08:18:15 PM UTC 24 |
| Finished | Sep 01 08:20:52 PM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854765382 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.3854765382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3518259874 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 49774022600 ps |
| CPU time | 140.88 seconds |
| Started | Sep 01 08:18:21 PM UTC 24 |
| Finished | Sep 01 08:20:44 PM UTC 24 |
| Peak memory | 304028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3518259874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.3518259874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.2095974435 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 62947000 ps |
| CPU time | 211.82 seconds |
| Started | Sep 01 08:18:14 PM UTC 24 |
| Finished | Sep 01 08:21:49 PM UTC 24 |
| Peak memory | 271484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095974435 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.2095974435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.1307718222 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 29093900 ps |
| CPU time | 45.21 seconds |
| Started | Sep 01 08:18:23 PM UTC 24 |
| Finished | Sep 01 08:19:10 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307718222 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.1307718222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.3279272647 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 52818300 ps |
| CPU time | 63.66 seconds |
| Started | Sep 01 08:18:27 PM UTC 24 |
| Finished | Sep 01 08:19:33 PM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3279272647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.3279272647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.2893885794 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 1582340500 ps |
| CPU time | 76.31 seconds |
| Started | Sep 01 08:18:33 PM UTC 24 |
| Finished | Sep 01 08:19:51 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893885794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.2893885794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1638542889 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 51510500 ps |
| CPU time | 225.99 seconds |
| Started | Sep 01 08:18:10 PM UTC 24 |
| Finished | Sep 01 08:22:00 PM UTC 24 |
| Peak memory | 289612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638542889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1638542889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.1670045794 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 20873200 ps |
| CPU time | 26.77 seconds |
| Started | Sep 01 08:19:03 PM UTC 24 |
| Finished | Sep 01 08:19:31 PM UTC 24 |
| Peak memory | 269300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670045794 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.1670045794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2453256813 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 26546000 ps |
| CPU time | 21.71 seconds |
| Started | Sep 01 08:19:02 PM UTC 24 |
| Finished | Sep 01 08:19:25 PM UTC 24 |
| Peak memory | 284936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453256813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2453256813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.223875947 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 12353500 ps |
| CPU time | 36.22 seconds |
| Started | Sep 01 08:18:58 PM UTC 24 |
| Finished | Sep 01 08:19:36 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=223875947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_disable.223875947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.475873106 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 4312915500 ps |
| CPU time | 193.62 seconds |
| Started | Sep 01 08:18:36 PM UTC 24 |
| Finished | Sep 01 08:21:53 PM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475873106 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.475873106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.3713827710 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3847535500 ps |
| CPU time | 236.99 seconds |
| Started | Sep 01 08:18:46 PM UTC 24 |
| Finished | Sep 01 08:22:47 PM UTC 24 |
| Peak memory | 294052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713827710 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.3713827710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3460078661 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 13486819400 ps |
| CPU time | 333.61 seconds |
| Started | Sep 01 08:18:49 PM UTC 24 |
| Finished | Sep 01 08:24:28 PM UTC 24 |
| Peak memory | 304024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3460078661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.flash_ctrl_intr_rd_slow_flash.3460078661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.1977586749 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 338047600 ps |
| CPU time | 144.18 seconds |
| Started | Sep 01 08:18:42 PM UTC 24 |
| Finished | Sep 01 08:21:09 PM UTC 24 |
| Peak memory | 271080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977586749 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.1977586749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3770546860 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 38980700 ps |
| CPU time | 37.55 seconds |
| Started | Sep 01 08:18:53 PM UTC 24 |
| Finished | Sep 01 08:19:32 PM UTC 24 |
| Peak memory | 287660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770546860 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.3770546860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3804483500 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 84826500 ps |
| CPU time | 53.92 seconds |
| Started | Sep 01 08:18:57 PM UTC 24 |
| Finished | Sep 01 08:19:52 PM UTC 24 |
| Peak memory | 281772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3804483500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_rw_evict_all_en.3804483500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.3651374125 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3122394000 ps |
| CPU time | 76.73 seconds |
| Started | Sep 01 08:18:58 PM UTC 24 |
| Finished | Sep 01 08:20:17 PM UTC 24 |
| Peak memory | 275476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651374125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3651374125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.310012169 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 87780100 ps |
| CPU time | 105.81 seconds |
| Started | Sep 01 08:18:36 PM UTC 24 |
| Finished | Sep 01 08:20:24 PM UTC 24 |
| Peak memory | 287580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310012169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.310012169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.3392563262 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 80302900 ps |
| CPU time | 26 seconds |
| Started | Sep 01 08:19:33 PM UTC 24 |
| Finished | Sep 01 08:20:00 PM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392563262 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.3392563262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.596074265 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 16059700 ps |
| CPU time | 26.47 seconds |
| Started | Sep 01 08:19:32 PM UTC 24 |
| Finished | Sep 01 08:20:00 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596074265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.596074265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.3363997871 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 19464600 ps |
| CPU time | 32.85 seconds |
| Started | Sep 01 08:19:24 PM UTC 24 |
| Finished | Sep 01 08:19:59 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3363997871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ ctrl_disable.3363997871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.2151764466 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2203228600 ps |
| CPU time | 170.78 seconds |
| Started | Sep 01 08:19:04 PM UTC 24 |
| Finished | Sep 01 08:21:58 PM UTC 24 |
| Peak memory | 273156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151764466 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.2151764466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.277519567 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2201071500 ps |
| CPU time | 195.03 seconds |
| Started | Sep 01 08:19:11 PM UTC 24 |
| Finished | Sep 01 08:22:29 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277519567 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.277519567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1747043182 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 12064213600 ps |
| CPU time | 197.22 seconds |
| Started | Sep 01 08:19:18 PM UTC 24 |
| Finished | Sep 01 08:22:38 PM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1747043182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.flash_ctrl_intr_rd_slow_flash.1747043182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.2129027394 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 74351200 ps |
| CPU time | 192.35 seconds |
| Started | Sep 01 08:19:09 PM UTC 24 |
| Finished | Sep 01 08:22:24 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129027394 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.2129027394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.2851463507 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 32562400 ps |
| CPU time | 42.05 seconds |
| Started | Sep 01 08:19:21 PM UTC 24 |
| Finished | Sep 01 08:20:04 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851463507 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.2851463507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.550657174 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 38327100 ps |
| CPU time | 40.78 seconds |
| Started | Sep 01 08:19:23 PM UTC 24 |
| Finished | Sep 01 08:20:06 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=550657174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ct rl_rw_evict_all_en.550657174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.3633572184 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1711453600 ps |
| CPU time | 88.27 seconds |
| Started | Sep 01 08:19:26 PM UTC 24 |
| Finished | Sep 01 08:20:57 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633572184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3633572184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.3573723184 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 167186600 ps |
| CPU time | 208.15 seconds |
| Started | Sep 01 08:19:04 PM UTC 24 |
| Finished | Sep 01 08:22:36 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573723184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3573723184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1319100818 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 268595900 ps |
| CPU time | 28.18 seconds |
| Started | Sep 01 08:19:52 PM UTC 24 |
| Finished | Sep 01 08:20:22 PM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319100818 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.1319100818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.2635460067 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 28787300 ps |
| CPU time | 14.96 seconds |
| Started | Sep 01 08:19:45 PM UTC 24 |
| Finished | Sep 01 08:20:01 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635460067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2635460067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.223342374 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 78619300 ps |
| CPU time | 35.79 seconds |
| Started | Sep 01 08:19:41 PM UTC 24 |
| Finished | Sep 01 08:20:19 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=223342374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c trl_disable.223342374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.2026576858 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14599009700 ps |
| CPU time | 149.76 seconds |
| Started | Sep 01 08:19:34 PM UTC 24 |
| Finished | Sep 01 08:22:06 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026576858 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.2026576858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.1173118186 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3432889100 ps |
| CPU time | 249.13 seconds |
| Started | Sep 01 08:19:37 PM UTC 24 |
| Finished | Sep 01 08:23:50 PM UTC 24 |
| Peak memory | 293852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173118186 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.1173118186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2520292873 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 47381842300 ps |
| CPU time | 358.55 seconds |
| Started | Sep 01 08:19:38 PM UTC 24 |
| Finished | Sep 01 08:25:42 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2520292873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.flash_ctrl_intr_rd_slow_flash.2520292873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.4028563225 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 39509700 ps |
| CPU time | 189 seconds |
| Started | Sep 01 08:19:37 PM UTC 24 |
| Finished | Sep 01 08:22:49 PM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028563225 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.4028563225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.2584039679 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 40291800 ps |
| CPU time | 36.67 seconds |
| Started | Sep 01 08:19:38 PM UTC 24 |
| Finished | Sep 01 08:20:16 PM UTC 24 |
| Peak memory | 281584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584039679 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.2584039679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.276691702 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 72028300 ps |
| CPU time | 44.33 seconds |
| Started | Sep 01 08:19:38 PM UTC 24 |
| Finished | Sep 01 08:20:24 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=276691702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ct rl_rw_evict_all_en.276691702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.2704835097 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 69015100 ps |
| CPU time | 221.03 seconds |
| Started | Sep 01 08:19:33 PM UTC 24 |
| Finished | Sep 01 08:23:17 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704835097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2704835097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.2983994556 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 105438100 ps |
| CPU time | 25.72 seconds |
| Started | Sep 01 08:20:17 PM UTC 24 |
| Finished | Sep 01 08:20:44 PM UTC 24 |
| Peak memory | 271352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983994556 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.2983994556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2462420350 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 31924000 ps |
| CPU time | 21.95 seconds |
| Started | Sep 01 08:20:12 PM UTC 24 |
| Finished | Sep 01 08:20:35 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462420350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2462420350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.467735733 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 28791700 ps |
| CPU time | 34.11 seconds |
| Started | Sep 01 08:20:05 PM UTC 24 |
| Finished | Sep 01 08:20:40 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=467735733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c trl_disable.467735733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3924972917 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 1275924200 ps |
| CPU time | 70.16 seconds |
| Started | Sep 01 08:19:53 PM UTC 24 |
| Finished | Sep 01 08:21:05 PM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924972917 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.3924972917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.123572868 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 5404457500 ps |
| CPU time | 180.13 seconds |
| Started | Sep 01 08:20:00 PM UTC 24 |
| Finished | Sep 01 08:23:04 PM UTC 24 |
| Peak memory | 304096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123572868 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.123572868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2551491940 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 12770771500 ps |
| CPU time | 171.25 seconds |
| Started | Sep 01 08:20:00 PM UTC 24 |
| Finished | Sep 01 08:22:55 PM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2551491940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.flash_ctrl_intr_rd_slow_flash.2551491940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.2890818473 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 37827100 ps |
| CPU time | 221.88 seconds |
| Started | Sep 01 08:19:59 PM UTC 24 |
| Finished | Sep 01 08:23:45 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890818473 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.2890818473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.1894466756 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 27892100 ps |
| CPU time | 44.16 seconds |
| Started | Sep 01 08:20:02 PM UTC 24 |
| Finished | Sep 01 08:20:47 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894466756 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.1894466756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.1227961863 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 69547700 ps |
| CPU time | 42.4 seconds |
| Started | Sep 01 08:20:05 PM UTC 24 |
| Finished | Sep 01 08:20:49 PM UTC 24 |
| Peak memory | 287952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1227961863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c trl_rw_evict_all_en.1227961863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2072793741 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9122086700 ps |
| CPU time | 105.78 seconds |
| Started | Sep 01 08:20:06 PM UTC 24 |
| Finished | Sep 01 08:21:54 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072793741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2072793741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.3409770372 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 23492100 ps |
| CPU time | 152.71 seconds |
| Started | Sep 01 08:19:53 PM UTC 24 |
| Finished | Sep 01 08:22:29 PM UTC 24 |
| Peak memory | 289648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409770372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3409770372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.853233409 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 70691700 ps |
| CPU time | 20.14 seconds |
| Started | Sep 01 08:20:38 PM UTC 24 |
| Finished | Sep 01 08:20:59 PM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853233409 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.853233409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2390710337 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 50071100 ps |
| CPU time | 23.47 seconds |
| Started | Sep 01 08:20:37 PM UTC 24 |
| Finished | Sep 01 08:21:02 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390710337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2390710337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.1880863131 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 12731800 ps |
| CPU time | 39.28 seconds |
| Started | Sep 01 08:20:29 PM UTC 24 |
| Finished | Sep 01 08:21:10 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1880863131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ ctrl_disable.1880863131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.2871538094 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 17917070500 ps |
| CPU time | 168.68 seconds |
| Started | Sep 01 08:20:20 PM UTC 24 |
| Finished | Sep 01 08:23:11 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871538094 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.2871538094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.33809301 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3813296400 ps |
| CPU time | 160.5 seconds |
| Started | Sep 01 08:20:25 PM UTC 24 |
| Finished | Sep 01 08:23:08 PM UTC 24 |
| Peak memory | 293852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33809301 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.33809301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2249846132 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 152500627700 ps |
| CPU time | 394.44 seconds |
| Started | Sep 01 08:20:25 PM UTC 24 |
| Finished | Sep 01 08:27:05 PM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2249846132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.2249846132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.2229867054 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 41277600 ps |
| CPU time | 238.29 seconds |
| Started | Sep 01 08:20:23 PM UTC 24 |
| Finished | Sep 01 08:24:25 PM UTC 24 |
| Peak memory | 271080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229867054 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.2229867054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.2688662849 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 162966100 ps |
| CPU time | 45.79 seconds |
| Started | Sep 01 08:20:28 PM UTC 24 |
| Finished | Sep 01 08:21:15 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688662849 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.2688662849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.1091791476 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 77317000 ps |
| CPU time | 38.5 seconds |
| Started | Sep 01 08:20:28 PM UTC 24 |
| Finished | Sep 01 08:21:08 PM UTC 24 |
| Peak memory | 287720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1091791476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c trl_rw_evict_all_en.1091791476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.2784736129 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5076682300 ps |
| CPU time | 70.5 seconds |
| Started | Sep 01 08:20:30 PM UTC 24 |
| Finished | Sep 01 08:21:43 PM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784736129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2784736129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.3577874019 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 32349700 ps |
| CPU time | 81.15 seconds |
| Started | Sep 01 08:20:17 PM UTC 24 |
| Finished | Sep 01 08:21:40 PM UTC 24 |
| Peak memory | 283644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577874019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3577874019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1864368579 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 596093400 ps |
| CPU time | 26.02 seconds |
| Started | Sep 01 07:29:57 PM UTC 24 |
| Finished | Sep 01 07:30:25 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864368579 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1864368579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3383956960 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 41173200 ps |
| CPU time | 23.79 seconds |
| Started | Sep 01 07:29:52 PM UTC 24 |
| Finished | Sep 01 07:30:17 PM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383956960 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.3383956960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1645141296 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 24428700 ps |
| CPU time | 19.94 seconds |
| Started | Sep 01 07:29:31 PM UTC 24 |
| Finished | Sep 01 07:29:52 PM UTC 24 |
| Peak memory | 295372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645141296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1645141296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3707855308 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4208102400 ps |
| CPU time | 219.63 seconds |
| Started | Sep 01 07:27:45 PM UTC 24 |
| Finished | Sep 01 07:31:28 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3707855308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.3707855308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.336362262 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 10546800 ps |
| CPU time | 45.37 seconds |
| Started | Sep 01 07:29:05 PM UTC 24 |
| Finished | Sep 01 07:29:52 PM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=336362262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_disable.336362262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2180254787 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 772914500 ps |
| CPU time | 545.69 seconds |
| Started | Sep 01 07:24:41 PM UTC 24 |
| Finished | Sep 01 07:33:55 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180254787 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2180254787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.968230274 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 7324073600 ps |
| CPU time | 3294.02 seconds |
| Started | Sep 01 07:25:52 PM UTC 24 |
| Finished | Sep 01 08:21:24 PM UTC 24 |
| Peak memory | 278096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968230274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.968230274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.880768031 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1522410500 ps |
| CPU time | 1426.42 seconds |
| Started | Sep 01 07:25:51 PM UTC 24 |
| Finished | Sep 01 07:49:53 PM UTC 24 |
| Peak memory | 285712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880768031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.880768031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1730844654 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 444314000 ps |
| CPU time | 44.94 seconds |
| Started | Sep 01 07:24:57 PM UTC 24 |
| Finished | Sep 01 07:25:43 PM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 30844654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.1730844654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.2153586955 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 628489600 ps |
| CPU time | 42.95 seconds |
| Started | Sep 01 07:29:36 PM UTC 24 |
| Finished | Sep 01 07:30:21 PM UTC 24 |
| Peak memory | 273300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153586 955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f s_sup.2153586955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.77884949 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 179892057000 ps |
| CPU time | 2873.08 seconds |
| Started | Sep 01 07:25:20 PM UTC 24 |
| Finished | Sep 01 08:13:52 PM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77884949 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.77884949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1217444812 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 32137200 ps |
| CPU time | 82.51 seconds |
| Started | Sep 01 07:24:24 PM UTC 24 |
| Finished | Sep 01 07:25:48 PM UTC 24 |
| Peak memory | 273268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217444812 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1217444812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3626711165 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 10031521700 ps |
| CPU time | 60.73 seconds |
| Started | Sep 01 07:29:54 PM UTC 24 |
| Finished | Sep 01 07:30:57 PM UTC 24 |
| Peak memory | 279684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3626711165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3626711165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2286015611 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 46692000 ps |
| CPU time | 26.23 seconds |
| Started | Sep 01 07:29:53 PM UTC 24 |
| Finished | Sep 01 07:30:21 PM UTC 24 |
| Peak memory | 269424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2286015611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2286015611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.2793568477 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 50126396900 ps |
| CPU time | 893.96 seconds |
| Started | Sep 01 07:24:46 PM UTC 24 |
| Finished | Sep 01 07:39:52 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793568477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.2793568477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.692503565 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 725120100 ps |
| CPU time | 77.26 seconds |
| Started | Sep 01 07:24:40 PM UTC 24 |
| Finished | Sep 01 07:25:59 PM UTC 24 |
| Peak memory | 273420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692503565 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.692503565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.120565752 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 15003105500 ps |
| CPU time | 544.98 seconds |
| Started | Sep 01 07:27:55 PM UTC 24 |
| Finished | Sep 01 07:37:08 PM UTC 24 |
| Peak memory | 328696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=120565752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integrity.120565752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1813753271 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2443385000 ps |
| CPU time | 167.83 seconds |
| Started | Sep 01 07:28:01 PM UTC 24 |
| Finished | Sep 01 07:30:53 PM UTC 24 |
| Peak memory | 306140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813753271 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.1813753271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.469944165 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 11623067000 ps |
| CPU time | 214.71 seconds |
| Started | Sep 01 07:28:17 PM UTC 24 |
| Finished | Sep 01 07:31:56 PM UTC 24 |
| Peak memory | 304024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=469944165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_rd_slow_flash.469944165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.2702289557 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 8604594400 ps |
| CPU time | 78.5 seconds |
| Started | Sep 01 07:28:03 PM UTC 24 |
| Finished | Sep 01 07:29:24 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702289557 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.2702289557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2009051231 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 21611674000 ps |
| CPU time | 216.38 seconds |
| Started | Sep 01 07:28:27 PM UTC 24 |
| Finished | Sep 01 07:32:06 PM UTC 24 |
| Peak memory | 271268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009051231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2009051231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.2948557710 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 992260300 ps |
| CPU time | 101.92 seconds |
| Started | Sep 01 07:25:52 PM UTC 24 |
| Finished | Sep 01 07:27:36 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948557710 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2948557710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.906361904 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 15259000 ps |
| CPU time | 24.65 seconds |
| Started | Sep 01 07:29:52 PM UTC 24 |
| Finished | Sep 01 07:30:18 PM UTC 24 |
| Peak memory | 271540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=906361904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_lcmgr_intg.906361904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.2102646846 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3592520900 ps |
| CPU time | 119.75 seconds |
| Started | Sep 01 07:25:52 PM UTC 24 |
| Finished | Sep 01 07:27:54 PM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102646846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2102646846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4263071899 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 7489539700 ps |
| CPU time | 129.26 seconds |
| Started | Sep 01 07:24:55 PM UTC 24 |
| Finished | Sep 01 07:27:07 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4263071899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.4263071899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.2986933291 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 139202000 ps |
| CPU time | 190.12 seconds |
| Started | Sep 01 07:24:47 PM UTC 24 |
| Finished | Sep 01 07:28:01 PM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986933291 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.2986933291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2734296337 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5641694900 ps |
| CPU time | 196.89 seconds |
| Started | Sep 01 07:27:48 PM UTC 24 |
| Finished | Sep 01 07:31:08 PM UTC 24 |
| Peak memory | 291804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2734296337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2734296337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.918728744 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 16473200 ps |
| CPU time | 25.76 seconds |
| Started | Sep 01 07:29:48 PM UTC 24 |
| Finished | Sep 01 07:30:15 PM UTC 24 |
| Peak memory | 293232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918728744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.918728744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1649482318 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 112233900 ps |
| CPU time | 441.22 seconds |
| Started | Sep 01 07:24:30 PM UTC 24 |
| Finished | Sep 01 07:31:58 PM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649482318 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1649482318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2680910801 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 919172300 ps |
| CPU time | 27.44 seconds |
| Started | Sep 01 07:29:38 PM UTC 24 |
| Finished | Sep 01 07:30:07 PM UTC 24 |
| Peak memory | 275492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2680910801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2680910801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.102934237 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 15851200 ps |
| CPU time | 19.15 seconds |
| Started | Sep 01 07:29:47 PM UTC 24 |
| Finished | Sep 01 07:30:07 PM UTC 24 |
| Peak memory | 275616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=102934237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.102934237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1163572717 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 32147400 ps |
| CPU time | 29.71 seconds |
| Started | Sep 01 07:28:33 PM UTC 24 |
| Finished | Sep 01 07:29:04 PM UTC 24 |
| Peak memory | 271240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163572717 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.1163572717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.346341287 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 517787200 ps |
| CPU time | 1452.7 seconds |
| Started | Sep 01 07:24:22 PM UTC 24 |
| Finished | Sep 01 07:48:49 PM UTC 24 |
| Peak memory | 298100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346341287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.346341287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3169203812 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 84835400 ps |
| CPU time | 131.34 seconds |
| Started | Sep 01 07:24:25 PM UTC 24 |
| Finished | Sep 01 07:26:39 PM UTC 24 |
| Peak memory | 273268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169203812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3169203812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.602941097 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 149108100 ps |
| CPU time | 57.24 seconds |
| Started | Sep 01 07:28:48 PM UTC 24 |
| Finished | Sep 01 07:29:47 PM UTC 24 |
| Peak memory | 289708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602941097 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.602941097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2175815625 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 31148200 ps |
| CPU time | 42.6 seconds |
| Started | Sep 01 07:27:18 PM UTC 24 |
| Finished | Sep 01 07:28:02 PM UTC 24 |
| Peak memory | 275424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2175815625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_read_word_sweep_derr.2175815625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1464011766 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 46282900 ps |
| CPU time | 39.23 seconds |
| Started | Sep 01 07:26:37 PM UTC 24 |
| Finished | Sep 01 07:27:18 PM UTC 24 |
| Peak memory | 275616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464011766 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.1464011766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1670813825 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 724542500 ps |
| CPU time | 140.93 seconds |
| Started | Sep 01 07:26:02 PM UTC 24 |
| Finished | Sep 01 07:28:26 PM UTC 24 |
| Peak memory | 308140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1670813825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.1670813825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.2225741909 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 817255200 ps |
| CPU time | 179.68 seconds |
| Started | Sep 01 07:27:22 PM UTC 24 |
| Finished | Sep 01 07:30:24 PM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225741909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2225741909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1316861478 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 629739800 ps |
| CPU time | 183.4 seconds |
| Started | Sep 01 07:26:39 PM UTC 24 |
| Finished | Sep 01 07:29:46 PM UTC 24 |
| Peak memory | 306172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1316861478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_ro_serr.1316861478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3843742084 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 13880938700 ps |
| CPU time | 507.64 seconds |
| Started | Sep 01 07:26:33 PM UTC 24 |
| Finished | Sep 01 07:35:08 PM UTC 24 |
| Peak memory | 320500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843742084 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.3843742084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.967244267 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5377280300 ps |
| CPU time | 224.25 seconds |
| Started | Sep 01 07:27:37 PM UTC 24 |
| Finished | Sep 01 07:31:25 PM UTC 24 |
| Peak memory | 295936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=967244267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_rw_derr.967244267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.2555777081 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 82042100 ps |
| CPU time | 53.63 seconds |
| Started | Sep 01 07:28:35 PM UTC 24 |
| Finished | Sep 01 07:29:30 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555777081 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.2555777081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.3598046031 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 30105900 ps |
| CPU time | 49.66 seconds |
| Started | Sep 01 07:28:44 PM UTC 24 |
| Finished | Sep 01 07:29:35 PM UTC 24 |
| Peak memory | 281772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3598046031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_rw_evict_all_en.3598046031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.4005450590 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1143024800 ps |
| CPU time | 218.88 seconds |
| Started | Sep 01 07:26:51 PM UTC 24 |
| Finished | Sep 01 07:30:33 PM UTC 24 |
| Peak memory | 304100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4005450590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.4005450590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2822031000 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16130794900 ps |
| CPU time | 6848.1 seconds |
| Started | Sep 01 07:29:11 PM UTC 24 |
| Finished | Sep 01 09:24:35 PM UTC 24 |
| Peak memory | 314524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822031000 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2822031000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2962585948 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2362732500 ps |
| CPU time | 66.57 seconds |
| Started | Sep 01 07:27:08 PM UTC 24 |
| Finished | Sep 01 07:28:17 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296 2585948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.2962585948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.2430448321 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1421447700 ps |
| CPU time | 102.93 seconds |
| Started | Sep 01 07:26:58 PM UTC 24 |
| Finished | Sep 01 07:28:43 PM UTC 24 |
| Peak memory | 275616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 30448321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se rr_counter.2430448321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1587401421 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 30895600 ps |
| CPU time | 151.35 seconds |
| Started | Sep 01 07:24:15 PM UTC 24 |
| Finished | Sep 01 07:26:49 PM UTC 24 |
| Peak memory | 277556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587401421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1587401421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2925998161 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 16812400 ps |
| CPU time | 31.23 seconds |
| Started | Sep 01 07:24:22 PM UTC 24 |
| Finished | Sep 01 07:24:54 PM UTC 24 |
| Peak memory | 271236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925998161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2925998161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1046762980 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 370955300 ps |
| CPU time | 545.72 seconds |
| Started | Sep 01 07:29:24 PM UTC 24 |
| Finished | Sep 01 07:38:37 PM UTC 24 |
| Peak memory | 289808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046762980 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.1046762980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1515820544 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 38249000 ps |
| CPU time | 30.61 seconds |
| Started | Sep 01 07:24:24 PM UTC 24 |
| Finished | Sep 01 07:24:56 PM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515820544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1515820544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1729693458 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3590603400 ps |
| CPU time | 186.98 seconds |
| Started | Sep 01 07:26:00 PM UTC 24 |
| Finished | Sep 01 07:29:11 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1729693458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.1729693458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.3424186887 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 493635400 ps |
| CPU time | 25.09 seconds |
| Started | Sep 01 08:20:51 PM UTC 24 |
| Finished | Sep 01 08:21:18 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424186887 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.3424186887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.719268516 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 79332800 ps |
| CPU time | 20.5 seconds |
| Started | Sep 01 08:20:49 PM UTC 24 |
| Finished | Sep 01 08:21:11 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719268516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.719268516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.1553022404 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 10939400 ps |
| CPU time | 33.78 seconds |
| Started | Sep 01 08:20:45 PM UTC 24 |
| Finished | Sep 01 08:21:20 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1553022404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ ctrl_disable.1553022404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.149865954 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 10424233500 ps |
| CPU time | 97.9 seconds |
| Started | Sep 01 08:20:42 PM UTC 24 |
| Finished | Sep 01 08:22:22 PM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149865954 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.149865954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.4170488377 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 40189600 ps |
| CPU time | 203.84 seconds |
| Started | Sep 01 08:20:45 PM UTC 24 |
| Finished | Sep 01 08:24:12 PM UTC 24 |
| Peak memory | 271584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170488377 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.4170488377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.4172249893 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 4030698500 ps |
| CPU time | 74.63 seconds |
| Started | Sep 01 08:20:48 PM UTC 24 |
| Finished | Sep 01 08:22:05 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172249893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.4172249893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.247752253 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 328282500 ps |
| CPU time | 163.68 seconds |
| Started | Sep 01 08:20:42 PM UTC 24 |
| Finished | Sep 01 08:23:29 PM UTC 24 |
| Peak memory | 287616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247752253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.247752253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.1875011364 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 22109700 ps |
| CPU time | 26.3 seconds |
| Started | Sep 01 08:21:06 PM UTC 24 |
| Finished | Sep 01 08:21:34 PM UTC 24 |
| Peak memory | 275620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875011364 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.1875011364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.2915590034 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 16185400 ps |
| CPU time | 24.36 seconds |
| Started | Sep 01 08:21:04 PM UTC 24 |
| Finished | Sep 01 08:21:30 PM UTC 24 |
| Peak memory | 284940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915590034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2915590034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.1230037466 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 22228400 ps |
| CPU time | 40.64 seconds |
| Started | Sep 01 08:21:00 PM UTC 24 |
| Finished | Sep 01 08:21:42 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1230037466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ ctrl_disable.1230037466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.121739815 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7745060900 ps |
| CPU time | 135.03 seconds |
| Started | Sep 01 08:20:54 PM UTC 24 |
| Finished | Sep 01 08:23:12 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121739815 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.121739815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.2188442670 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 38484400 ps |
| CPU time | 159.17 seconds |
| Started | Sep 01 08:20:58 PM UTC 24 |
| Finished | Sep 01 08:23:40 PM UTC 24 |
| Peak memory | 271292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188442670 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.2188442670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.2106197336 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 24840848200 ps |
| CPU time | 112.99 seconds |
| Started | Sep 01 08:21:03 PM UTC 24 |
| Finished | Sep 01 08:22:59 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106197336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2106197336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2282742651 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 61513300 ps |
| CPU time | 180.74 seconds |
| Started | Sep 01 08:20:54 PM UTC 24 |
| Finished | Sep 01 08:23:58 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282742651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2282742651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.107740021 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 19105900 ps |
| CPU time | 24.15 seconds |
| Started | Sep 01 08:21:19 PM UTC 24 |
| Finished | Sep 01 08:21:45 PM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107740021 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.107740021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.1287410489 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 53857900 ps |
| CPU time | 27.88 seconds |
| Started | Sep 01 08:21:16 PM UTC 24 |
| Finished | Sep 01 08:21:45 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287410489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1287410489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.1338614090 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 37834400 ps |
| CPU time | 26.77 seconds |
| Started | Sep 01 08:21:12 PM UTC 24 |
| Finished | Sep 01 08:21:40 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1338614090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ ctrl_disable.1338614090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.193357985 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3255297500 ps |
| CPU time | 127.17 seconds |
| Started | Sep 01 08:21:10 PM UTC 24 |
| Finished | Sep 01 08:23:19 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193357985 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.193357985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.859119258 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 652429600 ps |
| CPU time | 202.46 seconds |
| Started | Sep 01 08:21:11 PM UTC 24 |
| Finished | Sep 01 08:24:36 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859119258 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.859119258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.3549390427 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4920517000 ps |
| CPU time | 103.75 seconds |
| Started | Sep 01 08:21:12 PM UTC 24 |
| Finished | Sep 01 08:22:58 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549390427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3549390427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.1144631114 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 25450800 ps |
| CPU time | 89.32 seconds |
| Started | Sep 01 08:21:09 PM UTC 24 |
| Finished | Sep 01 08:22:40 PM UTC 24 |
| Peak memory | 285552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144631114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1144631114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.3288999528 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 28769700 ps |
| CPU time | 22.28 seconds |
| Started | Sep 01 08:21:41 PM UTC 24 |
| Finished | Sep 01 08:22:05 PM UTC 24 |
| Peak memory | 275424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288999528 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.3288999528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3306374503 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 16013600 ps |
| CPU time | 24.48 seconds |
| Started | Sep 01 08:21:41 PM UTC 24 |
| Finished | Sep 01 08:22:07 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306374503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3306374503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.2431917985 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 42647800 ps |
| CPU time | 29.86 seconds |
| Started | Sep 01 08:21:31 PM UTC 24 |
| Finished | Sep 01 08:22:02 PM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2431917985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ ctrl_disable.2431917985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.492282634 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 4170637000 ps |
| CPU time | 48.26 seconds |
| Started | Sep 01 08:21:22 PM UTC 24 |
| Finished | Sep 01 08:22:12 PM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492282634 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.492282634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1642438329 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 153667100 ps |
| CPU time | 162.39 seconds |
| Started | Sep 01 08:21:25 PM UTC 24 |
| Finished | Sep 01 08:24:10 PM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642438329 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.1642438329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.660011119 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 1512695200 ps |
| CPU time | 94.47 seconds |
| Started | Sep 01 08:21:35 PM UTC 24 |
| Finished | Sep 01 08:23:12 PM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660011119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.660011119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3112500332 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 99781200 ps |
| CPU time | 216.84 seconds |
| Started | Sep 01 08:21:21 PM UTC 24 |
| Finished | Sep 01 08:25:01 PM UTC 24 |
| Peak memory | 277372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112500332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3112500332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.4064108418 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 100531200 ps |
| CPU time | 27.61 seconds |
| Started | Sep 01 08:21:54 PM UTC 24 |
| Finished | Sep 01 08:22:23 PM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064108418 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.4064108418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.265192601 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 49097200 ps |
| CPU time | 24.04 seconds |
| Started | Sep 01 08:21:50 PM UTC 24 |
| Finished | Sep 01 08:22:16 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265192601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.265192601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.879307306 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 24374300 ps |
| CPU time | 30.92 seconds |
| Started | Sep 01 08:21:46 PM UTC 24 |
| Finished | Sep 01 08:22:18 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=879307306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_c trl_disable.879307306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.666854121 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 7883388000 ps |
| CPU time | 88.61 seconds |
| Started | Sep 01 08:21:44 PM UTC 24 |
| Finished | Sep 01 08:23:14 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666854121 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.666854121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.3635423428 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 38821300 ps |
| CPU time | 190.3 seconds |
| Started | Sep 01 08:21:45 PM UTC 24 |
| Finished | Sep 01 08:24:58 PM UTC 24 |
| Peak memory | 271676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635423428 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.3635423428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.711150902 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 1544993700 ps |
| CPU time | 59.11 seconds |
| Started | Sep 01 08:21:46 PM UTC 24 |
| Finished | Sep 01 08:22:47 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711150902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.711150902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.529648249 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 210179100 ps |
| CPU time | 163.64 seconds |
| Started | Sep 01 08:21:43 PM UTC 24 |
| Finished | Sep 01 08:24:29 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529648249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.529648249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.4092152299 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 38836100 ps |
| CPU time | 19.22 seconds |
| Started | Sep 01 08:22:06 PM UTC 24 |
| Finished | Sep 01 08:22:27 PM UTC 24 |
| Peak memory | 269276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092152299 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.4092152299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.1740826050 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 67849800 ps |
| CPU time | 29.95 seconds |
| Started | Sep 01 08:22:06 PM UTC 24 |
| Finished | Sep 01 08:22:38 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740826050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1740826050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.3027226390 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 28790300 ps |
| CPU time | 27.42 seconds |
| Started | Sep 01 08:22:03 PM UTC 24 |
| Finished | Sep 01 08:22:32 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3027226390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ ctrl_disable.3027226390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.1859166514 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 1858744100 ps |
| CPU time | 62.38 seconds |
| Started | Sep 01 08:21:59 PM UTC 24 |
| Finished | Sep 01 08:23:03 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859166514 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.1859166514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2750682831 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 81621200 ps |
| CPU time | 177.08 seconds |
| Started | Sep 01 08:22:01 PM UTC 24 |
| Finished | Sep 01 08:25:01 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750682831 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.2750682831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.2704775986 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1352115200 ps |
| CPU time | 66.28 seconds |
| Started | Sep 01 08:22:05 PM UTC 24 |
| Finished | Sep 01 08:23:13 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704775986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2704775986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1624336549 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 38152400 ps |
| CPU time | 60.32 seconds |
| Started | Sep 01 08:21:54 PM UTC 24 |
| Finished | Sep 01 08:22:56 PM UTC 24 |
| Peak memory | 283516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624336549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1624336549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.2505420310 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 44649400 ps |
| CPU time | 19.75 seconds |
| Started | Sep 01 08:22:23 PM UTC 24 |
| Finished | Sep 01 08:22:45 PM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505420310 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.2505420310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.2352722171 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 41824600 ps |
| CPU time | 26.32 seconds |
| Started | Sep 01 08:22:19 PM UTC 24 |
| Finished | Sep 01 08:22:47 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352722171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2352722171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.2975765497 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 15176400 ps |
| CPU time | 44.79 seconds |
| Started | Sep 01 08:22:13 PM UTC 24 |
| Finished | Sep 01 08:23:00 PM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2975765497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ ctrl_disable.2975765497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3039113186 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2503820500 ps |
| CPU time | 121.35 seconds |
| Started | Sep 01 08:22:09 PM UTC 24 |
| Finished | Sep 01 08:24:13 PM UTC 24 |
| Peak memory | 274684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039113186 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.3039113186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2688107968 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 136854500 ps |
| CPU time | 202.74 seconds |
| Started | Sep 01 08:22:09 PM UTC 24 |
| Finished | Sep 01 08:25:35 PM UTC 24 |
| Peak memory | 274944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688107968 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.2688107968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3254953831 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3943431400 ps |
| CPU time | 110.27 seconds |
| Started | Sep 01 08:22:17 PM UTC 24 |
| Finished | Sep 01 08:24:10 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254953831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3254953831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.3811962251 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 42516800 ps |
| CPU time | 208.68 seconds |
| Started | Sep 01 08:22:07 PM UTC 24 |
| Finished | Sep 01 08:25:39 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811962251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3811962251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.1003969964 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 47164500 ps |
| CPU time | 19.88 seconds |
| Started | Sep 01 08:22:32 PM UTC 24 |
| Finished | Sep 01 08:22:54 PM UTC 24 |
| Peak memory | 269280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003969964 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.1003969964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.3814975581 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 22961300 ps |
| CPU time | 27.25 seconds |
| Started | Sep 01 08:22:30 PM UTC 24 |
| Finished | Sep 01 08:22:59 PM UTC 24 |
| Peak memory | 295112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814975581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3814975581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.414533994 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 16859700 ps |
| CPU time | 38.5 seconds |
| Started | Sep 01 08:22:29 PM UTC 24 |
| Finished | Sep 01 08:23:09 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=414533994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_c trl_disable.414533994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.2510588666 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2521483100 ps |
| CPU time | 86.19 seconds |
| Started | Sep 01 08:22:25 PM UTC 24 |
| Finished | Sep 01 08:23:53 PM UTC 24 |
| Peak memory | 273112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510588666 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.2510588666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.1714420382 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 190708100 ps |
| CPU time | 180.47 seconds |
| Started | Sep 01 08:22:28 PM UTC 24 |
| Finished | Sep 01 08:25:31 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714420382 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.1714420382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2932203191 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 371907700 ps |
| CPU time | 54.75 seconds |
| Started | Sep 01 08:22:30 PM UTC 24 |
| Finished | Sep 01 08:23:27 PM UTC 24 |
| Peak memory | 275220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932203191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2932203191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1923364430 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 25324100 ps |
| CPU time | 147.9 seconds |
| Started | Sep 01 08:22:24 PM UTC 24 |
| Finished | Sep 01 08:24:55 PM UTC 24 |
| Peak memory | 289836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923364430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.1923364430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1126637087 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 42128800 ps |
| CPU time | 25.19 seconds |
| Started | Sep 01 08:22:48 PM UTC 24 |
| Finished | Sep 01 08:23:14 PM UTC 24 |
| Peak memory | 275576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126637087 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1126637087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.1906050949 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 50373100 ps |
| CPU time | 24.41 seconds |
| Started | Sep 01 08:22:46 PM UTC 24 |
| Finished | Sep 01 08:23:11 PM UTC 24 |
| Peak memory | 295248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906050949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1906050949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.1097187641 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 35568200 ps |
| CPU time | 35.48 seconds |
| Started | Sep 01 08:22:40 PM UTC 24 |
| Finished | Sep 01 08:23:17 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1097187641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.1097187641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.966944943 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 27311048800 ps |
| CPU time | 102.57 seconds |
| Started | Sep 01 08:22:38 PM UTC 24 |
| Finished | Sep 01 08:24:23 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966944943 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.966944943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3320821631 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 39724400 ps |
| CPU time | 167.52 seconds |
| Started | Sep 01 08:22:39 PM UTC 24 |
| Finished | Sep 01 08:25:30 PM UTC 24 |
| Peak memory | 271536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320821631 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.3320821631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.137481335 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 2646873200 ps |
| CPU time | 66.44 seconds |
| Started | Sep 01 08:22:42 PM UTC 24 |
| Finished | Sep 01 08:23:50 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137481335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.137481335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3719274906 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 62816500 ps |
| CPU time | 223.26 seconds |
| Started | Sep 01 08:22:37 PM UTC 24 |
| Finished | Sep 01 08:26:24 PM UTC 24 |
| Peak memory | 289648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719274906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3719274906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.2297929230 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 677292800 ps |
| CPU time | 19.48 seconds |
| Started | Sep 01 08:22:59 PM UTC 24 |
| Finished | Sep 01 08:23:19 PM UTC 24 |
| Peak memory | 269284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297929230 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.2297929230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.2110833208 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 106172800 ps |
| CPU time | 23.16 seconds |
| Started | Sep 01 08:22:57 PM UTC 24 |
| Finished | Sep 01 08:23:22 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110833208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2110833208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.3387775604 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 11484400 ps |
| CPU time | 32.21 seconds |
| Started | Sep 01 08:22:54 PM UTC 24 |
| Finished | Sep 01 08:23:28 PM UTC 24 |
| Peak memory | 285956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3387775604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ ctrl_disable.3387775604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.3855845023 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 1495071500 ps |
| CPU time | 114.51 seconds |
| Started | Sep 01 08:22:48 PM UTC 24 |
| Finished | Sep 01 08:24:45 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855845023 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.3855845023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1665279096 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 71771400 ps |
| CPU time | 162.76 seconds |
| Started | Sep 01 08:22:50 PM UTC 24 |
| Finished | Sep 01 08:25:36 PM UTC 24 |
| Peak memory | 271672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665279096 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.1665279096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.976648497 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 1531327100 ps |
| CPU time | 76.71 seconds |
| Started | Sep 01 08:22:55 PM UTC 24 |
| Finished | Sep 01 08:24:14 PM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976648497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.976648497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2443576948 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 30870700 ps |
| CPU time | 228.77 seconds |
| Started | Sep 01 08:22:48 PM UTC 24 |
| Finished | Sep 01 08:26:40 PM UTC 24 |
| Peak memory | 291656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443576948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2443576948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2719112182 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 244402700 ps |
| CPU time | 17.31 seconds |
| Started | Sep 01 07:33:06 PM UTC 24 |
| Finished | Sep 01 07:33:25 PM UTC 24 |
| Peak memory | 269476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719112182 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2719112182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.3863769078 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 14588500 ps |
| CPU time | 30.56 seconds |
| Started | Sep 01 07:32:54 PM UTC 24 |
| Finished | Sep 01 07:33:26 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863769078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3863769078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1513381598 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 13350800 ps |
| CPU time | 38.11 seconds |
| Started | Sep 01 07:32:19 PM UTC 24 |
| Finished | Sep 01 07:32:59 PM UTC 24 |
| Peak memory | 285856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1513381598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c trl_disable.1513381598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.670141442 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 10329956400 ps |
| CPU time | 3381.43 seconds |
| Started | Sep 01 07:30:25 PM UTC 24 |
| Finished | Sep 01 08:27:26 PM UTC 24 |
| Peak memory | 278040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670141442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.670141442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.4121142170 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1519408200 ps |
| CPU time | 1229.2 seconds |
| Started | Sep 01 07:30:21 PM UTC 24 |
| Finished | Sep 01 07:51:04 PM UTC 24 |
| Peak memory | 285720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121142170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.4121142170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.597175622 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 432702000 ps |
| CPU time | 29.44 seconds |
| Started | Sep 01 07:30:21 PM UTC 24 |
| Finished | Sep 01 07:30:52 PM UTC 24 |
| Peak memory | 273276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59 7175622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch _code.597175622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3669906702 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 10042511800 ps |
| CPU time | 81.85 seconds |
| Started | Sep 01 07:33:00 PM UTC 24 |
| Finished | Sep 01 07:34:24 PM UTC 24 |
| Peak memory | 283848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3669906702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3669906702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3632563532 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 120495200 ps |
| CPU time | 23.57 seconds |
| Started | Sep 01 07:32:58 PM UTC 24 |
| Finished | Sep 01 07:33:23 PM UTC 24 |
| Peak memory | 269424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3632563532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3632563532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.108723417 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 100145119800 ps |
| CPU time | 887.87 seconds |
| Started | Sep 01 07:30:17 PM UTC 24 |
| Finished | Sep 01 07:45:16 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108723417 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.108723417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2900913831 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3897726200 ps |
| CPU time | 154.37 seconds |
| Started | Sep 01 07:30:16 PM UTC 24 |
| Finished | Sep 01 07:32:53 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900913831 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.2900913831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3950138395 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 11792849100 ps |
| CPU time | 228.51 seconds |
| Started | Sep 01 07:31:46 PM UTC 24 |
| Finished | Sep 01 07:35:38 PM UTC 24 |
| Peak memory | 304024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3950138395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_intr_rd_slow_flash.3950138395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1521198499 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2585960400 ps |
| CPU time | 93.95 seconds |
| Started | Sep 01 07:31:28 PM UTC 24 |
| Finished | Sep 01 07:33:05 PM UTC 24 |
| Peak memory | 273280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521198499 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.1521198499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4088681126 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 46989347900 ps |
| CPU time | 370.38 seconds |
| Started | Sep 01 07:31:57 PM UTC 24 |
| Finished | Sep 01 07:38:13 PM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088681126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.4088681126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2861104675 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4049413400 ps |
| CPU time | 88.22 seconds |
| Started | Sep 01 07:30:25 PM UTC 24 |
| Finished | Sep 01 07:31:56 PM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861104675 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2861104675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.2230109231 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 46593700 ps |
| CPU time | 24.66 seconds |
| Started | Sep 01 07:32:57 PM UTC 24 |
| Finished | Sep 01 07:33:23 PM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2230109231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.2230109231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1695489517 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 30304258800 ps |
| CPU time | 680.13 seconds |
| Started | Sep 01 07:30:19 PM UTC 24 |
| Finished | Sep 01 07:41:48 PM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1695489517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.1695489517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1007684479 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 37673100 ps |
| CPU time | 128.4 seconds |
| Started | Sep 01 07:30:18 PM UTC 24 |
| Finished | Sep 01 07:32:29 PM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007684479 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.1007684479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.727198808 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2843638100 ps |
| CPU time | 243.91 seconds |
| Started | Sep 01 07:30:08 PM UTC 24 |
| Finished | Sep 01 07:34:15 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727198808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.727198808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.2235105671 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 11849219900 ps |
| CPU time | 237.99 seconds |
| Started | Sep 01 07:31:57 PM UTC 24 |
| Finished | Sep 01 07:35:59 PM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235105671 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.2235105671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2506256019 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 557707400 ps |
| CPU time | 1881.14 seconds |
| Started | Sep 01 07:30:08 PM UTC 24 |
| Finished | Sep 01 08:01:49 PM UTC 24 |
| Peak memory | 298056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506256019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2506256019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.592060305 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 111248400 ps |
| CPU time | 63.94 seconds |
| Started | Sep 01 07:32:11 PM UTC 24 |
| Finished | Sep 01 07:33:17 PM UTC 24 |
| Peak memory | 287916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592060305 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.592060305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.2339740685 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 538705200 ps |
| CPU time | 102.56 seconds |
| Started | Sep 01 07:30:34 PM UTC 24 |
| Finished | Sep 01 07:32:18 PM UTC 24 |
| Peak memory | 302040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2339740685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.2339740685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.1826244937 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 619205700 ps |
| CPU time | 118.78 seconds |
| Started | Sep 01 07:31:09 PM UTC 24 |
| Finished | Sep 01 07:33:11 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826244937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1826244937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.342279868 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 770639900 ps |
| CPU time | 143.52 seconds |
| Started | Sep 01 07:30:54 PM UTC 24 |
| Finished | Sep 01 07:33:20 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=342279868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ ctrl_ro_serr.342279868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3445695434 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 9318869000 ps |
| CPU time | 215.48 seconds |
| Started | Sep 01 07:31:18 PM UTC 24 |
| Finished | Sep 01 07:34:57 PM UTC 24 |
| Peak memory | 300028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3445695434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.flash_ctrl_rw_derr.3445695434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3715216842 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 66694300 ps |
| CPU time | 61.08 seconds |
| Started | Sep 01 07:32:07 PM UTC 24 |
| Finished | Sep 01 07:33:10 PM UTC 24 |
| Peak memory | 288012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3715216842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct rl_rw_evict_all_en.3715216842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.1047046990 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2014614100 ps |
| CPU time | 237.71 seconds |
| Started | Sep 01 07:30:58 PM UTC 24 |
| Finished | Sep 01 07:34:59 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1047046990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.1047046990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.230931277 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 27177800 ps |
| CPU time | 71.09 seconds |
| Started | Sep 01 07:30:05 PM UTC 24 |
| Finished | Sep 01 07:31:17 PM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230931277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.230931277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.3506884334 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1987848600 ps |
| CPU time | 202.29 seconds |
| Started | Sep 01 07:30:29 PM UTC 24 |
| Finished | Sep 01 07:33:55 PM UTC 24 |
| Peak memory | 275536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3506884334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.3506884334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.3691676644 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 42861200 ps |
| CPU time | 31.81 seconds |
| Started | Sep 01 08:23:00 PM UTC 24 |
| Finished | Sep 01 08:23:33 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691676644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3691676644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3566167072 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 41509800 ps |
| CPU time | 190.98 seconds |
| Started | Sep 01 08:23:00 PM UTC 24 |
| Finished | Sep 01 08:26:14 PM UTC 24 |
| Peak memory | 275544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566167072 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.3566167072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.339022287 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 24509400 ps |
| CPU time | 23.47 seconds |
| Started | Sep 01 08:23:04 PM UTC 24 |
| Finished | Sep 01 08:23:29 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339022287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.339022287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1045604262 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 152487600 ps |
| CPU time | 170.09 seconds |
| Started | Sep 01 08:23:02 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 271068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045604262 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.1045604262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.2339282602 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 17193400 ps |
| CPU time | 25.1 seconds |
| Started | Sep 01 08:23:09 PM UTC 24 |
| Finished | Sep 01 08:23:36 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339282602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2339282602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3751917685 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 241878500 ps |
| CPU time | 171.96 seconds |
| Started | Sep 01 08:23:04 PM UTC 24 |
| Finished | Sep 01 08:25:59 PM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751917685 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.3751917685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.3372131239 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 46138200 ps |
| CPU time | 18.56 seconds |
| Started | Sep 01 08:23:12 PM UTC 24 |
| Finished | Sep 01 08:23:31 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372131239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3372131239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3776948813 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 179848400 ps |
| CPU time | 200.29 seconds |
| Started | Sep 01 08:23:09 PM UTC 24 |
| Finished | Sep 01 08:26:33 PM UTC 24 |
| Peak memory | 271080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776948813 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.3776948813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.4054995119 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 39866900 ps |
| CPU time | 23.24 seconds |
| Started | Sep 01 08:23:13 PM UTC 24 |
| Finished | Sep 01 08:23:37 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054995119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.4054995119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1459425248 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 106387600 ps |
| CPU time | 171.44 seconds |
| Started | Sep 01 08:23:12 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 271400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459425248 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.1459425248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.2561251596 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 23316100 ps |
| CPU time | 20.91 seconds |
| Started | Sep 01 08:23:14 PM UTC 24 |
| Finished | Sep 01 08:23:36 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561251596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2561251596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3764704630 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 83424600 ps |
| CPU time | 191.23 seconds |
| Started | Sep 01 08:23:13 PM UTC 24 |
| Finished | Sep 01 08:26:27 PM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764704630 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.3764704630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.2357848623 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 54411900 ps |
| CPU time | 21.84 seconds |
| Started | Sep 01 08:23:15 PM UTC 24 |
| Finished | Sep 01 08:23:38 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357848623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2357848623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1546755300 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 38421800 ps |
| CPU time | 156.55 seconds |
| Started | Sep 01 08:23:15 PM UTC 24 |
| Finished | Sep 01 08:25:55 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546755300 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.1546755300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.381504328 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 14697100 ps |
| CPU time | 30.99 seconds |
| Started | Sep 01 08:23:19 PM UTC 24 |
| Finished | Sep 01 08:23:51 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381504328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.381504328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1535380710 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 235477000 ps |
| CPU time | 186.08 seconds |
| Started | Sep 01 08:23:19 PM UTC 24 |
| Finished | Sep 01 08:26:28 PM UTC 24 |
| Peak memory | 275636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535380710 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1535380710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.1287889833 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 17235000 ps |
| CPU time | 24.02 seconds |
| Started | Sep 01 08:23:20 PM UTC 24 |
| Finished | Sep 01 08:23:45 PM UTC 24 |
| Peak memory | 284936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287889833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1287889833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2771937588 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 128581200 ps |
| CPU time | 175.4 seconds |
| Started | Sep 01 08:23:20 PM UTC 24 |
| Finished | Sep 01 08:26:18 PM UTC 24 |
| Peak memory | 271028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771937588 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.2771937588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.3597078833 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 16205300 ps |
| CPU time | 24.96 seconds |
| Started | Sep 01 08:23:28 PM UTC 24 |
| Finished | Sep 01 08:23:54 PM UTC 24 |
| Peak memory | 295248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597078833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3597078833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2317112292 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 79504800 ps |
| CPU time | 173.53 seconds |
| Started | Sep 01 08:23:23 PM UTC 24 |
| Finished | Sep 01 08:26:19 PM UTC 24 |
| Peak memory | 275496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317112292 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.2317112292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3752431899 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 104003700 ps |
| CPU time | 26.67 seconds |
| Started | Sep 01 07:36:39 PM UTC 24 |
| Finished | Sep 01 07:37:07 PM UTC 24 |
| Peak memory | 269300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752431899 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3752431899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2787236949 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 18638500 ps |
| CPU time | 29.51 seconds |
| Started | Sep 01 07:36:19 PM UTC 24 |
| Finished | Sep 01 07:36:50 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787236949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2787236949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.736974555 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 35256200 ps |
| CPU time | 35.96 seconds |
| Started | Sep 01 07:35:40 PM UTC 24 |
| Finished | Sep 01 07:36:18 PM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=736974555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct rl_disable.736974555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.1563021762 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 2197296500 ps |
| CPU time | 3272.9 seconds |
| Started | Sep 01 07:33:55 PM UTC 24 |
| Finished | Sep 01 08:29:06 PM UTC 24 |
| Peak memory | 273240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563021762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.1563021762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2927083488 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1148576100 ps |
| CPU time | 1492.72 seconds |
| Started | Sep 01 07:33:27 PM UTC 24 |
| Finished | Sep 01 07:58:38 PM UTC 24 |
| Peak memory | 283728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927083488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2927083488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.1817993775 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 368813100 ps |
| CPU time | 31.88 seconds |
| Started | Sep 01 07:33:26 PM UTC 24 |
| Finished | Sep 01 07:33:59 PM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 17993775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc h_code.1817993775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.378775299 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 10127855400 ps |
| CPU time | 73.91 seconds |
| Started | Sep 01 07:36:34 PM UTC 24 |
| Finished | Sep 01 07:37:50 PM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=378775299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.378775299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1893684258 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 150398900 ps |
| CPU time | 19.99 seconds |
| Started | Sep 01 07:36:26 PM UTC 24 |
| Finished | Sep 01 07:36:47 PM UTC 24 |
| Peak memory | 275416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1893684258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1893684258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1443031744 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 130174298300 ps |
| CPU time | 870.88 seconds |
| Started | Sep 01 07:33:21 PM UTC 24 |
| Finished | Sep 01 07:48:01 PM UTC 24 |
| Peak memory | 275372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443031744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.1443031744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1774440271 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1242665300 ps |
| CPU time | 71.81 seconds |
| Started | Sep 01 07:33:18 PM UTC 24 |
| Finished | Sep 01 07:34:31 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774440271 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.1774440271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.3109197808 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8812029900 ps |
| CPU time | 199.45 seconds |
| Started | Sep 01 07:34:47 PM UTC 24 |
| Finished | Sep 01 07:38:10 PM UTC 24 |
| Peak memory | 304128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109197808 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.3109197808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.686588837 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5935661100 ps |
| CPU time | 172.69 seconds |
| Started | Sep 01 07:35:01 PM UTC 24 |
| Finished | Sep 01 07:37:56 PM UTC 24 |
| Peak memory | 304024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=686588837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_rd_slow_flash.686588837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.956926298 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 7231934100 ps |
| CPU time | 84.61 seconds |
| Started | Sep 01 07:34:58 PM UTC 24 |
| Finished | Sep 01 07:36:25 PM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956926298 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.956926298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3406076625 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 40785263700 ps |
| CPU time | 315.83 seconds |
| Started | Sep 01 07:35:09 PM UTC 24 |
| Finished | Sep 01 07:40:29 PM UTC 24 |
| Peak memory | 275580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406076625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3406076625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3406671094 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 8297130700 ps |
| CPU time | 99.47 seconds |
| Started | Sep 01 07:33:55 PM UTC 24 |
| Finished | Sep 01 07:35:37 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406671094 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3406671094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3153150248 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 24353400 ps |
| CPU time | 24.31 seconds |
| Started | Sep 01 07:36:19 PM UTC 24 |
| Finished | Sep 01 07:36:44 PM UTC 24 |
| Peak memory | 273396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3153150248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.3153150248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.1388656049 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 19893624100 ps |
| CPU time | 493.93 seconds |
| Started | Sep 01 07:33:24 PM UTC 24 |
| Finished | Sep 01 07:41:44 PM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1388656049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.1388656049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3291283745 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 648436100 ps |
| CPU time | 245.23 seconds |
| Started | Sep 01 07:33:24 PM UTC 24 |
| Finished | Sep 01 07:37:33 PM UTC 24 |
| Peak memory | 275480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291283745 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.3291283745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3370033302 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 49619400 ps |
| CPU time | 311.59 seconds |
| Started | Sep 01 07:33:15 PM UTC 24 |
| Finished | Sep 01 07:38:31 PM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370033302 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3370033302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.3513786336 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 32666700 ps |
| CPU time | 26.18 seconds |
| Started | Sep 01 07:35:12 PM UTC 24 |
| Finished | Sep 01 07:35:39 PM UTC 24 |
| Peak memory | 269196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513786336 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.3513786336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.1109155532 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 38067800 ps |
| CPU time | 376.76 seconds |
| Started | Sep 01 07:33:11 PM UTC 24 |
| Finished | Sep 01 07:39:33 PM UTC 24 |
| Peak memory | 291704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109155532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1109155532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2408562290 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 75625000 ps |
| CPU time | 52.12 seconds |
| Started | Sep 01 07:35:39 PM UTC 24 |
| Finished | Sep 01 07:36:33 PM UTC 24 |
| Peak memory | 283856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408562290 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2408562290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3713881173 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 4555092500 ps |
| CPU time | 151.39 seconds |
| Started | Sep 01 07:34:13 PM UTC 24 |
| Finished | Sep 01 07:36:47 PM UTC 24 |
| Peak memory | 302064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3713881173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.3713881173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3919968493 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 574282500 ps |
| CPU time | 166.82 seconds |
| Started | Sep 01 07:34:32 PM UTC 24 |
| Finished | Sep 01 07:37:22 PM UTC 24 |
| Peak memory | 291800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919968493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3919968493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.2933396533 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1964454800 ps |
| CPU time | 145.39 seconds |
| Started | Sep 01 07:34:22 PM UTC 24 |
| Finished | Sep 01 07:36:50 PM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2933396533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_ro_serr.2933396533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.895070571 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3731470400 ps |
| CPU time | 483.16 seconds |
| Started | Sep 01 07:34:16 PM UTC 24 |
| Finished | Sep 01 07:42:25 PM UTC 24 |
| Peak memory | 324544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895070571 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.895070571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2358239231 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 66693000 ps |
| CPU time | 59.03 seconds |
| Started | Sep 01 07:35:17 PM UTC 24 |
| Finished | Sep 01 07:36:18 PM UTC 24 |
| Peak memory | 285708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358239231 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.2358239231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1296637176 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 67634900 ps |
| CPU time | 57.89 seconds |
| Started | Sep 01 07:35:38 PM UTC 24 |
| Finished | Sep 01 07:36:38 PM UTC 24 |
| Peak memory | 287720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1296637176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct rl_rw_evict_all_en.1296637176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.767745785 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 7328168000 ps |
| CPU time | 264.34 seconds |
| Started | Sep 01 07:34:25 PM UTC 24 |
| Finished | Sep 01 07:38:54 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=767745785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.767745785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1080567530 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2576442700 ps |
| CPU time | 100.79 seconds |
| Started | Sep 01 07:35:59 PM UTC 24 |
| Finished | Sep 01 07:37:43 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080567530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1080567530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2130076146 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 25462100 ps |
| CPU time | 122.59 seconds |
| Started | Sep 01 07:33:11 PM UTC 24 |
| Finished | Sep 01 07:35:16 PM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130076146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2130076146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.45474974 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4297916500 ps |
| CPU time | 213.71 seconds |
| Started | Sep 01 07:34:01 PM UTC 24 |
| Finished | Sep 01 07:37:38 PM UTC 24 |
| Peak memory | 271476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =45474974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.45474974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3058693587 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 17112500 ps |
| CPU time | 27.04 seconds |
| Started | Sep 01 08:23:29 PM UTC 24 |
| Finished | Sep 01 08:23:58 PM UTC 24 |
| Peak memory | 295308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058693587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3058693587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.190407319 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 137039300 ps |
| CPU time | 154.15 seconds |
| Started | Sep 01 08:23:29 PM UTC 24 |
| Finished | Sep 01 08:26:06 PM UTC 24 |
| Peak memory | 271532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190407319 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.190407319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3967624547 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 85737300 ps |
| CPU time | 20.11 seconds |
| Started | Sep 01 08:23:32 PM UTC 24 |
| Finished | Sep 01 08:23:54 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967624547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3967624547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1624582600 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 45798500 ps |
| CPU time | 154.78 seconds |
| Started | Sep 01 08:23:29 PM UTC 24 |
| Finished | Sep 01 08:26:07 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624582600 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.1624582600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3115132636 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 98000400 ps |
| CPU time | 26.47 seconds |
| Started | Sep 01 08:23:34 PM UTC 24 |
| Finished | Sep 01 08:24:01 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115132636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3115132636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2627640949 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 138976300 ps |
| CPU time | 179.48 seconds |
| Started | Sep 01 08:23:34 PM UTC 24 |
| Finished | Sep 01 08:26:36 PM UTC 24 |
| Peak memory | 271648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627640949 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.2627640949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.4138436432 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 38392100 ps |
| CPU time | 26.34 seconds |
| Started | Sep 01 08:23:37 PM UTC 24 |
| Finished | Sep 01 08:24:05 PM UTC 24 |
| Peak memory | 294720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138436432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.4138436432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2203202734 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 72180600 ps |
| CPU time | 181.29 seconds |
| Started | Sep 01 08:23:34 PM UTC 24 |
| Finished | Sep 01 08:26:38 PM UTC 24 |
| Peak memory | 271272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203202734 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.2203202734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.1691436077 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15218700 ps |
| CPU time | 23.84 seconds |
| Started | Sep 01 08:23:38 PM UTC 24 |
| Finished | Sep 01 08:24:03 PM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691436077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1691436077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3207182655 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 214274400 ps |
| CPU time | 163.69 seconds |
| Started | Sep 01 08:23:37 PM UTC 24 |
| Finished | Sep 01 08:26:24 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207182655 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.3207182655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.3575700378 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 18489600 ps |
| CPU time | 18.19 seconds |
| Started | Sep 01 08:23:40 PM UTC 24 |
| Finished | Sep 01 08:24:00 PM UTC 24 |
| Peak memory | 295176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575700378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3575700378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3284833363 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 34136800 ps |
| CPU time | 148.81 seconds |
| Started | Sep 01 08:23:39 PM UTC 24 |
| Finished | Sep 01 08:26:11 PM UTC 24 |
| Peak memory | 271080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284833363 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.3284833363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.2068193685 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 39291500 ps |
| CPU time | 29.15 seconds |
| Started | Sep 01 08:23:46 PM UTC 24 |
| Finished | Sep 01 08:24:16 PM UTC 24 |
| Peak memory | 295372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068193685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2068193685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3753039177 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 211463600 ps |
| CPU time | 170.97 seconds |
| Started | Sep 01 08:23:41 PM UTC 24 |
| Finished | Sep 01 08:26:34 PM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753039177 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.3753039177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3091116727 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 52748100 ps |
| CPU time | 22.85 seconds |
| Started | Sep 01 08:23:51 PM UTC 24 |
| Finished | Sep 01 08:24:15 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091116727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3091116727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.357482645 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 158692700 ps |
| CPU time | 168.82 seconds |
| Started | Sep 01 08:23:46 PM UTC 24 |
| Finished | Sep 01 08:26:37 PM UTC 24 |
| Peak memory | 271584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357482645 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.357482645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.1490215236 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 28922900 ps |
| CPU time | 24.78 seconds |
| Started | Sep 01 08:23:52 PM UTC 24 |
| Finished | Sep 01 08:24:18 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490215236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1490215236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2425050471 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 160311000 ps |
| CPU time | 175.33 seconds |
| Started | Sep 01 08:23:51 PM UTC 24 |
| Finished | Sep 01 08:26:49 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425050471 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.2425050471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.2741302279 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 38955900 ps |
| CPU time | 22.23 seconds |
| Started | Sep 01 08:23:54 PM UTC 24 |
| Finished | Sep 01 08:24:18 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741302279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2741302279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3469194049 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 42733300 ps |
| CPU time | 167.24 seconds |
| Started | Sep 01 08:23:54 PM UTC 24 |
| Finished | Sep 01 08:26:44 PM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469194049 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.3469194049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.3196572527 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 59542800 ps |
| CPU time | 25.85 seconds |
| Started | Sep 01 07:40:56 PM UTC 24 |
| Finished | Sep 01 07:41:23 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196572527 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3196572527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1790683594 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 13775700 ps |
| CPU time | 31 seconds |
| Started | Sep 01 07:40:30 PM UTC 24 |
| Finished | Sep 01 07:41:02 PM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1790683594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.1790683594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1055675101 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 14836140900 ps |
| CPU time | 3206.17 seconds |
| Started | Sep 01 07:37:39 PM UTC 24 |
| Finished | Sep 01 08:31:40 PM UTC 24 |
| Peak memory | 274316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055675101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1055675101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.101511404 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1325430600 ps |
| CPU time | 1166.28 seconds |
| Started | Sep 01 07:37:34 PM UTC 24 |
| Finished | Sep 01 07:57:13 PM UTC 24 |
| Peak memory | 283468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101511404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.101511404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3828488589 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2332828200 ps |
| CPU time | 47.91 seconds |
| Started | Sep 01 07:37:23 PM UTC 24 |
| Finished | Sep 01 07:38:12 PM UTC 24 |
| Peak memory | 273276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 28488589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc h_code.3828488589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.867926735 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 10019643900 ps |
| CPU time | 129.83 seconds |
| Started | Sep 01 07:40:56 PM UTC 24 |
| Finished | Sep 01 07:43:08 PM UTC 24 |
| Peak memory | 316412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=867926735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.867926735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.3361908518 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 29013600 ps |
| CPU time | 26 seconds |
| Started | Sep 01 07:40:46 PM UTC 24 |
| Finished | Sep 01 07:41:13 PM UTC 24 |
| Peak memory | 275592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3361908518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3361908518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2033735614 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5374692300 ps |
| CPU time | 231.35 seconds |
| Started | Sep 01 07:36:50 PM UTC 24 |
| Finished | Sep 01 07:40:45 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033735614 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.2033735614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2598677483 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5417276100 ps |
| CPU time | 226.72 seconds |
| Started | Sep 01 07:38:55 PM UTC 24 |
| Finished | Sep 01 07:42:45 PM UTC 24 |
| Peak memory | 302240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598677483 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2598677483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1215371635 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 5841628200 ps |
| CPU time | 194.3 seconds |
| Started | Sep 01 07:39:29 PM UTC 24 |
| Finished | Sep 01 07:42:47 PM UTC 24 |
| Peak memory | 302164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1215371635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_intr_rd_slow_flash.1215371635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3420930241 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 21412395500 ps |
| CPU time | 129.34 seconds |
| Started | Sep 01 07:39:13 PM UTC 24 |
| Finished | Sep 01 07:41:25 PM UTC 24 |
| Peak memory | 275568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420930241 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.3420930241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2707746571 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 70038636000 ps |
| CPU time | 217.29 seconds |
| Started | Sep 01 07:39:34 PM UTC 24 |
| Finished | Sep 01 07:43:15 PM UTC 24 |
| Peak memory | 275556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707746571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2707746571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2940768171 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 12002074300 ps |
| CPU time | 87.34 seconds |
| Started | Sep 01 07:37:43 PM UTC 24 |
| Finished | Sep 01 07:39:12 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940768171 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2940768171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2308351075 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 29120300 ps |
| CPU time | 23.19 seconds |
| Started | Sep 01 07:40:37 PM UTC 24 |
| Finished | Sep 01 07:41:01 PM UTC 24 |
| Peak memory | 271376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2308351075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.2308351075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.852387191 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 10868952200 ps |
| CPU time | 200.28 seconds |
| Started | Sep 01 07:37:09 PM UTC 24 |
| Finished | Sep 01 07:40:32 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=852387191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_mp_regions.852387191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3182295800 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 37951900 ps |
| CPU time | 195.78 seconds |
| Started | Sep 01 07:37:07 PM UTC 24 |
| Finished | Sep 01 07:40:26 PM UTC 24 |
| Peak memory | 275632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182295800 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.3182295800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.178586172 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5483378600 ps |
| CPU time | 642.13 seconds |
| Started | Sep 01 07:36:48 PM UTC 24 |
| Finished | Sep 01 07:47:38 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178586172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.178586172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.1143390978 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4477804600 ps |
| CPU time | 186.18 seconds |
| Started | Sep 01 07:39:52 PM UTC 24 |
| Finished | Sep 01 07:43:02 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143390978 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.1143390978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1597584623 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 62600000 ps |
| CPU time | 328.44 seconds |
| Started | Sep 01 07:36:48 PM UTC 24 |
| Finished | Sep 01 07:42:21 PM UTC 24 |
| Peak memory | 285752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597584623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1597584623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1600898458 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 892659100 ps |
| CPU time | 36.12 seconds |
| Started | Sep 01 07:40:27 PM UTC 24 |
| Finished | Sep 01 07:41:04 PM UTC 24 |
| Peak memory | 287920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600898458 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.1600898458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.710062424 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 577105300 ps |
| CPU time | 150.21 seconds |
| Started | Sep 01 07:37:57 PM UTC 24 |
| Finished | Sep 01 07:40:30 PM UTC 24 |
| Peak memory | 308140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=710062424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.710062424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1707083977 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1293957000 ps |
| CPU time | 139.54 seconds |
| Started | Sep 01 07:38:13 PM UTC 24 |
| Finished | Sep 01 07:40:36 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1707083977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_ro_serr.1707083977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1407740752 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2908192800 ps |
| CPU time | 516.52 seconds |
| Started | Sep 01 07:38:11 PM UTC 24 |
| Finished | Sep 01 07:46:55 PM UTC 24 |
| Peak memory | 330928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407740752 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.1407740752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4133376342 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 19740532600 ps |
| CPU time | 306.83 seconds |
| Started | Sep 01 07:38:38 PM UTC 24 |
| Finished | Sep 01 07:43:49 PM UTC 24 |
| Peak memory | 306232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4133376342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_rw_derr.4133376342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2599113699 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 49562700 ps |
| CPU time | 52.71 seconds |
| Started | Sep 01 07:40:01 PM UTC 24 |
| Finished | Sep 01 07:40:55 PM UTC 24 |
| Peak memory | 287728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599113699 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.2599113699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.2092257344 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2866090200 ps |
| CPU time | 260.29 seconds |
| Started | Sep 01 07:38:13 PM UTC 24 |
| Finished | Sep 01 07:42:38 PM UTC 24 |
| Peak memory | 306144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2092257344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.2092257344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2568469000 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2136273200 ps |
| CPU time | 117.12 seconds |
| Started | Sep 01 07:40:31 PM UTC 24 |
| Finished | Sep 01 07:42:31 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568469000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2568469000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2633939150 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 38970200 ps |
| CPU time | 202.59 seconds |
| Started | Sep 01 07:36:45 PM UTC 24 |
| Finished | Sep 01 07:40:11 PM UTC 24 |
| Peak memory | 287808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633939150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2633939150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2956040018 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 17669143700 ps |
| CPU time | 185.33 seconds |
| Started | Sep 01 07:37:51 PM UTC 24 |
| Finished | Sep 01 07:40:59 PM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2956040018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.2956040018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.3504889041 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 41511000 ps |
| CPU time | 30.74 seconds |
| Started | Sep 01 08:23:59 PM UTC 24 |
| Finished | Sep 01 08:24:31 PM UTC 24 |
| Peak memory | 295112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504889041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3504889041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2290998993 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 38244500 ps |
| CPU time | 173.92 seconds |
| Started | Sep 01 08:23:55 PM UTC 24 |
| Finished | Sep 01 08:26:52 PM UTC 24 |
| Peak memory | 271388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290998993 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.2290998993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.3273724498 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 85280400 ps |
| CPU time | 23.02 seconds |
| Started | Sep 01 08:24:01 PM UTC 24 |
| Finished | Sep 01 08:24:25 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273724498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3273724498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1264588895 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 167026900 ps |
| CPU time | 158.57 seconds |
| Started | Sep 01 08:23:59 PM UTC 24 |
| Finished | Sep 01 08:26:40 PM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264588895 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.1264588895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3078340301 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 142557900 ps |
| CPU time | 25.59 seconds |
| Started | Sep 01 08:24:04 PM UTC 24 |
| Finished | Sep 01 08:24:31 PM UTC 24 |
| Peak memory | 285068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078340301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3078340301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1361771311 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 44764200 ps |
| CPU time | 163.78 seconds |
| Started | Sep 01 08:24:03 PM UTC 24 |
| Finished | Sep 01 08:26:49 PM UTC 24 |
| Peak memory | 271592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361771311 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.1361771311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.2858272977 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 15252200 ps |
| CPU time | 26.99 seconds |
| Started | Sep 01 08:24:06 PM UTC 24 |
| Finished | Sep 01 08:24:35 PM UTC 24 |
| Peak memory | 295376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858272977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2858272977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1813558464 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 86234300 ps |
| CPU time | 152.49 seconds |
| Started | Sep 01 08:24:05 PM UTC 24 |
| Finished | Sep 01 08:26:40 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813558464 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.1813558464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.2154071609 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 14451600 ps |
| CPU time | 18.56 seconds |
| Started | Sep 01 08:24:11 PM UTC 24 |
| Finished | Sep 01 08:24:31 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154071609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2154071609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.433770605 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 66146300 ps |
| CPU time | 134.74 seconds |
| Started | Sep 01 08:24:10 PM UTC 24 |
| Finished | Sep 01 08:26:27 PM UTC 24 |
| Peak memory | 271276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433770605 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.433770605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.883378517 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 48971700 ps |
| CPU time | 21.92 seconds |
| Started | Sep 01 08:24:14 PM UTC 24 |
| Finished | Sep 01 08:24:37 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883378517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.883378517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2346038515 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 131988400 ps |
| CPU time | 166.26 seconds |
| Started | Sep 01 08:24:14 PM UTC 24 |
| Finished | Sep 01 08:27:03 PM UTC 24 |
| Peak memory | 271544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346038515 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.2346038515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.2941405872 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 75182100 ps |
| CPU time | 30.36 seconds |
| Started | Sep 01 08:24:16 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941405872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.2941405872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1589160953 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 72449200 ps |
| CPU time | 146.17 seconds |
| Started | Sep 01 08:24:15 PM UTC 24 |
| Finished | Sep 01 08:26:43 PM UTC 24 |
| Peak memory | 275624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589160953 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.1589160953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.1487646181 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 16644300 ps |
| CPU time | 19.69 seconds |
| Started | Sep 01 08:24:19 PM UTC 24 |
| Finished | Sep 01 08:24:40 PM UTC 24 |
| Peak memory | 295184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487646181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.1487646181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1477629631 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 182248900 ps |
| CPU time | 176.1 seconds |
| Started | Sep 01 08:24:17 PM UTC 24 |
| Finished | Sep 01 08:27:16 PM UTC 24 |
| Peak memory | 275488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477629631 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.1477629631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.2262622018 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 14028500 ps |
| CPU time | 22.17 seconds |
| Started | Sep 01 08:24:24 PM UTC 24 |
| Finished | Sep 01 08:24:48 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262622018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2262622018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.4101484843 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 110560700 ps |
| CPU time | 154.05 seconds |
| Started | Sep 01 08:24:19 PM UTC 24 |
| Finished | Sep 01 08:26:56 PM UTC 24 |
| Peak memory | 271292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101484843 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.4101484843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2608614879 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 64264500 ps |
| CPU time | 24.94 seconds |
| Started | Sep 01 08:24:25 PM UTC 24 |
| Finished | Sep 01 08:24:52 PM UTC 24 |
| Peak memory | 295180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608614879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2608614879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.660286970 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 39942700 ps |
| CPU time | 173.56 seconds |
| Started | Sep 01 08:24:25 PM UTC 24 |
| Finished | Sep 01 08:27:22 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660286970 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.660286970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3678383710 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 37323400 ps |
| CPU time | 21.98 seconds |
| Started | Sep 01 07:44:55 PM UTC 24 |
| Finished | Sep 01 07:45:18 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678383710 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3678383710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.663164461 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 16634900 ps |
| CPU time | 23.18 seconds |
| Started | Sep 01 07:44:29 PM UTC 24 |
| Finished | Sep 01 07:44:54 PM UTC 24 |
| Peak memory | 295312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663164461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.663164461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3447406320 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 18955600 ps |
| CPU time | 44.32 seconds |
| Started | Sep 01 07:44:20 PM UTC 24 |
| Finished | Sep 01 07:45:06 PM UTC 24 |
| Peak memory | 285920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3447406320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c trl_disable.3447406320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1790160347 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 7111158500 ps |
| CPU time | 3047.14 seconds |
| Started | Sep 01 07:41:45 PM UTC 24 |
| Finished | Sep 01 08:33:09 PM UTC 24 |
| Peak memory | 278300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790160347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1790160347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3343890965 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 724927100 ps |
| CPU time | 1294.13 seconds |
| Started | Sep 01 07:41:26 PM UTC 24 |
| Finished | Sep 01 08:03:16 PM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343890965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3343890965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.626494219 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1184662900 ps |
| CPU time | 25.26 seconds |
| Started | Sep 01 07:41:24 PM UTC 24 |
| Finished | Sep 01 07:41:50 PM UTC 24 |
| Peak memory | 273272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62 6494219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch _code.626494219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.4122829500 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 10011865800 ps |
| CPU time | 124.86 seconds |
| Started | Sep 01 07:44:52 PM UTC 24 |
| Finished | Sep 01 07:46:59 PM UTC 24 |
| Peak memory | 314532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4122829500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.4122829500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.2678946005 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 26890600 ps |
| CPU time | 20.72 seconds |
| Started | Sep 01 07:44:41 PM UTC 24 |
| Finished | Sep 01 07:45:03 PM UTC 24 |
| Peak memory | 269424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2678946005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2678946005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2566590538 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 170172445500 ps |
| CPU time | 991.05 seconds |
| Started | Sep 01 07:41:05 PM UTC 24 |
| Finished | Sep 01 07:57:48 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566590538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2566590538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1954267925 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 5091385500 ps |
| CPU time | 119.04 seconds |
| Started | Sep 01 07:41:03 PM UTC 24 |
| Finished | Sep 01 07:43:05 PM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954267925 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.1954267925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.4181669583 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 580532300 ps |
| CPU time | 147.82 seconds |
| Started | Sep 01 07:42:48 PM UTC 24 |
| Finished | Sep 01 07:45:19 PM UTC 24 |
| Peak memory | 306176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181669583 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.4181669583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3035682262 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6054342900 ps |
| CPU time | 179.26 seconds |
| Started | Sep 01 07:43:05 PM UTC 24 |
| Finished | Sep 01 07:46:07 PM UTC 24 |
| Peak memory | 306364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3035682262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_intr_rd_slow_flash.3035682262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2309976927 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 8698575500 ps |
| CPU time | 96.02 seconds |
| Started | Sep 01 07:43:03 PM UTC 24 |
| Finished | Sep 01 07:44:41 PM UTC 24 |
| Peak memory | 275304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309976927 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.2309976927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.455584507 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 44844267800 ps |
| CPU time | 285.39 seconds |
| Started | Sep 01 07:43:08 PM UTC 24 |
| Finished | Sep 01 07:47:58 PM UTC 24 |
| Peak memory | 275360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455584507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.455584507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2969199555 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 76918200 ps |
| CPU time | 23.66 seconds |
| Started | Sep 01 07:44:38 PM UTC 24 |
| Finished | Sep 01 07:45:03 PM UTC 24 |
| Peak memory | 275472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2969199555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_lcmgr_intg.2969199555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2768844100 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 45727891100 ps |
| CPU time | 366.3 seconds |
| Started | Sep 01 07:41:14 PM UTC 24 |
| Finished | Sep 01 07:47:26 PM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2768844100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.2768844100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3905727676 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 55653100 ps |
| CPU time | 218.92 seconds |
| Started | Sep 01 07:41:08 PM UTC 24 |
| Finished | Sep 01 07:44:51 PM UTC 24 |
| Peak memory | 271396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905727676 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.3905727676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1914215240 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2735260700 ps |
| CPU time | 345.96 seconds |
| Started | Sep 01 07:41:03 PM UTC 24 |
| Finished | Sep 01 07:46:54 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914215240 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1914215240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.49058790 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4031515100 ps |
| CPU time | 167.04 seconds |
| Started | Sep 01 07:43:09 PM UTC 24 |
| Finished | Sep 01 07:45:59 PM UTC 24 |
| Peak memory | 271212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49058790 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.49058790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3766430002 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5548137400 ps |
| CPU time | 1452.06 seconds |
| Started | Sep 01 07:41:02 PM UTC 24 |
| Finished | Sep 01 08:05:32 PM UTC 24 |
| Peak memory | 295800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766430002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3766430002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3969086974 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 79287000 ps |
| CPU time | 36.85 seconds |
| Started | Sep 01 07:43:50 PM UTC 24 |
| Finished | Sep 01 07:44:28 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969086974 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.3969086974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1018312005 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 578473800 ps |
| CPU time | 146.48 seconds |
| Started | Sep 01 07:42:08 PM UTC 24 |
| Finished | Sep 01 07:44:37 PM UTC 24 |
| Peak memory | 291764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1018312005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.1018312005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.26133191 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3146213100 ps |
| CPU time | 175.38 seconds |
| Started | Sep 01 07:42:39 PM UTC 24 |
| Finished | Sep 01 07:45:37 PM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26133191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.26133191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1037792245 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2033546100 ps |
| CPU time | 162.27 seconds |
| Started | Sep 01 07:42:26 PM UTC 24 |
| Finished | Sep 01 07:45:11 PM UTC 24 |
| Peak memory | 306152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1037792245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.1037792245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.662147020 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3572449500 ps |
| CPU time | 555.67 seconds |
| Started | Sep 01 07:42:22 PM UTC 24 |
| Finished | Sep 01 07:51:46 PM UTC 24 |
| Peak memory | 324804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662147020 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.662147020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1675938142 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1613357300 ps |
| CPU time | 302.41 seconds |
| Started | Sep 01 07:42:46 PM UTC 24 |
| Finished | Sep 01 07:47:53 PM UTC 24 |
| Peak memory | 298000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1675938142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.1675938142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.4199030885 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 30934600 ps |
| CPU time | 62.57 seconds |
| Started | Sep 01 07:43:15 PM UTC 24 |
| Finished | Sep 01 07:44:20 PM UTC 24 |
| Peak memory | 287724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199030885 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.4199030885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1690941747 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 105313300 ps |
| CPU time | 47.75 seconds |
| Started | Sep 01 07:43:32 PM UTC 24 |
| Finished | Sep 01 07:44:21 PM UTC 24 |
| Peak memory | 281580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1690941747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_rw_evict_all_en.1690941747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.695862794 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 6185369400 ps |
| CPU time | 247.7 seconds |
| Started | Sep 01 07:42:32 PM UTC 24 |
| Finished | Sep 01 07:46:44 PM UTC 24 |
| Peak memory | 291816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=695862794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.695862794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3404741529 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2757577800 ps |
| CPU time | 108.21 seconds |
| Started | Sep 01 07:44:22 PM UTC 24 |
| Finished | Sep 01 07:46:13 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404741529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3404741529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.19713201 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 20834400 ps |
| CPU time | 125.35 seconds |
| Started | Sep 01 07:41:00 PM UTC 24 |
| Finished | Sep 01 07:43:08 PM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19713201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.19713201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1823734076 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3524770600 ps |
| CPU time | 248.63 seconds |
| Started | Sep 01 07:41:51 PM UTC 24 |
| Finished | Sep 01 07:46:04 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1823734076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.1823734076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1224609077 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 99453800 ps |
| CPU time | 24.24 seconds |
| Started | Sep 01 07:48:03 PM UTC 24 |
| Finished | Sep 01 07:48:28 PM UTC 24 |
| Peak memory | 275700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224609077 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1224609077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3824155176 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 21452100 ps |
| CPU time | 31.61 seconds |
| Started | Sep 01 07:47:50 PM UTC 24 |
| Finished | Sep 01 07:48:23 PM UTC 24 |
| Peak memory | 295248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824155176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3824155176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2622024707 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 16444700 ps |
| CPU time | 34.4 seconds |
| Started | Sep 01 07:47:39 PM UTC 24 |
| Finished | Sep 01 07:48:15 PM UTC 24 |
| Peak memory | 285856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2622024707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c trl_disable.2622024707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3686255341 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2054292900 ps |
| CPU time | 3134.07 seconds |
| Started | Sep 01 07:45:38 PM UTC 24 |
| Finished | Sep 01 08:38:29 PM UTC 24 |
| Peak memory | 276004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686255341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.3686255341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2468146505 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 6292925900 ps |
| CPU time | 1789.8 seconds |
| Started | Sep 01 07:45:27 PM UTC 24 |
| Finished | Sep 01 08:15:40 PM UTC 24 |
| Peak memory | 285720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468146505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2468146505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1708791376 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 799139900 ps |
| CPU time | 45.07 seconds |
| Started | Sep 01 07:45:19 PM UTC 24 |
| Finished | Sep 01 07:46:07 PM UTC 24 |
| Peak memory | 273268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17 08791376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.1708791376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1747980438 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 10034503900 ps |
| CPU time | 67.98 seconds |
| Started | Sep 01 07:48:01 PM UTC 24 |
| Finished | Sep 01 07:49:10 PM UTC 24 |
| Peak memory | 298056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1747980438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1747980438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.2683500074 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 47125300 ps |
| CPU time | 23.53 seconds |
| Started | Sep 01 07:47:58 PM UTC 24 |
| Finished | Sep 01 07:48:23 PM UTC 24 |
| Peak memory | 271324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2683500074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2683500074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.419406153 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 40127148100 ps |
| CPU time | 884.21 seconds |
| Started | Sep 01 07:45:12 PM UTC 24 |
| Finished | Sep 01 08:00:07 PM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419406153 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.419406153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.696383439 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 581254900 ps |
| CPU time | 49.33 seconds |
| Started | Sep 01 07:45:11 PM UTC 24 |
| Finished | Sep 01 07:46:02 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696383439 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.696383439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3644253402 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 18132788900 ps |
| CPU time | 276.66 seconds |
| Started | Sep 01 07:46:41 PM UTC 24 |
| Finished | Sep 01 07:51:22 PM UTC 24 |
| Peak memory | 293856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644253402 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.3644253402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.377681009 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 110863848100 ps |
| CPU time | 361.03 seconds |
| Started | Sep 01 07:46:55 PM UTC 24 |
| Finished | Sep 01 07:53:01 PM UTC 24 |
| Peak memory | 304060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=377681009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_rd_slow_flash.377681009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.46952372 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1809099500 ps |
| CPU time | 90.38 seconds |
| Started | Sep 01 07:46:45 PM UTC 24 |
| Finished | Sep 01 07:48:17 PM UTC 24 |
| Peak memory | 275500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46952372 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.46952372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.144128637 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 90830269300 ps |
| CPU time | 340.32 seconds |
| Started | Sep 01 07:46:56 PM UTC 24 |
| Finished | Sep 01 07:52:41 PM UTC 24 |
| Peak memory | 271252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144128637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.144128637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2168426794 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9399836800 ps |
| CPU time | 58.77 seconds |
| Started | Sep 01 07:46:00 PM UTC 24 |
| Finished | Sep 01 07:47:00 PM UTC 24 |
| Peak memory | 271084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168426794 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2168426794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1358756153 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 15554100 ps |
| CPU time | 27.8 seconds |
| Started | Sep 01 07:47:53 PM UTC 24 |
| Finished | Sep 01 07:48:22 PM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1358756153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.1358756153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2879277645 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 26342112800 ps |
| CPU time | 350.37 seconds |
| Started | Sep 01 07:45:18 PM UTC 24 |
| Finished | Sep 01 07:51:14 PM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2879277645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.2879277645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3434037442 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 36760000 ps |
| CPU time | 191.23 seconds |
| Started | Sep 01 07:45:16 PM UTC 24 |
| Finished | Sep 01 07:48:31 PM UTC 24 |
| Peak memory | 275576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434037442 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.3434037442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2983842597 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 88837300 ps |
| CPU time | 108.02 seconds |
| Started | Sep 01 07:45:07 PM UTC 24 |
| Finished | Sep 01 07:46:57 PM UTC 24 |
| Peak memory | 273484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983842597 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2983842597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1758255602 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 8227824800 ps |
| CPU time | 149.2 seconds |
| Started | Sep 01 07:46:58 PM UTC 24 |
| Finished | Sep 01 07:49:30 PM UTC 24 |
| Peak memory | 273284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758255602 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.1758255602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1121076707 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 294982700 ps |
| CPU time | 498.43 seconds |
| Started | Sep 01 07:45:04 PM UTC 24 |
| Finished | Sep 01 07:53:29 PM UTC 24 |
| Peak memory | 291704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121076707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1121076707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3575117627 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 145793300 ps |
| CPU time | 49.3 seconds |
| Started | Sep 01 07:47:27 PM UTC 24 |
| Finished | Sep 01 07:48:18 PM UTC 24 |
| Peak memory | 287692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575117627 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.3575117627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1123408298 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 538285100 ps |
| CPU time | 117.4 seconds |
| Started | Sep 01 07:46:04 PM UTC 24 |
| Finished | Sep 01 07:48:04 PM UTC 24 |
| Peak memory | 291760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1123408298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1123408298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2062496336 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4895499100 ps |
| CPU time | 192.79 seconds |
| Started | Sep 01 07:46:09 PM UTC 24 |
| Finished | Sep 01 07:49:25 PM UTC 24 |
| Peak memory | 292000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062496336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2062496336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.412608701 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1143006900 ps |
| CPU time | 142.47 seconds |
| Started | Sep 01 07:46:07 PM UTC 24 |
| Finished | Sep 01 07:48:32 PM UTC 24 |
| Peak memory | 306368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=412608701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ ctrl_ro_serr.412608701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.3920043186 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 6136035400 ps |
| CPU time | 456.46 seconds |
| Started | Sep 01 07:46:05 PM UTC 24 |
| Finished | Sep 01 07:53:48 PM UTC 24 |
| Peak memory | 320476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920043186 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.3920043186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2705510058 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3071284800 ps |
| CPU time | 258.25 seconds |
| Started | Sep 01 07:46:14 PM UTC 24 |
| Finished | Sep 01 07:50:36 PM UTC 24 |
| Peak memory | 297992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2705510058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.flash_ctrl_rw_derr.2705510058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2211657745 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 101634800 ps |
| CPU time | 48.02 seconds |
| Started | Sep 01 07:46:59 PM UTC 24 |
| Finished | Sep 01 07:47:49 PM UTC 24 |
| Peak memory | 285676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211657745 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.2211657745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1185807102 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 36450800 ps |
| CPU time | 46.55 seconds |
| Started | Sep 01 07:47:01 PM UTC 24 |
| Finished | Sep 01 07:47:50 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1185807102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_rw_evict_all_en.1185807102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1480941123 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1718110300 ps |
| CPU time | 189.54 seconds |
| Started | Sep 01 07:46:08 PM UTC 24 |
| Finished | Sep 01 07:49:21 PM UTC 24 |
| Peak memory | 306148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1480941123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.1480941123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2941438181 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1125825100 ps |
| CPU time | 62.78 seconds |
| Started | Sep 01 07:47:50 PM UTC 24 |
| Finished | Sep 01 07:48:55 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941438181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2941438181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3910387191 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 91346700 ps |
| CPU time | 173.2 seconds |
| Started | Sep 01 07:45:04 PM UTC 24 |
| Finished | Sep 01 07:48:00 PM UTC 24 |
| Peak memory | 289656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910387191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3910387191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1242084376 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 8432312200 ps |
| CPU time | 200.17 seconds |
| Started | Sep 01 07:46:03 PM UTC 24 |
| Finished | Sep 01 07:49:26 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1242084376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.1242084376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
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