| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.2262622018 |
|
|
Sep 01 08:24:24 PM UTC 24 |
Sep 01 08:24:48 PM UTC 24 |
14028500 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2608614879 |
|
|
Sep 01 08:24:25 PM UTC 24 |
Sep 01 08:24:52 PM UTC 24 |
64264500 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1923364430 |
|
|
Sep 01 08:22:24 PM UTC 24 |
Sep 01 08:24:55 PM UTC 24 |
25324100 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.3635423428 |
|
|
Sep 01 08:21:45 PM UTC 24 |
Sep 01 08:24:58 PM UTC 24 |
38821300 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3112500332 |
|
|
Sep 01 08:21:21 PM UTC 24 |
Sep 01 08:25:01 PM UTC 24 |
99781200 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2750682831 |
|
|
Sep 01 08:22:01 PM UTC 24 |
Sep 01 08:25:01 PM UTC 24 |
81621200 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.398000911 |
|
|
Sep 01 08:17:22 PM UTC 24 |
Sep 01 08:25:16 PM UTC 24 |
24692227800 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3320821631 |
|
|
Sep 01 08:22:39 PM UTC 24 |
Sep 01 08:25:30 PM UTC 24 |
39724400 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.1714420382 |
|
|
Sep 01 08:22:28 PM UTC 24 |
Sep 01 08:25:31 PM UTC 24 |
190708100 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2688107968 |
|
|
Sep 01 08:22:09 PM UTC 24 |
Sep 01 08:25:35 PM UTC 24 |
136854500 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1665279096 |
|
|
Sep 01 08:22:50 PM UTC 24 |
Sep 01 08:25:36 PM UTC 24 |
71771400 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.3811962251 |
|
|
Sep 01 08:22:07 PM UTC 24 |
Sep 01 08:25:39 PM UTC 24 |
42516800 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2520292873 |
|
|
Sep 01 08:19:38 PM UTC 24 |
Sep 01 08:25:42 PM UTC 24 |
47381842300 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1546755300 |
|
|
Sep 01 08:23:15 PM UTC 24 |
Sep 01 08:25:55 PM UTC 24 |
38421800 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1045604262 |
|
|
Sep 01 08:23:02 PM UTC 24 |
Sep 01 08:25:55 PM UTC 24 |
152487600 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3751917685 |
|
|
Sep 01 08:23:04 PM UTC 24 |
Sep 01 08:25:59 PM UTC 24 |
241878500 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.190407319 |
|
|
Sep 01 08:23:29 PM UTC 24 |
Sep 01 08:26:06 PM UTC 24 |
137039300 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1459425248 |
|
|
Sep 01 08:23:12 PM UTC 24 |
Sep 01 08:26:06 PM UTC 24 |
106387600 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1624582600 |
|
|
Sep 01 08:23:29 PM UTC 24 |
Sep 01 08:26:07 PM UTC 24 |
45798500 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3284833363 |
|
|
Sep 01 08:23:39 PM UTC 24 |
Sep 01 08:26:11 PM UTC 24 |
34136800 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3566167072 |
|
|
Sep 01 08:23:00 PM UTC 24 |
Sep 01 08:26:14 PM UTC 24 |
41509800 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2771937588 |
|
|
Sep 01 08:23:20 PM UTC 24 |
Sep 01 08:26:18 PM UTC 24 |
128581200 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2317112292 |
|
|
Sep 01 08:23:23 PM UTC 24 |
Sep 01 08:26:19 PM UTC 24 |
79504800 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3207182655 |
|
|
Sep 01 08:23:37 PM UTC 24 |
Sep 01 08:26:24 PM UTC 24 |
214274400 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3719274906 |
|
|
Sep 01 08:22:37 PM UTC 24 |
Sep 01 08:26:24 PM UTC 24 |
62816500 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3764704630 |
|
|
Sep 01 08:23:13 PM UTC 24 |
Sep 01 08:26:27 PM UTC 24 |
83424600 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.433770605 |
|
|
Sep 01 08:24:10 PM UTC 24 |
Sep 01 08:26:27 PM UTC 24 |
66146300 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1535380710 |
|
|
Sep 01 08:23:19 PM UTC 24 |
Sep 01 08:26:28 PM UTC 24 |
235477000 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3776948813 |
|
|
Sep 01 08:23:09 PM UTC 24 |
Sep 01 08:26:33 PM UTC 24 |
179848400 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3753039177 |
|
|
Sep 01 08:23:41 PM UTC 24 |
Sep 01 08:26:34 PM UTC 24 |
211463600 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2627640949 |
|
|
Sep 01 08:23:34 PM UTC 24 |
Sep 01 08:26:36 PM UTC 24 |
138976300 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.357482645 |
|
|
Sep 01 08:23:46 PM UTC 24 |
Sep 01 08:26:37 PM UTC 24 |
158692700 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2203202734 |
|
|
Sep 01 08:23:34 PM UTC 24 |
Sep 01 08:26:38 PM UTC 24 |
72180600 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1264588895 |
|
|
Sep 01 08:23:59 PM UTC 24 |
Sep 01 08:26:40 PM UTC 24 |
167026900 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2443576948 |
|
|
Sep 01 08:22:48 PM UTC 24 |
Sep 01 08:26:40 PM UTC 24 |
30870700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1813558464 |
|
|
Sep 01 08:24:05 PM UTC 24 |
Sep 01 08:26:40 PM UTC 24 |
86234300 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1589160953 |
|
|
Sep 01 08:24:15 PM UTC 24 |
Sep 01 08:26:43 PM UTC 24 |
72449200 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3469194049 |
|
|
Sep 01 08:23:54 PM UTC 24 |
Sep 01 08:26:44 PM UTC 24 |
42733300 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1361771311 |
|
|
Sep 01 08:24:03 PM UTC 24 |
Sep 01 08:26:49 PM UTC 24 |
44764200 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2425050471 |
|
|
Sep 01 08:23:51 PM UTC 24 |
Sep 01 08:26:49 PM UTC 24 |
160311000 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2290998993 |
|
|
Sep 01 08:23:55 PM UTC 24 |
Sep 01 08:26:52 PM UTC 24 |
38244500 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.4101484843 |
|
|
Sep 01 08:24:19 PM UTC 24 |
Sep 01 08:26:56 PM UTC 24 |
110560700 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2346038515 |
|
|
Sep 01 08:24:14 PM UTC 24 |
Sep 01 08:27:03 PM UTC 24 |
131988400 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2249846132 |
|
|
Sep 01 08:20:25 PM UTC 24 |
Sep 01 08:27:05 PM UTC 24 |
152500627700 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1477629631 |
|
|
Sep 01 08:24:17 PM UTC 24 |
Sep 01 08:27:16 PM UTC 24 |
182248900 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.660286970 |
|
|
Sep 01 08:24:25 PM UTC 24 |
Sep 01 08:27:22 PM UTC 24 |
39942700 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.670141442 |
|
|
Sep 01 07:30:25 PM UTC 24 |
Sep 01 08:27:26 PM UTC 24 |
10329956400 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.1563021762 |
|
|
Sep 01 07:33:55 PM UTC 24 |
Sep 01 08:29:06 PM UTC 24 |
2197296500 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1055675101 |
|
|
Sep 01 07:37:39 PM UTC 24 |
Sep 01 08:31:40 PM UTC 24 |
14836140900 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1790160347 |
|
|
Sep 01 07:41:45 PM UTC 24 |
Sep 01 08:33:09 PM UTC 24 |
7111158500 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3686255341 |
|
|
Sep 01 07:45:38 PM UTC 24 |
Sep 01 08:38:29 PM UTC 24 |
2054292900 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.202907875 |
|
|
Sep 01 07:06:52 PM UTC 24 |
Sep 01 08:56:51 PM UTC 24 |
1587070700 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.2143082470 |
|
|
Sep 01 07:11:45 PM UTC 24 |
Sep 01 09:10:33 PM UTC 24 |
1660311700 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.59855745 |
|
|
Sep 01 07:17:14 PM UTC 24 |
Sep 01 09:11:59 PM UTC 24 |
1952442200 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2822031000 |
|
|
Sep 01 07:29:11 PM UTC 24 |
Sep 01 09:24:35 PM UTC 24 |
16130794900 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1350794777 |
|
|
Sep 01 07:23:01 PM UTC 24 |
Sep 01 09:28:59 PM UTC 24 |
2181032900 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.941425912 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:15 PM UTC 24 |
21303700 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2080185500 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:15 PM UTC 24 |
96070100 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2609750584 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:15 PM UTC 24 |
17495900 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2866067514 |
|
|
Sep 01 07:04:01 PM UTC 24 |
Sep 01 07:04:19 PM UTC 24 |
23424700 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.1573425710 |
|
|
Sep 01 07:04:01 PM UTC 24 |
Sep 01 07:04:20 PM UTC 24 |
40035000 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.495599376 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:20 PM UTC 24 |
47317700 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.315842050 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:21 PM UTC 24 |
15071400 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3276257371 |
|
|
Sep 01 07:04:01 PM UTC 24 |
Sep 01 07:04:21 PM UTC 24 |
38947600 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.4265432068 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:22 PM UTC 24 |
15801900 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1612287518 |
|
|
Sep 01 07:04:01 PM UTC 24 |
Sep 01 07:04:22 PM UTC 24 |
119466700 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3446624236 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:22 PM UTC 24 |
117540000 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1812631968 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:23 PM UTC 24 |
108791600 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1905108274 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:25 PM UTC 24 |
44688500 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.936956806 |
|
|
Sep 01 07:04:01 PM UTC 24 |
Sep 01 07:04:26 PM UTC 24 |
15371300 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.68109369 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:26 PM UTC 24 |
390438400 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2772367586 |
|
|
Sep 01 07:04:07 PM UTC 24 |
Sep 01 07:04:26 PM UTC 24 |
86766900 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3017474492 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:26 PM UTC 24 |
14834300 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2682580807 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:27 PM UTC 24 |
13665600 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.211053221 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:27 PM UTC 24 |
127623600 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2492571416 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:28 PM UTC 24 |
55455400 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3196488486 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:29 PM UTC 24 |
59800000 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1790610984 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:30 PM UTC 24 |
66369400 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.300981876 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:30 PM UTC 24 |
18789400 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3405049058 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:31 PM UTC 24 |
692252900 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.209371500 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:31 PM UTC 24 |
70433400 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.167121052 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:32 PM UTC 24 |
14609500 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1631491773 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:34 PM UTC 24 |
57562500 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1511245328 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:34 PM UTC 24 |
42495000 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3004556068 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:35 PM UTC 24 |
143454400 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2729471078 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:35 PM UTC 24 |
66695800 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3500279747 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:36 PM UTC 24 |
218518100 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.27881549 |
|
|
Sep 01 07:04:07 PM UTC 24 |
Sep 01 07:04:36 PM UTC 24 |
14799200 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1038629747 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:38 PM UTC 24 |
112267200 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.463315866 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:38 PM UTC 24 |
163424100 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3718532087 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:38 PM UTC 24 |
162289000 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.840036739 |
|
|
Sep 01 07:04:16 PM UTC 24 |
Sep 01 07:04:39 PM UTC 24 |
69805300 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2354332494 |
|
|
Sep 01 07:04:21 PM UTC 24 |
Sep 01 07:04:40 PM UTC 24 |
29832400 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3099740639 |
|
|
Sep 01 07:04:22 PM UTC 24 |
Sep 01 07:04:40 PM UTC 24 |
47880600 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1282732188 |
|
|
Sep 01 07:04:21 PM UTC 24 |
Sep 01 07:04:40 PM UTC 24 |
13914900 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3425820536 |
|
|
Sep 01 07:04:16 PM UTC 24 |
Sep 01 07:04:41 PM UTC 24 |
329651400 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2422436396 |
|
|
Sep 01 07:04:16 PM UTC 24 |
Sep 01 07:04:42 PM UTC 24 |
126877900 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3524542190 |
|
|
Sep 01 07:04:24 PM UTC 24 |
Sep 01 07:04:46 PM UTC 24 |
43675200 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1992579335 |
|
|
Sep 01 07:04:20 PM UTC 24 |
Sep 01 07:04:46 PM UTC 24 |
18296300 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3828347602 |
|
|
Sep 01 07:04:25 PM UTC 24 |
Sep 01 07:04:46 PM UTC 24 |
63616800 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1956787214 |
|
|
Sep 01 07:04:22 PM UTC 24 |
Sep 01 07:04:48 PM UTC 24 |
44675500 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.3475394921 |
|
|
Sep 01 07:04:28 PM UTC 24 |
Sep 01 07:04:48 PM UTC 24 |
24411500 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1868396843 |
|
|
Sep 01 07:04:31 PM UTC 24 |
Sep 01 07:04:49 PM UTC 24 |
16405400 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1464895294 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:04:49 PM UTC 24 |
91983200 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2244883655 |
|
|
Sep 01 07:04:28 PM UTC 24 |
Sep 01 07:04:50 PM UTC 24 |
14594400 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2602174023 |
|
|
Sep 01 07:04:30 PM UTC 24 |
Sep 01 07:04:52 PM UTC 24 |
43692000 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1348576382 |
|
|
Sep 01 07:04:24 PM UTC 24 |
Sep 01 07:04:52 PM UTC 24 |
204704200 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1007717444 |
|
|
Sep 01 07:04:25 PM UTC 24 |
Sep 01 07:04:53 PM UTC 24 |
37526500 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4094418826 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:04:53 PM UTC 24 |
8101735800 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2760852852 |
|
|
Sep 01 07:04:31 PM UTC 24 |
Sep 01 07:04:53 PM UTC 24 |
15120600 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2252053249 |
|
|
Sep 01 07:04:27 PM UTC 24 |
Sep 01 07:04:53 PM UTC 24 |
11775700 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2989643208 |
|
|
Sep 01 07:04:32 PM UTC 24 |
Sep 01 07:04:55 PM UTC 24 |
52972200 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4236769203 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:55 PM UTC 24 |
5438713800 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1701077385 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:04:57 PM UTC 24 |
99920800 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.549718753 |
|
|
Sep 01 07:04:37 PM UTC 24 |
Sep 01 07:04:58 PM UTC 24 |
33473900 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2354333904 |
|
|
Sep 01 07:04:28 PM UTC 24 |
Sep 01 07:04:58 PM UTC 24 |
124415200 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1567153164 |
|
|
Sep 01 07:04:34 PM UTC 24 |
Sep 01 07:04:59 PM UTC 24 |
170374300 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2952838202 |
|
|
Sep 01 07:04:33 PM UTC 24 |
Sep 01 07:04:59 PM UTC 24 |
1529406700 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2388069631 |
|
|
Sep 01 07:04:24 PM UTC 24 |
Sep 01 07:04:59 PM UTC 24 |
226396800 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4210184426 |
|
|
Sep 01 07:04:30 PM UTC 24 |
Sep 01 07:05:00 PM UTC 24 |
41651000 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.561761852 |
|
|
Sep 01 07:04:36 PM UTC 24 |
Sep 01 07:05:00 PM UTC 24 |
57380400 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3223579469 |
|
|
Sep 01 07:04:42 PM UTC 24 |
Sep 01 07:05:02 PM UTC 24 |
37613800 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.653571949 |
|
|
Sep 01 07:04:37 PM UTC 24 |
Sep 01 07:05:02 PM UTC 24 |
14551200 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1757501466 |
|
|
Sep 01 07:04:41 PM UTC 24 |
Sep 01 07:05:03 PM UTC 24 |
17686000 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2396724494 |
|
|
Sep 01 07:03:58 PM UTC 24 |
Sep 01 07:05:04 PM UTC 24 |
1321048500 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2197578861 |
|
|
Sep 01 07:04:39 PM UTC 24 |
Sep 01 07:05:05 PM UTC 24 |
117657700 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2724270625 |
|
|
Sep 01 07:04:41 PM UTC 24 |
Sep 01 07:05:05 PM UTC 24 |
46100300 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.774845177 |
|
|
Sep 01 07:04:41 PM UTC 24 |
Sep 01 07:05:05 PM UTC 24 |
18882400 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2636481349 |
|
|
Sep 01 07:04:36 PM UTC 24 |
Sep 01 07:05:05 PM UTC 24 |
21271600 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.87914622 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:05:05 PM UTC 24 |
7482322500 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3990744090 |
|
|
Sep 01 07:04:30 PM UTC 24 |
Sep 01 07:05:06 PM UTC 24 |
754040500 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3304296283 |
|
|
Sep 01 07:04:38 PM UTC 24 |
Sep 01 07:05:08 PM UTC 24 |
67477500 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3425157794 |
|
|
Sep 01 07:04:40 PM UTC 24 |
Sep 01 07:05:09 PM UTC 24 |
57012300 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1081758796 |
|
|
Sep 01 07:04:48 PM UTC 24 |
Sep 01 07:05:11 PM UTC 24 |
11586700 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2698246455 |
|
|
Sep 01 07:04:48 PM UTC 24 |
Sep 01 07:05:12 PM UTC 24 |
89712300 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2249327342 |
|
|
Sep 01 07:04:48 PM UTC 24 |
Sep 01 07:05:12 PM UTC 24 |
31331500 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3251766600 |
|
|
Sep 01 07:04:48 PM UTC 24 |
Sep 01 07:05:13 PM UTC 24 |
213248100 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1962063324 |
|
|
Sep 01 07:04:50 PM UTC 24 |
Sep 01 07:05:14 PM UTC 24 |
116623400 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1330386688 |
|
|
Sep 01 07:04:54 PM UTC 24 |
Sep 01 07:05:16 PM UTC 24 |
12787000 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3053613884 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:05:17 PM UTC 24 |
98379000 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.4082408829 |
|
|
Sep 01 07:04:54 PM UTC 24 |
Sep 01 07:05:18 PM UTC 24 |
37724700 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2401554907 |
|
|
Sep 01 07:04:24 PM UTC 24 |
Sep 01 07:05:18 PM UTC 24 |
1583300700 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2943076445 |
|
|
Sep 01 07:04:53 PM UTC 24 |
Sep 01 07:05:19 PM UTC 24 |
672155400 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1169318586 |
|
|
Sep 01 07:04:04 PM UTC 24 |
Sep 01 07:05:19 PM UTC 24 |
2640392500 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1663712166 |
|
|
Sep 01 07:05:01 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
24627800 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2417133674 |
|
|
Sep 01 07:05:01 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
66605500 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3684139719 |
|
|
Sep 01 07:04:58 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
137650500 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1825947468 |
|
|
Sep 01 07:04:51 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
72700800 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3051418210 |
|
|
Sep 01 07:04:57 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
65976500 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3514704999 |
|
|
Sep 01 07:04:30 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
125159800 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1415854029 |
|
|
Sep 01 07:04:16 PM UTC 24 |
Sep 01 07:05:20 PM UTC 24 |
1484526300 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2145089713 |
|
|
Sep 01 07:04:54 PM UTC 24 |
Sep 01 07:05:22 PM UTC 24 |
23343600 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3154748799 |
|
|
Sep 01 07:05:01 PM UTC 24 |
Sep 01 07:05:23 PM UTC 24 |
19346200 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1024842086 |
|
|
Sep 01 07:05:04 PM UTC 24 |
Sep 01 07:05:24 PM UTC 24 |
13402300 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1375767328 |
|
|
Sep 01 07:04:48 PM UTC 24 |
Sep 01 07:05:24 PM UTC 24 |
303336400 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.869772656 |
|
|
Sep 01 07:04:53 PM UTC 24 |
Sep 01 07:05:24 PM UTC 24 |
351345300 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3702168210 |
|
|
Sep 01 07:05:01 PM UTC 24 |
Sep 01 07:05:25 PM UTC 24 |
18383700 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.118889237 |
|
|
Sep 01 07:04:39 PM UTC 24 |
Sep 01 07:05:25 PM UTC 24 |
256721100 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.598934148 |
|
|
Sep 01 07:04:58 PM UTC 24 |
Sep 01 07:05:26 PM UTC 24 |
163218500 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.893645877 |
|
|
Sep 01 07:05:03 PM UTC 24 |
Sep 01 07:05:26 PM UTC 24 |
68939400 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4028281509 |
|
|
Sep 01 07:05:01 PM UTC 24 |
Sep 01 07:05:27 PM UTC 24 |
354405700 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1412595736 |
|
|
Sep 01 07:05:02 PM UTC 24 |
Sep 01 07:05:27 PM UTC 24 |
175159600 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3175298195 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:05:28 PM UTC 24 |
3077254200 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3000171910 |
|
|
Sep 01 07:05:00 PM UTC 24 |
Sep 01 07:05:28 PM UTC 24 |
61676600 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1773633405 |
|
|
Sep 01 07:05:05 PM UTC 24 |
Sep 01 07:05:28 PM UTC 24 |
57115600 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2380820535 |
|
|
Sep 01 07:05:05 PM UTC 24 |
Sep 01 07:05:28 PM UTC 24 |
60214500 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.75381920 |
|
|
Sep 01 07:05:05 PM UTC 24 |
Sep 01 07:05:29 PM UTC 24 |
19274600 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1601957863 |
|
|
Sep 01 07:04:08 PM UTC 24 |
Sep 01 07:05:30 PM UTC 24 |
6196999100 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4126573371 |
|
|
Sep 01 07:05:02 PM UTC 24 |
Sep 01 07:05:30 PM UTC 24 |
61526100 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.171806931 |
|
|
Sep 01 07:05:12 PM UTC 24 |
Sep 01 07:05:32 PM UTC 24 |
16115100 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3125883988 |
|
|
Sep 01 07:05:14 PM UTC 24 |
Sep 01 07:05:32 PM UTC 24 |
18224400 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2129735427 |
|
|
Sep 01 07:04:51 PM UTC 24 |
Sep 01 07:05:33 PM UTC 24 |
242095700 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2628464866 |
|
|
Sep 01 07:05:08 PM UTC 24 |
Sep 01 07:05:33 PM UTC 24 |
11479700 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3620027693 |
|
|
Sep 01 07:05:12 PM UTC 24 |
Sep 01 07:05:34 PM UTC 24 |
34785200 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2119109202 |
|
|
Sep 01 07:05:17 PM UTC 24 |
Sep 01 07:05:35 PM UTC 24 |
16086200 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1904944776 |
|
|
Sep 01 07:04:24 PM UTC 24 |
Sep 01 07:05:35 PM UTC 24 |
84963400 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1964978571 |
|
|
Sep 01 07:05:13 PM UTC 24 |
Sep 01 07:05:35 PM UTC 24 |
200559000 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2715361146 |
|
|
Sep 01 07:05:13 PM UTC 24 |
Sep 01 07:05:37 PM UTC 24 |
130488700 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2379910741 |
|
|
Sep 01 07:05:07 PM UTC 24 |
Sep 01 07:05:38 PM UTC 24 |
114459500 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1060223798 |
|
|
Sep 01 07:05:13 PM UTC 24 |
Sep 01 07:05:39 PM UTC 24 |
442965800 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4287213995 |
|
|
Sep 01 07:05:18 PM UTC 24 |
Sep 01 07:05:42 PM UTC 24 |
43882300 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.396666187 |
|
|
Sep 01 07:05:21 PM UTC 24 |
Sep 01 07:05:43 PM UTC 24 |
12629300 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1377190009 |
|
|
Sep 01 07:05:21 PM UTC 24 |
Sep 01 07:05:43 PM UTC 24 |
31225000 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.133603760 |
|
|
Sep 01 07:05:22 PM UTC 24 |
Sep 01 07:05:43 PM UTC 24 |
106137300 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1640676350 |
|
|
Sep 01 07:05:15 PM UTC 24 |
Sep 01 07:05:44 PM UTC 24 |
97526600 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2699825789 |
|
|
Sep 01 07:05:19 PM UTC 24 |
Sep 01 07:05:44 PM UTC 24 |
877406300 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4077975128 |
|
|
Sep 01 07:05:22 PM UTC 24 |
Sep 01 07:05:44 PM UTC 24 |
306353400 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3407929052 |
|
|
Sep 01 07:05:22 PM UTC 24 |
Sep 01 07:05:45 PM UTC 24 |
89192700 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.211865118 |
|
|
Sep 01 07:05:21 PM UTC 24 |
Sep 01 07:05:45 PM UTC 24 |
153944200 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.254688256 |
|
|
Sep 01 07:05:19 PM UTC 24 |
Sep 01 07:05:45 PM UTC 24 |
331641200 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4038398663 |
|
|
Sep 01 07:05:19 PM UTC 24 |
Sep 01 07:05:46 PM UTC 24 |
237961400 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1284969149 |
|
|
Sep 01 07:05:29 PM UTC 24 |
Sep 01 07:05:46 PM UTC 24 |
111351300 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2191004318 |
|
|
Sep 01 07:05:13 PM UTC 24 |
Sep 01 07:05:46 PM UTC 24 |
72884600 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.910866538 |
|
|
Sep 01 07:05:25 PM UTC 24 |
Sep 01 07:05:46 PM UTC 24 |
62869300 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1223655472 |
|
|
Sep 01 07:05:22 PM UTC 24 |
Sep 01 07:05:47 PM UTC 24 |
52620400 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1819674067 |
|
|
Sep 01 07:05:29 PM UTC 24 |
Sep 01 07:05:47 PM UTC 24 |
19450600 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2693620529 |
|
|
Sep 01 07:05:05 PM UTC 24 |
Sep 01 07:05:47 PM UTC 24 |
291155000 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1459339558 |
|
|
Sep 01 07:05:24 PM UTC 24 |
Sep 01 07:05:47 PM UTC 24 |
36566600 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2777811164 |
|
|
Sep 01 07:05:25 PM UTC 24 |
Sep 01 07:05:47 PM UTC 24 |
229394700 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1824779501 |
|
|
Sep 01 07:05:25 PM UTC 24 |
Sep 01 07:05:49 PM UTC 24 |
17869500 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4101613723 |
|
|
Sep 01 07:05:25 PM UTC 24 |
Sep 01 07:05:49 PM UTC 24 |
383281400 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1823560167 |
|
|
Sep 01 07:05:29 PM UTC 24 |
Sep 01 07:05:49 PM UTC 24 |
17804900 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.57723822 |
|
|
Sep 01 07:05:25 PM UTC 24 |
Sep 01 07:05:51 PM UTC 24 |
13268100 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3807762964 |
|
|
Sep 01 07:05:29 PM UTC 24 |
Sep 01 07:05:53 PM UTC 24 |
534380900 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1887340321 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:05:54 PM UTC 24 |
28218100 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1439977 |
|
|
Sep 01 07:05:28 PM UTC 24 |
Sep 01 07:05:54 PM UTC 24 |
109478400 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.402519111 |
|
|
Sep 01 07:05:29 PM UTC 24 |
Sep 01 07:05:55 PM UTC 24 |
112167600 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.910446854 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:05:56 PM UTC 24 |
248194000 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.249805170 |
|
|
Sep 01 07:05:28 PM UTC 24 |
Sep 01 07:05:57 PM UTC 24 |
12160300 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.232729949 |
|
|
Sep 01 07:05:38 PM UTC 24 |
Sep 01 07:05:58 PM UTC 24 |
24582300 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3972673667 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:05:58 PM UTC 24 |
14276800 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.355875616 |
|
|
Sep 01 07:05:38 PM UTC 24 |
Sep 01 07:06:00 PM UTC 24 |
168723900 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3620870949 |
|
|
Sep 01 07:05:38 PM UTC 24 |
Sep 01 07:06:00 PM UTC 24 |
47415400 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3323792856 |
|
|
Sep 01 07:05:38 PM UTC 24 |
Sep 01 07:06:01 PM UTC 24 |
35396000 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3453309308 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:06:03 PM UTC 24 |
331379500 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1602121579 |
|
|
Sep 01 07:05:43 PM UTC 24 |
Sep 01 07:06:03 PM UTC 24 |
42184700 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.480734535 |
|
|
Sep 01 07:05:44 PM UTC 24 |
Sep 01 07:06:03 PM UTC 24 |
17115400 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.377375420 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:06:03 PM UTC 24 |
106261200 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2015143838 |
|
|
Sep 01 07:05:44 PM UTC 24 |
Sep 01 07:06:04 PM UTC 24 |
47129300 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2903752901 |
|
|
Sep 01 07:05:44 PM UTC 24 |
Sep 01 07:06:04 PM UTC 24 |
30583800 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3619256793 |
|
|
Sep 01 07:05:44 PM UTC 24 |
Sep 01 07:06:04 PM UTC 24 |
50541700 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3581256823 |
|
|
Sep 01 07:05:45 PM UTC 24 |
Sep 01 07:06:05 PM UTC 24 |
72127400 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.938514416 |
|
|
Sep 01 07:05:34 PM UTC 24 |
Sep 01 07:06:05 PM UTC 24 |
12297400 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3854193085 |
|
|
Sep 01 07:05:30 PM UTC 24 |
Sep 01 07:06:06 PM UTC 24 |
97367500 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.1965334862 |
|
|
Sep 01 07:05:47 PM UTC 24 |
Sep 01 07:06:06 PM UTC 24 |
44732800 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2623400669 |
|
|
Sep 01 07:05:38 PM UTC 24 |
Sep 01 07:06:06 PM UTC 24 |
118266900 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.784373640 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:06 PM UTC 24 |
24981700 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.358328072 |
|
|
Sep 01 07:05:40 PM UTC 24 |
Sep 01 07:06:07 PM UTC 24 |
334273400 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1324046264 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:07 PM UTC 24 |
28331900 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2002800669 |
|
|
Sep 01 07:05:47 PM UTC 24 |
Sep 01 07:06:08 PM UTC 24 |
74206600 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1341875868 |
|
|
Sep 01 07:05:47 PM UTC 24 |
Sep 01 07:06:08 PM UTC 24 |
71390700 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.304394634 |
|
|
Sep 01 07:05:47 PM UTC 24 |
Sep 01 07:06:08 PM UTC 24 |
31665000 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2326081158 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:09 PM UTC 24 |
42298800 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.838227618 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:10 PM UTC 24 |
15062100 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.3549097281 |
|
|
Sep 01 07:05:45 PM UTC 24 |
Sep 01 07:06:10 PM UTC 24 |
30497900 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.923995878 |
|
|
Sep 01 07:05:47 PM UTC 24 |
Sep 01 07:06:10 PM UTC 24 |
31022700 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2286331498 |
|
|
Sep 01 07:05:45 PM UTC 24 |
Sep 01 07:06:10 PM UTC 24 |
44265200 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3388589449 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:11 PM UTC 24 |
43079900 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2290374603 |
|
|
Sep 01 07:05:52 PM UTC 24 |
Sep 01 07:06:12 PM UTC 24 |
55196900 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.571458487 |
|
|
Sep 01 07:05:53 PM UTC 24 |
Sep 01 07:06:13 PM UTC 24 |
52230900 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3089343989 |
|
|
Sep 01 07:05:52 PM UTC 24 |
Sep 01 07:06:13 PM UTC 24 |
92869800 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3990951599 |
|
|
Sep 01 07:05:53 PM UTC 24 |
Sep 01 07:06:14 PM UTC 24 |
43302100 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.209655012 |
|
|
Sep 01 07:05:52 PM UTC 24 |
Sep 01 07:06:15 PM UTC 24 |
31493100 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2542447645 |
|
|
Sep 01 07:05:55 PM UTC 24 |
Sep 01 07:06:15 PM UTC 24 |
91236000 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3522409441 |
|
|
Sep 01 07:05:48 PM UTC 24 |
Sep 01 07:06:15 PM UTC 24 |
22741400 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.4040575751 |
|
|
Sep 01 07:05:56 PM UTC 24 |
Sep 01 07:06:16 PM UTC 24 |
18253200 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.4056584422 |
|
|
Sep 01 07:05:57 PM UTC 24 |
Sep 01 07:06:17 PM UTC 24 |
76203600 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3943053449 |
|
|
Sep 01 07:05:55 PM UTC 24 |
Sep 01 07:06:18 PM UTC 24 |
52862800 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1059162558 |
|
|
Sep 01 07:05:57 PM UTC 24 |
Sep 01 07:06:20 PM UTC 24 |
29643500 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.715940756 |
|
|
Sep 01 07:05:55 PM UTC 24 |
Sep 01 07:06:23 PM UTC 24 |
58465400 ps |