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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.73 93.97 98.31 91.84 98.25 96.89 98.24


Total test records in report: 1271
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T644 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2927083488 Sep 01 07:33:27 PM UTC 24 Sep 01 07:58:38 PM UTC 24 1148576100 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1264749211 Sep 01 07:56:11 PM UTC 24 Sep 01 07:58:39 PM UTC 24 2152785500 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3846645303 Sep 01 07:55:39 PM UTC 24 Sep 01 07:58:50 PM UTC 24 27071800 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2868481856 Sep 01 07:57:17 PM UTC 24 Sep 01 07:58:51 PM UTC 24 39491127500 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3339772584 Sep 01 07:58:52 PM UTC 24 Sep 01 07:59:09 PM UTC 24 99811600 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.3951079994 Sep 01 07:55:54 PM UTC 24 Sep 01 07:59:18 PM UTC 24 35315600 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1186839970 Sep 01 07:57:46 PM UTC 24 Sep 01 07:59:23 PM UTC 24 10036265200 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.904200306 Sep 01 07:55:53 PM UTC 24 Sep 01 07:59:25 PM UTC 24 4101213700 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3459393338 Sep 01 07:51:08 PM UTC 24 Sep 01 07:59:52 PM UTC 24 3775205500 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.916757937 Sep 01 07:58:05 PM UTC 24 Sep 01 07:59:59 PM UTC 24 2436671300 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.1969461420 Sep 01 07:59:09 PM UTC 24 Sep 01 08:00:00 PM UTC 24 29914200 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.419406153 Sep 01 07:45:12 PM UTC 24 Sep 01 08:00:07 PM UTC 24 40127148100 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.2936371970 Sep 01 07:59:18 PM UTC 24 Sep 01 08:00:08 PM UTC 24 28893600 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.2728043309 Sep 01 07:58:07 PM UTC 24 Sep 01 08:00:10 PM UTC 24 1928219700 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.3747064966 Sep 01 07:59:26 PM UTC 24 Sep 01 08:00:12 PM UTC 24 10656100 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3161189888 Sep 01 07:59:24 PM UTC 24 Sep 01 08:00:30 PM UTC 24 79696400 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.540583893 Sep 01 08:00:01 PM UTC 24 Sep 01 08:00:31 PM UTC 24 92754900 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.4013546142 Sep 01 07:51:20 PM UTC 24 Sep 01 08:00:35 PM UTC 24 51912426000 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.3933422311 Sep 01 08:00:00 PM UTC 24 Sep 01 08:00:35 PM UTC 24 87979800 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.99335683 Sep 01 08:00:08 PM UTC 24 Sep 01 08:00:39 PM UTC 24 25478700 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.3569647359 Sep 01 08:00:12 PM UTC 24 Sep 01 08:00:41 PM UTC 24 67941700 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.4199754112 Sep 01 07:56:12 PM UTC 24 Sep 01 08:00:43 PM UTC 24 4003586300 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2516165337 Sep 01 07:56:52 PM UTC 24 Sep 01 08:00:44 PM UTC 24 9675693500 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.2431172469 Sep 01 07:58:16 PM UTC 24 Sep 01 08:01:03 PM UTC 24 9735928600 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.2291047215 Sep 01 07:57:55 PM UTC 24 Sep 01 08:01:03 PM UTC 24 23841100 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2119052010 Sep 01 07:08:54 PM UTC 24 Sep 01 08:01:32 PM UTC 24 1640092000 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.3374621691 Sep 01 07:59:53 PM UTC 24 Sep 01 08:01:34 PM UTC 24 3005841700 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1097025124 Sep 01 07:58:06 PM UTC 24 Sep 01 08:01:36 PM UTC 24 323302600 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2506256019 Sep 01 07:30:08 PM UTC 24 Sep 01 08:01:49 PM UTC 24 557707400 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.1829515827 Sep 01 07:06:08 PM UTC 24 Sep 01 08:01:50 PM UTC 24 20893762600 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.2608540046 Sep 01 08:00:36 PM UTC 24 Sep 01 08:02:16 PM UTC 24 1467603700 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1694375334 Sep 01 08:00:43 PM UTC 24 Sep 01 08:02:22 PM UTC 24 2106937100 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.4045228543 Sep 01 07:58:03 PM UTC 24 Sep 01 08:02:38 PM UTC 24 55364600 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1196009790 Sep 01 08:01:51 PM UTC 24 Sep 01 08:02:47 PM UTC 24 44304600 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3749810018 Sep 01 08:01:51 PM UTC 24 Sep 01 08:02:56 PM UTC 24 84560200 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3470921477 Sep 01 07:58:12 PM UTC 24 Sep 01 08:03:04 PM UTC 24 2780935400 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.3478690891 Sep 01 08:02:22 PM UTC 24 Sep 01 08:03:05 PM UTC 24 34809200 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.553335090 Sep 01 07:56:31 PM UTC 24 Sep 01 08:03:13 PM UTC 24 14584154100 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1916061727 Sep 01 08:02:57 PM UTC 24 Sep 01 08:03:16 PM UTC 24 26168600 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3343890965 Sep 01 07:41:26 PM UTC 24 Sep 01 08:03:16 PM UTC 24 724927100 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.3126828203 Sep 01 08:02:17 PM UTC 24 Sep 01 08:03:16 PM UTC 24 80100100 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.665982693 Sep 01 08:02:47 PM UTC 24 Sep 01 08:03:18 PM UTC 24 16015500 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1964640295 Sep 01 07:58:40 PM UTC 24 Sep 01 08:03:19 PM UTC 24 1831235900 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.1854261641 Sep 01 08:00:39 PM UTC 24 Sep 01 08:03:24 PM UTC 24 86257000 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.609979673 Sep 01 08:00:08 PM UTC 24 Sep 01 08:03:26 PM UTC 24 10012782400 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2833470223 Sep 01 08:01:04 PM UTC 24 Sep 01 08:03:29 PM UTC 24 998184200 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.766666062 Sep 01 08:03:05 PM UTC 24 Sep 01 08:03:34 PM UTC 24 19484900 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.2752709463 Sep 01 07:58:06 PM UTC 24 Sep 01 08:03:34 PM UTC 24 32573565100 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.1014600651 Sep 01 08:03:14 PM UTC 24 Sep 01 08:03:44 PM UTC 24 52636400 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.3728542214 Sep 01 08:00:45 PM UTC 24 Sep 01 08:03:46 PM UTC 24 10463142100 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3356224889 Sep 01 07:55:52 PM UTC 24 Sep 01 08:03:46 PM UTC 24 210765100 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1149842358 Sep 01 07:58:51 PM UTC 24 Sep 01 08:03:51 PM UTC 24 35132045200 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2028266582 Sep 01 08:00:13 PM UTC 24 Sep 01 08:04:07 PM UTC 24 79360700 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3843601326 Sep 01 08:03:06 PM UTC 24 Sep 01 08:04:09 PM UTC 24 10036597500 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.2831479127 Sep 01 08:01:33 PM UTC 24 Sep 01 08:04:13 PM UTC 24 1726889400 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.4105422041 Sep 01 07:09:00 PM UTC 24 Sep 01 08:04:14 PM UTC 24 15688782600 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.938989516 Sep 01 08:03:51 PM UTC 24 Sep 01 08:04:17 PM UTC 24 32060800 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.146179447 Sep 01 08:02:38 PM UTC 24 Sep 01 08:04:19 PM UTC 24 8798076300 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.2401460083 Sep 01 07:48:23 PM UTC 24 Sep 01 08:04:26 PM UTC 24 80137857900 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1910996112 Sep 01 07:50:48 PM UTC 24 Sep 01 08:04:27 PM UTC 24 160179163200 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.735052218 Sep 01 07:53:30 PM UTC 24 Sep 01 08:04:32 PM UTC 24 3622710100 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2680922953 Sep 01 08:04:14 PM UTC 24 Sep 01 08:04:41 PM UTC 24 29258800 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1759959180 Sep 01 08:04:20 PM UTC 24 Sep 01 08:04:53 PM UTC 24 39549200 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.3985668720 Sep 01 08:04:27 PM UTC 24 Sep 01 08:04:53 PM UTC 24 42544700 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3652034851 Sep 01 08:04:28 PM UTC 24 Sep 01 08:04:54 PM UTC 24 26651600 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.619979988 Sep 01 07:50:40 PM UTC 24 Sep 01 08:04:58 PM UTC 24 131441200 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1839881068 Sep 01 08:04:08 PM UTC 24 Sep 01 08:04:59 PM UTC 24 142143600 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.2644756870 Sep 01 07:55:55 PM UTC 24 Sep 01 08:05:03 PM UTC 24 9290149600 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.670405742 Sep 01 08:01:37 PM UTC 24 Sep 01 08:05:05 PM UTC 24 2215548900 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2743529139 Sep 01 08:04:10 PM UTC 24 Sep 01 08:05:07 PM UTC 24 28492300 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3039984622 Sep 01 08:03:30 PM UTC 24 Sep 01 08:05:10 PM UTC 24 4166762700 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.2744018491 Sep 01 08:04:42 PM UTC 24 Sep 01 08:05:10 PM UTC 24 51068800 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.96181969 Sep 01 08:04:13 PM UTC 24 Sep 01 08:05:13 PM UTC 24 378101200 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3042374092 Sep 01 07:52:57 PM UTC 24 Sep 01 08:05:23 PM UTC 24 128324100 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3766430002 Sep 01 07:41:02 PM UTC 24 Sep 01 08:05:32 PM UTC 24 5548137400 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3907626868 Sep 01 08:04:18 PM UTC 24 Sep 01 08:05:38 PM UTC 24 377668400 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3166010591 Sep 01 08:03:36 PM UTC 24 Sep 01 08:05:39 PM UTC 24 998943100 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3884014357 Sep 01 08:01:35 PM UTC 24 Sep 01 08:05:48 PM UTC 24 26502524800 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3083733487 Sep 01 08:03:16 PM UTC 24 Sep 01 08:05:56 PM UTC 24 236437700 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2965179583 Sep 01 07:08:36 PM UTC 24 Sep 01 08:05:59 PM UTC 24 239376370500 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1279117016 Sep 01 08:05:39 PM UTC 24 Sep 01 08:06:10 PM UTC 24 19953200 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.102611586 Sep 01 08:05:40 PM UTC 24 Sep 01 08:06:16 PM UTC 24 40875100 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.3477347615 Sep 01 08:05:08 PM UTC 24 Sep 01 08:06:16 PM UTC 24 6475000700 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2830418541 Sep 01 08:06:12 PM UTC 24 Sep 01 08:06:42 PM UTC 24 14610000 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1008586073 Sep 01 08:06:00 PM UTC 24 Sep 01 08:06:43 PM UTC 24 10012500 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3779934430 Sep 01 08:03:18 PM UTC 24 Sep 01 08:06:43 PM UTC 24 9901175300 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.3775855379 Sep 01 08:06:17 PM UTC 24 Sep 01 08:06:44 PM UTC 24 25703500 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.1574666152 Sep 01 07:56:11 PM UTC 24 Sep 01 08:06:45 PM UTC 24 9938557700 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1500552458 Sep 01 08:06:17 PM UTC 24 Sep 01 08:06:46 PM UTC 24 25434400 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1552375426 Sep 01 08:05:50 PM UTC 24 Sep 01 08:06:48 PM UTC 24 33069200 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.2776650072 Sep 01 08:05:11 PM UTC 24 Sep 01 08:06:55 PM UTC 24 1030928800 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3842881660 Sep 01 08:03:47 PM UTC 24 Sep 01 08:06:56 PM UTC 24 1953693300 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.3791739978 Sep 01 08:05:57 PM UTC 24 Sep 01 08:06:57 PM UTC 24 69444200 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1393942664 Sep 01 08:03:35 PM UTC 24 Sep 01 08:07:02 PM UTC 24 14321028200 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.993445955 Sep 01 08:04:33 PM UTC 24 Sep 01 08:07:07 PM UTC 24 10018745100 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.3137575479 Sep 01 08:06:44 PM UTC 24 Sep 01 08:07:09 PM UTC 24 27756100 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.4281052357 Sep 01 07:13:57 PM UTC 24 Sep 01 08:07:12 PM UTC 24 226521847300 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1975057467 Sep 01 08:03:27 PM UTC 24 Sep 01 08:07:17 PM UTC 24 16856150700 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.2087351536 Sep 01 07:50:39 PM UTC 24 Sep 01 08:07:24 PM UTC 24 279025800 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.848981969 Sep 01 08:06:11 PM UTC 24 Sep 01 08:07:50 PM UTC 24 10341429500 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.3615137102 Sep 01 08:07:25 PM UTC 24 Sep 01 08:07:55 PM UTC 24 22541300 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.853067633 Sep 01 08:03:25 PM UTC 24 Sep 01 08:07:55 PM UTC 24 77170100 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.2966581551 Sep 01 08:05:11 PM UTC 24 Sep 01 08:08:00 PM UTC 24 3414567000 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.2481710336 Sep 01 08:04:53 PM UTC 24 Sep 01 08:08:10 PM UTC 24 60582900 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.533992333 Sep 01 08:06:46 PM UTC 24 Sep 01 08:08:13 PM UTC 24 49581400 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.1383936953 Sep 01 08:03:17 PM UTC 24 Sep 01 08:08:27 PM UTC 24 53454200 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1104379065 Sep 01 08:03:48 PM UTC 24 Sep 01 08:08:33 PM UTC 24 23928843000 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.2334802672 Sep 01 08:06:47 PM UTC 24 Sep 01 08:08:33 PM UTC 24 1042560900 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.297376750 Sep 01 08:08:00 PM UTC 24 Sep 01 08:08:38 PM UTC 24 13107500 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.4249197526 Sep 01 08:08:14 PM UTC 24 Sep 01 08:08:42 PM UTC 24 50426400 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.2549250615 Sep 01 08:06:58 PM UTC 24 Sep 01 08:08:45 PM UTC 24 4650482900 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.3182979288 Sep 01 08:08:28 PM UTC 24 Sep 01 08:08:53 PM UTC 24 15518900 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.3299045670 Sep 01 08:07:56 PM UTC 24 Sep 01 08:08:53 PM UTC 24 31863700 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.1466020354 Sep 01 08:07:51 PM UTC 24 Sep 01 08:08:57 PM UTC 24 59939000 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.144492226 Sep 01 08:08:39 PM UTC 24 Sep 01 08:08:57 PM UTC 24 105961600 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.233692715 Sep 01 08:05:24 PM UTC 24 Sep 01 08:08:59 PM UTC 24 1629086100 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3269558119 Sep 01 08:08:34 PM UTC 24 Sep 01 08:08:59 PM UTC 24 16467200 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.3554657656 Sep 01 08:04:59 PM UTC 24 Sep 01 08:09:00 PM UTC 24 5578159200 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.104556826 Sep 01 08:07:08 PM UTC 24 Sep 01 08:09:02 PM UTC 24 1039813300 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1416835984 Sep 01 08:07:56 PM UTC 24 Sep 01 08:09:03 PM UTC 24 405049600 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1196647771 Sep 01 08:01:05 PM UTC 24 Sep 01 08:09:13 PM UTC 24 6297752000 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1621079494 Sep 01 08:05:05 PM UTC 24 Sep 01 08:09:13 PM UTC 24 94948100 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2516215355 Sep 01 07:18:58 PM UTC 24 Sep 01 08:09:16 PM UTC 24 325644453500 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1167143985 Sep 01 08:00:42 PM UTC 24 Sep 01 08:09:35 PM UTC 24 18709352000 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.1756948466 Sep 01 08:08:10 PM UTC 24 Sep 01 08:09:41 PM UTC 24 644133200 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.315871885 Sep 01 07:53:11 PM UTC 24 Sep 01 08:09:42 PM UTC 24 160178534400 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2406872050 Sep 01 08:06:44 PM UTC 24 Sep 01 08:09:47 PM UTC 24 10013386300 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.3823690692 Sep 01 08:09:25 PM UTC 24 Sep 01 08:09:53 PM UTC 24 28715500 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2123828850 Sep 01 08:08:34 PM UTC 24 Sep 01 08:09:58 PM UTC 24 10105104100 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.1626978559 Sep 01 08:03:17 PM UTC 24 Sep 01 08:10:06 PM UTC 24 205790100 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1955494747 Sep 01 08:04:55 PM UTC 24 Sep 01 08:10:10 PM UTC 24 714373500 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.1129482365 Sep 01 08:06:56 PM UTC 24 Sep 01 08:10:11 PM UTC 24 40138600 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2160103644 Sep 01 07:58:39 PM UTC 24 Sep 01 08:10:14 PM UTC 24 19105723800 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1116961603 Sep 01 08:09:35 PM UTC 24 Sep 01 08:10:17 PM UTC 24 42885700 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.4077082701 Sep 01 08:09:26 PM UTC 24 Sep 01 08:10:18 PM UTC 24 77359400 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.3669544195 Sep 01 08:07:13 PM UTC 24 Sep 01 08:10:19 PM UTC 24 1633566700 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1689460448 Sep 01 08:09:44 PM UTC 24 Sep 01 08:10:25 PM UTC 24 75844400 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3513378704 Sep 01 08:09:59 PM UTC 24 Sep 01 08:10:26 PM UTC 24 48680600 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2026187252 Sep 01 08:09:43 PM UTC 24 Sep 01 08:10:26 PM UTC 24 158572200 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.2411514735 Sep 01 08:09:54 PM UTC 24 Sep 01 08:10:28 PM UTC 24 41711100 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.1291565044 Sep 01 08:10:06 PM UTC 24 Sep 01 08:10:31 PM UTC 24 48073500 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.962456430 Sep 01 08:10:11 PM UTC 24 Sep 01 08:10:44 PM UTC 24 63685800 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2061054875 Sep 01 08:00:32 PM UTC 24 Sep 01 08:10:50 PM UTC 24 507976100 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.3015484753 Sep 01 08:08:56 PM UTC 24 Sep 01 08:10:56 PM UTC 24 3703473300 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.4029877687 Sep 01 08:07:04 PM UTC 24 Sep 01 08:11:00 PM UTC 24 4802905500 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.2233627626 Sep 01 08:09:03 PM UTC 24 Sep 01 08:11:10 PM UTC 24 2616465600 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.654824916 Sep 01 08:10:46 PM UTC 24 Sep 01 08:11:12 PM UTC 24 50211800 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4265493135 Sep 01 08:10:29 PM UTC 24 Sep 01 08:11:15 PM UTC 24 11265800 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.4237167753 Sep 01 08:05:06 PM UTC 24 Sep 01 08:11:16 PM UTC 24 24385235700 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.2919594696 Sep 01 08:09:00 PM UTC 24 Sep 01 08:11:16 PM UTC 24 5376415200 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.994557145 Sep 01 08:10:51 PM UTC 24 Sep 01 08:11:19 PM UTC 24 35417400 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.83697675 Sep 01 08:10:27 PM UTC 24 Sep 01 08:11:22 PM UTC 24 38514900 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.4262183163 Sep 01 07:14:18 PM UTC 24 Sep 01 08:11:27 PM UTC 24 14534375100 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2444648953 Sep 01 08:10:32 PM UTC 24 Sep 01 08:11:34 PM UTC 24 914155500 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.741734758 Sep 01 08:10:18 PM UTC 24 Sep 01 08:11:35 PM UTC 24 631846200 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.713249043 Sep 01 08:10:29 PM UTC 24 Sep 01 08:11:35 PM UTC 24 33036900 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.991755842 Sep 01 08:09:48 PM UTC 24 Sep 01 08:11:36 PM UTC 24 6963769000 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1168810530 Sep 01 08:11:22 PM UTC 24 Sep 01 08:12:03 PM UTC 24 23987700 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.4099821462 Sep 01 08:06:44 PM UTC 24 Sep 01 08:12:04 PM UTC 24 62450000 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.2351754395 Sep 01 08:11:36 PM UTC 24 Sep 01 08:12:07 PM UTC 24 162049100 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.4187524996 Sep 01 08:11:35 PM UTC 24 Sep 01 08:12:09 PM UTC 24 15454900 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.1253200535 Sep 01 08:11:20 PM UTC 24 Sep 01 08:12:10 PM UTC 24 50083200 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.3044586003 Sep 01 08:11:17 PM UTC 24 Sep 01 08:12:11 PM UTC 24 43291300 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1553784519 Sep 01 08:11:17 PM UTC 24 Sep 01 08:12:12 PM UTC 24 468229300 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.3515825569 Sep 01 08:09:00 PM UTC 24 Sep 01 08:12:13 PM UTC 24 9577722000 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.112743533 Sep 01 08:00:31 PM UTC 24 Sep 01 08:12:19 PM UTC 24 54819500 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1206627392 Sep 01 08:10:10 PM UTC 24 Sep 01 08:12:26 PM UTC 24 10012328300 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1994241488 Sep 01 08:03:45 PM UTC 24 Sep 01 08:12:33 PM UTC 24 4293909500 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1148090522 Sep 01 08:05:33 PM UTC 24 Sep 01 08:12:33 PM UTC 24 13529960500 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3384832940 Sep 01 08:12:09 PM UTC 24 Sep 01 08:12:37 PM UTC 24 37521500 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1416965731 Sep 01 08:08:43 PM UTC 24 Sep 01 08:12:38 PM UTC 24 24755700 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.371414894 Sep 01 07:55:54 PM UTC 24 Sep 01 08:12:39 PM UTC 24 240192705200 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.3060046439 Sep 01 08:12:13 PM UTC 24 Sep 01 08:12:39 PM UTC 24 22207300 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.830276557 Sep 01 08:09:14 PM UTC 24 Sep 01 08:12:42 PM UTC 24 5883086900 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3463731591 Sep 01 07:14:16 PM UTC 24 Sep 01 08:12:43 PM UTC 24 1106809700 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.4133557516 Sep 01 08:11:00 PM UTC 24 Sep 01 08:12:46 PM UTC 24 7477574300 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.1902570907 Sep 01 08:12:20 PM UTC 24 Sep 01 08:12:47 PM UTC 24 21706300 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3046998664 Sep 01 08:12:11 PM UTC 24 Sep 01 08:12:50 PM UTC 24 45366700 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3343667739 Sep 01 08:12:27 PM UTC 24 Sep 01 08:12:52 PM UTC 24 24912000 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1893291395 Sep 01 08:09:00 PM UTC 24 Sep 01 08:12:54 PM UTC 24 9245333800 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.1917281688 Sep 01 08:11:28 PM UTC 24 Sep 01 08:12:57 PM UTC 24 422149500 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.548965000 Sep 01 08:08:58 PM UTC 24 Sep 01 08:13:02 PM UTC 24 138632300 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.4265320862 Sep 01 08:10:20 PM UTC 24 Sep 01 08:13:03 PM UTC 24 3864618800 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.3475670840 Sep 01 08:12:41 PM UTC 24 Sep 01 08:13:07 PM UTC 24 21631600 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.3626243678 Sep 01 07:19:00 PM UTC 24 Sep 01 08:13:12 PM UTC 24 451657900 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.116287238 Sep 01 08:10:15 PM UTC 24 Sep 01 08:13:17 PM UTC 24 32087800 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.401278236 Sep 01 08:12:44 PM UTC 24 Sep 01 08:13:18 PM UTC 24 28069000 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.3733718839 Sep 01 08:12:53 PM UTC 24 Sep 01 08:13:18 PM UTC 24 61786400 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.705357043 Sep 01 08:12:51 PM UTC 24 Sep 01 08:13:18 PM UTC 24 49345600 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3411164757 Sep 01 08:12:47 PM UTC 24 Sep 01 08:13:34 PM UTC 24 10648600 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3211047687 Sep 01 08:12:43 PM UTC 24 Sep 01 08:13:37 PM UTC 24 29464100 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.385644532 Sep 01 08:13:12 PM UTC 24 Sep 01 08:13:39 PM UTC 24 19990600 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.384373296 Sep 01 08:12:14 PM UTC 24 Sep 01 08:13:41 PM UTC 24 4390456500 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1399955652 Sep 01 08:09:13 PM UTC 24 Sep 01 08:13:46 PM UTC 24 6854101600 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.3267060349 Sep 01 08:13:19 PM UTC 24 Sep 01 08:13:48 PM UTC 24 84473800 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.77884949 Sep 01 07:25:20 PM UTC 24 Sep 01 08:13:52 PM UTC 24 179892057000 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.3992659531 Sep 01 08:13:35 PM UTC 24 Sep 01 08:13:53 PM UTC 24 37012300 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2682025939 Sep 01 08:12:47 PM UTC 24 Sep 01 08:13:54 PM UTC 24 5681640700 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3373295268 Sep 01 08:10:19 PM UTC 24 Sep 01 08:13:56 PM UTC 24 71417900 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.2780611655 Sep 01 08:13:19 PM UTC 24 Sep 01 08:13:57 PM UTC 24 51522600 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4209894932 Sep 01 08:10:26 PM UTC 24 Sep 01 08:14:00 PM UTC 24 23993303900 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.1384143485 Sep 01 08:10:57 PM UTC 24 Sep 01 08:14:01 PM UTC 24 20951900 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.2498524956 Sep 01 08:13:18 PM UTC 24 Sep 01 08:14:04 PM UTC 24 30138900 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.3922176751 Sep 01 08:05:14 PM UTC 24 Sep 01 08:14:06 PM UTC 24 13639599700 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.2111057091 Sep 01 08:13:14 PM UTC 24 Sep 01 08:14:07 PM UTC 24 28621900 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.266827696 Sep 01 08:13:57 PM UTC 24 Sep 01 08:14:15 PM UTC 24 296423900 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.2078902131 Sep 01 08:11:36 PM UTC 24 Sep 01 08:14:19 PM UTC 24 26727100 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1540767543 Sep 01 08:10:27 PM UTC 24 Sep 01 08:14:19 PM UTC 24 2247968900 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.2116590442 Sep 01 07:58:05 PM UTC 24 Sep 01 08:14:19 PM UTC 24 160179583700 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3784125045 Sep 01 08:12:33 PM UTC 24 Sep 01 08:14:26 PM UTC 24 3007426000 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3978165967 Sep 01 08:07:18 PM UTC 24 Sep 01 08:14:27 PM UTC 24 38257627900 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.2583763970 Sep 01 08:11:10 PM UTC 24 Sep 01 08:14:28 PM UTC 24 37083500 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.603841207 Sep 01 08:14:02 PM UTC 24 Sep 01 08:14:30 PM UTC 24 69833500 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2549358437 Sep 01 07:48:16 PM UTC 24 Sep 01 08:14:31 PM UTC 24 217991100 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.446277856 Sep 01 08:14:01 PM UTC 24 Sep 01 08:14:32 PM UTC 24 21259200 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1297975918 Sep 01 07:19:07 PM UTC 24 Sep 01 08:14:38 PM UTC 24 23488070900 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3852222751 Sep 01 08:13:58 PM UTC 24 Sep 01 08:14:40 PM UTC 24 27602300 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3982620762 Sep 01 08:13:58 PM UTC 24 Sep 01 08:14:41 PM UTC 24 27767900 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.3944052209 Sep 01 08:13:19 PM UTC 24 Sep 01 08:14:42 PM UTC 24 6025906900 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.936406263 Sep 01 08:12:05 PM UTC 24 Sep 01 08:14:50 PM UTC 24 1907527600 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.3173963926 Sep 01 08:14:21 PM UTC 24 Sep 01 08:14:50 PM UTC 24 21986100 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.4287226301 Sep 01 08:13:58 PM UTC 24 Sep 01 08:14:52 PM UTC 24 125083100 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2394888210 Sep 01 08:14:32 PM UTC 24 Sep 01 08:14:53 PM UTC 24 72500100 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.457856383 Sep 01 08:13:38 PM UTC 24 Sep 01 08:14:56 PM UTC 24 30415200 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2515096550 Sep 01 08:11:37 PM UTC 24 Sep 01 08:15:00 PM UTC 24 11858933800 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.3069739354 Sep 01 08:14:30 PM UTC 24 Sep 01 08:15:00 PM UTC 24 25648200 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2438539773 Sep 01 08:11:12 PM UTC 24 Sep 01 08:15:01 PM UTC 24 3009124800 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4168402970 Sep 01 08:12:07 PM UTC 24 Sep 01 08:15:04 PM UTC 24 5882044200 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.2320942136 Sep 01 08:14:28 PM UTC 24 Sep 01 08:15:05 PM UTC 24 12021900 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.1170921892 Sep 01 08:12:58 PM UTC 24 Sep 01 08:15:05 PM UTC 24 10807007900 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.4001927073 Sep 01 08:14:21 PM UTC 24 Sep 01 08:15:06 PM UTC 24 41752200 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4130259514 Sep 01 07:06:07 PM UTC 24 Sep 01 08:15:09 PM UTC 24 232816464000 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.384645142 Sep 01 08:06:58 PM UTC 24 Sep 01 08:15:15 PM UTC 24 6760550400 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1180219536 Sep 01 08:13:58 PM UTC 24 Sep 01 08:15:16 PM UTC 24 6199412400 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.3882666584 Sep 01 08:14:26 PM UTC 24 Sep 01 08:15:17 PM UTC 24 28920800 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3407220178 Sep 01 08:15:01 PM UTC 24 Sep 01 08:15:21 PM UTC 24 13416900 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.182226525 Sep 01 08:15:01 PM UTC 24 Sep 01 08:15:25 PM UTC 24 105731400 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.1386925325 Sep 01 08:12:39 PM UTC 24 Sep 01 08:15:28 PM UTC 24 3706821100 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.485565358 Sep 01 08:14:06 PM UTC 24 Sep 01 08:15:29 PM UTC 24 3116538600 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.4282838382 Sep 01 08:14:54 PM UTC 24 Sep 01 08:15:31 PM UTC 24 10559100 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.4172679796 Sep 01 08:14:51 PM UTC 24 Sep 01 08:15:35 PM UTC 24 44163600 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.617015049 Sep 01 08:15:18 PM UTC 24 Sep 01 08:15:38 PM UTC 24 26052400 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2468146505 Sep 01 07:45:27 PM UTC 24 Sep 01 08:15:40 PM UTC 24 6292925900 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.791810654 Sep 01 08:15:26 PM UTC 24 Sep 01 08:15:46 PM UTC 24 54694600 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.2947574634 Sep 01 08:15:29 PM UTC 24 Sep 01 08:15:48 PM UTC 24 112674500 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.811642676 Sep 01 08:14:52 PM UTC 24 Sep 01 08:15:49 PM UTC 24 45330900 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.904689913 Sep 01 08:12:38 PM UTC 24 Sep 01 08:15:49 PM UTC 24 74993400 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.2993923524 Sep 01 08:15:20 PM UTC 24 Sep 01 08:15:52 PM UTC 24 31261100 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1007674736 Sep 01 08:13:07 PM UTC 24 Sep 01 08:15:58 PM UTC 24 35164181300 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.3319439533 Sep 01 08:15:20 PM UTC 24 Sep 01 08:15:58 PM UTC 24 50571400 ps
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