FLASH_CTRL Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.799m	2.807ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	48.140s	26.367us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	55.660s	113.557us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.471m	2.179ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.323m	1.653ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	30.180s	419.840us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
		flash_ctrl_csr_aliasing	1.323m	1.653ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	29.180s	17.650us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	29.690s	52.207us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	46.320s	255.797us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.879m	229.433us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	53.961m	1.333s	3	3	100.00
		flash_ctrl_hw_rma_reset	18.790m	350.244ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.840s	34.712us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	54.830m	244.222ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.344m	3.356ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.601m	4.805ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	55.085m	53.804ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.394m	771.022us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.048m	228.093us	38	40	95.00
		flash_ctrl_rw_evict_all_en	1.026m	28.360us	38	40	95.00
		flash_ctrl_re_evict	1.110m	66.892us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.239m	763.603us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.239m	763.603us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	14.423m	13.420ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	45.940s	1.832ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	33.201m	1.491ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	52.323m	18.659ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	25.011m	1.622ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	53.477m	2.770ms	2	5	40.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	26.060s	26.385us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.763m	2.776ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	43.130s	10.497us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.730s	46.758us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	38.309m	4.710ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.635m	10.725ms	50	50	100.00
		flash_ctrl_otp_reset	4.114m	39.011us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	53.961m	1.333s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.274m	4.727ms	39	40	97.50
		flash_ctrl_intr_wr	1.601m	4.398ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.817m	20.042ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.331m	252.923ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.779m	3.625ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.395m	10.641ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	44.630s	153.774us	5	5	100.00
		flash_ctrl_ro_derr	2.889m	685.059us	10	10	100.00
		flash_ctrl_rw_derr	4.333m	2.967ms	10	10	100.00
		flash_ctrl_derr_detect	4.843m	709.819us	5	5	100.00
		flash_ctrl_integrity	8.852m	15.635ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	41.530s	92.156us	5	5	100.00
		flash_ctrl_ro_serr	2.761m	520.601us	10	10	100.00
		flash_ctrl_rw_serr	4.222m	3.195ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.802m	1.515ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.150m	10.023ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.858m	28.932ms	19	20	95.00
		flash_ctrl_write_word_sweep	29.980s	170.601us	1	1	100.00
		flash_ctrl_read_word_sweep	30.440s	74.622us	1	1	100.00
		flash_ctrl_ro	2.439m	1.166ms	20	20	100.00
		flash_ctrl_rw	9.939m	4.274ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	1.061m	4.264ms	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.843m	83.076ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.276m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	30.230s	55.391us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	28.310s	49.579us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	35.650s	208.173us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	35.650s	208.173us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	55.660s	113.557us	5	5	100.00
		flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
		flash_ctrl_csr_aliasing	1.323m	1.653ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	50.560s	166.166us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	55.660s	113.557us	5	5	100.00
		flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
		flash_ctrl_csr_aliasing	1.323m	1.653ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	50.560s	166.166us	20	20	100.00
V2		TOTAL			1001	1013	98.82
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	33.080s	14.115us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
		flash_ctrl_tl_intg_err	24.839m	1.747ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	24.839m	1.747ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	24.839m	1.747ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	56.610s	72.984us	3	3	100.00
		flash_ctrl_wr_intg	29.670s	277.634us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.799m	2.807ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.114m	39.011us	80	80	100.00
		flash_ctrl_disable	43.130s	10.497us	50	50	100.00
		flash_ctrl_sec_info_access	2.225m	24.943ms	50	50	100.00
		flash_ctrl_connect	32.730s	46.758us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	27.520s	22.496us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	32.310s	54.621us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	31.420s	54.074us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	43.130s	10.497us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	56.610s	72.984us	3	3	100.00
		flash_ctrl_access_after_disable	28.210s	21.875us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	46.360s	39.287us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	43.130s	10.497us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	45.940s	1.832ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.939m	4.274ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.222m	3.195ms	10	10	100.00
		flash_ctrl_rw_derr	4.333m	2.967ms	10	10	100.00
		flash_ctrl_integrity	8.852m	15.635ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	53.961m	1.333s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	41.250s	695.745us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	28.660s	25.305us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	28.800s	16.434us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.898h	3.873ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.241m	82.480us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1268	1281	98.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.96	95.25	93.98	98.31	91.84	97.18	96.99	98.18

Failure Buckets

• Job timed out after * minutes has 7 failures:

  • Test flash_ctrl_serr_counter has 1 failures.

    • 0.flash_ctrl_serr_counter.33273582205520250985204417498726139246864392639019299210031062395743772777562
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_error_prog_type has 3 failures.

    • 1.flash_ctrl_error_prog_type.102494197276331117854647828649867813498500803795535853914362770085625559508697
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest/run.log

        Job timed out after 60 minutes
      

    • 2.flash_ctrl_error_prog_type.93303240659211953613981068611980930011090425075133749940833217678345135065544
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 1 more failures.

  • Test flash_ctrl_fs_sup has 1 failures.

    • 1.flash_ctrl_fs_sup.73205801287384715336194717899225789572793686333070958112553068330773219836639
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_integrity has 1 failures.

    • 3.flash_ctrl_integrity.3706906886001005860966875338428329798153350320878211383269684398204711706875
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_wo has 1 failures.

    • 12.flash_ctrl_wo.88875733941239418163716009444615698773342148014965218042281581158618956117947
      Log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict_all_en has 2 failures.

    • 0.flash_ctrl_rw_evict_all_en.25818081281860458206441924002982488341756935091591793764046276881605205658205
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 44393.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 44393.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.flash_ctrl_rw_evict_all_en.64811632866634709459684407479306166315974370112987299508027340632699218531998
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 20301.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 20301.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict has 1 failures.

    • 6.flash_ctrl_rw_evict.23306041365989083147912611996020508538677249671244833965960438379573885899618
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 11084.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 11084.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:

  • Test flash_ctrl_phy_host_grant_err has 1 failures.

    • 4.flash_ctrl_phy_host_grant_err.72642871229921401444657704060027260679384897996406789930005453492460556262594
      Line 112, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log

            Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
        UVM_ERROR @ 20781.3 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
        UVM_INFO @ 20781.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 17.flash_ctrl_rw_evict.16272140119941230510247068647723393203891316575770912647190975379231010367834
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 16071.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 16071.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f81f4e_9658b358:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 25.flash_ctrl_intr_rd.57958918560696760600557513181004361718555348675928520881447492188739241434625
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 5443171.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    67f81f4e_9658b358:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 5443171.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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