FLASH_CTRL Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	6.050m	2.118ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	42.640s	13.819us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.045m	56.383us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.310m	1.237ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.594m	3.238ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	34.350s	158.951us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
		flash_ctrl_csr_aliasing	1.594m	3.238ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	26.990s	17.370us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	26.310s	218.808us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	51.700s	42.107us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.934m	430.140us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.265m	146.249ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.252m	40.124ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.250s	47.285us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	59.164m	277.917ms	4	5	80.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.994m	7.569ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.089m	35.109ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.238h	445.096ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.395m	2.522ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.007m	47.083us	38	40	95.00
		flash_ctrl_rw_evict_all_en	1.009m	252.545us	37	40	92.50
		flash_ctrl_re_evict	1.066m	72.148us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.627m	2.378ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.627m	2.378ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.335m	58.950ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	42.380s	1.679ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	30.402m	956.607us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	55.025m	5.202ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	26.795m	1.136ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.598m	718.568us	3	5	60.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	26.490s	23.422us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.799m	3.043ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.490s	15.208us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.600s	14.861us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	39.499m	4.793ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.643m	41.571ms	50	50	100.00
		flash_ctrl_otp_reset	3.945m	55.493us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.265m	146.249ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.413m	4.965ms	38	40	95.00
		flash_ctrl_intr_wr	1.663m	5.087ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.624m	24.547ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.140m	144.472ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.869m	865.253us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.353m	11.808ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	45.020s	59.713us	5	5	100.00
		flash_ctrl_ro_derr	3.007m	1.102ms	10	10	100.00
		flash_ctrl_rw_derr	4.395m	2.424ms	9	10	90.00
		flash_ctrl_derr_detect	4.144m	742.482us	5	5	100.00
		flash_ctrl_integrity	11.810m	4.238ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	40.680s	40.546us	5	5	100.00
		flash_ctrl_ro_serr	2.445m	998.043us	10	10	100.00
		flash_ctrl_rw_serr	4.497m	1.631ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.585m	727.789us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.115m	3.601ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.475m	4.001ms	19	20	95.00
		flash_ctrl_write_word_sweep	21.090s	268.032us	1	1	100.00
		flash_ctrl_read_word_sweep	18.410s	42.251us	1	1	100.00
		flash_ctrl_ro	2.576m	5.216ms	20	20	100.00
		flash_ctrl_rw	9.649m	4.681ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.036m	1.395ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	21.495m	231.881ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	6.750m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.750s	84.641us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	26.330s	15.353us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	37.690s	908.880us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	37.690s	908.880us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.045m	56.383us	5	5	100.00
		flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
		flash_ctrl_csr_aliasing	1.594m	3.238ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	45.640s	110.672us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.045m	56.383us	5	5	100.00
		flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
		flash_ctrl_csr_aliasing	1.594m	3.238ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	45.640s	110.672us	20	20	100.00
V2		TOTAL			999	1013	98.62
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	29.520s	13.297us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
		flash_ctrl_tl_intg_err	21.971m	8.261ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	21.971m	8.261ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	21.971m	8.261ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	44.030s	1.091ms	3	3	100.00
		flash_ctrl_wr_intg	30.580s	161.876us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	6.050m	2.118ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	3.945m	55.493us	80	80	100.00
		flash_ctrl_disable	45.490s	15.208us	50	50	100.00
		flash_ctrl_sec_info_access	2.330m	30.469ms	50	50	100.00
		flash_ctrl_connect	32.600s	14.861us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	25.930s	30.592us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	32.930s	333.591us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	28.790s	23.530us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.490s	15.208us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	44.030s	1.091ms	3	3	100.00
		flash_ctrl_access_after_disable	28.870s	14.282us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	49.170s	64.692us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.490s	15.208us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	42.380s	1.679ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.649m	4.681ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.497m	1.631ms	10	10	100.00
		flash_ctrl_rw_derr	4.395m	2.424ms	9	10	90.00
		flash_ctrl_integrity	11.810m	4.238ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.265m	146.249ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	37.780s	755.088us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	27.760s	5.983us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	28.420s	110.877us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.950h	6.030ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.083m	277.636us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1266	1281	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	95.24	93.99	98.31	92.52	97.18	96.99	98.21

Failure Buckets

Job timed out after * minutes has 7 failures:
- Test flash_ctrl_error_prog_type has 2 failures.
  - 0.flash_ctrl_error_prog_type.108787423208892535032775178549883965904143627122124368708994080795017011864596
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.flash_ctrl_error_prog_type.37581551209608306074558013553872932950887877283699558836745300022806554150752
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_host_ctrl_arb has 1 failures.
  - 2.flash_ctrl_host_ctrl_arb.23527186743976560269706596568239323444050035798254040575385400393224706655971
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.28666316397444172640267556064552525845838133840981237847767595846432746781630
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 5.flash_ctrl_rw_derr.34907413362503295994716266048719810074270594629666838887773166706542403070005
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw has 1 failures.
  - 9.flash_ctrl_rw.43457348087961466093455960730671350167472358866609731711790863645049406052427
    Log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 1 more tests.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 5 failures:

Test flash_ctrl_rw_evict_all_en has 3 failures.

0.flash_ctrl_rw_evict_all_en.73934374230236813169424297956994785463940656571896220955384301279672418981812
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 12559.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 12559.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_evict_all_en.99945461396331597287844819547152776705867766995264632033889805873777617880612
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 24877.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24877.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test flash_ctrl_rw_evict has 2 failures.

2.flash_ctrl_rw_evict.64984210439607685479143097292629056878281132920481412174729001498269374845353
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 41962.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 41962.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.flash_ctrl_rw_evict.16432675468264742751062814219630730740348599320243805806720495368655742605398
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 11319.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 11319.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 2.flash_ctrl_phy_host_grant_err.41639932288455094062085578010870880167960852743253915976838977592913594931012
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 5983.0 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 5983.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ef4e438_9fd76a3f:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 24.flash_ctrl_intr_rd.15285105904817016999681590811453603612610378263640469349134093335062336637941
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 691255.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    2ef4e438_9fd76a3f:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 691255.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp c69543bc_33b55288:ffffffff_33b* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 39.flash_ctrl_intr_rd.52446319370011863395652627554223468119521013210353549027105712785422010935388
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2807879.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    c69543bc_33b55288:ffffffff_33b55288  mismatch!!
  UVM_INFO @ 2807879.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```