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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.23 93.90 98.31 92.52 97.14 97.08 98.15


Total test records in report: 1262
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T210 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.359723464 Sep 24 06:03:54 PM UTC 24 Sep 24 06:08:48 PM UTC 24 11547652900 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2559436607 Sep 24 06:07:15 PM UTC 24 Sep 24 06:08:56 PM UTC 24 3147150600 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.3092197733 Sep 24 06:06:43 PM UTC 24 Sep 24 06:09:15 PM UTC 24 177866500 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3228734457 Sep 24 06:00:35 PM UTC 24 Sep 24 06:09:43 PM UTC 24 1913224000 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3860402454 Sep 24 06:07:25 PM UTC 24 Sep 24 06:09:53 PM UTC 24 747527200 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.695363120 Sep 24 05:50:04 PM UTC 24 Sep 24 06:10:04 PM UTC 24 108381270300 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.4158795357 Sep 24 06:07:27 PM UTC 24 Sep 24 06:10:05 PM UTC 24 518074700 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.2987295065 Sep 24 06:09:44 PM UTC 24 Sep 24 06:10:06 PM UTC 24 18066000 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3157261298 Sep 24 06:02:48 PM UTC 24 Sep 24 06:10:10 PM UTC 24 6398709300 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2426855917 Sep 24 05:49:41 PM UTC 24 Sep 24 06:10:13 PM UTC 24 383968400 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.14265136 Sep 24 06:07:46 PM UTC 24 Sep 24 06:10:15 PM UTC 24 638944200 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3005841545 Sep 24 06:07:11 PM UTC 24 Sep 24 06:10:22 PM UTC 24 81868900 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.592306642 Sep 24 06:08:49 PM UTC 24 Sep 24 06:10:22 PM UTC 24 8674207300 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3792705790 Sep 24 06:09:54 PM UTC 24 Sep 24 06:10:33 PM UTC 24 44411500 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3483054703 Sep 24 06:10:16 PM UTC 24 Sep 24 06:10:36 PM UTC 24 44505200 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1442683096 Sep 24 06:10:07 PM UTC 24 Sep 24 06:10:38 PM UTC 24 58826500 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.3075100635 Sep 24 05:54:43 PM UTC 24 Sep 24 06:10:42 PM UTC 24 160169531700 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1272465710 Sep 24 06:10:14 PM UTC 24 Sep 24 06:10:43 PM UTC 24 43282900 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1289387036 Sep 24 06:04:59 PM UTC 24 Sep 24 06:10:49 PM UTC 24 80443242300 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.2578715996 Sep 24 06:10:22 PM UTC 24 Sep 24 06:10:51 PM UTC 24 15506300 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2877239806 Sep 24 06:10:34 PM UTC 24 Sep 24 06:10:54 PM UTC 24 24710400 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3389906347 Sep 24 06:10:05 PM UTC 24 Sep 24 06:11:01 PM UTC 24 179244200 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.2799178239 Sep 24 06:10:06 PM UTC 24 Sep 24 06:11:09 PM UTC 24 87656100 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.366223906 Sep 24 06:07:11 PM UTC 24 Sep 24 06:11:14 PM UTC 24 8010036200 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.4286015556 Sep 24 06:07:01 PM UTC 24 Sep 24 06:11:15 PM UTC 24 5398748000 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.3468966759 Sep 24 06:07:39 PM UTC 24 Sep 24 06:11:24 PM UTC 24 5698003400 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.716357546 Sep 24 06:11:01 PM UTC 24 Sep 24 06:11:53 PM UTC 24 599725800 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.4099468291 Sep 24 06:07:20 PM UTC 24 Sep 24 06:11:56 PM UTC 24 9928508300 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3076094918 Sep 24 06:10:11 PM UTC 24 Sep 24 06:12:13 PM UTC 24 3780133400 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3728848672 Sep 24 06:08:57 PM UTC 24 Sep 24 06:12:13 PM UTC 24 24389165200 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2145770627 Sep 24 06:10:37 PM UTC 24 Sep 24 06:12:15 PM UTC 24 96483700 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2426377316 Sep 24 06:10:24 PM UTC 24 Sep 24 06:12:24 PM UTC 24 10012579800 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3411188508 Sep 24 06:08:43 PM UTC 24 Sep 24 06:12:32 PM UTC 24 33260248200 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.2908880948 Sep 24 06:11:16 PM UTC 24 Sep 24 06:12:39 PM UTC 24 1596089700 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.705144834 Sep 24 06:10:44 PM UTC 24 Sep 24 06:12:39 PM UTC 24 4209506400 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3252013066 Sep 24 06:07:49 PM UTC 24 Sep 24 06:12:41 PM UTC 24 7044953700 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.2395149360 Sep 24 06:10:39 PM UTC 24 Sep 24 06:12:57 PM UTC 24 37963100 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2869539140 Sep 24 06:09:16 PM UTC 24 Sep 24 06:13:04 PM UTC 24 92944307700 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1738076501 Sep 24 06:12:58 PM UTC 24 Sep 24 06:13:25 PM UTC 24 18410400 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2715245397 Sep 24 06:10:51 PM UTC 24 Sep 24 06:13:37 PM UTC 24 345268900 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1668222792 Sep 24 05:50:49 PM UTC 24 Sep 24 06:13:38 PM UTC 24 701282300 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.2300937663 Sep 24 06:11:25 PM UTC 24 Sep 24 06:13:40 PM UTC 24 3835293700 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.3100810193 Sep 24 06:06:57 PM UTC 24 Sep 24 06:13:51 PM UTC 24 55674700 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1401885980 Sep 24 06:12:40 PM UTC 24 Sep 24 06:13:57 PM UTC 24 5392516500 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1612607001 Sep 24 06:13:05 PM UTC 24 Sep 24 06:14:00 PM UTC 24 154477100 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1696828755 Sep 24 06:13:39 PM UTC 24 Sep 24 06:14:12 PM UTC 24 31849700 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.175610675 Sep 24 06:11:54 PM UTC 24 Sep 24 06:14:12 PM UTC 24 628635900 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1238261370 Sep 24 05:55:28 PM UTC 24 Sep 24 06:14:22 PM UTC 24 340349900 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.374323421 Sep 24 06:13:58 PM UTC 24 Sep 24 06:14:23 PM UTC 24 26182000 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.584315368 Sep 24 06:13:53 PM UTC 24 Sep 24 06:14:25 PM UTC 24 14907300 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3008975129 Sep 24 06:14:01 PM UTC 24 Sep 24 06:14:26 PM UTC 24 15319200 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.1203287273 Sep 24 06:13:38 PM UTC 24 Sep 24 06:14:37 PM UTC 24 88245400 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4075376783 Sep 24 06:14:13 PM UTC 24 Sep 24 06:14:40 PM UTC 24 205785100 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2136616269 Sep 24 05:54:01 PM UTC 24 Sep 24 06:14:43 PM UTC 24 167198609600 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.1468751158 Sep 24 06:12:16 PM UTC 24 Sep 24 06:15:02 PM UTC 24 5745557300 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2828046739 Sep 24 06:12:33 PM UTC 24 Sep 24 06:15:08 PM UTC 24 1436642500 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3509174855 Sep 24 06:13:41 PM UTC 24 Sep 24 06:15:09 PM UTC 24 2641116300 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3755125869 Sep 24 06:14:44 PM UTC 24 Sep 24 06:15:11 PM UTC 24 1612271300 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1470881039 Sep 24 06:00:45 PM UTC 24 Sep 24 06:15:25 PM UTC 24 40129508900 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1770812655 Sep 24 06:12:14 PM UTC 24 Sep 24 06:15:32 PM UTC 24 877440400 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2978633358 Sep 24 06:04:12 PM UTC 24 Sep 24 06:15:45 PM UTC 24 8412737300 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3869996960 Sep 24 06:10:43 PM UTC 24 Sep 24 06:16:22 PM UTC 24 336948100 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3475873678 Sep 24 06:07:26 PM UTC 24 Sep 24 06:16:43 PM UTC 24 4277796300 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.3916463550 Sep 24 06:12:25 PM UTC 24 Sep 24 06:16:46 PM UTC 24 10859113700 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2917237056 Sep 24 06:15:10 PM UTC 24 Sep 24 06:16:57 PM UTC 24 2682732500 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.199113933 Sep 24 06:12:14 PM UTC 24 Sep 24 06:17:04 PM UTC 24 7955446400 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3004347465 Sep 24 06:12:41 PM UTC 24 Sep 24 06:17:34 PM UTC 24 12342721400 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.4061460160 Sep 24 06:15:26 PM UTC 24 Sep 24 06:17:35 PM UTC 24 1792642400 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3690516612 Sep 24 06:12:42 PM UTC 24 Sep 24 06:17:38 PM UTC 24 38354938800 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.1160644341 Sep 24 05:47:24 PM UTC 24 Sep 24 06:17:39 PM UTC 24 1767297900 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.425983230 Sep 24 06:15:45 PM UTC 24 Sep 24 06:17:41 PM UTC 24 627515700 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3677163002 Sep 24 06:14:26 PM UTC 24 Sep 24 06:17:58 PM UTC 24 2009491500 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3544521125 Sep 24 05:46:46 PM UTC 24 Sep 24 06:18:03 PM UTC 24 448531366000 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.885407850 Sep 24 06:17:40 PM UTC 24 Sep 24 06:18:11 PM UTC 24 35808600 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.3165450070 Sep 24 06:14:22 PM UTC 24 Sep 24 06:18:11 PM UTC 24 24593900 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.377007790 Sep 24 06:17:42 PM UTC 24 Sep 24 06:18:24 PM UTC 24 39527000 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.4071850871 Sep 24 06:14:37 PM UTC 24 Sep 24 06:18:26 PM UTC 24 38645500 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1782654776 Sep 24 06:18:04 PM UTC 24 Sep 24 06:18:41 PM UTC 24 10790700 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2500303415 Sep 24 06:17:04 PM UTC 24 Sep 24 06:18:41 PM UTC 24 4460786900 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1290682816 Sep 24 06:18:12 PM UTC 24 Sep 24 06:18:42 PM UTC 24 14231500 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3127936353 Sep 24 06:17:41 PM UTC 24 Sep 24 06:18:43 PM UTC 24 30251500 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.1662754246 Sep 24 06:18:24 PM UTC 24 Sep 24 06:18:51 PM UTC 24 45410400 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1134793832 Sep 24 06:18:26 PM UTC 24 Sep 24 06:18:52 PM UTC 24 25086400 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1137654051 Sep 24 06:17:59 PM UTC 24 Sep 24 06:18:58 PM UTC 24 227681500 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.380376118 Sep 24 05:46:44 PM UTC 24 Sep 24 06:19:02 PM UTC 24 664884600 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1864769972 Sep 24 06:18:43 PM UTC 24 Sep 24 06:19:07 PM UTC 24 173962500 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.3565644114 Sep 24 06:15:12 PM UTC 24 Sep 24 06:19:08 PM UTC 24 4674499700 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.1061796758 Sep 24 06:18:11 PM UTC 24 Sep 24 06:19:31 PM UTC 24 1958616200 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3777150823 Sep 24 06:19:08 PM UTC 24 Sep 24 06:19:45 PM UTC 24 142324700 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.802495073 Sep 24 06:14:13 PM UTC 24 Sep 24 06:19:49 PM UTC 24 10011936300 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.1393992121 Sep 24 06:16:44 PM UTC 24 Sep 24 06:19:59 PM UTC 24 2508334700 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3499086740 Sep 24 06:18:43 PM UTC 24 Sep 24 06:20:16 PM UTC 24 22620200 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3293896694 Sep 24 06:16:58 PM UTC 24 Sep 24 06:20:19 PM UTC 24 2937147200 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4082141632 Sep 24 06:16:47 PM UTC 24 Sep 24 06:20:32 PM UTC 24 1805960500 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.358754576 Sep 24 06:18:42 PM UTC 24 Sep 24 06:20:43 PM UTC 24 10017865100 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3729602785 Sep 24 06:19:50 PM UTC 24 Sep 24 06:20:55 PM UTC 24 5264914600 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1748130907 Sep 24 06:17:34 PM UTC 24 Sep 24 06:20:58 PM UTC 24 63473305100 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.2830116140 Sep 24 06:07:05 PM UTC 24 Sep 24 06:21:14 PM UTC 24 60141139700 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1862221531 Sep 24 06:14:24 PM UTC 24 Sep 24 06:21:16 PM UTC 24 167463600 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2214451208 Sep 24 05:47:33 PM UTC 24 Sep 24 06:21:16 PM UTC 24 105223770300 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2350385271 Sep 24 06:17:35 PM UTC 24 Sep 24 06:21:23 PM UTC 24 22398119400 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1843864330 Sep 24 06:19:03 PM UTC 24 Sep 24 06:21:54 PM UTC 24 37475400 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.652974040 Sep 24 06:16:23 PM UTC 24 Sep 24 06:21:57 PM UTC 24 6083477300 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.3045102601 Sep 24 06:18:53 PM UTC 24 Sep 24 06:21:57 PM UTC 24 18266775900 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1231280465 Sep 24 06:21:55 PM UTC 24 Sep 24 06:22:22 PM UTC 24 39047300 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.267496970 Sep 24 06:14:41 PM UTC 24 Sep 24 06:22:33 PM UTC 24 12522018700 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.897384082 Sep 24 06:20:16 PM UTC 24 Sep 24 06:22:39 PM UTC 24 979747500 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1474196056 Sep 24 06:20:33 PM UTC 24 Sep 24 06:22:42 PM UTC 24 558634000 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.2472521397 Sep 24 06:10:55 PM UTC 24 Sep 24 06:22:44 PM UTC 24 9170916500 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3657724887 Sep 24 06:21:58 PM UTC 24 Sep 24 06:22:52 PM UTC 24 29806900 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1966922382 Sep 24 06:21:59 PM UTC 24 Sep 24 06:22:53 PM UTC 24 29374900 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3529245202 Sep 24 06:22:23 PM UTC 24 Sep 24 06:23:10 PM UTC 24 57304700 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3179496362 Sep 24 06:22:43 PM UTC 24 Sep 24 06:23:10 PM UTC 24 73523900 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2609158310 Sep 24 06:22:35 PM UTC 24 Sep 24 06:23:15 PM UTC 24 13066000 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1714360636 Sep 24 06:22:53 PM UTC 24 Sep 24 06:23:18 PM UTC 24 67081900 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3161144689 Sep 24 06:23:11 PM UTC 24 Sep 24 06:23:29 PM UTC 24 134742900 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2129813034 Sep 24 06:11:57 PM UTC 24 Sep 24 06:23:37 PM UTC 24 16198711800 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1750342350 Sep 24 06:14:23 PM UTC 24 Sep 24 06:23:45 PM UTC 24 244549700 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.1114818408 Sep 24 06:20:43 PM UTC 24 Sep 24 06:23:45 PM UTC 24 6410638800 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1252399595 Sep 24 06:22:54 PM UTC 24 Sep 24 06:23:51 PM UTC 24 10033027300 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.3733289587 Sep 24 05:50:38 PM UTC 24 Sep 24 06:23:57 PM UTC 24 100821303300 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.1489879345 Sep 24 06:23:19 PM UTC 24 Sep 24 06:24:02 PM UTC 24 698756400 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.568220539 Sep 24 05:59:36 PM UTC 24 Sep 24 06:24:02 PM UTC 24 6004794900 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1048661434 Sep 24 06:20:56 PM UTC 24 Sep 24 06:24:07 PM UTC 24 1438950500 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3766289429 Sep 24 06:20:00 PM UTC 24 Sep 24 06:24:14 PM UTC 24 17837024000 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2208973073 Sep 24 06:22:40 PM UTC 24 Sep 24 06:24:18 PM UTC 24 1687228600 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.1079783068 Sep 24 06:23:11 PM UTC 24 Sep 24 06:24:20 PM UTC 24 27286000 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2600654740 Sep 24 06:23:45 PM UTC 24 Sep 24 06:24:22 PM UTC 24 1897118500 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3905111908 Sep 24 06:20:59 PM UTC 24 Sep 24 06:24:23 PM UTC 24 1328417700 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3672297100 Sep 24 06:19:07 PM UTC 24 Sep 24 06:24:36 PM UTC 24 11652855000 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.2116699759 Sep 24 06:15:32 PM UTC 24 Sep 24 06:25:08 PM UTC 24 14206299300 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3598378106 Sep 24 06:21:15 PM UTC 24 Sep 24 06:25:09 PM UTC 24 4599479900 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.4040654632 Sep 24 06:24:03 PM UTC 24 Sep 24 06:25:18 PM UTC 24 2021879300 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.357875932 Sep 24 06:21:23 PM UTC 24 Sep 24 06:25:56 PM UTC 24 43964455300 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3911706750 Sep 24 06:25:57 PM UTC 24 Sep 24 06:26:14 PM UTC 24 27366600 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.340592615 Sep 24 06:24:03 PM UTC 24 Sep 24 06:26:22 PM UTC 24 6877178100 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1879029771 Sep 24 06:21:17 PM UTC 24 Sep 24 06:26:23 PM UTC 24 11912519500 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1766176926 Sep 24 06:24:08 PM UTC 24 Sep 24 06:26:27 PM UTC 24 541472600 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2053165005 Sep 24 06:01:47 PM UTC 24 Sep 24 06:26:32 PM UTC 24 2461004100 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3056425513 Sep 24 06:23:38 PM UTC 24 Sep 24 06:26:38 PM UTC 24 74155100 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2220672717 Sep 24 06:25:09 PM UTC 24 Sep 24 06:26:48 PM UTC 24 2346283000 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2366557825 Sep 24 06:24:19 PM UTC 24 Sep 24 06:26:48 PM UTC 24 5624990700 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.852808787 Sep 24 06:18:52 PM UTC 24 Sep 24 06:26:50 PM UTC 24 136447500 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.959723924 Sep 24 06:26:15 PM UTC 24 Sep 24 06:26:53 PM UTC 24 30800400 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2546933966 Sep 24 06:26:28 PM UTC 24 Sep 24 06:26:54 PM UTC 24 34441500 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2661269279 Sep 24 06:26:39 PM UTC 24 Sep 24 06:27:00 PM UTC 24 15316800 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.147568231 Sep 24 06:26:49 PM UTC 24 Sep 24 06:27:05 PM UTC 24 121262400 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3434509366 Sep 24 06:26:24 PM UTC 24 Sep 24 06:27:06 PM UTC 24 271975600 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1627848223 Sep 24 06:26:49 PM UTC 24 Sep 24 06:27:11 PM UTC 24 15328500 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.992970446 Sep 24 06:24:24 PM UTC 24 Sep 24 06:27:14 PM UTC 24 4200409400 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1109647348 Sep 24 06:24:38 PM UTC 24 Sep 24 06:27:15 PM UTC 24 1303059900 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2177101261 Sep 24 06:26:53 PM UTC 24 Sep 24 06:27:17 PM UTC 24 98606500 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3430506013 Sep 24 06:24:22 PM UTC 24 Sep 24 06:27:22 PM UTC 24 619784300 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2252233713 Sep 24 06:20:20 PM UTC 24 Sep 24 06:27:27 PM UTC 24 12189366600 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1219361876 Sep 24 06:24:21 PM UTC 24 Sep 24 06:27:36 PM UTC 24 14212312800 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1881202566 Sep 24 06:26:51 PM UTC 24 Sep 24 06:27:55 PM UTC 24 10028180800 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.321201040 Sep 24 06:26:33 PM UTC 24 Sep 24 06:27:56 PM UTC 24 2505685100 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.1061462320 Sep 24 05:47:44 PM UTC 24 Sep 24 06:28:05 PM UTC 24 2626418500 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3779414695 Sep 24 06:27:06 PM UTC 24 Sep 24 06:28:16 PM UTC 24 1159708400 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.885867066 Sep 24 06:27:56 PM UTC 24 Sep 24 06:28:22 PM UTC 24 129697600 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3355648384 Sep 24 06:25:10 PM UTC 24 Sep 24 06:28:27 PM UTC 24 51447568900 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1782821853 Sep 24 06:23:45 PM UTC 24 Sep 24 06:28:27 PM UTC 24 23530691800 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.2225376666 Sep 24 06:27:16 PM UTC 24 Sep 24 06:28:49 PM UTC 24 7629757100 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2853032437 Sep 24 06:28:06 PM UTC 24 Sep 24 06:28:58 PM UTC 24 39412100 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.816612386 Sep 24 06:28:17 PM UTC 24 Sep 24 06:28:59 PM UTC 24 44342900 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.1848803225 Sep 24 06:07:12 PM UTC 24 Sep 24 06:29:01 PM UTC 24 1042456100 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.3821611098 Sep 24 06:28:29 PM UTC 24 Sep 24 06:29:05 PM UTC 24 24027100 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2874282352 Sep 24 06:28:51 PM UTC 24 Sep 24 06:29:11 PM UTC 24 45143700 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.4140993926 Sep 24 06:28:59 PM UTC 24 Sep 24 06:29:17 PM UTC 24 16596500 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2473673710 Sep 24 06:29:06 PM UTC 24 Sep 24 06:29:25 PM UTC 24 121657800 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3796272097 Sep 24 06:28:24 PM UTC 24 Sep 24 06:29:25 PM UTC 24 293411600 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2411502632 Sep 24 06:29:00 PM UTC 24 Sep 24 06:29:26 PM UTC 24 34669700 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3384305547 Sep 24 06:23:13 PM UTC 24 Sep 24 06:29:27 PM UTC 24 73464600 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2139555653 Sep 24 06:11:10 PM UTC 24 Sep 24 06:29:28 PM UTC 24 4377162500 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2992879452 Sep 24 06:27:22 PM UTC 24 Sep 24 06:29:29 PM UTC 24 2280761000 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.57883180 Sep 24 06:27:13 PM UTC 24 Sep 24 06:29:31 PM UTC 24 48217700 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3961295912 Sep 24 06:27:37 PM UTC 24 Sep 24 06:30:04 PM UTC 24 945678400 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1369491648 Sep 24 06:25:19 PM UTC 24 Sep 24 06:30:18 PM UTC 24 72045672800 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3497994657 Sep 24 06:06:55 PM UTC 24 Sep 24 06:30:34 PM UTC 24 449537000 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2266905168 Sep 24 06:28:29 PM UTC 24 Sep 24 06:30:36 PM UTC 24 7707070300 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.935321409 Sep 24 06:29:26 PM UTC 24 Sep 24 06:30:48 PM UTC 24 88866400 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1469857303 Sep 24 06:29:02 PM UTC 24 Sep 24 06:30:50 PM UTC 24 10034176600 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4032608815 Sep 24 05:46:46 PM UTC 24 Sep 24 06:30:51 PM UTC 24 1212467282700 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2656136437 Sep 24 06:27:18 PM UTC 24 Sep 24 06:31:05 PM UTC 24 9155359200 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1737454311 Sep 24 06:10:49 PM UTC 24 Sep 24 06:31:15 PM UTC 24 480322671400 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.798942597 Sep 24 06:30:49 PM UTC 24 Sep 24 06:31:16 PM UTC 24 61158200 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1480488141 Sep 24 06:14:27 PM UTC 24 Sep 24 06:31:18 PM UTC 24 100150674400 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3662542621 Sep 24 06:27:55 PM UTC 24 Sep 24 06:31:18 PM UTC 24 38522169100 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2206985439 Sep 24 06:29:30 PM UTC 24 Sep 24 06:31:25 PM UTC 24 3498962600 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2379053725 Sep 24 06:29:32 PM UTC 24 Sep 24 06:31:32 PM UTC 24 3255391900 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.229074880 Sep 24 06:30:52 PM UTC 24 Sep 24 06:31:41 PM UTC 24 47849200 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.629676688 Sep 24 06:27:15 PM UTC 24 Sep 24 06:31:41 PM UTC 24 17702737800 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3493772559 Sep 24 06:30:51 PM UTC 24 Sep 24 06:31:43 PM UTC 24 126387600 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2259326350 Sep 24 06:26:55 PM UTC 24 Sep 24 06:31:44 PM UTC 24 1401632800 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3714796597 Sep 24 06:27:02 PM UTC 24 Sep 24 06:31:47 PM UTC 24 156252900 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1840018835 Sep 24 06:31:19 PM UTC 24 Sep 24 06:31:48 PM UTC 24 48843900 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1753357169 Sep 24 06:31:19 PM UTC 24 Sep 24 06:31:49 PM UTC 24 47840300 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1185190813 Sep 24 06:31:05 PM UTC 24 Sep 24 06:31:49 PM UTC 24 555712300 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.370003861 Sep 24 06:31:26 PM UTC 24 Sep 24 06:31:53 PM UTC 24 44846100 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.3760455263 Sep 24 05:47:05 PM UTC 24 Sep 24 06:31:54 PM UTC 24 3726609100 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.859773102 Sep 24 06:31:16 PM UTC 24 Sep 24 06:31:54 PM UTC 24 27623500 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4153652137 Sep 24 06:29:11 PM UTC 24 Sep 24 06:31:55 PM UTC 24 60146600 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1232884356 Sep 24 06:31:42 PM UTC 24 Sep 24 06:32:01 PM UTC 24 40284900 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1920923077 Sep 24 06:23:16 PM UTC 24 Sep 24 06:32:08 PM UTC 24 147547600 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.1080856318 Sep 24 06:30:06 PM UTC 24 Sep 24 06:32:17 PM UTC 24 543996700 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.593602382 Sep 24 06:29:27 PM UTC 24 Sep 24 06:32:27 PM UTC 24 10247466800 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3561789001 Sep 24 06:18:44 PM UTC 24 Sep 24 06:32:36 PM UTC 24 169454300 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.4106370644 Sep 24 06:32:17 PM UTC 24 Sep 24 06:32:38 PM UTC 24 19750900 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.873740036 Sep 24 06:30:35 PM UTC 24 Sep 24 06:32:57 PM UTC 24 757982600 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.3986744635 Sep 24 06:32:27 PM UTC 24 Sep 24 06:33:05 PM UTC 24 102780500 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.433871737 Sep 24 06:18:59 PM UTC 24 Sep 24 06:33:12 PM UTC 24 80136806400 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.117750728 Sep 24 06:29:28 PM UTC 24 Sep 24 06:33:13 PM UTC 24 466457300 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.604411836 Sep 24 06:31:42 PM UTC 24 Sep 24 06:33:15 PM UTC 24 38171000 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2745492107 Sep 24 06:31:54 PM UTC 24 Sep 24 06:33:18 PM UTC 24 1932145900 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2127931738 Sep 24 06:32:38 PM UTC 24 Sep 24 06:33:28 PM UTC 24 29349400 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.926726119 Sep 24 06:33:13 PM UTC 24 Sep 24 06:33:31 PM UTC 24 47543100 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.563623088 Sep 24 06:33:13 PM UTC 24 Sep 24 06:33:33 PM UTC 24 23723100 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2676204365 Sep 24 06:31:18 PM UTC 24 Sep 24 06:33:34 PM UTC 24 9682776300 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3815579422 Sep 24 06:30:37 PM UTC 24 Sep 24 06:33:35 PM UTC 24 9151057000 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.915849493 Sep 24 06:33:16 PM UTC 24 Sep 24 06:33:38 PM UTC 24 27205200 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3540014008 Sep 24 06:32:58 PM UTC 24 Sep 24 06:33:44 PM UTC 24 10662300 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2151203246 Sep 24 06:32:39 PM UTC 24 Sep 24 06:33:47 PM UTC 24 105919300 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1981841212 Sep 24 06:33:29 PM UTC 24 Sep 24 06:33:50 PM UTC 24 78786600 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.1260690206 Sep 24 06:31:55 PM UTC 24 Sep 24 06:33:53 PM UTC 24 691244700 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2611366752 Sep 24 06:31:48 PM UTC 24 Sep 24 06:34:00 PM UTC 24 3529168200 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2050571879 Sep 24 06:33:36 PM UTC 24 Sep 24 06:34:24 PM UTC 24 1936031800 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2299140861 Sep 24 06:33:06 PM UTC 24 Sep 24 06:34:30 PM UTC 24 2271251700 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2500631333 Sep 24 06:32:09 PM UTC 24 Sep 24 06:34:39 PM UTC 24 23890288700 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.4249531882 Sep 24 06:31:55 PM UTC 24 Sep 24 06:34:45 PM UTC 24 18901489300 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1876935120 Sep 24 06:33:32 PM UTC 24 Sep 24 06:35:05 PM UTC 24 67837900 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1264861185 Sep 24 06:31:50 PM UTC 24 Sep 24 06:35:06 PM UTC 24 108175600 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.506664300 Sep 24 06:24:15 PM UTC 24 Sep 24 06:35:12 PM UTC 24 22017849200 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.165784166 Sep 24 06:33:51 PM UTC 24 Sep 24 06:35:20 PM UTC 24 12344820200 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2375374744 Sep 24 06:34:46 PM UTC 24 Sep 24 06:35:20 PM UTC 24 341579800 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3992303099 Sep 24 06:31:33 PM UTC 24 Sep 24 06:35:41 PM UTC 24 10019864500 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2685349651 Sep 24 06:35:06 PM UTC 24 Sep 24 06:35:43 PM UTC 24 110147900 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1358543743 Sep 24 06:33:20 PM UTC 24 Sep 24 06:35:47 PM UTC 24 10032269900 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1964812898 Sep 24 06:27:28 PM UTC 24 Sep 24 06:35:54 PM UTC 24 6239182000 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.162617518 Sep 24 06:32:02 PM UTC 24 Sep 24 06:36:01 PM UTC 24 7833179200 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3607132920 Sep 24 06:35:07 PM UTC 24 Sep 24 06:36:02 PM UTC 24 40621200 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1774329489 Sep 24 06:34:01 PM UTC 24 Sep 24 06:36:04 PM UTC 24 1050381100 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1729157293 Sep 24 06:35:21 PM UTC 24 Sep 24 06:36:07 PM UTC 24 19083900 ps
T658 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.1548259872 Sep 24 06:35:48 PM UTC 24 Sep 24 06:36:07 PM UTC 24 26433300 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.2437906356 Sep 24 06:35:42 PM UTC 24 Sep 24 06:36:08 PM UTC 24 24456700 ps
T660 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1278591083 Sep 24 06:35:43 PM UTC 24 Sep 24 06:36:08 PM UTC 24 64789700 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3446276409 Sep 24 06:35:14 PM UTC 24 Sep 24 06:36:12 PM UTC 24 113887500 ps
T661 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.3045840620 Sep 24 06:33:54 PM UTC 24 Sep 24 06:36:21 PM UTC 24 1882458800 ps
T662 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.3596909104 Sep 24 06:36:02 PM UTC 24 Sep 24 06:36:21 PM UTC 24 42875900 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.3536484034 Sep 24 05:47:46 PM UTC 24 Sep 24 06:36:38 PM UTC 24 16235235200 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3817337002 Sep 24 05:46:49 PM UTC 24 Sep 24 06:36:49 PM UTC 24 1264103500 ps
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