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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.23 93.90 98.31 92.52 97.14 97.08 98.15


Total test records in report: 1262
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T1262 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.6863441 Sep 24 05:26:04 PM UTC 24 Sep 24 05:37:18 PM UTC 24 1415943700 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.187997202 Sep 24 05:26:00 PM UTC 24 Sep 24 05:38:07 PM UTC 24 443331600 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2870321105 Sep 24 05:24:39 PM UTC 24 Sep 24 05:44:15 PM UTC 24 6697510500 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.316248744 Sep 24 05:24:39 PM UTC 24 Sep 24 05:44:36 PM UTC 24 445027300 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2519917648 Sep 24 05:24:43 PM UTC 24 Sep 24 05:44:45 PM UTC 24 944707300 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.931900081 Sep 24 05:25:17 PM UTC 24 Sep 24 05:44:57 PM UTC 24 1322630000 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4283589424 Sep 24 05:24:41 PM UTC 24 Sep 24 05:45:21 PM UTC 24 1661641100 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4219179839 Sep 24 05:25:48 PM UTC 24 Sep 24 05:45:23 PM UTC 24 1435523400 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.685717398 Sep 24 05:25:22 PM UTC 24 Sep 24 05:45:40 PM UTC 24 353292900 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1974089427 Sep 24 05:25:13 PM UTC 24 Sep 24 05:45:41 PM UTC 24 1394163200 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2590367657 Sep 24 05:25:45 PM UTC 24 Sep 24 05:45:54 PM UTC 24 872852400 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2474078801 Sep 24 05:25:55 PM UTC 24 Sep 24 05:45:59 PM UTC 24 3316869500 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3362093026
Short name T3
Test name
Test status
Simulation time 1800077800 ps
CPU time 27.93 seconds
Started Sep 24 05:46:47 PM UTC 24
Finished Sep 24 05:47:17 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33
62093026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc
h_code.3362093026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3895873125
Short name T8
Test name
Test status
Simulation time 164882500 ps
CPU time 28.19 seconds
Started Sep 24 05:47:06 PM UTC 24
Finished Sep 24 05:47:35 PM UTC 24
Peak memory 275600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3895873125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_wr_intg.3895873125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.491300834
Short name T72
Test name
Test status
Simulation time 148269700 ps
CPU time 18.22 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 292768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=491300834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.491300834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2533723337
Short name T34
Test name
Test status
Simulation time 994033800 ps
CPU time 83 seconds
Started Sep 24 05:46:50 PM UTC 24
Finished Sep 24 05:48:15 PM UTC 24
Peak memory 270876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533723337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2533723337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.863741936
Short name T37
Test name
Test status
Simulation time 73087700 ps
CPU time 39.38 seconds
Started Sep 24 05:47:01 PM UTC 24
Finished Sep 24 05:47:42 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=863741936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctr
l_rw_evict_all_en.863741936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1227439856
Short name T28
Test name
Test status
Simulation time 27923694500 ps
CPU time 317.15 seconds
Started Sep 24 05:46:47 PM UTC 24
Finished Sep 24 05:52:09 PM UTC 24
Peak memory 283420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1227439856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_mp_regions.1227439856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.4185982397
Short name T135
Test name
Test status
Simulation time 160189496200 ps
CPU time 1014.05 seconds
Started Sep 24 05:46:46 PM UTC 24
Finished Sep 24 06:03:53 PM UTC 24
Peak memory 277832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185982397
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.4185982397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.630002329
Short name T142
Test name
Test status
Simulation time 1356581900 ps
CPU time 6817.92 seconds
Started Sep 24 06:05:43 PM UTC 24
Finished Sep 24 08:00:36 PM UTC 24
Peak memory 320344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630002329 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.630002329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3361719491
Short name T236
Test name
Test status
Simulation time 92218900 ps
CPU time 19.9 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:11 PM UTC 24
Peak memory 274348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361719491 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.3361719491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2648533537
Short name T71
Test name
Test status
Simulation time 2444930000 ps
CPU time 129.49 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:49:05 PM UTC 24
Peak memory 306428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2648533537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_ro_serr.2648533537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.4245832053
Short name T49
Test name
Test status
Simulation time 97320300 ps
CPU time 40.92 seconds
Started Sep 24 05:47:05 PM UTC 24
Finished Sep 24 05:47:47 PM UTC 24
Peak memory 285532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424583205
3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.4245832053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2305450158
Short name T250
Test name
Test status
Simulation time 333173900 ps
CPU time 33.54 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:14 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305450158 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2305450158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.409394218
Short name T60
Test name
Test status
Simulation time 1703749500 ps
CPU time 115.7 seconds
Started Sep 24 05:47:50 PM UTC 24
Finished Sep 24 05:49:49 PM UTC 24
Peak memory 272924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409394218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.409394218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2587333040
Short name T54
Test name
Test status
Simulation time 2440773100 ps
CPU time 207.81 seconds
Started Sep 24 05:46:59 PM UTC 24
Finished Sep 24 05:50:30 PM UTC 24
Peak memory 291972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2587333040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_oversize_error.2587333040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.175086976
Short name T133
Test name
Test status
Simulation time 41331700 ps
CPU time 171.26 seconds
Started Sep 24 05:46:46 PM UTC 24
Finished Sep 24 05:49:40 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175086976 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.175086976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2507992165
Short name T16
Test name
Test status
Simulation time 89442500 ps
CPU time 25.11 seconds
Started Sep 24 05:50:21 PM UTC 24
Finished Sep 24 05:50:48 PM UTC 24
Peak memory 268744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507992165 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2507992165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2162491274
Short name T101
Test name
Test status
Simulation time 81941877600 ps
CPU time 1120.27 seconds
Started Sep 24 05:47:12 PM UTC 24
Finished Sep 24 06:06:07 PM UTC 24
Peak memory 273072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2162491274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_rma_err.2162491274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2065355660
Short name T335
Test name
Test status
Simulation time 33050800 ps
CPU time 16.02 seconds
Started Sep 24 05:24:46 PM UTC 24
Finished Sep 24 05:25:13 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065355660 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2065355660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3056425513
Short name T94
Test name
Test status
Simulation time 74155100 ps
CPU time 176.9 seconds
Started Sep 24 06:23:38 PM UTC 24
Finished Sep 24 06:26:38 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056425513 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.3056425513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.4253871373
Short name T177
Test name
Test status
Simulation time 139870900 ps
CPU time 216.1 seconds
Started Sep 24 06:42:31 PM UTC 24
Finished Sep 24 06:46:11 PM UTC 24
Peak memory 271012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253871373 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.4253871373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4170086698
Short name T129
Test name
Test status
Simulation time 53239500 ps
CPU time 19.36 seconds
Started Sep 24 05:24:48 PM UTC 24
Finished Sep 24 05:25:16 PM UTC 24
Peak memory 276392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4170086698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.4170086698
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.4286015556
Short name T307
Test name
Test status
Simulation time 5398748000 ps
CPU time 248.59 seconds
Started Sep 24 06:07:01 PM UTC 24
Finished Sep 24 06:11:15 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286015556 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.4286015556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3392356792
Short name T79
Test name
Test status
Simulation time 1712999600 ps
CPU time 81.67 seconds
Started Sep 24 05:55:42 PM UTC 24
Finished Sep 24 05:57:06 PM UTC 24
Peak memory 271068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392356792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3392356792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2932207424
Short name T83
Test name
Test status
Simulation time 7236976700 ps
CPU time 77.56 seconds
Started Sep 24 05:47:48 PM UTC 24
Finished Sep 24 05:49:08 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932207424 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2932207424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1340615893
Short name T245
Test name
Test status
Simulation time 822438900 ps
CPU time 528.72 seconds
Started Sep 24 05:24:49 PM UTC 24
Finished Sep 24 05:33:46 PM UTC 24
Peak memory 276636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340615893 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.1340615893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3979719508
Short name T224
Test name
Test status
Simulation time 440215000 ps
CPU time 25 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:26 PM UTC 24
Peak memory 292904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3979719508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3979719508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.216752774
Short name T48
Test name
Test status
Simulation time 31894121800 ps
CPU time 244.44 seconds
Started Sep 24 05:47:00 PM UTC 24
Finished Sep 24 05:51:08 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=216752774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_rd_slow_flash.216752774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.530120660
Short name T169
Test name
Test status
Simulation time 1897757300 ps
CPU time 110.78 seconds
Started Sep 24 05:53:17 PM UTC 24
Finished Sep 24 05:55:11 PM UTC 24
Peak memory 275164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530120660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.530120660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2364228052
Short name T490
Test name
Test status
Simulation time 10034974600 ps
CPU time 120.85 seconds
Started Sep 24 06:06:38 PM UTC 24
Finished Sep 24 06:08:42 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2364228052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2364228052
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.637119489
Short name T88
Test name
Test status
Simulation time 11706072800 ps
CPU time 591.04 seconds
Started Sep 24 05:50:34 PM UTC 24
Finished Sep 24 06:00:33 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637119489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.637119489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3994668390
Short name T131
Test name
Test status
Simulation time 63885800 ps
CPU time 21.08 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:02 PM UTC 24
Peak memory 276540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994668390 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3994668390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4032608815
Short name T182
Test name
Test status
Simulation time 1212467282700 ps
CPU time 2617.18 seconds
Started Sep 24 05:46:46 PM UTC 24
Finished Sep 24 06:30:51 PM UTC 24
Peak memory 277996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032608815 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.4032608815
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3804355994
Short name T11
Test name
Test status
Simulation time 14427500 ps
CPU time 19.6 seconds
Started Sep 24 05:47:10 PM UTC 24
Finished Sep 24 05:47:31 PM UTC 24
Peak memory 282884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804355994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3804355994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3847988118
Short name T96
Test name
Test status
Simulation time 42030400 ps
CPU time 181.61 seconds
Started Sep 24 06:36:09 PM UTC 24
Finished Sep 24 06:39:14 PM UTC 24
Peak memory 271284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847988118 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.3847988118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1264861185
Short name T95
Test name
Test status
Simulation time 108175600 ps
CPU time 192.12 seconds
Started Sep 24 06:31:50 PM UTC 24
Finished Sep 24 06:35:06 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264861185 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.1264861185
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2404429411
Short name T155
Test name
Test status
Simulation time 84910700 ps
CPU time 50.14 seconds
Started Sep 24 05:49:10 PM UTC 24
Finished Sep 24 05:50:01 PM UTC 24
Peak memory 285856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404429411 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.2404429411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3835561260
Short name T198
Test name
Test status
Simulation time 1228097500 ps
CPU time 194.63 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:50:11 PM UTC 24
Peak memory 296032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3835561260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rw_derr.3835561260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3125585898
Short name T73
Test name
Test status
Simulation time 155114000 ps
CPU time 18.91 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:00 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125585898 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.3125585898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.1255377700
Short name T174
Test name
Test status
Simulation time 30732700 ps
CPU time 20.86 seconds
Started Sep 24 05:50:11 PM UTC 24
Finished Sep 24 05:50:33 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1255377700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_lcmgr_intg.1255377700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1418661720
Short name T229
Test name
Test status
Simulation time 21856500 ps
CPU time 15.3 seconds
Started Sep 24 05:24:40 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418661720 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1418661720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1402244059
Short name T23
Test name
Test status
Simulation time 23801500 ps
CPU time 27.56 seconds
Started Sep 24 05:53:36 PM UTC 24
Finished Sep 24 05:54:05 PM UTC 24
Peak memory 273220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1402244059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1402244059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.134259812
Short name T50
Test name
Test status
Simulation time 2354761900 ps
CPU time 61.81 seconds
Started Sep 24 05:47:07 PM UTC 24
Finished Sep 24 05:48:11 PM UTC 24
Peak memory 273200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342598
12 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fs
_sup.134259812
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.316248744
Short name T387
Test name
Test status
Simulation time 445027300 ps
CPU time 1181.32 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:44:36 PM UTC 24
Peak memory 278504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316248744 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.316248744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.32293147
Short name T32
Test name
Test status
Simulation time 775466100 ps
CPU time 28.73 seconds
Started Sep 24 05:47:09 PM UTC 24
Finished Sep 24 05:47:39 PM UTC 24
Peak memory 275524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=32293147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.32293147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2450273371
Short name T47
Test name
Test status
Simulation time 456089700 ps
CPU time 110.51 seconds
Started Sep 24 05:57:26 PM UTC 24
Finished Sep 24 05:59:19 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450273371 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.2450273371
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1982556426
Short name T340
Test name
Test status
Simulation time 29707300 ps
CPU time 20.97 seconds
Started Sep 24 05:25:15 PM UTC 24
Finished Sep 24 05:25:38 PM UTC 24
Peak memory 274428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982556426 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1982556426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3720442630
Short name T27
Test name
Test status
Simulation time 6611345300 ps
CPU time 170.36 seconds
Started Sep 24 05:47:27 PM UTC 24
Finished Sep 24 05:50:20 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720442630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3720442630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.682786543
Short name T108
Test name
Test status
Simulation time 10034920500 ps
CPU time 107.7 seconds
Started Sep 24 05:50:13 PM UTC 24
Finished Sep 24 05:52:03 PM UTC 24
Peak memory 283592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=682786543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.682786543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3598378106
Short name T344
Test name
Test status
Simulation time 4599479900 ps
CPU time 230.89 seconds
Started Sep 24 06:21:15 PM UTC 24
Finished Sep 24 06:25:09 PM UTC 24
Peak memory 306292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598378106 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.3598378106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3480679517
Short name T76
Test name
Test status
Simulation time 61715500 ps
CPU time 41.02 seconds
Started Sep 24 05:59:18 PM UTC 24
Finished Sep 24 06:00:01 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3480679517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_disable.3480679517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2474078801
Short name T382
Test name
Test status
Simulation time 3316869500 ps
CPU time 1188.15 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:45:59 PM UTC 24
Peak memory 278512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474078801 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.2474078801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1949928972
Short name T126
Test name
Test status
Simulation time 17690500 ps
CPU time 24.9 seconds
Started Sep 24 05:47:18 PM UTC 24
Finished Sep 24 05:47:44 PM UTC 24
Peak memory 269448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1949928972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_hw_read_seed_err.1949928972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.4211229620
Short name T208
Test name
Test status
Simulation time 994471500 ps
CPU time 131.85 seconds
Started Sep 24 06:03:28 PM UTC 24
Finished Sep 24 06:05:42 PM UTC 24
Peak memory 292104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211229620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.4211229620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3205674256
Short name T105
Test name
Test status
Simulation time 83045300 ps
CPU time 29.66 seconds
Started Sep 24 06:06:08 PM UTC 24
Finished Sep 24 06:06:39 PM UTC 24
Peak memory 284616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205674256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3205674256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.809211781
Short name T81
Test name
Test status
Simulation time 9909855000 ps
CPU time 339.23 seconds
Started Sep 24 05:50:46 PM UTC 24
Finished Sep 24 05:56:31 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=809211781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_mp_regions.809211781
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4075997388
Short name T193
Test name
Test status
Simulation time 15251100 ps
CPU time 21.14 seconds
Started Sep 24 05:49:59 PM UTC 24
Finished Sep 24 05:50:21 PM UTC 24
Peak memory 275556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4075997388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.4075997388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2659009147
Short name T207
Test name
Test status
Simulation time 71274800 ps
CPU time 22.2 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:21 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659009147 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2659009147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.138644884
Short name T98
Test name
Test status
Simulation time 765357600 ps
CPU time 37.27 seconds
Started Sep 24 05:53:45 PM UTC 24
Finished Sep 24 05:54:24 PM UTC 24
Peak memory 275720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=138644884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.138644884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1252399595
Short name T269
Test name
Test status
Simulation time 10033027300 ps
CPU time 55.47 seconds
Started Sep 24 06:22:54 PM UTC 24
Finished Sep 24 06:23:51 PM UTC 24
Peak memory 275628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1252399595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1252399595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1116015565
Short name T352
Test name
Test status
Simulation time 1542533500 ps
CPU time 147.14 seconds
Started Sep 24 06:47:06 PM UTC 24
Finished Sep 24 06:49:36 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116015565 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.1116015565
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.1891074419
Short name T365
Test name
Test status
Simulation time 30781800 ps
CPU time 52.51 seconds
Started Sep 24 05:58:28 PM UTC 24
Finished Sep 24 05:59:22 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891074419 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.1891074419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.3821611098
Short name T122
Test name
Test status
Simulation time 24027100 ps
CPU time 35.18 seconds
Started Sep 24 06:28:29 PM UTC 24
Finished Sep 24 06:29:05 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3821611098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_
ctrl_disable.3821611098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3817337002
Short name T111
Test name
Test status
Simulation time 1264103500 ps
CPU time 2968.22 seconds
Started Sep 24 05:46:49 PM UTC 24
Finished Sep 24 06:36:49 PM UTC 24
Peak memory 277936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38
17337002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_error_prog_type.3817337002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1077648686
Short name T279
Test name
Test status
Simulation time 1306385200 ps
CPU time 1206.05 seconds
Started Sep 24 05:46:49 PM UTC 24
Finished Sep 24 06:07:09 PM UTC 24
Peak memory 288444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077648686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1077648686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.3435663367
Short name T312
Test name
Test status
Simulation time 5752521000 ps
CPU time 98.68 seconds
Started Sep 24 06:49:47 PM UTC 24
Finished Sep 24 06:51:28 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435663367 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.3435663367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4219179839
Short name T388
Test name
Test status
Simulation time 1435523400 ps
CPU time 1160.35 seconds
Started Sep 24 05:25:48 PM UTC 24
Finished Sep 24 05:45:23 PM UTC 24
Peak memory 278508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219179839 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.4219179839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2685033651
Short name T215
Test name
Test status
Simulation time 132438100 ps
CPU time 43.35 seconds
Started Sep 24 06:47:25 PM UTC 24
Finished Sep 24 06:48:10 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685033651 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.2685033651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1814272410
Short name T56
Test name
Test status
Simulation time 926362300 ps
CPU time 32.23 seconds
Started Sep 24 05:50:47 PM UTC 24
Finished Sep 24 05:51:20 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18
14272410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc
h_code.1814272410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1415210116
Short name T19
Test name
Test status
Simulation time 24445600 ps
CPU time 20.53 seconds
Started Sep 24 05:47:05 PM UTC 24
Finished Sep 24 05:47:26 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415210116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1415210116
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.548096241
Short name T397
Test name
Test status
Simulation time 1458166400 ps
CPU time 42.73 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:29 PM UTC 24
Peak memory 276516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548096241 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.548096241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2634148547
Short name T421
Test name
Test status
Simulation time 4152811900 ps
CPU time 515.32 seconds
Started Sep 24 05:46:59 PM UTC 24
Finished Sep 24 05:55:41 PM UTC 24
Peak memory 334864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2634148547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr
ity.2634148547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3194069758
Short name T43
Test name
Test status
Simulation time 326109400 ps
CPU time 66.01 seconds
Started Sep 24 05:47:03 PM UTC 24
Finished Sep 24 05:48:11 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194069758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3194069758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.343630472
Short name T413
Test name
Test status
Simulation time 555198700 ps
CPU time 88.76 seconds
Started Sep 24 06:35:21 PM UTC 24
Finished Sep 24 06:36:52 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343630472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.343630472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.3491298095
Short name T412
Test name
Test status
Simulation time 1993080300 ps
CPU time 82.98 seconds
Started Sep 24 06:58:12 PM UTC 24
Finished Sep 24 06:59:37 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491298095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3491298095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2430865839
Short name T99
Test name
Test status
Simulation time 866324500 ps
CPU time 26.99 seconds
Started Sep 24 06:06:09 PM UTC 24
Finished Sep 24 06:06:37 PM UTC 24
Peak memory 275524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2430865839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2430865839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1219546881
Short name T26
Test name
Test status
Simulation time 154144500 ps
CPU time 47.43 seconds
Started Sep 24 05:47:01 PM UTC 24
Finished Sep 24 05:47:50 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219546881 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.1219546881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.160713910
Short name T14
Test name
Test status
Simulation time 1323141700 ps
CPU time 6970.15 seconds
Started Sep 24 05:49:33 PM UTC 24
Finished Sep 24 07:47:04 PM UTC 24
Peak memory 312144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160713910 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.160713910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3455453286
Short name T178
Test name
Test status
Simulation time 80138005200 ps
CPU time 931.68 seconds
Started Sep 24 06:23:29 PM UTC 24
Finished Sep 24 06:39:14 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455453286
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.3455453286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.2199860745
Short name T277
Test name
Test status
Simulation time 4493324500 ps
CPU time 3333.45 seconds
Started Sep 24 05:46:50 PM UTC 24
Finished Sep 24 06:43:00 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199860745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.2199860745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.4081466298
Short name T919
Test name
Test status
Simulation time 42363300 ps
CPU time 45.35 seconds
Started Sep 24 06:56:23 PM UTC 24
Finished Sep 24 06:57:10 PM UTC 24
Peak memory 285592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4081466298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c
trl_rw_evict_all_en.4081466298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3127936353
Short name T371
Test name
Test status
Simulation time 30251500 ps
CPU time 60.44 seconds
Started Sep 24 06:17:41 PM UTC 24
Finished Sep 24 06:18:43 PM UTC 24
Peak memory 287876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127936353 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.3127936353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.985017790
Short name T670
Test name
Test status
Simulation time 44295900 ps
CPU time 19.95 seconds
Started Sep 24 06:37:42 PM UTC 24
Finished Sep 24 06:38:03 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=985017790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_lcmgr_intg.985017790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.113780352
Short name T248
Test name
Test status
Simulation time 158580200 ps
CPU time 15.34 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113780352 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.113780352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.899713353
Short name T234
Test name
Test status
Simulation time 52404500 ps
CPU time 21.07 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:06 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899713353 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.899713353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2590367657
Short name T389
Test name
Test status
Simulation time 872852400 ps
CPU time 1193.55 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:45:54 PM UTC 24
Peak memory 278508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590367657 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2590367657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.3549474730
Short name T31
Test name
Test status
Simulation time 67525200 ps
CPU time 24.88 seconds
Started Sep 24 05:47:10 PM UTC 24
Finished Sep 24 05:47:37 PM UTC 24
Peak memory 275104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549474730 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.3549474730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.4236962439
Short name T75
Test name
Test status
Simulation time 26049300 ps
CPU time 36.82 seconds
Started Sep 24 05:49:18 PM UTC 24
Finished Sep 24 05:49:56 PM UTC 24
Peak memory 285548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4236962439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_disable.4236962439
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.2638023456
Short name T173
Test name
Test status
Simulation time 15716700 ps
CPU time 23.85 seconds
Started Sep 24 05:50:12 PM UTC 24
Finished Sep 24 05:50:37 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2638023456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_hw_read_seed_err.2638023456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3450675827
Short name T116
Test name
Test status
Simulation time 80494800 ps
CPU time 42.84 seconds
Started Sep 24 05:49:06 PM UTC 24
Finished Sep 24 05:49:51 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3450675827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw_evict_all_en.3450675827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2266905168
Short name T416
Test name
Test status
Simulation time 7707070300 ps
CPU time 124.49 seconds
Started Sep 24 06:28:29 PM UTC 24
Finished Sep 24 06:30:36 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266905168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2266905168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.859773102
Short name T427
Test name
Test status
Simulation time 27623500 ps
CPU time 35.98 seconds
Started Sep 24 06:31:16 PM UTC 24
Finished Sep 24 06:31:54 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=859773102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_disable.859773102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2299140861
Short name T437
Test name
Test status
Simulation time 2271251700 ps
CPU time 82.21 seconds
Started Sep 24 06:33:06 PM UTC 24
Finished Sep 24 06:34:30 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299140861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2299140861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1729157293
Short name T78
Test name
Test status
Simulation time 19083900 ps
CPU time 43.93 seconds
Started Sep 24 06:35:21 PM UTC 24
Finished Sep 24 06:36:07 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1729157293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_
ctrl_disable.1729157293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2778364161
Short name T433
Test name
Test status
Simulation time 17459800 ps
CPU time 23.44 seconds
Started Sep 24 06:41:33 PM UTC 24
Finished Sep 24 06:41:58 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2778364161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_
ctrl_disable.2778364161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.1724027245
Short name T374
Test name
Test status
Simulation time 68205300 ps
CPU time 48.47 seconds
Started Sep 24 06:48:33 PM UTC 24
Finished Sep 24 06:49:23 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1724027245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c
trl_rw_evict_all_en.1724027245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.2632142554
Short name T419
Test name
Test status
Simulation time 6472335600 ps
CPU time 86.52 seconds
Started Sep 24 06:50:12 PM UTC 24
Finished Sep 24 06:51:40 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632142554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.2632142554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2266619016
Short name T144
Test name
Test status
Simulation time 11233327000 ps
CPU time 336.92 seconds
Started Sep 24 06:01:18 PM UTC 24
Finished Sep 24 06:07:00 PM UTC 24
Peak memory 283376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2266619016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.2266619016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.4175095031
Short name T406
Test name
Test status
Simulation time 37713100 ps
CPU time 43.22 seconds
Started Sep 24 07:00:19 PM UTC 24
Finished Sep 24 07:01:04 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4175095031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_
ctrl_disable.4175095031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3077112738
Short name T256
Test name
Test status
Simulation time 96097000 ps
CPU time 21.07 seconds
Started Sep 24 05:25:34 PM UTC 24
Finished Sep 24 05:25:57 PM UTC 24
Peak memory 276532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077112738 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.3077112738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1218174269
Short name T40
Test name
Test status
Simulation time 4913682700 ps
CPU time 80.28 seconds
Started Sep 24 05:47:00 PM UTC 24
Finished Sep 24 05:48:22 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218174269 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.1218174269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.2274440021
Short name T194
Test name
Test status
Simulation time 32701500 ps
CPU time 27.88 seconds
Started Sep 24 05:50:01 PM UTC 24
Finished Sep 24 05:50:30 PM UTC 24
Peak memory 271452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274440021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2274440021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3905111908
Short name T209
Test name
Test status
Simulation time 1328417700 ps
CPU time 200.04 seconds
Started Sep 24 06:20:59 PM UTC 24
Finished Sep 24 06:24:23 PM UTC 24
Peak memory 293944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3905111908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_rw_derr.3905111908
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3860038174
Short name T112
Test name
Test status
Simulation time 12561764600 ps
CPU time 351.34 seconds
Started Sep 24 06:51:40 PM UTC 24
Finished Sep 24 06:57:37 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3860038174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.flash_ctrl_intr_rd_slow_flash.3860038174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.39185148
Short name T255
Test name
Test status
Simulation time 335043500 ps
CPU time 21.67 seconds
Started Sep 24 05:25:29 PM UTC 24
Finished Sep 24 05:25:52 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39185148 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.39185148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1092895315
Short name T259
Test name
Test status
Simulation time 80795300 ps
CPU time 24.99 seconds
Started Sep 24 05:25:17 PM UTC 24
Finished Sep 24 05:25:43 PM UTC 24
Peak memory 286628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1092895315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1092895315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2519837421
Short name T201
Test name
Test status
Simulation time 107951000 ps
CPU time 149.47 seconds
Started Sep 24 05:46:45 PM UTC 24
Finished Sep 24 05:49:17 PM UTC 24
Peak memory 273220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519837421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2519837421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.642392304
Short name T82
Test name
Test status
Simulation time 3627641300 ps
CPU time 170.55 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:49:47 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642392304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.642392304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.787669983
Short name T9
Test name
Test status
Simulation time 15242800 ps
CPU time 20.16 seconds
Started Sep 24 05:49:51 PM UTC 24
Finished Sep 24 05:50:13 PM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=787669983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.787669983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3781485971
Short name T97
Test name
Test status
Simulation time 857843900 ps
CPU time 40.61 seconds
Started Sep 24 05:49:58 PM UTC 24
Finished Sep 24 05:50:40 PM UTC 24
Peak memory 275560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3781485971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3781485971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2682229864
Short name T211
Test name
Test status
Simulation time 264530947100 ps
CPU time 3133.92 seconds
Started Sep 24 05:54:58 PM UTC 24
Finished Sep 24 06:47:47 PM UTC 24
Peak memory 277996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682229864 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.2682229864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2417288269
Short name T100
Test name
Test status
Simulation time 814907600 ps
CPU time 25.59 seconds
Started Sep 24 05:59:48 PM UTC 24
Finished Sep 24 06:00:15 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2417288269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2417288269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.359723464
Short name T210
Test name
Test status
Simulation time 11547652900 ps
CPU time 289.43 seconds
Started Sep 24 06:03:54 PM UTC 24
Finished Sep 24 06:08:48 PM UTC 24
Peak memory 287740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=359723464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_derr_detect.359723464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1304079523
Short name T1156
Test name
Test status
Simulation time 5078606000 ps
CPU time 53.65 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:35 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304079523 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1304079523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3371068114
Short name T251
Test name
Test status
Simulation time 64268400 ps
CPU time 36.87 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:18 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371068114 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.3371068114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1204968092
Short name T230
Test name
Test status
Simulation time 27085600 ps
CPU time 15.75 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204968092 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.1204968092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.46590317
Short name T1132
Test name
Test status
Simulation time 29963500 ps
CPU time 15.28 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46590317 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.46590317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.389499450
Short name T281
Test name
Test status
Simulation time 217812400 ps
CPU time 40.21 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:25:21 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
389499450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_s
ame_csr_outstanding.389499450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1713893013
Short name T1135
Test name
Test status
Simulation time 111581900 ps
CPU time 18.27 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171
3893013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha
dow_reg_errors.1713893013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.915332006
Short name T1134
Test name
Test status
Simulation time 38404600 ps
CPU time 18.11 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=915332006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.915332006
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3197972301
Short name T128
Test name
Test status
Simulation time 43466700 ps
CPU time 18.25 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197972301 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3197972301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2870321105
Short name T392
Test name
Test status
Simulation time 6697510500 ps
CPU time 1162.06 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:44:15 PM UTC 24
Peak memory 278504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870321105 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.2870321105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2354227168
Short name T1169
Test name
Test status
Simulation time 473206600 ps
CPU time 39.67 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:49 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354227168 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.2354227168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2853675495
Short name T285
Test name
Test status
Simulation time 33837600 ps
CPU time 39.33 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:42 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853675495 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.2853675495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3533939725
Short name T226
Test name
Test status
Simulation time 289974500 ps
CPU time 22.37 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:32 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3533939725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3533939725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2130145065
Short name T249
Test name
Test status
Simulation time 111311600 ps
CPU time 15.17 seconds
Started Sep 24 05:24:40 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 274236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130145065 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2130145065
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2195842778
Short name T1133
Test name
Test status
Simulation time 31392700 ps
CPU time 15.15 seconds
Started Sep 24 05:24:40 PM UTC 24
Finished Sep 24 05:24:56 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195842778 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2195842778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3295583107
Short name T282
Test name
Test status
Simulation time 1023686700 ps
CPU time 25.39 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:35 PM UTC 24
Peak memory 274544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3295583107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
same_csr_outstanding.3295583107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2041517744
Short name T1137
Test name
Test status
Simulation time 37298100 ps
CPU time 18.67 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204
1517744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha
dow_reg_errors.2041517744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3192048414
Short name T1136
Test name
Test status
Simulation time 13804200 ps
CPU time 18.26 seconds
Started Sep 24 05:24:39 PM UTC 24
Finished Sep 24 05:24:59 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3192048414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3192048414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2327695477
Short name T1173
Test name
Test status
Simulation time 26157200 ps
CPU time 19.11 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:25:51 PM UTC 24
Peak memory 286820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2327695477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2327695477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.173832673
Short name T1183
Test name
Test status
Simulation time 273568200 ps
CPU time 25.53 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:25:58 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173832673 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.173832673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2423153126
Short name T1172
Test name
Test status
Simulation time 26695800 ps
CPU time 18.81 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:25:51 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423153126 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.2423153126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3100476999
Short name T1170
Test name
Test status
Simulation time 36363600 ps
CPU time 17.82 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:25:50 PM UTC 24
Peak memory 274404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3100476999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_same_csr_outstanding.3100476999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.197097384
Short name T1174
Test name
Test status
Simulation time 31654800 ps
CPU time 20.17 seconds
Started Sep 24 05:25:30 PM UTC 24
Finished Sep 24 05:25:52 PM UTC 24
Peak memory 274408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197
097384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sha
dow_reg_errors.197097384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1110383327
Short name T1168
Test name
Test status
Simulation time 13717500 ps
CPU time 16.71 seconds
Started Sep 24 05:25:30 PM UTC 24
Finished Sep 24 05:25:48 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1110383327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1110383327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3491210556
Short name T247
Test name
Test status
Simulation time 418131600 ps
CPU time 558.14 seconds
Started Sep 24 05:25:30 PM UTC 24
Finished Sep 24 05:34:56 PM UTC 24
Peak memory 276392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491210556 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.3491210556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.648117330
Short name T1190
Test name
Test status
Simulation time 51324700 ps
CPU time 26.28 seconds
Started Sep 24 05:25:34 PM UTC 24
Finished Sep 24 05:26:02 PM UTC 24
Peak memory 286828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=648117330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.648117330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1394936726
Short name T1182
Test name
Test status
Simulation time 102208500 ps
CPU time 22.85 seconds
Started Sep 24 05:25:33 PM UTC 24
Finished Sep 24 05:25:57 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394936726 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.1394936726
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1362316168
Short name T1177
Test name
Test status
Simulation time 23500900 ps
CPU time 18.65 seconds
Started Sep 24 05:25:33 PM UTC 24
Finished Sep 24 05:25:53 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362316168 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.1362316168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3404072719
Short name T1227
Test name
Test status
Simulation time 1192980300 ps
CPU time 53.9 seconds
Started Sep 24 05:25:34 PM UTC 24
Finished Sep 24 05:26:30 PM UTC 24
Peak memory 274532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3404072719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_same_csr_outstanding.3404072719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3579496591
Short name T1180
Test name
Test status
Simulation time 37246200 ps
CPU time 19.67 seconds
Started Sep 24 05:25:33 PM UTC 24
Finished Sep 24 05:25:54 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357
9496591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh
adow_reg_errors.3579496591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4189737833
Short name T1179
Test name
Test status
Simulation time 12879400 ps
CPU time 19.3 seconds
Started Sep 24 05:25:33 PM UTC 24
Finished Sep 24 05:25:54 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4189737833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f
lash_ctrl_shadow_reg_errors_with_csr_rw.4189737833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2514165084
Short name T1176
Test name
Test status
Simulation time 43445400 ps
CPU time 20.23 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:25:52 PM UTC 24
Peak memory 276596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514165084 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.2514165084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2546107588
Short name T246
Test name
Test status
Simulation time 1499236300 ps
CPU time 497.24 seconds
Started Sep 24 05:25:31 PM UTC 24
Finished Sep 24 05:33:55 PM UTC 24
Peak memory 276592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546107588 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.2546107588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2001207803
Short name T1189
Test name
Test status
Simulation time 160108100 ps
CPU time 23.22 seconds
Started Sep 24 05:25:37 PM UTC 24
Finished Sep 24 05:26:01 PM UTC 24
Peak memory 286632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2001207803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2001207803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2031874952
Short name T1188
Test name
Test status
Simulation time 81786200 ps
CPU time 21.82 seconds
Started Sep 24 05:25:36 PM UTC 24
Finished Sep 24 05:25:59 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031874952 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.2031874952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2542925421
Short name T1178
Test name
Test status
Simulation time 158623300 ps
CPU time 16.87 seconds
Started Sep 24 05:25:36 PM UTC 24
Finished Sep 24 05:25:54 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542925421 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.2542925421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1918366455
Short name T287
Test name
Test status
Simulation time 542246700 ps
CPU time 23.84 seconds
Started Sep 24 05:25:36 PM UTC 24
Finished Sep 24 05:26:01 PM UTC 24
Peak memory 276452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1918366455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_same_csr_outstanding.1918366455
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.804034057
Short name T1175
Test name
Test status
Simulation time 18387900 ps
CPU time 16.7 seconds
Started Sep 24 05:25:34 PM UTC 24
Finished Sep 24 05:25:52 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804
034057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sha
dow_reg_errors.804034057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1197052049
Short name T1185
Test name
Test status
Simulation time 10938500 ps
CPU time 21.3 seconds
Started Sep 24 05:25:36 PM UTC 24
Finished Sep 24 05:25:58 PM UTC 24
Peak memory 274388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1197052049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1197052049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.459630617
Short name T384
Test name
Test status
Simulation time 714820700 ps
CPU time 650.38 seconds
Started Sep 24 05:25:34 PM UTC 24
Finished Sep 24 05:36:33 PM UTC 24
Peak memory 276532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459630617 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.459630617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4057512609
Short name T1194
Test name
Test status
Simulation time 38516000 ps
CPU time 20.12 seconds
Started Sep 24 05:25:44 PM UTC 24
Finished Sep 24 05:26:05 PM UTC 24
Peak memory 286696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4057512609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.4057512609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1948702166
Short name T1195
Test name
Test status
Simulation time 127417600 ps
CPU time 20.32 seconds
Started Sep 24 05:25:44 PM UTC 24
Finished Sep 24 05:26:05 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948702166 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.1948702166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1950611755
Short name T1191
Test name
Test status
Simulation time 53163100 ps
CPU time 17.69 seconds
Started Sep 24 05:25:44 PM UTC 24
Finished Sep 24 05:26:03 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950611755 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1950611755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2729456039
Short name T1240
Test name
Test status
Simulation time 480912200 ps
CPU time 49.77 seconds
Started Sep 24 05:25:44 PM UTC 24
Finished Sep 24 05:26:35 PM UTC 24
Peak memory 274532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2729456039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_same_csr_outstanding.2729456039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3309031454
Short name T1187
Test name
Test status
Simulation time 14510200 ps
CPU time 18.35 seconds
Started Sep 24 05:25:39 PM UTC 24
Finished Sep 24 05:25:59 PM UTC 24
Peak memory 274404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330
9031454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh
adow_reg_errors.3309031454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.797844386
Short name T1193
Test name
Test status
Simulation time 29724300 ps
CPU time 24.86 seconds
Started Sep 24 05:25:39 PM UTC 24
Finished Sep 24 05:26:05 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=797844386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.797844386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2852661661
Short name T1184
Test name
Test status
Simulation time 73088100 ps
CPU time 18.86 seconds
Started Sep 24 05:25:38 PM UTC 24
Finished Sep 24 05:25:58 PM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852661661 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.2852661661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2380738126
Short name T383
Test name
Test status
Simulation time 423659700 ps
CPU time 587.04 seconds
Started Sep 24 05:25:38 PM UTC 24
Finished Sep 24 05:35:33 PM UTC 24
Peak memory 276656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380738126 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.2380738126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3568794644
Short name T1196
Test name
Test status
Simulation time 98731700 ps
CPU time 19.22 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:06 PM UTC 24
Peak memory 286696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3568794644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3568794644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.482516569
Short name T288
Test name
Test status
Simulation time 74876800 ps
CPU time 23.76 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:10 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482516569 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.482516569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1700683310
Short name T338
Test name
Test status
Simulation time 28860800 ps
CPU time 20.87 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:07 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700683310 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.1700683310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1689616567
Short name T1204
Test name
Test status
Simulation time 662026700 ps
CPU time 24.29 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:11 PM UTC 24
Peak memory 276624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1689616567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_same_csr_outstanding.1689616567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4198713970
Short name T1192
Test name
Test status
Simulation time 48917400 ps
CPU time 16.51 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:03 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419
8713970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh
adow_reg_errors.4198713970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1072640685
Short name T1205
Test name
Test status
Simulation time 85327700 ps
CPU time 25.18 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:12 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1072640685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1072640685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2304277928
Short name T1207
Test name
Test status
Simulation time 43579600 ps
CPU time 26.05 seconds
Started Sep 24 05:25:45 PM UTC 24
Finished Sep 24 05:26:13 PM UTC 24
Peak memory 276532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304277928 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.2304277928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.688043910
Short name T289
Test name
Test status
Simulation time 54895900 ps
CPU time 22.8 seconds
Started Sep 24 05:25:51 PM UTC 24
Finished Sep 24 05:26:15 PM UTC 24
Peak memory 286828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=688043910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.688043910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.305374076
Short name T1202
Test name
Test status
Simulation time 22734300 ps
CPU time 18.8 seconds
Started Sep 24 05:25:49 PM UTC 24
Finished Sep 24 05:26:09 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305374076 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.305374076
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2202624615
Short name T339
Test name
Test status
Simulation time 17181200 ps
CPU time 20.92 seconds
Started Sep 24 05:25:49 PM UTC 24
Finished Sep 24 05:26:11 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202624615 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.2202624615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3925661791
Short name T1203
Test name
Test status
Simulation time 37881100 ps
CPU time 19.6 seconds
Started Sep 24 05:25:50 PM UTC 24
Finished Sep 24 05:26:11 PM UTC 24
Peak memory 274336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3925661791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_same_csr_outstanding.3925661791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3671354568
Short name T1198
Test name
Test status
Simulation time 28233100 ps
CPU time 18.17 seconds
Started Sep 24 05:25:48 PM UTC 24
Finished Sep 24 05:26:07 PM UTC 24
Peak memory 274404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367
1354568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh
adow_reg_errors.3671354568
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.257558582
Short name T1197
Test name
Test status
Simulation time 32568700 ps
CPU time 16.05 seconds
Started Sep 24 05:25:49 PM UTC 24
Finished Sep 24 05:26:06 PM UTC 24
Peak memory 274084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=257558582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.257558582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4194439029
Short name T1200
Test name
Test status
Simulation time 242531600 ps
CPU time 20.14 seconds
Started Sep 24 05:25:47 PM UTC 24
Finished Sep 24 05:26:08 PM UTC 24
Peak memory 276596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194439029 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.4194439029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.59482063
Short name T1199
Test name
Test status
Simulation time 549934100 ps
CPU time 23.85 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:20 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=59482063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.59482063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1889520218
Short name T1211
Test name
Test status
Simulation time 384946600 ps
CPU time 20.74 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:17 PM UTC 24
Peak memory 274536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889520218 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.1889520218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3608711239
Short name T1206
Test name
Test status
Simulation time 15877600 ps
CPU time 15.75 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:12 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608711239 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.3608711239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2363893140
Short name T290
Test name
Test status
Simulation time 479093300 ps
CPU time 28.13 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:25 PM UTC 24
Peak memory 274340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2363893140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_same_csr_outstanding.2363893140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1514026260
Short name T1210
Test name
Test status
Simulation time 24105900 ps
CPU time 20.52 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:17 PM UTC 24
Peak memory 274140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151
4026260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh
adow_reg_errors.1514026260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1201113340
Short name T1213
Test name
Test status
Simulation time 13453500 ps
CPU time 21.76 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:18 PM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1201113340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1201113340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.431695593
Short name T1209
Test name
Test status
Simulation time 33452700 ps
CPU time 23.18 seconds
Started Sep 24 05:25:51 PM UTC 24
Finished Sep 24 05:26:16 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431695593 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.431695593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1964929622
Short name T1261
Test name
Test status
Simulation time 400824500 ps
CPU time 638.73 seconds
Started Sep 24 05:25:51 PM UTC 24
Finished Sep 24 05:36:39 PM UTC 24
Peak memory 276392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964929622 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.1964929622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2495704560
Short name T291
Test name
Test status
Simulation time 91340900 ps
CPU time 24.3 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:26 PM UTC 24
Peak memory 286632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2495704560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2495704560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.589649198
Short name T1165
Test name
Test status
Simulation time 32123500 ps
CPU time 21.93 seconds
Started Sep 24 05:25:57 PM UTC 24
Finished Sep 24 05:26:21 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589649198 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.589649198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.4007853895
Short name T1208
Test name
Test status
Simulation time 53988000 ps
CPU time 17.13 seconds
Started Sep 24 05:25:56 PM UTC 24
Finished Sep 24 05:26:15 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007853895 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.4007853895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4019694420
Short name T1219
Test name
Test status
Simulation time 124254400 ps
CPU time 23.97 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:25 PM UTC 24
Peak memory 274340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4019694420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_same_csr_outstanding.4019694420
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3120860467
Short name T1214
Test name
Test status
Simulation time 11176400 ps
CPU time 23.33 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:20 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312
0860467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh
adow_reg_errors.3120860467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1497715045
Short name T1212
Test name
Test status
Simulation time 47929200 ps
CPU time 21.16 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:18 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1497715045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1497715045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2447256368
Short name T257
Test name
Test status
Simulation time 46529600 ps
CPU time 23.49 seconds
Started Sep 24 05:25:55 PM UTC 24
Finished Sep 24 05:26:20 PM UTC 24
Peak memory 276332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447256368 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.2447256368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2097418974
Short name T1224
Test name
Test status
Simulation time 31627700 ps
CPU time 23.34 seconds
Started Sep 24 05:26:03 PM UTC 24
Finished Sep 24 05:26:27 PM UTC 24
Peak memory 286824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2097418974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2097418974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3307656850
Short name T1231
Test name
Test status
Simulation time 142248500 ps
CPU time 29.37 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:31 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307656850 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.3307656850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2484741424
Short name T1215
Test name
Test status
Simulation time 40250600 ps
CPU time 19.43 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:21 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484741424 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.2484741424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2876473520
Short name T292
Test name
Test status
Simulation time 103134600 ps
CPU time 24.65 seconds
Started Sep 24 05:26:02 PM UTC 24
Finished Sep 24 05:26:27 PM UTC 24
Peak memory 274532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2876473520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_same_csr_outstanding.2876473520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1332261824
Short name T1216
Test name
Test status
Simulation time 23053900 ps
CPU time 21.86 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:23 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133
2261824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh
adow_reg_errors.1332261824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3697451290
Short name T1220
Test name
Test status
Simulation time 13752700 ps
CPU time 24.17 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:26 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3697451290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3697451290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.825653988
Short name T378
Test name
Test status
Simulation time 390778000 ps
CPU time 22.04 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:26:24 PM UTC 24
Peak memory 276536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825653988 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.825653988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.187997202
Short name T390
Test name
Test status
Simulation time 443331600 ps
CPU time 716.76 seconds
Started Sep 24 05:26:00 PM UTC 24
Finished Sep 24 05:38:07 PM UTC 24
Peak memory 276596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187997202 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.187997202
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1566217618
Short name T1235
Test name
Test status
Simulation time 219583100 ps
CPU time 24.67 seconds
Started Sep 24 05:26:07 PM UTC 24
Finished Sep 24 05:26:33 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1566217618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1566217618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1492711798
Short name T1226
Test name
Test status
Simulation time 177175800 ps
CPU time 21.48 seconds
Started Sep 24 05:26:06 PM UTC 24
Finished Sep 24 05:26:29 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492711798 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1492711798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.1029323662
Short name T1233
Test name
Test status
Simulation time 42068100 ps
CPU time 24.44 seconds
Started Sep 24 05:26:06 PM UTC 24
Finished Sep 24 05:26:32 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029323662 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.1029323662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3076874350
Short name T1239
Test name
Test status
Simulation time 168459600 ps
CPU time 26.8 seconds
Started Sep 24 05:26:07 PM UTC 24
Finished Sep 24 05:26:35 PM UTC 24
Peak memory 274532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3076874350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_same_csr_outstanding.3076874350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.11617142
Short name T1217
Test name
Test status
Simulation time 12993400 ps
CPU time 19.71 seconds
Started Sep 24 05:26:04 PM UTC 24
Finished Sep 24 05:26:25 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116
17142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shad
ow_reg_errors.11617142
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.431942691
Short name T1218
Test name
Test status
Simulation time 55145200 ps
CPU time 17.78 seconds
Started Sep 24 05:26:06 PM UTC 24
Finished Sep 24 05:26:25 PM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=431942691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.431942691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3827703362
Short name T1221
Test name
Test status
Simulation time 83294900 ps
CPU time 22.03 seconds
Started Sep 24 05:26:03 PM UTC 24
Finished Sep 24 05:26:26 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827703362 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.3827703362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.6863441
Short name T1262
Test name
Test status
Simulation time 1415943700 ps
CPU time 664.58 seconds
Started Sep 24 05:26:04 PM UTC 24
Finished Sep 24 05:37:18 PM UTC 24
Peak memory 276652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6863441 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.6863441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3541128655
Short name T398
Test name
Test status
Simulation time 1036833600 ps
CPU time 34.52 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:26 PM UTC 24
Peak memory 273820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541128655 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.3541128655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2022799605
Short name T395
Test name
Test status
Simulation time 1144849000 ps
CPU time 34.4 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:26 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022799605 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.2022799605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1163958287
Short name T1150
Test name
Test status
Simulation time 62194100 ps
CPU time 36.48 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:28 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163958287 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.1163958287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3175364354
Short name T130
Test name
Test status
Simulation time 83643300 ps
CPU time 26.68 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:19 PM UTC 24
Peak memory 286208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3175364354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3175364354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.88299362
Short name T334
Test name
Test status
Simulation time 24039700 ps
CPU time 15.32 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:07 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88299362 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.88299362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1972574699
Short name T231
Test name
Test status
Simulation time 60554700 ps
CPU time 15.64 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:07 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972574699 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.1972574699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.43309609
Short name T1138
Test name
Test status
Simulation time 27744100 ps
CPU time 16.03 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:07 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43309609 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.43309609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2600986237
Short name T237
Test name
Test status
Simulation time 116165000 ps
CPU time 22.34 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:14 PM UTC 24
Peak memory 274476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2600986237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
same_csr_outstanding.2600986237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2058909664
Short name T1152
Test name
Test status
Simulation time 25305500 ps
CPU time 22.9 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:33 PM UTC 24
Peak memory 274108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205
8909664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha
dow_reg_errors.2058909664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1189252165
Short name T1148
Test name
Test status
Simulation time 25270900 ps
CPU time 22.06 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:28 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1189252165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1189252165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3758391604
Short name T225
Test name
Test status
Simulation time 210735400 ps
CPU time 20.05 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:25:30 PM UTC 24
Peak memory 276408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758391604 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3758391604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4283589424
Short name T386
Test name
Test status
Simulation time 1661641100 ps
CPU time 1197.44 seconds
Started Sep 24 05:24:41 PM UTC 24
Finished Sep 24 05:45:21 PM UTC 24
Peak memory 276308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283589424 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.4283589424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1295266631
Short name T1223
Test name
Test status
Simulation time 24111600 ps
CPU time 16.59 seconds
Started Sep 24 05:26:08 PM UTC 24
Finished Sep 24 05:26:26 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295266631 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.1295266631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2264492064
Short name T1222
Test name
Test status
Simulation time 45415500 ps
CPU time 16.4 seconds
Started Sep 24 05:26:08 PM UTC 24
Finished Sep 24 05:26:26 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264492064 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.2264492064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.1757181263
Short name T1225
Test name
Test status
Simulation time 19861400 ps
CPU time 17.4 seconds
Started Sep 24 05:26:09 PM UTC 24
Finished Sep 24 05:26:28 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757181263 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.1757181263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3455779095
Short name T1229
Test name
Test status
Simulation time 16033800 ps
CPU time 19.41 seconds
Started Sep 24 05:26:09 PM UTC 24
Finished Sep 24 05:26:30 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455779095 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.3455779095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3935364220
Short name T1232
Test name
Test status
Simulation time 50290300 ps
CPU time 20.35 seconds
Started Sep 24 05:26:10 PM UTC 24
Finished Sep 24 05:26:31 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935364220 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.3935364220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.1937035054
Short name T1241
Test name
Test status
Simulation time 270266100 ps
CPU time 22.41 seconds
Started Sep 24 05:26:12 PM UTC 24
Finished Sep 24 05:26:36 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937035054 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.1937035054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2865508005
Short name T1245
Test name
Test status
Simulation time 17152200 ps
CPU time 23.71 seconds
Started Sep 24 05:26:12 PM UTC 24
Finished Sep 24 05:26:37 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865508005 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.2865508005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3446430143
Short name T1230
Test name
Test status
Simulation time 36413400 ps
CPU time 17.11 seconds
Started Sep 24 05:26:12 PM UTC 24
Finished Sep 24 05:26:30 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446430143 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.3446430143
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2561057632
Short name T1228
Test name
Test status
Simulation time 17296900 ps
CPU time 17.11 seconds
Started Sep 24 05:26:12 PM UTC 24
Finished Sep 24 05:26:30 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561057632 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.2561057632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.1176373845
Short name T1234
Test name
Test status
Simulation time 50492900 ps
CPU time 18.78 seconds
Started Sep 24 05:26:13 PM UTC 24
Finished Sep 24 05:26:33 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176373845 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.1176373845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1985398841
Short name T1162
Test name
Test status
Simulation time 1083225600 ps
CPU time 48.78 seconds
Started Sep 24 05:24:47 PM UTC 24
Finished Sep 24 05:25:41 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985398841 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1985398841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3166691523
Short name T400
Test name
Test status
Simulation time 669977800 ps
CPU time 40.07 seconds
Started Sep 24 05:24:47 PM UTC 24
Finished Sep 24 05:25:32 PM UTC 24
Peak memory 276316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166691523 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.3166691523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.640734185
Short name T74
Test name
Test status
Simulation time 29270900 ps
CPU time 36.33 seconds
Started Sep 24 05:24:46 PM UTC 24
Finished Sep 24 05:25:33 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640734185 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.640734185
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.908467134
Short name T132
Test name
Test status
Simulation time 58155400 ps
CPU time 16.72 seconds
Started Sep 24 05:24:47 PM UTC 24
Finished Sep 24 05:25:08 PM UTC 24
Peak memory 274508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908467134 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.908467134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3697627031
Short name T232
Test name
Test status
Simulation time 16786300 ps
CPU time 15.8 seconds
Started Sep 24 05:24:46 PM UTC 24
Finished Sep 24 05:25:13 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697627031 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.3697627031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3269337234
Short name T1139
Test name
Test status
Simulation time 17773800 ps
CPU time 15.41 seconds
Started Sep 24 05:24:46 PM UTC 24
Finished Sep 24 05:25:12 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269337234 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.3269337234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2083594517
Short name T235
Test name
Test status
Simulation time 131317200 ps
CPU time 16.66 seconds
Started Sep 24 05:24:47 PM UTC 24
Finished Sep 24 05:25:08 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2083594517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
same_csr_outstanding.2083594517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2768232224
Short name T1140
Test name
Test status
Simulation time 22745300 ps
CPU time 22.1 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:25:14 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276
8232224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha
dow_reg_errors.2768232224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1519204694
Short name T1143
Test name
Test status
Simulation time 19743600 ps
CPU time 18.97 seconds
Started Sep 24 05:24:46 PM UTC 24
Finished Sep 24 05:25:16 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1519204694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1519204694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2519917648
Short name T385
Test name
Test status
Simulation time 944707300 ps
CPU time 1178.98 seconds
Started Sep 24 05:24:43 PM UTC 24
Finished Sep 24 05:44:45 PM UTC 24
Peak memory 278504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519917648 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.2519917648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.267490429
Short name T1244
Test name
Test status
Simulation time 45208000 ps
CPU time 22.51 seconds
Started Sep 24 05:26:13 PM UTC 24
Finished Sep 24 05:26:37 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267490429 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.267490429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2071444579
Short name T1238
Test name
Test status
Simulation time 79726300 ps
CPU time 19.99 seconds
Started Sep 24 05:26:13 PM UTC 24
Finished Sep 24 05:26:34 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071444579 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.2071444579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.2577553935
Short name T1236
Test name
Test status
Simulation time 17030200 ps
CPU time 17.81 seconds
Started Sep 24 05:26:15 PM UTC 24
Finished Sep 24 05:26:34 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577553935 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.2577553935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1237837050
Short name T1237
Test name
Test status
Simulation time 31854300 ps
CPU time 17.02 seconds
Started Sep 24 05:26:16 PM UTC 24
Finished Sep 24 05:26:34 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237837050 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.1237837050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.4019639182
Short name T1248
Test name
Test status
Simulation time 61402000 ps
CPU time 21.68 seconds
Started Sep 24 05:26:17 PM UTC 24
Finished Sep 24 05:26:40 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019639182 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.4019639182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2056729418
Short name T1243
Test name
Test status
Simulation time 17576800 ps
CPU time 18.36 seconds
Started Sep 24 05:26:17 PM UTC 24
Finished Sep 24 05:26:37 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056729418 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2056729418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3940107236
Short name T1242
Test name
Test status
Simulation time 16432000 ps
CPU time 17.15 seconds
Started Sep 24 05:26:18 PM UTC 24
Finished Sep 24 05:26:37 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940107236 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.3940107236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1864878007
Short name T1255
Test name
Test status
Simulation time 14504300 ps
CPU time 24.46 seconds
Started Sep 24 05:26:18 PM UTC 24
Finished Sep 24 05:26:44 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864878007 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.1864878007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1748975744
Short name T1253
Test name
Test status
Simulation time 21703200 ps
CPU time 21.94 seconds
Started Sep 24 05:26:20 PM UTC 24
Finished Sep 24 05:26:43 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748975744 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.1748975744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1240798298
Short name T1246
Test name
Test status
Simulation time 56995000 ps
CPU time 17.64 seconds
Started Sep 24 05:26:21 PM UTC 24
Finished Sep 24 05:26:39 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240798298 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.1240798298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3168892401
Short name T1171
Test name
Test status
Simulation time 818553300 ps
CPU time 51.39 seconds
Started Sep 24 05:24:58 PM UTC 24
Finished Sep 24 05:25:51 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168892401 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3168892401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2776534960
Short name T1258
Test name
Test status
Simulation time 9240748300 ps
CPU time 105.34 seconds
Started Sep 24 05:24:58 PM UTC 24
Finished Sep 24 05:26:45 PM UTC 24
Peak memory 276328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776534960 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.2776534960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.816054762
Short name T1153
Test name
Test status
Simulation time 20772100 ps
CPU time 33.93 seconds
Started Sep 24 05:24:57 PM UTC 24
Finished Sep 24 05:25:33 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816054762 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.816054762
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1515106630
Short name T298
Test name
Test status
Simulation time 57358100 ps
CPU time 24.38 seconds
Started Sep 24 05:24:57 PM UTC 24
Finished Sep 24 05:25:23 PM UTC 24
Peak memory 274476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515106630 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.1515106630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4010421421
Short name T337
Test name
Test status
Simulation time 53036000 ps
CPU time 17.77 seconds
Started Sep 24 05:24:57 PM UTC 24
Finished Sep 24 05:25:16 PM UTC 24
Peak memory 274428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010421421 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.4010421421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3470462807
Short name T233
Test name
Test status
Simulation time 115068000 ps
CPU time 19.71 seconds
Started Sep 24 05:24:57 PM UTC 24
Finished Sep 24 05:25:18 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470462807 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.3470462807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3889921127
Short name T1142
Test name
Test status
Simulation time 52200500 ps
CPU time 16.65 seconds
Started Sep 24 05:24:57 PM UTC 24
Finished Sep 24 05:25:15 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889921127 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.3889921127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2617474165
Short name T252
Test name
Test status
Simulation time 304517300 ps
CPU time 23.41 seconds
Started Sep 24 05:24:58 PM UTC 24
Finished Sep 24 05:25:22 PM UTC 24
Peak memory 276652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2617474165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
same_csr_outstanding.2617474165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1262159553
Short name T1144
Test name
Test status
Simulation time 37221300 ps
CPU time 20.12 seconds
Started Sep 24 05:24:55 PM UTC 24
Finished Sep 24 05:25:16 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126
2159553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha
dow_reg_errors.1262159553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.439865730
Short name T1141
Test name
Test status
Simulation time 12302900 ps
CPU time 18.4 seconds
Started Sep 24 05:24:55 PM UTC 24
Finished Sep 24 05:25:15 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=439865730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.439865730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2808788001
Short name T206
Test name
Test status
Simulation time 211223400 ps
CPU time 19.46 seconds
Started Sep 24 05:24:49 PM UTC 24
Finished Sep 24 05:25:11 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808788001 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2808788001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.4155026306
Short name T1247
Test name
Test status
Simulation time 44246800 ps
CPU time 17.84 seconds
Started Sep 24 05:26:21 PM UTC 24
Finished Sep 24 05:26:40 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155026306 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.4155026306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1537926465
Short name T1249
Test name
Test status
Simulation time 18619700 ps
CPU time 17.99 seconds
Started Sep 24 05:26:22 PM UTC 24
Finished Sep 24 05:26:41 PM UTC 24
Peak memory 274024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537926465 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.1537926465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.954552288
Short name T1254
Test name
Test status
Simulation time 43553400 ps
CPU time 19.86 seconds
Started Sep 24 05:26:22 PM UTC 24
Finished Sep 24 05:26:43 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954552288 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.954552288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2714667066
Short name T1256
Test name
Test status
Simulation time 56303700 ps
CPU time 21.45 seconds
Started Sep 24 05:26:22 PM UTC 24
Finished Sep 24 05:26:44 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714667066 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.2714667066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3871983414
Short name T1250
Test name
Test status
Simulation time 54704400 ps
CPU time 16.59 seconds
Started Sep 24 05:26:24 PM UTC 24
Finished Sep 24 05:26:42 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871983414 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.3871983414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.2290756310
Short name T1251
Test name
Test status
Simulation time 15270700 ps
CPU time 16.85 seconds
Started Sep 24 05:26:24 PM UTC 24
Finished Sep 24 05:26:42 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290756310 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.2290756310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1996475855
Short name T1252
Test name
Test status
Simulation time 21904000 ps
CPU time 16.31 seconds
Started Sep 24 05:26:25 PM UTC 24
Finished Sep 24 05:26:43 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996475855 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.1996475855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3201284658
Short name T1259
Test name
Test status
Simulation time 25168100 ps
CPU time 17.88 seconds
Started Sep 24 05:26:26 PM UTC 24
Finished Sep 24 05:26:45 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201284658 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.3201284658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1816379672
Short name T1257
Test name
Test status
Simulation time 42666300 ps
CPU time 17.32 seconds
Started Sep 24 05:26:26 PM UTC 24
Finished Sep 24 05:26:45 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816379672 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.1816379672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.2438776868
Short name T1260
Test name
Test status
Simulation time 15174700 ps
CPU time 18.62 seconds
Started Sep 24 05:26:26 PM UTC 24
Finished Sep 24 05:26:46 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438776868 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.2438776868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.672262632
Short name T402
Test name
Test status
Simulation time 90251600 ps
CPU time 26.07 seconds
Started Sep 24 05:25:02 PM UTC 24
Finished Sep 24 05:25:33 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=672262632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.672262632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1112532041
Short name T396
Test name
Test status
Simulation time 32454000 ps
CPU time 22.44 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:24 PM UTC 24
Peak memory 273860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112532041 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.1112532041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.580065013
Short name T342
Test name
Test status
Simulation time 17209200 ps
CPU time 23.46 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:25 PM UTC 24
Peak memory 274348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580065013 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.580065013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.6138832
Short name T1147
Test name
Test status
Simulation time 111792200 ps
CPU time 25.07 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:27 PM UTC 24
Peak memory 275732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
6138832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sam
e_csr_outstanding.6138832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3914466704
Short name T1146
Test name
Test status
Simulation time 40544900 ps
CPU time 19.87 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:21 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391
4466704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha
dow_reg_errors.3914466704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.826995235
Short name T1145
Test name
Test status
Simulation time 15023400 ps
CPU time 18.87 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:20 PM UTC 24
Peak memory 274400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=826995235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.826995235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1352079828
Short name T223
Test name
Test status
Simulation time 237044400 ps
CPU time 22.74 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:25:24 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352079828 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1352079828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2089148233
Short name T391
Test name
Test status
Simulation time 260744100 ps
CPU time 673.13 seconds
Started Sep 24 05:25:00 PM UTC 24
Finished Sep 24 05:36:22 PM UTC 24
Peak memory 278512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089148233 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2089148233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.801555598
Short name T283
Test name
Test status
Simulation time 107098900 ps
CPU time 22.41 seconds
Started Sep 24 05:25:12 PM UTC 24
Finished Sep 24 05:25:36 PM UTC 24
Peak memory 286628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=801555598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.801555598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1210386974
Short name T401
Test name
Test status
Simulation time 29734300 ps
CPU time 21.36 seconds
Started Sep 24 05:25:09 PM UTC 24
Finished Sep 24 05:25:32 PM UTC 24
Peak memory 274476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210386974 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.1210386974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.861619972
Short name T336
Test name
Test status
Simulation time 29332600 ps
CPU time 23.45 seconds
Started Sep 24 05:25:09 PM UTC 24
Finished Sep 24 05:25:33 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861619972 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.861619972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.520693336
Short name T1157
Test name
Test status
Simulation time 164828600 ps
CPU time 23.38 seconds
Started Sep 24 05:25:12 PM UTC 24
Finished Sep 24 05:25:37 PM UTC 24
Peak memory 274352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
520693336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_s
ame_csr_outstanding.520693336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2764530200
Short name T1149
Test name
Test status
Simulation time 12626200 ps
CPU time 19.17 seconds
Started Sep 24 05:25:08 PM UTC 24
Finished Sep 24 05:25:28 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276
4530200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha
dow_reg_errors.2764530200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1346503047
Short name T1154
Test name
Test status
Simulation time 17383900 ps
CPU time 22.72 seconds
Started Sep 24 05:25:09 PM UTC 24
Finished Sep 24 05:25:34 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1346503047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1346503047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2218896308
Short name T253
Test name
Test status
Simulation time 113988900 ps
CPU time 26.25 seconds
Started Sep 24 05:25:08 PM UTC 24
Finished Sep 24 05:25:35 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218896308 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2218896308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1954714571
Short name T379
Test name
Test status
Simulation time 353715300 ps
CPU time 639.92 seconds
Started Sep 24 05:25:08 PM UTC 24
Finished Sep 24 05:35:56 PM UTC 24
Peak memory 276672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954714571 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.1954714571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2795464206
Short name T284
Test name
Test status
Simulation time 147636300 ps
CPU time 23.51 seconds
Started Sep 24 05:25:15 PM UTC 24
Finished Sep 24 05:25:40 PM UTC 24
Peak memory 274412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795464206 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.2795464206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.616381240
Short name T1186
Test name
Test status
Simulation time 872509000 ps
CPU time 41.46 seconds
Started Sep 24 05:25:16 PM UTC 24
Finished Sep 24 05:25:58 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
616381240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_s
ame_csr_outstanding.616381240
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2103132326
Short name T1158
Test name
Test status
Simulation time 15918500 ps
CPU time 22.34 seconds
Started Sep 24 05:25:14 PM UTC 24
Finished Sep 24 05:25:38 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210
3132326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha
dow_reg_errors.2103132326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.508548111
Short name T1155
Test name
Test status
Simulation time 22789900 ps
CPU time 17.92 seconds
Started Sep 24 05:25:15 PM UTC 24
Finished Sep 24 05:25:34 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=508548111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.508548111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3968502086
Short name T258
Test name
Test status
Simulation time 71213500 ps
CPU time 26.54 seconds
Started Sep 24 05:25:13 PM UTC 24
Finished Sep 24 05:25:41 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968502086 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3968502086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1974089427
Short name T393
Test name
Test status
Simulation time 1394163200 ps
CPU time 1211.43 seconds
Started Sep 24 05:25:13 PM UTC 24
Finished Sep 24 05:45:41 PM UTC 24
Peak memory 278548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974089427 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.1974089427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3640938623
Short name T286
Test name
Test status
Simulation time 737473600 ps
CPU time 20.57 seconds
Started Sep 24 05:25:21 PM UTC 24
Finished Sep 24 05:25:43 PM UTC 24
Peak memory 286824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3640938623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3640938623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4250901472
Short name T399
Test name
Test status
Simulation time 34520600 ps
CPU time 17.09 seconds
Started Sep 24 05:25:19 PM UTC 24
Finished Sep 24 05:25:37 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250901472 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.4250901472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.501307191
Short name T341
Test name
Test status
Simulation time 30817900 ps
CPU time 21.34 seconds
Started Sep 24 05:25:19 PM UTC 24
Finished Sep 24 05:25:41 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501307191 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.501307191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3449723333
Short name T1166
Test name
Test status
Simulation time 2721293700 ps
CPU time 25.87 seconds
Started Sep 24 05:25:20 PM UTC 24
Finished Sep 24 05:25:47 PM UTC 24
Peak memory 276388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3449723333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
same_csr_outstanding.3449723333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2400877734
Short name T1161
Test name
Test status
Simulation time 24366700 ps
CPU time 21.18 seconds
Started Sep 24 05:25:18 PM UTC 24
Finished Sep 24 05:25:40 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240
0877734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha
dow_reg_errors.2400877734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.925220799
Short name T1159
Test name
Test status
Simulation time 44159600 ps
CPU time 19.75 seconds
Started Sep 24 05:25:18 PM UTC 24
Finished Sep 24 05:25:39 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=925220799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.925220799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3057162696
Short name T1151
Test name
Test status
Simulation time 191867000 ps
CPU time 20.82 seconds
Started Sep 24 05:25:17 PM UTC 24
Finished Sep 24 05:25:39 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057162696 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3057162696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.931900081
Short name T380
Test name
Test status
Simulation time 1322630000 ps
CPU time 1165.54 seconds
Started Sep 24 05:25:17 PM UTC 24
Finished Sep 24 05:44:57 PM UTC 24
Peak memory 276456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931900081 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.931900081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.184403427
Short name T1181
Test name
Test status
Simulation time 85716800 ps
CPU time 24.58 seconds
Started Sep 24 05:25:29 PM UTC 24
Finished Sep 24 05:25:55 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=184403427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.184403427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1093670672
Short name T1167
Test name
Test status
Simulation time 54494400 ps
CPU time 22.25 seconds
Started Sep 24 05:25:25 PM UTC 24
Finished Sep 24 05:25:48 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093670672 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.1093670672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1203954236
Short name T1163
Test name
Test status
Simulation time 18663900 ps
CPU time 19.4 seconds
Started Sep 24 05:25:25 PM UTC 24
Finished Sep 24 05:25:45 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203954236 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1203954236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2293948642
Short name T1201
Test name
Test status
Simulation time 983366500 ps
CPU time 42.12 seconds
Started Sep 24 05:25:25 PM UTC 24
Finished Sep 24 05:26:08 PM UTC 24
Peak memory 276588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2293948642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
same_csr_outstanding.2293948642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1859277984
Short name T1160
Test name
Test status
Simulation time 42202200 ps
CPU time 15.79 seconds
Started Sep 24 05:25:22 PM UTC 24
Finished Sep 24 05:25:39 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185
9277984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha
dow_reg_errors.1859277984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3426110416
Short name T1164
Test name
Test status
Simulation time 12154100 ps
CPU time 21.84 seconds
Started Sep 24 05:25:23 PM UTC 24
Finished Sep 24 05:25:47 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3426110416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3426110416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4111578730
Short name T254
Test name
Test status
Simulation time 94982200 ps
CPU time 24.03 seconds
Started Sep 24 05:25:22 PM UTC 24
Finished Sep 24 05:25:48 PM UTC 24
Peak memory 276212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111578730 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4111578730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.685717398
Short name T381
Test name
Test status
Simulation time 353292900 ps
CPU time 1202.07 seconds
Started Sep 24 05:25:22 PM UTC 24
Finished Sep 24 05:45:40 PM UTC 24
Peak memory 278092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685717398 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.685717398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1168527572
Short name T5
Test name
Test status
Simulation time 29466100 ps
CPU time 16.36 seconds
Started Sep 24 05:47:06 PM UTC 24
Finished Sep 24 05:47:23 PM UTC 24
Peak memory 275364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1168527572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1168527572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2748595770
Short name T114
Test name
Test status
Simulation time 42700800 ps
CPU time 25.93 seconds
Started Sep 24 05:47:22 PM UTC 24
Finished Sep 24 05:47:50 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748595770 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2748595770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2598859167
Short name T6
Test name
Test status
Simulation time 13035300 ps
CPU time 28.21 seconds
Started Sep 24 05:47:02 PM UTC 24
Finished Sep 24 05:47:32 PM UTC 24
Peak memory 285448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2598859167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_disable.2598859167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.4035070125
Short name T63
Test name
Test status
Simulation time 3521792900 ps
CPU time 528.31 seconds
Started Sep 24 05:46:46 PM UTC 24
Finished Sep 24 05:55:42 PM UTC 24
Peak memory 277872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035070125 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.4035070125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.1542157120
Short name T823
Test name
Test status
Simulation time 54782485600 ps
CPU time 3888.94 seconds
Started Sep 24 05:46:47 PM UTC 24
Finished Sep 24 06:52:21 PM UTC 24
Peak memory 277816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542157120 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.1542157120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1559674475
Short name T57
Test name
Test status
Simulation time 39577200 ps
CPU time 48.49 seconds
Started Sep 24 05:47:21 PM UTC 24
Finished Sep 24 05:48:11 PM UTC 24
Peak memory 287476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155967447
5 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho
st_addr_infection.1559674475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.4135092833
Short name T36
Test name
Test status
Simulation time 136038400 ps
CPU time 83.1 seconds
Started Sep 24 05:46:45 PM UTC 24
Finished Sep 24 05:48:10 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135092833 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.4135092833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1614619594
Short name T134
Test name
Test status
Simulation time 10012213900 ps
CPU time 206.9 seconds
Started Sep 24 05:47:18 PM UTC 24
Finished Sep 24 05:50:48 PM UTC 24
Peak memory 359252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1614619594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1614619594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3544521125
Short name T137
Test name
Test status
Simulation time 448531366000 ps
CPU time 1854.9 seconds
Started Sep 24 05:46:46 PM UTC 24
Finished Sep 24 06:18:03 PM UTC 24
Peak memory 273800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544521125
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.3544521125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.601284870
Short name T55
Test name
Test status
Simulation time 1685368100 ps
CPU time 70.43 seconds
Started Sep 24 05:46:45 PM UTC 24
Finished Sep 24 05:47:57 PM UTC 24
Peak memory 273028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601284870 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.601284870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3575828828
Short name T44
Test name
Test status
Simulation time 2788213300 ps
CPU time 165.07 seconds
Started Sep 24 05:47:00 PM UTC 24
Finished Sep 24 05:49:48 PM UTC 24
Peak memory 302196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575828828 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.3575828828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.985364731
Short name T42
Test name
Test status
Simulation time 18754347900 ps
CPU time 199.18 seconds
Started Sep 24 05:47:00 PM UTC 24
Finished Sep 24 05:50:22 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985364731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.985364731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3665694341
Short name T33
Test name
Test status
Simulation time 5929520400 ps
CPU time 77.67 seconds
Started Sep 24 05:46:50 PM UTC 24
Finished Sep 24 05:48:09 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665694341 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3665694341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1254793278
Short name T7
Test name
Test status
Simulation time 135310000 ps
CPU time 19.16 seconds
Started Sep 24 05:47:14 PM UTC 24
Finished Sep 24 05:47:34 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1254793278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_lcmgr_intg.1254793278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.514480531
Short name T221
Test name
Test status
Simulation time 1374052800 ps
CPU time 454.59 seconds
Started Sep 24 05:46:45 PM UTC 24
Finished Sep 24 05:54:26 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514480531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.514480531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2610838892
Short name T12
Test name
Test status
Simulation time 44643000 ps
CPU time 23.44 seconds
Started Sep 24 05:47:09 PM UTC 24
Finished Sep 24 05:47:34 PM UTC 24
Peak memory 273484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2610838892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2610838892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.666371784
Short name T22
Test name
Test status
Simulation time 20028200 ps
CPU time 25.53 seconds
Started Sep 24 05:47:01 PM UTC 24
Finished Sep 24 05:47:28 PM UTC 24
Peak memory 271288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666371784 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.666371784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.380376118
Short name T332
Test name
Test status
Simulation time 664884600 ps
CPU time 1917.81 seconds
Started Sep 24 05:46:44 PM UTC 24
Finished Sep 24 06:19:02 PM UTC 24
Peak memory 300392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380376118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.380376118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.526399833
Short name T69
Test name
Test status
Simulation time 109477800 ps
CPU time 71.63 seconds
Started Sep 24 05:47:19 PM UTC 24
Finished Sep 24 05:48:32 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526399833 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.526399833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.3526670049
Short name T2
Test name
Test status
Simulation time 44839900 ps
CPU time 18.22 seconds
Started Sep 24 05:46:52 PM UTC 24
Finished Sep 24 05:47:11 PM UTC 24
Peak memory 275124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526670049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.3526670049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.1189309751
Short name T18
Test name
Test status
Simulation time 31072100 ps
CPU time 28.65 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:47:23 PM UTC 24
Peak memory 275576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1189309751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_read_word_sweep_derr.1189309751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2651971941
Short name T17
Test name
Test status
Simulation time 42346200 ps
CPU time 28.62 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:47:23 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651971941 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.2651971941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2815781916
Short name T70
Test name
Test status
Simulation time 592008400 ps
CPU time 121.49 seconds
Started Sep 24 05:46:52 PM UTC 24
Finished Sep 24 05:48:56 PM UTC 24
Peak memory 304164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2815781916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.2815781916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.3986963636
Short name T217
Test name
Test status
Simulation time 7293874500 ps
CPU time 486.54 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:55:07 PM UTC 24
Peak memory 332796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986963636 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.3986963636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.285605622
Short name T38
Test name
Test status
Simulation time 45460100 ps
CPU time 39.9 seconds
Started Sep 24 05:47:01 PM UTC 24
Finished Sep 24 05:47:42 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285605622 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.285605622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.97757740
Short name T118
Test name
Test status
Simulation time 1862623200 ps
CPU time 246.65 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:51:04 PM UTC 24
Peak memory 291852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=97757740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.97757740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.3201989184
Short name T13
Test name
Test status
Simulation time 6744563000 ps
CPU time 6803.01 seconds
Started Sep 24 05:47:02 PM UTC 24
Finished Sep 24 07:41:43 PM UTC 24
Peak memory 312080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201989184 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3201989184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.4211760660
Short name T66
Test name
Test status
Simulation time 2493805000 ps
CPU time 93.12 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:48:29 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421
1760660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_address.4211760660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3112501217
Short name T51
Test name
Test status
Simulation time 2546307200 ps
CPU time 96.53 seconds
Started Sep 24 05:46:53 PM UTC 24
Finished Sep 24 05:48:32 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31
12501217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se
rr_counter.3112501217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2484129477
Short name T220
Test name
Test status
Simulation time 69893100 ps
CPU time 238.33 seconds
Started Sep 24 05:46:44 PM UTC 24
Finished Sep 24 05:50:46 PM UTC 24
Peak memory 292136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484129477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2484129477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.152837606
Short name T10
Test name
Test status
Simulation time 19319900 ps
CPU time 41.77 seconds
Started Sep 24 05:46:44 PM UTC 24
Finished Sep 24 05:47:27 PM UTC 24
Peak memory 271120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152837606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.152837606
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.3760455263
Short name T627
Test name
Test status
Simulation time 3726609100 ps
CPU time 2659.24 seconds
Started Sep 24 05:47:05 PM UTC 24
Finished Sep 24 06:31:54 PM UTC 24
Peak memory 302504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760455263 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.3760455263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.286768877
Short name T4
Test name
Test status
Simulation time 45718100 ps
CPU time 31.17 seconds
Started Sep 24 05:46:45 PM UTC 24
Finished Sep 24 05:47:18 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286768877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.286768877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3405433477
Short name T143
Test name
Test status
Simulation time 10388801900 ps
CPU time 180.55 seconds
Started Sep 24 05:46:50 PM UTC 24
Finished Sep 24 05:49:53 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3405433477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.3405433477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2952283265
Short name T1
Test name
Test status
Simulation time 61928800 ps
CPU time 17.46 seconds
Started Sep 24 05:46:51 PM UTC 24
Finished Sep 24 05:47:10 PM UTC 24
Peak memory 269132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952283265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2952283265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.526616490
Short name T244
Test name
Test status
Simulation time 19625100 ps
CPU time 28.03 seconds
Started Sep 24 05:50:02 PM UTC 24
Finished Sep 24 05:50:31 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526616490 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.526616490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.961601751
Short name T24
Test name
Test status
Simulation time 23906900 ps
CPU time 23.03 seconds
Started Sep 24 05:49:48 PM UTC 24
Finished Sep 24 05:50:13 PM UTC 24
Peak memory 284812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961601751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.961601751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3060999564
Short name T150
Test name
Test status
Simulation time 804921000 ps
CPU time 234.18 seconds
Started Sep 24 05:48:23 PM UTC 24
Finished Sep 24 05:52:21 PM UTC 24
Peak memory 287924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3060999564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_derr_detect.3060999564
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3916836734
Short name T62
Test name
Test status
Simulation time 1396356400 ps
CPU time 419.29 seconds
Started Sep 24 05:47:32 PM UTC 24
Finished Sep 24 05:54:37 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916836734 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3916836734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.3536484034
Short name T275
Test name
Test status
Simulation time 16235235200 ps
CPU time 2900.1 seconds
Started Sep 24 05:47:46 PM UTC 24
Finished Sep 24 06:36:38 PM UTC 24
Peak memory 275884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536484034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.3536484034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.1061462320
Short name T110
Test name
Test status
Simulation time 2626418500 ps
CPU time 2394.14 seconds
Started Sep 24 05:47:44 PM UTC 24
Finished Sep 24 06:28:05 PM UTC 24
Peak memory 277868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10
61462320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_error_prog_type.1061462320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.3356272360
Short name T278
Test name
Test status
Simulation time 614303200 ps
CPU time 1034.38 seconds
Started Sep 24 05:47:44 PM UTC 24
Finished Sep 24 06:05:11 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356272360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3356272360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.971943863
Short name T52
Test name
Test status
Simulation time 306803400 ps
CPU time 32.46 seconds
Started Sep 24 05:47:39 PM UTC 24
Finished Sep 24 05:48:13 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97
1943863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch
_code.971943863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.4226095242
Short name T156
Test name
Test status
Simulation time 327427300 ps
CPU time 41.04 seconds
Started Sep 24 05:49:55 PM UTC 24
Finished Sep 24 05:50:37 PM UTC 24
Peak memory 275492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226095
242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f
s_sup.4226095242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.276085991
Short name T1089
Test name
Test status
Simulation time 271945620400 ps
CPU time 4494.76 seconds
Started Sep 24 05:47:41 PM UTC 24
Finished Sep 24 07:03:28 PM UTC 24
Peak memory 288196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276085991 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.276085991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1336240752
Short name T189
Test name
Test status
Simulation time 27328700 ps
CPU time 42.62 seconds
Started Sep 24 05:50:13 PM UTC 24
Finished Sep 24 05:50:57 PM UTC 24
Peak memory 285364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133624075
2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho
st_addr_infection.1336240752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4237788265
Short name T103
Test name
Test status
Simulation time 56602100 ps
CPU time 78.92 seconds
Started Sep 24 05:47:25 PM UTC 24
Finished Sep 24 05:48:46 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237788265 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4237788265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2214451208
Short name T138
Test name
Test status
Simulation time 105223770300 ps
CPU time 1999.02 seconds
Started Sep 24 05:47:33 PM UTC 24
Finished Sep 24 06:21:16 PM UTC 24
Peak memory 277768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214451208
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2214451208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2239972427
Short name T140
Test name
Test status
Simulation time 160174774700 ps
CPU time 840.13 seconds
Started Sep 24 05:47:35 PM UTC 24
Finished Sep 24 06:01:46 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239972427
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.2239972427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1067783037
Short name T119
Test name
Test status
Simulation time 3077290200 ps
CPU time 253.73 seconds
Started Sep 24 05:47:29 PM UTC 24
Finished Sep 24 05:51:47 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067783037 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.1067783037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2523773560
Short name T302
Test name
Test status
Simulation time 15348183900 ps
CPU time 665.67 seconds
Started Sep 24 05:48:30 PM UTC 24
Finished Sep 24 05:59:45 PM UTC 24
Peak memory 330748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2523773560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr
ity.2523773560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2256369728
Short name T45
Test name
Test status
Simulation time 3657603400 ps
CPU time 145.61 seconds
Started Sep 24 05:48:33 PM UTC 24
Finished Sep 24 05:51:01 PM UTC 24
Peak memory 301692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256369728 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.2256369728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.137476206
Short name T80
Test name
Test status
Simulation time 6220040600 ps
CPU time 212.17 seconds
Started Sep 24 05:48:46 PM UTC 24
Finished Sep 24 05:52:22 PM UTC 24
Peak memory 301900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=137476206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_rd_slow_flash.137476206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1355909589
Short name T41
Test name
Test status
Simulation time 1898112100 ps
CPU time 95.16 seconds
Started Sep 24 05:48:33 PM UTC 24
Finished Sep 24 05:50:10 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355909589 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.1355909589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3956827159
Short name T468
Test name
Test status
Simulation time 352753354500 ps
CPU time 829.89 seconds
Started Sep 24 05:48:52 PM UTC 24
Finished Sep 24 06:02:53 PM UTC 24
Peak memory 275324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956827159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3956827159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1009696019
Short name T30
Test name
Test status
Simulation time 15867218200 ps
CPU time 372.23 seconds
Started Sep 24 05:47:37 PM UTC 24
Finished Sep 24 05:53:55 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1009696019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_mp_regions.1009696019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1168033254
Short name T84
Test name
Test status
Simulation time 143820000 ps
CPU time 179.64 seconds
Started Sep 24 05:47:35 PM UTC 24
Finished Sep 24 05:50:38 PM UTC 24
Peak memory 271604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168033254 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1168033254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2572096834
Short name T204
Test name
Test status
Simulation time 22048259400 ps
CPU time 198.9 seconds
Started Sep 24 05:48:30 PM UTC 24
Finished Sep 24 05:51:52 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2572096834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_oversize_error.2572096834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1687897851
Short name T29
Test name
Test status
Simulation time 3632178200 ps
CPU time 288.99 seconds
Started Sep 24 05:47:28 PM UTC 24
Finished Sep 24 05:52:21 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687897851 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1687897851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.245670043
Short name T202
Test name
Test status
Simulation time 821037300 ps
CPU time 33.56 seconds
Started Sep 24 05:48:57 PM UTC 24
Finished Sep 24 05:49:32 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245670043 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.245670043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.1160644341
Short name T536
Test name
Test status
Simulation time 1767297900 ps
CPU time 1795.08 seconds
Started Sep 24 05:47:24 PM UTC 24
Finished Sep 24 06:17:39 PM UTC 24
Peak memory 300396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160644341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1160644341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.702347493
Short name T243
Test name
Test status
Simulation time 81278100 ps
CPU time 37.88 seconds
Started Sep 24 05:49:49 PM UTC 24
Finished Sep 24 05:50:29 PM UTC 24
Peak memory 285536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702347493
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.702347493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1264564267
Short name T127
Test name
Test status
Simulation time 32555100 ps
CPU time 35.21 seconds
Started Sep 24 05:48:14 PM UTC 24
Finished Sep 24 05:48:51 PM UTC 24
Peak memory 275316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1264564267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_read_word_sweep_derr.1264564267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3547253859
Short name T200
Test name
Test status
Simulation time 56408700 ps
CPU time 47.53 seconds
Started Sep 24 05:48:10 PM UTC 24
Finished Sep 24 05:48:59 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547253859 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.3547253859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.695363120
Short name T102
Test name
Test status
Simulation time 108381270300 ps
CPU time 1184.65 seconds
Started Sep 24 05:50:04 PM UTC 24
Finished Sep 24 06:10:04 PM UTC 24
Peak memory 272980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=695363120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.f
lash_ctrl_rma_err.695363120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2380982131
Short name T197
Test name
Test status
Simulation time 2380434300 ps
CPU time 118.52 seconds
Started Sep 24 05:47:59 PM UTC 24
Finished Sep 24 05:50:00 PM UTC 24
Peak memory 301960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2380982131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.2380982131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3027683799
Short name T199
Test name
Test status
Simulation time 567587000 ps
CPU time 146.91 seconds
Started Sep 24 05:48:17 PM UTC 24
Finished Sep 24 05:50:46 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027683799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3027683799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.28056066
Short name T117
Test name
Test status
Simulation time 2153944800 ps
CPU time 136.78 seconds
Started Sep 24 05:48:12 PM UTC 24
Finished Sep 24 05:50:31 PM UTC 24
Peak memory 306172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=28056066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_ro_serr.28056066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.3164607452
Short name T305
Test name
Test status
Simulation time 20689552200 ps
CPU time 521.03 seconds
Started Sep 24 05:48:07 PM UTC 24
Finished Sep 24 05:56:55 PM UTC 24
Peak memory 324596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164607452 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.3164607452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1359890877
Short name T203
Test name
Test status
Simulation time 3041964600 ps
CPU time 206.26 seconds
Started Sep 24 05:48:17 PM UTC 24
Finished Sep 24 05:51:46 PM UTC 24
Peak memory 297988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1359890877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rw_derr.1359890877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.3627922648
Short name T39
Test name
Test status
Simulation time 34500100 ps
CPU time 33.18 seconds
Started Sep 24 05:49:00 PM UTC 24
Finished Sep 24 05:49:35 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627922648 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.3627922648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1774721464
Short name T212
Test name
Test status
Simulation time 19767257900 ps
CPU time 200.83 seconds
Started Sep 24 05:48:12 PM UTC 24
Finished Sep 24 05:51:36 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1774721464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.1774721464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.31578190
Short name T46
Test name
Test status
Simulation time 5733453500 ps
CPU time 85.67 seconds
Started Sep 24 05:49:36 PM UTC 24
Finished Sep 24 05:51:04 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31578190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.31578190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3617589372
Short name T154
Test name
Test status
Simulation time 3325390200 ps
CPU time 103.82 seconds
Started Sep 24 05:48:12 PM UTC 24
Finished Sep 24 05:49:58 PM UTC 24
Peak memory 285836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361
7589372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_address.3617589372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1965633313
Short name T260
Test name
Test status
Simulation time 3231574300 ps
CPU time 108.06 seconds
Started Sep 24 05:48:12 PM UTC 24
Finished Sep 24 05:50:03 PM UTC 24
Peak memory 275640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19
65633313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se
rr_counter.1965633313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3591817206
Short name T219
Test name
Test status
Simulation time 35306000 ps
CPU time 198.91 seconds
Started Sep 24 05:47:24 PM UTC 24
Finished Sep 24 05:50:46 PM UTC 24
Peak memory 287372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591817206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3591817206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.46838627
Short name T68
Test name
Test status
Simulation time 19601100 ps
CPU time 49.6 seconds
Started Sep 24 05:47:24 PM UTC 24
Finished Sep 24 05:48:15 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46838627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.46838627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2426855917
Short name T301
Test name
Test status
Simulation time 383968400 ps
CPU time 1217.57 seconds
Started Sep 24 05:49:41 PM UTC 24
Finished Sep 24 06:10:13 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426855917 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.2426855917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1276676682
Short name T53
Test name
Test status
Simulation time 86940800 ps
CPU time 39.46 seconds
Started Sep 24 05:47:25 PM UTC 24
Finished Sep 24 05:48:06 PM UTC 24
Peak memory 272912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276676682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1276676682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.956506387
Short name T191
Test name
Test status
Simulation time 2182215900 ps
CPU time 201.4 seconds
Started Sep 24 05:47:52 PM UTC 24
Finished Sep 24 05:51:18 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=956506387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.956506387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2805169688
Short name T20
Test name
Test status
Simulation time 111858100 ps
CPU time 30.14 seconds
Started Sep 24 05:49:49 PM UTC 24
Finished Sep 24 05:50:21 PM UTC 24
Peak memory 271248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2805169688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_wr_intg.2805169688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2473673710
Short name T602
Test name
Test status
Simulation time 121657800 ps
CPU time 17.46 seconds
Started Sep 24 06:29:06 PM UTC 24
Finished Sep 24 06:29:25 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473673710 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.2473673710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2874282352
Short name T600
Test name
Test status
Simulation time 45143700 ps
CPU time 18.41 seconds
Started Sep 24 06:28:51 PM UTC 24
Finished Sep 24 06:29:11 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874282352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2874282352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1469857303
Short name T611
Test name
Test status
Simulation time 10034176600 ps
CPU time 105.47 seconds
Started Sep 24 06:29:02 PM UTC 24
Finished Sep 24 06:30:50 PM UTC 24
Peak memory 299868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1469857303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1469857303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2411502632
Short name T603
Test name
Test status
Simulation time 34669700 ps
CPU time 24.17 seconds
Started Sep 24 06:29:00 PM UTC 24
Finished Sep 24 06:29:26 PM UTC 24
Peak memory 271520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2411502632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_hw_read_seed_err.2411502632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.3935058719
Short name T431
Test name
Test status
Simulation time 80154955200 ps
CPU time 972.52 seconds
Started Sep 24 06:27:08 PM UTC 24
Finished Sep 24 06:43:32 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935058719
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res
et.3935058719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3779414695
Short name T593
Test name
Test status
Simulation time 1159708400 ps
CPU time 67.53 seconds
Started Sep 24 06:27:06 PM UTC 24
Finished Sep 24 06:28:16 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779414695 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.3779414695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3961295912
Short name T608
Test name
Test status
Simulation time 945678400 ps
CPU time 144.28 seconds
Started Sep 24 06:27:37 PM UTC 24
Finished Sep 24 06:30:04 PM UTC 24
Peak memory 302192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961295912 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.3961295912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3662542621
Short name T616
Test name
Test status
Simulation time 38522169100 ps
CPU time 199.45 seconds
Started Sep 24 06:27:55 PM UTC 24
Finished Sep 24 06:31:18 PM UTC 24
Peak memory 303852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3662542621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_intr_rd_slow_flash.3662542621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.2225376666
Short name T596
Test name
Test status
Simulation time 7629757100 ps
CPU time 91.68 seconds
Started Sep 24 06:27:16 PM UTC 24
Finished Sep 24 06:28:49 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225376666 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2225376666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.4140993926
Short name T601
Test name
Test status
Simulation time 16596500 ps
CPU time 17.24 seconds
Started Sep 24 06:28:59 PM UTC 24
Finished Sep 24 06:29:17 PM UTC 24
Peak memory 275532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4140993926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_lcmgr_intg.4140993926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.629676688
Short name T160
Test name
Test status
Simulation time 17702737800 ps
CPU time 261.7 seconds
Started Sep 24 06:27:15 PM UTC 24
Finished Sep 24 06:31:41 PM UTC 24
Peak memory 283604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=629676688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_mp_regions.629676688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.57883180
Short name T607
Test name
Test status
Simulation time 48217700 ps
CPU time 135.85 seconds
Started Sep 24 06:27:13 PM UTC 24
Finished Sep 24 06:29:31 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57883180 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.57883180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3714796597
Short name T622
Test name
Test status
Simulation time 156252900 ps
CPU time 280.19 seconds
Started Sep 24 06:27:02 PM UTC 24
Finished Sep 24 06:31:47 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714796597 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3714796597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.885867066
Short name T594
Test name
Test status
Simulation time 129697600 ps
CPU time 24.81 seconds
Started Sep 24 06:27:56 PM UTC 24
Finished Sep 24 06:28:22 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885867066 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.885867066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.1294930055
Short name T869
Test name
Test status
Simulation time 486758700 ps
CPU time 1644.33 seconds
Started Sep 24 06:27:00 PM UTC 24
Finished Sep 24 06:54:44 PM UTC 24
Peak memory 297612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294930055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1294930055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3796272097
Short name T355
Test name
Test status
Simulation time 293411600 ps
CPU time 59.93 seconds
Started Sep 24 06:28:24 PM UTC 24
Finished Sep 24 06:29:25 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796272097 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.3796272097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2992879452
Short name T606
Test name
Test status
Simulation time 2280761000 ps
CPU time 124.94 seconds
Started Sep 24 06:27:22 PM UTC 24
Finished Sep 24 06:29:29 PM UTC 24
Peak memory 291984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2992879452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.2992879452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1964812898
Short name T654
Test name
Test status
Simulation time 6239182000 ps
CPU time 498.74 seconds
Started Sep 24 06:27:28 PM UTC 24
Finished Sep 24 06:35:54 PM UTC 24
Peak memory 320504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964812898 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.1964812898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2853032437
Short name T597
Test name
Test status
Simulation time 39412100 ps
CPU time 50.97 seconds
Started Sep 24 06:28:06 PM UTC 24
Finished Sep 24 06:28:58 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853032437 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.2853032437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.816612386
Short name T598
Test name
Test status
Simulation time 44342900 ps
CPU time 40.66 seconds
Started Sep 24 06:28:17 PM UTC 24
Finished Sep 24 06:28:59 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=816612386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ct
rl_rw_evict_all_en.816612386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2259326350
Short name T621
Test name
Test status
Simulation time 1401632800 ps
CPU time 284.43 seconds
Started Sep 24 06:26:55 PM UTC 24
Finished Sep 24 06:31:44 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259326350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2259326350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2656136437
Short name T612
Test name
Test status
Simulation time 9155359200 ps
CPU time 222.88 seconds
Started Sep 24 06:27:18 PM UTC 24
Finished Sep 24 06:31:05 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2656136437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.2656136437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1232884356
Short name T629
Test name
Test status
Simulation time 40284900 ps
CPU time 18.09 seconds
Started Sep 24 06:31:42 PM UTC 24
Finished Sep 24 06:32:01 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232884356 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1232884356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1840018835
Short name T623
Test name
Test status
Simulation time 48843900 ps
CPU time 28.13 seconds
Started Sep 24 06:31:19 PM UTC 24
Finished Sep 24 06:31:48 PM UTC 24
Peak memory 294928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840018835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1840018835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3992303099
Short name T272
Test name
Test status
Simulation time 10019864500 ps
CPU time 243.52 seconds
Started Sep 24 06:31:33 PM UTC 24
Finished Sep 24 06:35:41 PM UTC 24
Peak memory 303908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3992303099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3992303099
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.370003861
Short name T626
Test name
Test status
Simulation time 44846100 ps
CPU time 25.28 seconds
Started Sep 24 06:31:26 PM UTC 24
Finished Sep 24 06:31:53 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=370003861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.flash_ctrl_hw_read_seed_err.370003861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.2438425967
Short name T737
Test name
Test status
Simulation time 160172020200 ps
CPU time 968.68 seconds
Started Sep 24 06:29:27 PM UTC 24
Finished Sep 24 06:45:47 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438425967
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res
et.2438425967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.593602382
Short name T631
Test name
Test status
Simulation time 10247466800 ps
CPU time 177.23 seconds
Started Sep 24 06:29:27 PM UTC 24
Finished Sep 24 06:32:27 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593602382 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.593602382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.873740036
Short name T634
Test name
Test status
Simulation time 757982600 ps
CPU time 139.39 seconds
Started Sep 24 06:30:35 PM UTC 24
Finished Sep 24 06:32:57 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873740036 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.873740036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3815579422
Short name T641
Test name
Test status
Simulation time 9151057000 ps
CPU time 174.56 seconds
Started Sep 24 06:30:37 PM UTC 24
Finished Sep 24 06:33:35 PM UTC 24
Peak memory 303844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3815579422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_intr_rd_slow_flash.3815579422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2206985439
Short name T617
Test name
Test status
Simulation time 3498962600 ps
CPU time 112.58 seconds
Started Sep 24 06:29:30 PM UTC 24
Finished Sep 24 06:31:25 PM UTC 24
Peak memory 275012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206985439 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2206985439
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1753357169
Short name T624
Test name
Test status
Simulation time 47840300 ps
CPU time 28.96 seconds
Started Sep 24 06:31:19 PM UTC 24
Finished Sep 24 06:31:49 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1753357169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_lcmgr_intg.1753357169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3966460129
Short name T161
Test name
Test status
Simulation time 34720696200 ps
CPU time 436.64 seconds
Started Sep 24 06:29:29 PM UTC 24
Finished Sep 24 06:36:51 PM UTC 24
Peak memory 283520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3966460129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_mp_regions.3966460129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.117750728
Short name T333
Test name
Test status
Simulation time 466457300 ps
CPU time 221.15 seconds
Started Sep 24 06:29:28 PM UTC 24
Finished Sep 24 06:33:13 PM UTC 24
Peak memory 271200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117750728 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.117750728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.935321409
Short name T610
Test name
Test status
Simulation time 88866400 ps
CPU time 81.13 seconds
Started Sep 24 06:29:26 PM UTC 24
Finished Sep 24 06:30:48 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935321409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.935321409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.798942597
Short name T614
Test name
Test status
Simulation time 61158200 ps
CPU time 25.49 seconds
Started Sep 24 06:30:49 PM UTC 24
Finished Sep 24 06:31:16 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798942597 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.798942597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.482296658
Short name T684
Test name
Test status
Simulation time 70882800 ps
CPU time 592.42 seconds
Started Sep 24 06:29:18 PM UTC 24
Finished Sep 24 06:39:19 PM UTC 24
Peak memory 291472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482296658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.482296658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1185190813
Short name T625
Test name
Test status
Simulation time 555712300 ps
CPU time 42.37 seconds
Started Sep 24 06:31:05 PM UTC 24
Finished Sep 24 06:31:49 PM UTC 24
Peak memory 283776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185190813 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.1185190813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.1080856318
Short name T630
Test name
Test status
Simulation time 543996700 ps
CPU time 128.63 seconds
Started Sep 24 06:30:06 PM UTC 24
Finished Sep 24 06:32:17 PM UTC 24
Peak memory 304368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1080856318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.1080856318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.221584678
Short name T678
Test name
Test status
Simulation time 6798579600 ps
CPU time 494.34 seconds
Started Sep 24 06:30:19 PM UTC 24
Finished Sep 24 06:38:39 PM UTC 24
Peak memory 324644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221584678 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.221584678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3493772559
Short name T620
Test name
Test status
Simulation time 126387600 ps
CPU time 49.9 seconds
Started Sep 24 06:30:51 PM UTC 24
Finished Sep 24 06:31:43 PM UTC 24
Peak memory 281728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493772559 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.3493772559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.229074880
Short name T619
Test name
Test status
Simulation time 47849200 ps
CPU time 46.49 seconds
Started Sep 24 06:30:52 PM UTC 24
Finished Sep 24 06:31:41 PM UTC 24
Peak memory 287740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=229074880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ct
rl_rw_evict_all_en.229074880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2676204365
Short name T640
Test name
Test status
Simulation time 9682776300 ps
CPU time 133.7 seconds
Started Sep 24 06:31:18 PM UTC 24
Finished Sep 24 06:33:34 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676204365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2676204365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4153652137
Short name T628
Test name
Test status
Simulation time 60146600 ps
CPU time 160.76 seconds
Started Sep 24 06:29:11 PM UTC 24
Finished Sep 24 06:31:55 PM UTC 24
Peak memory 289420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153652137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4153652137
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2379053725
Short name T618
Test name
Test status
Simulation time 3255391900 ps
CPU time 117.93 seconds
Started Sep 24 06:29:32 PM UTC 24
Finished Sep 24 06:31:32 PM UTC 24
Peak memory 271420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2379053725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.2379053725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1981841212
Short name T644
Test name
Test status
Simulation time 78786600 ps
CPU time 20.18 seconds
Started Sep 24 06:33:29 PM UTC 24
Finished Sep 24 06:33:50 PM UTC 24
Peak memory 269320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981841212 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.1981841212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.563623088
Short name T639
Test name
Test status
Simulation time 23723100 ps
CPU time 18.84 seconds
Started Sep 24 06:33:13 PM UTC 24
Finished Sep 24 06:33:33 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563623088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.563623088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3540014008
Short name T405
Test name
Test status
Simulation time 10662300 ps
CPU time 44.56 seconds
Started Sep 24 06:32:58 PM UTC 24
Finished Sep 24 06:33:44 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3540014008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_
ctrl_disable.3540014008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1358543743
Short name T653
Test name
Test status
Simulation time 10032269900 ps
CPU time 144.64 seconds
Started Sep 24 06:33:20 PM UTC 24
Finished Sep 24 06:35:47 PM UTC 24
Peak memory 283404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1358543743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1358543743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.915849493
Short name T642
Test name
Test status
Simulation time 27205200 ps
CPU time 20.26 seconds
Started Sep 24 06:33:16 PM UTC 24
Finished Sep 24 06:33:38 PM UTC 24
Peak memory 275424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=915849493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.flash_ctrl_hw_read_seed_err.915849493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.1641005598
Short name T750
Test name
Test status
Simulation time 40120394300 ps
CPU time 923.42 seconds
Started Sep 24 06:31:49 PM UTC 24
Finished Sep 24 06:47:25 PM UTC 24
Peak memory 274968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641005598
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res
et.1641005598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2611366752
Short name T317
Test name
Test status
Simulation time 3529168200 ps
CPU time 129.13 seconds
Started Sep 24 06:31:48 PM UTC 24
Finished Sep 24 06:34:00 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611366752 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.2611366752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.162617518
Short name T655
Test name
Test status
Simulation time 7833179200 ps
CPU time 235.32 seconds
Started Sep 24 06:32:02 PM UTC 24
Finished Sep 24 06:36:01 PM UTC 24
Peak memory 301932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162617518 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.162617518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2500631333
Short name T646
Test name
Test status
Simulation time 23890288700 ps
CPU time 147.36 seconds
Started Sep 24 06:32:09 PM UTC 24
Finished Sep 24 06:34:39 PM UTC 24
Peak memory 304108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2500631333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_intr_rd_slow_flash.2500631333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2745492107
Short name T637
Test name
Test status
Simulation time 1932145900 ps
CPU time 82.59 seconds
Started Sep 24 06:31:54 PM UTC 24
Finished Sep 24 06:33:18 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745492107 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2745492107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.926726119
Short name T638
Test name
Test status
Simulation time 47543100 ps
CPU time 16.1 seconds
Started Sep 24 06:33:13 PM UTC 24
Finished Sep 24 06:33:31 PM UTC 24
Peak memory 275268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=926726119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_lcmgr_intg.926726119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2823511955
Short name T162
Test name
Test status
Simulation time 191831616800 ps
CPU time 499.23 seconds
Started Sep 24 06:31:50 PM UTC 24
Finished Sep 24 06:40:16 PM UTC 24
Peak memory 285376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2823511955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_mp_regions.2823511955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1030816167
Short name T697
Test name
Test status
Simulation time 294601400 ps
CPU time 537.4 seconds
Started Sep 24 06:31:44 PM UTC 24
Finished Sep 24 06:40:48 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030816167 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1030816167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.4106370644
Short name T633
Test name
Test status
Simulation time 19750900 ps
CPU time 18.78 seconds
Started Sep 24 06:32:17 PM UTC 24
Finished Sep 24 06:32:38 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106370644 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.4106370644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.54946753
Short name T665
Test name
Test status
Simulation time 192752000 ps
CPU time 336.74 seconds
Started Sep 24 06:31:44 PM UTC 24
Finished Sep 24 06:37:25 PM UTC 24
Peak memory 291664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54946753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.54946753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2151203246
Short name T643
Test name
Test status
Simulation time 105919300 ps
CPU time 65.91 seconds
Started Sep 24 06:32:39 PM UTC 24
Finished Sep 24 06:33:47 PM UTC 24
Peak memory 285856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151203246 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2151203246
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.1260690206
Short name T645
Test name
Test status
Simulation time 691244700 ps
CPU time 115.55 seconds
Started Sep 24 06:31:55 PM UTC 24
Finished Sep 24 06:33:53 PM UTC 24
Peak memory 304012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1260690206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.1260690206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.2525846262
Short name T363
Test name
Test status
Simulation time 3551891700 ps
CPU time 547.89 seconds
Started Sep 24 06:31:56 PM UTC 24
Finished Sep 24 06:41:11 PM UTC 24
Peak memory 324820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525846262 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.2525846262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.3986744635
Short name T372
Test name
Test status
Simulation time 102780500 ps
CPU time 36.29 seconds
Started Sep 24 06:32:27 PM UTC 24
Finished Sep 24 06:33:05 PM UTC 24
Peak memory 281464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986744635 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.3986744635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2127931738
Short name T359
Test name
Test status
Simulation time 29349400 ps
CPU time 48.68 seconds
Started Sep 24 06:32:38 PM UTC 24
Finished Sep 24 06:33:28 PM UTC 24
Peak memory 287932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2127931738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw_evict_all_en.2127931738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.604411836
Short name T636
Test name
Test status
Simulation time 38171000 ps
CPU time 91.3 seconds
Started Sep 24 06:31:42 PM UTC 24
Finished Sep 24 06:33:15 PM UTC 24
Peak memory 285456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604411836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.604411836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.4249531882
Short name T647
Test name
Test status
Simulation time 18901489300 ps
CPU time 167.72 seconds
Started Sep 24 06:31:55 PM UTC 24
Finished Sep 24 06:34:45 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4249531882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.4249531882
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.3596909104
Short name T662
Test name
Test status
Simulation time 42875900 ps
CPU time 18.25 seconds
Started Sep 24 06:36:02 PM UTC 24
Finished Sep 24 06:36:21 PM UTC 24
Peak memory 269240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596909104 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.3596909104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.2437906356
Short name T659
Test name
Test status
Simulation time 24456700 ps
CPU time 23.93 seconds
Started Sep 24 06:35:42 PM UTC 24
Finished Sep 24 06:36:08 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437906356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2437906356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.259030438
Short name T671
Test name
Test status
Simulation time 10013330200 ps
CPU time 133.3 seconds
Started Sep 24 06:35:55 PM UTC 24
Finished Sep 24 06:38:11 PM UTC 24
Peak memory 371548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=259030438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.259030438
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.1548259872
Short name T658
Test name
Test status
Simulation time 26433300 ps
CPU time 18.52 seconds
Started Sep 24 06:35:48 PM UTC 24
Finished Sep 24 06:36:07 PM UTC 24
Peak memory 269280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1548259872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_hw_read_seed_err.1548259872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.3220157200
Short name T803
Test name
Test status
Simulation time 40126210000 ps
CPU time 1041.04 seconds
Started Sep 24 06:33:38 PM UTC 24
Finished Sep 24 06:51:12 PM UTC 24
Peak memory 274968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220157200
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res
et.3220157200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2050571879
Short name T325
Test name
Test status
Simulation time 1936031800 ps
CPU time 46.08 seconds
Started Sep 24 06:33:36 PM UTC 24
Finished Sep 24 06:34:24 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050571879 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.2050571879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.589313749
Short name T345
Test name
Test status
Simulation time 2551070900 ps
CPU time 169.42 seconds
Started Sep 24 06:34:31 PM UTC 24
Finished Sep 24 06:37:24 PM UTC 24
Peak memory 306348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589313749 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.589313749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1389716839
Short name T680
Test name
Test status
Simulation time 29924962300 ps
CPU time 254.33 seconds
Started Sep 24 06:34:40 PM UTC 24
Finished Sep 24 06:38:59 PM UTC 24
Peak memory 303880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1389716839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_intr_rd_slow_flash.1389716839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.165784166
Short name T650
Test name
Test status
Simulation time 12344820200 ps
CPU time 86.36 seconds
Started Sep 24 06:33:51 PM UTC 24
Finished Sep 24 06:35:20 PM UTC 24
Peak memory 275012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165784166 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.165784166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1278591083
Short name T660
Test name
Test status
Simulation time 64789700 ps
CPU time 23.3 seconds
Started Sep 24 06:35:43 PM UTC 24
Finished Sep 24 06:36:08 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1278591083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_lcmgr_intg.1278591083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3609267405
Short name T666
Test name
Test status
Simulation time 2793756500 ps
CPU time 221.4 seconds
Started Sep 24 06:33:47 PM UTC 24
Finished Sep 24 06:37:32 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3609267405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_mp_regions.3609267405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.828672708
Short name T172
Test name
Test status
Simulation time 76637400 ps
CPU time 221.31 seconds
Started Sep 24 06:33:45 PM UTC 24
Finished Sep 24 06:37:30 PM UTC 24
Peak memory 271140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828672708 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.828672708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3752802262
Short name T738
Test name
Test status
Simulation time 2967146500 ps
CPU time 724.45 seconds
Started Sep 24 06:33:35 PM UTC 24
Finished Sep 24 06:45:48 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752802262 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3752802262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2375374744
Short name T651
Test name
Test status
Simulation time 341579800 ps
CPU time 32.5 seconds
Started Sep 24 06:34:46 PM UTC 24
Finished Sep 24 06:35:20 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375374744 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.2375374744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3099637653
Short name T818
Test name
Test status
Simulation time 230118300 ps
CPU time 1103.06 seconds
Started Sep 24 06:33:34 PM UTC 24
Finished Sep 24 06:52:10 PM UTC 24
Peak memory 293516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099637653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3099637653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3446276409
Short name T368
Test name
Test status
Simulation time 113887500 ps
CPU time 56.31 seconds
Started Sep 24 06:35:14 PM UTC 24
Finished Sep 24 06:36:12 PM UTC 24
Peak memory 287776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446276409 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.3446276409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1774329489
Short name T657
Test name
Test status
Simulation time 1050381100 ps
CPU time 120.49 seconds
Started Sep 24 06:34:01 PM UTC 24
Finished Sep 24 06:36:04 PM UTC 24
Peak memory 302088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1774329489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1774329489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2133543654
Short name T703
Test name
Test status
Simulation time 3331264300 ps
CPU time 447.77 seconds
Started Sep 24 06:34:25 PM UTC 24
Finished Sep 24 06:41:59 PM UTC 24
Peak memory 320552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133543654 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.2133543654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2685349651
Short name T652
Test name
Test status
Simulation time 110147900 ps
CPU time 34.69 seconds
Started Sep 24 06:35:06 PM UTC 24
Finished Sep 24 06:35:43 PM UTC 24
Peak memory 285856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685349651 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.2685349651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3607132920
Short name T656
Test name
Test status
Simulation time 40621200 ps
CPU time 54 seconds
Started Sep 24 06:35:07 PM UTC 24
Finished Sep 24 06:36:02 PM UTC 24
Peak memory 285592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3607132920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw_evict_all_en.3607132920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1876935120
Short name T648
Test name
Test status
Simulation time 67837900 ps
CPU time 91.38 seconds
Started Sep 24 06:33:32 PM UTC 24
Finished Sep 24 06:35:05 PM UTC 24
Peak memory 285328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876935120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1876935120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.3045840620
Short name T661
Test name
Test status
Simulation time 1882458800 ps
CPU time 144.44 seconds
Started Sep 24 06:33:54 PM UTC 24
Finished Sep 24 06:36:21 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3045840620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.3045840620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.1890826049
Short name T675
Test name
Test status
Simulation time 224639900 ps
CPU time 26.21 seconds
Started Sep 24 06:38:03 PM UTC 24
Finished Sep 24 06:38:31 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890826049 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.1890826049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.1171142754
Short name T669
Test name
Test status
Simulation time 28959700 ps
CPU time 26.2 seconds
Started Sep 24 06:37:34 PM UTC 24
Finished Sep 24 06:38:02 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171142754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1171142754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1765726887
Short name T123
Test name
Test status
Simulation time 11597600 ps
CPU time 40.31 seconds
Started Sep 24 06:37:26 PM UTC 24
Finished Sep 24 06:38:08 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1765726887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_
ctrl_disable.1765726887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3747823508
Short name T683
Test name
Test status
Simulation time 10057602200 ps
CPU time 72.03 seconds
Started Sep 24 06:38:02 PM UTC 24
Finished Sep 24 06:39:16 PM UTC 24
Peak memory 285724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3747823508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3747823508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.1863095953
Short name T672
Test name
Test status
Simulation time 60880900 ps
CPU time 17.82 seconds
Started Sep 24 06:37:56 PM UTC 24
Finished Sep 24 06:38:15 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1863095953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
14.flash_ctrl_hw_read_seed_err.1863095953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.994897625
Short name T814
Test name
Test status
Simulation time 80135121500 ps
CPU time 932.12 seconds
Started Sep 24 06:36:08 PM UTC 24
Finished Sep 24 06:51:52 PM UTC 24
Peak memory 273128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994897625 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_reset.994897625
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.167435292
Short name T677
Test name
Test status
Simulation time 6889803600 ps
CPU time 147.95 seconds
Started Sep 24 06:36:08 PM UTC 24
Finished Sep 24 06:38:39 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167435292 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.167435292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1514027984
Short name T346
Test name
Test status
Simulation time 954579200 ps
CPU time 197.34 seconds
Started Sep 24 06:36:50 PM UTC 24
Finished Sep 24 06:40:11 PM UTC 24
Peak memory 306288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514027984 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.1514027984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3821006523
Short name T699
Test name
Test status
Simulation time 32598317100 ps
CPU time 252.3 seconds
Started Sep 24 06:36:53 PM UTC 24
Finished Sep 24 06:41:09 PM UTC 24
Peak memory 303844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3821006523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_intr_rd_slow_flash.3821006523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.746323817
Short name T667
Test name
Test status
Simulation time 4037466900 ps
CPU time 76.75 seconds
Started Sep 24 06:36:22 PM UTC 24
Finished Sep 24 06:37:40 PM UTC 24
Peak memory 270924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746323817 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.746323817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.3560194009
Short name T163
Test name
Test status
Simulation time 25641782500 ps
CPU time 359.54 seconds
Started Sep 24 06:36:12 PM UTC 24
Finished Sep 24 06:42:17 PM UTC 24
Peak memory 283428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3560194009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_mp_regions.3560194009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.3553394840
Short name T679
Test name
Test status
Simulation time 1379222700 ps
CPU time 162.66 seconds
Started Sep 24 06:36:07 PM UTC 24
Finished Sep 24 06:38:53 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553394840 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3553394840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2563305571
Short name T664
Test name
Test status
Simulation time 23931900 ps
CPU time 28.79 seconds
Started Sep 24 06:36:53 PM UTC 24
Finished Sep 24 06:37:23 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563305571 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.2563305571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.4105405464
Short name T685
Test name
Test status
Simulation time 173090800 ps
CPU time 204.65 seconds
Started Sep 24 06:36:05 PM UTC 24
Finished Sep 24 06:39:33 PM UTC 24
Peak memory 281224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105405464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.4105405464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.2068538782
Short name T674
Test name
Test status
Simulation time 84556200 ps
CPU time 62.49 seconds
Started Sep 24 06:37:25 PM UTC 24
Finished Sep 24 06:38:30 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068538782 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.2068538782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.4082979666
Short name T681
Test name
Test status
Simulation time 2141848100 ps
CPU time 138.21 seconds
Started Sep 24 06:36:39 PM UTC 24
Finished Sep 24 06:39:00 PM UTC 24
Peak memory 291868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4082979666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.4082979666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.1440067127
Short name T364
Test name
Test status
Simulation time 60845755300 ps
CPU time 477.83 seconds
Started Sep 24 06:36:50 PM UTC 24
Finished Sep 24 06:44:54 PM UTC 24
Peak memory 330784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440067127 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.1440067127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.2551815769
Short name T360
Test name
Test status
Simulation time 28080500 ps
CPU time 42.03 seconds
Started Sep 24 06:37:11 PM UTC 24
Finished Sep 24 06:37:55 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551815769 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.2551815769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1461578490
Short name T668
Test name
Test status
Simulation time 185108700 ps
CPU time 35.65 seconds
Started Sep 24 06:37:24 PM UTC 24
Finished Sep 24 06:38:01 PM UTC 24
Peak memory 287740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1461578490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw_evict_all_en.1461578490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.1913168935
Short name T682
Test name
Test status
Simulation time 6139213800 ps
CPU time 95.49 seconds
Started Sep 24 06:37:31 PM UTC 24
Finished Sep 24 06:39:08 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913168935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1913168935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3227167487
Short name T673
Test name
Test status
Simulation time 47694700 ps
CPU time 130.31 seconds
Started Sep 24 06:36:03 PM UTC 24
Finished Sep 24 06:38:16 PM UTC 24
Peak memory 287368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227167487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3227167487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3205420806
Short name T687
Test name
Test status
Simulation time 5388891600 ps
CPU time 213.86 seconds
Started Sep 24 06:36:23 PM UTC 24
Finished Sep 24 06:40:00 PM UTC 24
Peak memory 271436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3205420806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.3205420806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3699454743
Short name T694
Test name
Test status
Simulation time 62596900 ps
CPU time 27.75 seconds
Started Sep 24 06:40:04 PM UTC 24
Finished Sep 24 06:40:33 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699454743 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.3699454743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.2227980590
Short name T107
Test name
Test status
Simulation time 54443900 ps
CPU time 28.49 seconds
Started Sep 24 06:39:33 PM UTC 24
Finished Sep 24 06:40:03 PM UTC 24
Peak memory 284880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227980590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2227980590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2974675941
Short name T430
Test name
Test status
Simulation time 16443200 ps
CPU time 43.15 seconds
Started Sep 24 06:39:17 PM UTC 24
Finished Sep 24 06:40:02 PM UTC 24
Peak memory 285368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2974675941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_
ctrl_disable.2974675941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1821053101
Short name T700
Test name
Test status
Simulation time 10120807000 ps
CPU time 69.37 seconds
Started Sep 24 06:40:03 PM UTC 24
Finished Sep 24 06:41:14 PM UTC 24
Peak memory 275320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1821053101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1821053101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.325336984
Short name T692
Test name
Test status
Simulation time 15592300 ps
CPU time 23.69 seconds
Started Sep 24 06:40:01 PM UTC 24
Finished Sep 24 06:40:26 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=325336984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.flash_ctrl_hw_read_seed_err.325336984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1394083666
Short name T810
Test name
Test status
Simulation time 90142717300 ps
CPU time 792.68 seconds
Started Sep 24 06:38:17 PM UTC 24
Finished Sep 24 06:51:39 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394083666
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res
et.1394083666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.614320752
Short name T696
Test name
Test status
Simulation time 3087086600 ps
CPU time 149.01 seconds
Started Sep 24 06:38:15 PM UTC 24
Finished Sep 24 06:40:47 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614320752 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.614320752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.4077826211
Short name T713
Test name
Test status
Simulation time 5768041000 ps
CPU time 235.33 seconds
Started Sep 24 06:38:59 PM UTC 24
Finished Sep 24 06:42:58 PM UTC 24
Peak memory 293772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077826211 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.4077826211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.842501836
Short name T715
Test name
Test status
Simulation time 11436592400 ps
CPU time 276.88 seconds
Started Sep 24 06:39:01 PM UTC 24
Finished Sep 24 06:43:41 PM UTC 24
Peak memory 301800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=842501836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_intr_rd_slow_flash.842501836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1620183601
Short name T693
Test name
Test status
Simulation time 891044500 ps
CPU time 107.16 seconds
Started Sep 24 06:38:40 PM UTC 24
Finished Sep 24 06:40:29 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620183601 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1620183601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2484819012
Short name T690
Test name
Test status
Simulation time 15183000 ps
CPU time 30.33 seconds
Started Sep 24 06:39:42 PM UTC 24
Finished Sep 24 06:40:14 PM UTC 24
Peak memory 271460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2484819012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_lcmgr_intg.2484819012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.2233278167
Short name T164
Test name
Test status
Simulation time 21574280700 ps
CPU time 513.15 seconds
Started Sep 24 06:38:32 PM UTC 24
Finished Sep 24 06:47:12 PM UTC 24
Peak memory 283524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2233278167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_mp_regions.2233278167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.2823184923
Short name T181
Test name
Test status
Simulation time 37048400 ps
CPU time 177.1 seconds
Started Sep 24 06:38:31 PM UTC 24
Finished Sep 24 06:41:31 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823184923 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.2823184923
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2916364178
Short name T708
Test name
Test status
Simulation time 186398100 ps
CPU time 255.33 seconds
Started Sep 24 06:38:11 PM UTC 24
Finished Sep 24 06:42:30 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916364178 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2916364178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1669771569
Short name T686
Test name
Test status
Simulation time 30274800 ps
CPU time 30.3 seconds
Started Sep 24 06:39:10 PM UTC 24
Finished Sep 24 06:39:42 PM UTC 24
Peak memory 271372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669771569 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.1669771569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.3827847602
Short name T993
Test name
Test status
Simulation time 8615493000 ps
CPU time 1299.03 seconds
Started Sep 24 06:38:09 PM UTC 24
Finished Sep 24 07:00:04 PM UTC 24
Peak memory 295564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827847602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3827847602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1805367950
Short name T691
Test name
Test status
Simulation time 250970000 ps
CPU time 59.2 seconds
Started Sep 24 06:39:15 PM UTC 24
Finished Sep 24 06:40:16 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805367950 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.1805367950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1270013963
Short name T781
Test name
Test status
Simulation time 50080362500 ps
CPU time 665.44 seconds
Started Sep 24 06:38:53 PM UTC 24
Finished Sep 24 06:50:08 PM UTC 24
Peak memory 320712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270013963 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.1270013963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.4213372020
Short name T688
Test name
Test status
Simulation time 42277800 ps
CPU time 56.36 seconds
Started Sep 24 06:39:10 PM UTC 24
Finished Sep 24 06:40:08 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213372020 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.4213372020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1289344123
Short name T689
Test name
Test status
Simulation time 72968400 ps
CPU time 52.94 seconds
Started Sep 24 06:39:15 PM UTC 24
Finished Sep 24 06:40:10 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1289344123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw_evict_all_en.1289344123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.1456174864
Short name T695
Test name
Test status
Simulation time 3230212600 ps
CPU time 74.75 seconds
Started Sep 24 06:39:19 PM UTC 24
Finished Sep 24 06:40:36 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456174864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1456174864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.3415690604
Short name T712
Test name
Test status
Simulation time 30566600 ps
CPU time 283.51 seconds
Started Sep 24 06:38:04 PM UTC 24
Finished Sep 24 06:42:52 PM UTC 24
Peak memory 289424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415690604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3415690604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.2960327258
Short name T702
Test name
Test status
Simulation time 8820855600 ps
CPU time 179.36 seconds
Started Sep 24 06:38:40 PM UTC 24
Finished Sep 24 06:41:42 PM UTC 24
Peak memory 275532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2960327258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.2960327258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3124946557
Short name T710
Test name
Test status
Simulation time 75754200 ps
CPU time 24.56 seconds
Started Sep 24 06:42:07 PM UTC 24
Finished Sep 24 06:42:33 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124946557 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.3124946557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1319241645
Short name T706
Test name
Test status
Simulation time 16990100 ps
CPU time 27.81 seconds
Started Sep 24 06:41:56 PM UTC 24
Finished Sep 24 06:42:25 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319241645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1319241645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2943329779
Short name T270
Test name
Test status
Simulation time 10019070600 ps
CPU time 89.98 seconds
Started Sep 24 06:42:02 PM UTC 24
Finished Sep 24 06:43:34 PM UTC 24
Peak memory 302060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2943329779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2943329779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3955324966
Short name T353
Test name
Test status
Simulation time 45212800 ps
CPU time 28.97 seconds
Started Sep 24 06:42:00 PM UTC 24
Finished Sep 24 06:42:30 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3955324966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.flash_ctrl_hw_read_seed_err.3955324966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2177762612
Short name T952
Test name
Test status
Simulation time 350258716900 ps
CPU time 1085.17 seconds
Started Sep 24 06:40:18 PM UTC 24
Finished Sep 24 06:58:36 PM UTC 24
Peak memory 275104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177762612
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res
et.2177762612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.4221212473
Short name T711
Test name
Test status
Simulation time 3858646800 ps
CPU time 140.97 seconds
Started Sep 24 06:40:15 PM UTC 24
Finished Sep 24 06:42:39 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221212473 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.4221212473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3255516385
Short name T722
Test name
Test status
Simulation time 1233997800 ps
CPU time 204.84 seconds
Started Sep 24 06:40:50 PM UTC 24
Finished Sep 24 06:44:18 PM UTC 24
Peak memory 304240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255516385 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.3255516385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1262679026
Short name T745
Test name
Test status
Simulation time 48856666800 ps
CPU time 312.97 seconds
Started Sep 24 06:41:10 PM UTC 24
Finished Sep 24 06:46:28 PM UTC 24
Peak memory 303848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1262679026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_intr_rd_slow_flash.1262679026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.1721253683
Short name T704
Test name
Test status
Simulation time 3099685800 ps
CPU time 94.43 seconds
Started Sep 24 06:40:30 PM UTC 24
Finished Sep 24 06:42:07 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721253683 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1721253683
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.2134946333
Short name T707
Test name
Test status
Simulation time 26616500 ps
CPU time 25.51 seconds
Started Sep 24 06:41:59 PM UTC 24
Finished Sep 24 06:42:26 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2134946333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_lcmgr_intg.2134946333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.4098969336
Short name T716
Test name
Test status
Simulation time 8131596200 ps
CPU time 201.73 seconds
Started Sep 24 06:40:27 PM UTC 24
Finished Sep 24 06:43:52 PM UTC 24
Peak memory 275328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4098969336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_mp_regions.4098969336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.873180895
Short name T176
Test name
Test status
Simulation time 43759800 ps
CPU time 164.15 seconds
Started Sep 24 06:40:18 PM UTC 24
Finished Sep 24 06:43:05 PM UTC 24
Peak memory 271352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873180895 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.873180895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.2119589703
Short name T731
Test name
Test status
Simulation time 187491600 ps
CPU time 260.88 seconds
Started Sep 24 06:40:12 PM UTC 24
Finished Sep 24 06:44:37 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119589703 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2119589703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.2008836722
Short name T701
Test name
Test status
Simulation time 57454800 ps
CPU time 21 seconds
Started Sep 24 06:41:10 PM UTC 24
Finished Sep 24 06:41:32 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008836722 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.2008836722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.3375743009
Short name T762
Test name
Test status
Simulation time 47984700 ps
CPU time 494.84 seconds
Started Sep 24 06:40:11 PM UTC 24
Finished Sep 24 06:48:32 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375743009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3375743009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.2394678175
Short name T705
Test name
Test status
Simulation time 72469800 ps
CPU time 50.51 seconds
Started Sep 24 06:41:31 PM UTC 24
Finished Sep 24 06:42:23 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394678175 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.2394678175
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.1598401709
Short name T709
Test name
Test status
Simulation time 930294500 ps
CPU time 113.75 seconds
Started Sep 24 06:40:36 PM UTC 24
Finished Sep 24 06:42:32 PM UTC 24
Peak memory 291888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1598401709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.1598401709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.4277152015
Short name T773
Test name
Test status
Simulation time 6326640300 ps
CPU time 516.53 seconds
Started Sep 24 06:40:49 PM UTC 24
Finished Sep 24 06:49:32 PM UTC 24
Peak memory 322600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277152015 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.4277152015
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1015915434
Short name T369
Test name
Test status
Simulation time 28452700 ps
CPU time 52.54 seconds
Started Sep 24 06:41:12 PM UTC 24
Finished Sep 24 06:42:06 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015915434 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.1015915434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3675163354
Short name T366
Test name
Test status
Simulation time 30282400 ps
CPU time 44.66 seconds
Started Sep 24 06:41:15 PM UTC 24
Finished Sep 24 06:42:01 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3675163354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw_evict_all_en.3675163354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3027745162
Short name T410
Test name
Test status
Simulation time 513772600 ps
CPU time 67.5 seconds
Started Sep 24 06:41:44 PM UTC 24
Finished Sep 24 06:42:53 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027745162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3027745162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.2401883708
Short name T698
Test name
Test status
Simulation time 33951900 ps
CPU time 58.23 seconds
Started Sep 24 06:40:09 PM UTC 24
Finished Sep 24 06:41:09 PM UTC 24
Peak memory 285328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401883708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2401883708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.4079059799
Short name T717
Test name
Test status
Simulation time 28842636300 ps
CPU time 195.57 seconds
Started Sep 24 06:40:34 PM UTC 24
Finished Sep 24 06:43:53 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4079059799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.4079059799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1025965409
Short name T730
Test name
Test status
Simulation time 22140300 ps
CPU time 27.07 seconds
Started Sep 24 06:44:03 PM UTC 24
Finished Sep 24 06:44:31 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025965409 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.1025965409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.975514478
Short name T725
Test name
Test status
Simulation time 24163800 ps
CPU time 24.83 seconds
Started Sep 24 06:43:53 PM UTC 24
Finished Sep 24 06:44:19 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975514478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.975514478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1695950301
Short name T718
Test name
Test status
Simulation time 10245000 ps
CPU time 25.78 seconds
Started Sep 24 06:43:35 PM UTC 24
Finished Sep 24 06:44:02 PM UTC 24
Peak memory 285756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1695950301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_
ctrl_disable.1695950301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.10774645
Short name T772
Test name
Test status
Simulation time 10012213900 ps
CPU time 320.08 seconds
Started Sep 24 06:44:03 PM UTC 24
Finished Sep 24 06:49:28 PM UTC 24
Peak memory 314144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=10774645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.10774645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.905260174
Short name T728
Test name
Test status
Simulation time 96166300 ps
CPU time 21.97 seconds
Started Sep 24 06:43:58 PM UTC 24
Finished Sep 24 06:44:21 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=905260174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.flash_ctrl_hw_read_seed_err.905260174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.1351781590
Short name T920
Test name
Test status
Simulation time 40120234300 ps
CPU time 876.19 seconds
Started Sep 24 06:42:26 PM UTC 24
Finished Sep 24 06:57:13 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351781590
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res
et.1351781590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.4088601516
Short name T320
Test name
Test status
Simulation time 6749898100 ps
CPU time 148.37 seconds
Started Sep 24 06:42:26 PM UTC 24
Finished Sep 24 06:44:57 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088601516 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.4088601516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1001749494
Short name T732
Test name
Test status
Simulation time 886154400 ps
CPU time 128.66 seconds
Started Sep 24 06:42:54 PM UTC 24
Finished Sep 24 06:45:05 PM UTC 24
Peak memory 304048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001749494 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1001749494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.857551165
Short name T787
Test name
Test status
Simulation time 12945663300 ps
CPU time 430.78 seconds
Started Sep 24 06:42:59 PM UTC 24
Finished Sep 24 06:50:16 PM UTC 24
Peak memory 301800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=857551165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_intr_rd_slow_flash.857551165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.2841654806
Short name T719
Test name
Test status
Simulation time 8526133900 ps
CPU time 86.36 seconds
Started Sep 24 06:42:33 PM UTC 24
Finished Sep 24 06:44:02 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841654806 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2841654806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1708682030
Short name T724
Test name
Test status
Simulation time 38222400 ps
CPU time 23.76 seconds
Started Sep 24 06:43:54 PM UTC 24
Finished Sep 24 06:44:19 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1708682030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_lcmgr_intg.1708682030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.188147591
Short name T727
Test name
Test status
Simulation time 1185949200 ps
CPU time 106.83 seconds
Started Sep 24 06:42:31 PM UTC 24
Finished Sep 24 06:44:20 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=188147591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_mp_regions.188147591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.465192558
Short name T721
Test name
Test status
Simulation time 279719100 ps
CPU time 111.5 seconds
Started Sep 24 06:42:24 PM UTC 24
Finished Sep 24 06:44:18 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465192558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.465192558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.2560261360
Short name T714
Test name
Test status
Simulation time 140528200 ps
CPU time 28.14 seconds
Started Sep 24 06:43:01 PM UTC 24
Finished Sep 24 06:43:31 PM UTC 24
Peak memory 271288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560261360 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.2560261360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2031710751
Short name T958
Test name
Test status
Simulation time 2962243700 ps
CPU time 975.14 seconds
Started Sep 24 06:42:18 PM UTC 24
Finished Sep 24 06:58:45 PM UTC 24
Peak memory 295564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031710751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2031710751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.738638511
Short name T729
Test name
Test status
Simulation time 129085100 ps
CPU time 48.08 seconds
Started Sep 24 06:43:33 PM UTC 24
Finished Sep 24 06:44:23 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738638511 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.738638511
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.2809318698
Short name T723
Test name
Test status
Simulation time 489956000 ps
CPU time 96.91 seconds
Started Sep 24 06:42:40 PM UTC 24
Finished Sep 24 06:44:19 PM UTC 24
Peak memory 302088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2809318698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.2809318698
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.2445215654
Short name T800
Test name
Test status
Simulation time 4232687100 ps
CPU time 487.08 seconds
Started Sep 24 06:42:53 PM UTC 24
Finished Sep 24 06:51:07 PM UTC 24
Peak memory 320800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445215654 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.2445215654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.342067025
Short name T358
Test name
Test status
Simulation time 28864300 ps
CPU time 49.29 seconds
Started Sep 24 06:43:05 PM UTC 24
Finished Sep 24 06:43:56 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342067025 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.342067025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.3740667197
Short name T726
Test name
Test status
Simulation time 68230400 ps
CPU time 47.02 seconds
Started Sep 24 06:43:31 PM UTC 24
Finished Sep 24 06:44:20 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3740667197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw_evict_all_en.3740667197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1802284760
Short name T417
Test name
Test status
Simulation time 488019700 ps
CPU time 93.57 seconds
Started Sep 24 06:43:42 PM UTC 24
Finished Sep 24 06:45:17 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802284760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1802284760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.3091861433
Short name T735
Test name
Test status
Simulation time 42325700 ps
CPU time 204.72 seconds
Started Sep 24 06:42:08 PM UTC 24
Finished Sep 24 06:45:36 PM UTC 24
Peak memory 289612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091861433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3091861433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.3428241685
Short name T733
Test name
Test status
Simulation time 7036860500 ps
CPU time 169.38 seconds
Started Sep 24 06:42:34 PM UTC 24
Finished Sep 24 06:45:27 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3428241685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.3428241685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1640991709
Short name T746
Test name
Test status
Simulation time 41471400 ps
CPU time 25.36 seconds
Started Sep 24 06:46:04 PM UTC 24
Finished Sep 24 06:46:31 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640991709 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1640991709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.933733033
Short name T740
Test name
Test status
Simulation time 51265200 ps
CPU time 25.16 seconds
Started Sep 24 06:45:47 PM UTC 24
Finished Sep 24 06:46:13 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933733033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.933733033
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1562114543
Short name T408
Test name
Test status
Simulation time 15324700 ps
CPU time 32.64 seconds
Started Sep 24 06:45:29 PM UTC 24
Finished Sep 24 06:46:03 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1562114543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_
ctrl_disable.1562114543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2283448269
Short name T271
Test name
Test status
Simulation time 10019148200 ps
CPU time 162.89 seconds
Started Sep 24 06:46:02 PM UTC 24
Finished Sep 24 06:48:48 PM UTC 24
Peak memory 302036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2283448269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2283448269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.174241941
Short name T742
Test name
Test status
Simulation time 16710000 ps
CPU time 25.45 seconds
Started Sep 24 06:45:49 PM UTC 24
Finished Sep 24 06:46:16 PM UTC 24
Peak memory 269256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=174241941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.flash_ctrl_hw_read_seed_err.174241941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.2294259644
Short name T998
Test name
Test status
Simulation time 40122073600 ps
CPU time 942.94 seconds
Started Sep 24 06:44:20 PM UTC 24
Finished Sep 24 07:00:15 PM UTC 24
Peak memory 274968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294259644
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res
et.2294259644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3500070137
Short name T749
Test name
Test status
Simulation time 2453568800 ps
CPU time 181.71 seconds
Started Sep 24 06:44:19 PM UTC 24
Finished Sep 24 06:47:24 PM UTC 24
Peak memory 273228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500070137 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.3500070137
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.731211269
Short name T764
Test name
Test status
Simulation time 1450063100 ps
CPU time 247.92 seconds
Started Sep 24 06:44:38 PM UTC 24
Finished Sep 24 06:48:49 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731211269 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.731211269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3040841886
Short name T766
Test name
Test status
Simulation time 43005940400 ps
CPU time 243.35 seconds
Started Sep 24 06:44:56 PM UTC 24
Finished Sep 24 06:49:03 PM UTC 24
Peak memory 303844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3040841886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_intr_rd_slow_flash.3040841886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.3782549080
Short name T736
Test name
Test status
Simulation time 6244383400 ps
CPU time 81.56 seconds
Started Sep 24 06:44:22 PM UTC 24
Finished Sep 24 06:45:46 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782549080 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3782549080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2843143720
Short name T739
Test name
Test status
Simulation time 136708300 ps
CPU time 23.71 seconds
Started Sep 24 06:45:48 PM UTC 24
Finished Sep 24 06:46:13 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2843143720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_lcmgr_intg.2843143720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.4012053745
Short name T747
Test name
Test status
Simulation time 1884181500 ps
CPU time 156.18 seconds
Started Sep 24 06:44:22 PM UTC 24
Finished Sep 24 06:47:01 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4012053745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_mp_regions.4012053745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.3794382163
Short name T753
Test name
Test status
Simulation time 135763400 ps
CPU time 200 seconds
Started Sep 24 06:44:20 PM UTC 24
Finished Sep 24 06:47:44 PM UTC 24
Peak memory 271288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794382163 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.3794382163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.3868203058
Short name T906
Test name
Test status
Simulation time 1432067200 ps
CPU time 716.44 seconds
Started Sep 24 06:44:19 PM UTC 24
Finished Sep 24 06:56:25 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868203058 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3868203058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.2630642533
Short name T734
Test name
Test status
Simulation time 19358000 ps
CPU time 29.07 seconds
Started Sep 24 06:44:58 PM UTC 24
Finished Sep 24 06:45:28 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630642533 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.2630642533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1127140633
Short name T801
Test name
Test status
Simulation time 250790800 ps
CPU time 403.69 seconds
Started Sep 24 06:44:18 PM UTC 24
Finished Sep 24 06:51:07 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127140633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1127140633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.4133740201
Short name T362
Test name
Test status
Simulation time 119760000 ps
CPU time 37.12 seconds
Started Sep 24 06:45:27 PM UTC 24
Finished Sep 24 06:46:06 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133740201 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.4133740201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.3684161688
Short name T748
Test name
Test status
Simulation time 656401200 ps
CPU time 165.18 seconds
Started Sep 24 06:44:24 PM UTC 24
Finished Sep 24 06:47:13 PM UTC 24
Peak memory 304100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3684161688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.3684161688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.2417773304
Short name T861
Test name
Test status
Simulation time 8600782100 ps
CPU time 577.27 seconds
Started Sep 24 06:44:32 PM UTC 24
Finished Sep 24 06:54:17 PM UTC 24
Peak memory 330752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417773304 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.2417773304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.789360535
Short name T361
Test name
Test status
Simulation time 30664800 ps
CPU time 53.42 seconds
Started Sep 24 06:45:06 PM UTC 24
Finished Sep 24 06:46:01 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789360535 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.789360535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.711477628
Short name T741
Test name
Test status
Simulation time 28246400 ps
CPU time 53.89 seconds
Started Sep 24 06:45:18 PM UTC 24
Finished Sep 24 06:46:14 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=711477628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ct
rl_rw_evict_all_en.711477628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.1839670860
Short name T438
Test name
Test status
Simulation time 6031833100 ps
CPU time 89.23 seconds
Started Sep 24 06:45:38 PM UTC 24
Finished Sep 24 06:47:09 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839670860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1839670860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.185014035
Short name T744
Test name
Test status
Simulation time 22332000 ps
CPU time 125.36 seconds
Started Sep 24 06:44:17 PM UTC 24
Finished Sep 24 06:46:25 PM UTC 24
Peak memory 287568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185014035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.185014035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.3843490363
Short name T751
Test name
Test status
Simulation time 9035120200 ps
CPU time 181.85 seconds
Started Sep 24 06:44:22 PM UTC 24
Finished Sep 24 06:47:27 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3843490363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.3843490363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1468629301
Short name T763
Test name
Test status
Simulation time 90920900 ps
CPU time 29.57 seconds
Started Sep 24 06:48:05 PM UTC 24
Finished Sep 24 06:48:37 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468629301 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.1468629301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.3048150727
Short name T759
Test name
Test status
Simulation time 17160200 ps
CPU time 29.75 seconds
Started Sep 24 06:47:44 PM UTC 24
Finished Sep 24 06:48:15 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048150727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3048150727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1785907702
Short name T756
Test name
Test status
Simulation time 11766300 ps
CPU time 34.78 seconds
Started Sep 24 06:47:28 PM UTC 24
Finished Sep 24 06:48:05 PM UTC 24
Peak memory 285500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1785907702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_
ctrl_disable.1785907702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1164753622
Short name T791
Test name
Test status
Simulation time 10019604700 ps
CPU time 171.74 seconds
Started Sep 24 06:47:48 PM UTC 24
Finished Sep 24 06:50:43 PM UTC 24
Peak memory 297764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1164753622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1164753622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.2598262787
Short name T758
Test name
Test status
Simulation time 47418800 ps
CPU time 24.25 seconds
Started Sep 24 06:47:47 PM UTC 24
Finished Sep 24 06:48:13 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2598262787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.flash_ctrl_hw_read_seed_err.2598262787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.1246834912
Short name T1036
Test name
Test status
Simulation time 160159277600 ps
CPU time 908.49 seconds
Started Sep 24 06:46:15 PM UTC 24
Finished Sep 24 07:01:35 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246834912
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res
et.1246834912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1879587790
Short name T770
Test name
Test status
Simulation time 9971412000 ps
CPU time 184.87 seconds
Started Sep 24 06:46:14 PM UTC 24
Finished Sep 24 06:49:22 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879587790 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.1879587790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3660629906
Short name T326
Test name
Test status
Simulation time 13216702900 ps
CPU time 304.32 seconds
Started Sep 24 06:47:09 PM UTC 24
Finished Sep 24 06:52:18 PM UTC 24
Peak memory 302020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3660629906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_intr_rd_slow_flash.3660629906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3908958260
Short name T752
Test name
Test status
Simulation time 5863351700 ps
CPU time 75.75 seconds
Started Sep 24 06:46:25 PM UTC 24
Finished Sep 24 06:47:43 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908958260 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3908958260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.2310090462
Short name T757
Test name
Test status
Simulation time 153253800 ps
CPU time 24.91 seconds
Started Sep 24 06:47:45 PM UTC 24
Finished Sep 24 06:48:11 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2310090462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_lcmgr_intg.2310090462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1962129919
Short name T771
Test name
Test status
Simulation time 6047658100 ps
CPU time 179.28 seconds
Started Sep 24 06:46:21 PM UTC 24
Finished Sep 24 06:49:24 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1962129919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_mp_regions.1962129919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.229565885
Short name T426
Test name
Test status
Simulation time 172567100 ps
CPU time 177.76 seconds
Started Sep 24 06:46:17 PM UTC 24
Finished Sep 24 06:49:18 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229565885 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.229565885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3190757122
Short name T838
Test name
Test status
Simulation time 736732100 ps
CPU time 414.66 seconds
Started Sep 24 06:46:14 PM UTC 24
Finished Sep 24 06:53:14 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190757122 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3190757122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.3526505290
Short name T754
Test name
Test status
Simulation time 712362800 ps
CPU time 33.53 seconds
Started Sep 24 06:47:13 PM UTC 24
Finished Sep 24 06:47:48 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526505290 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.3526505290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2683149640
Short name T844
Test name
Test status
Simulation time 118359200 ps
CPU time 435.39 seconds
Started Sep 24 06:46:13 PM UTC 24
Finished Sep 24 06:53:34 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683149640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2683149640
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.422688686
Short name T760
Test name
Test status
Simulation time 41789700 ps
CPU time 66.28 seconds
Started Sep 24 06:47:14 PM UTC 24
Finished Sep 24 06:48:22 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422688686 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.422688686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.2782425034
Short name T755
Test name
Test status
Simulation time 109350700 ps
CPU time 37.32 seconds
Started Sep 24 06:47:25 PM UTC 24
Finished Sep 24 06:48:04 PM UTC 24
Peak memory 287776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2782425034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw_evict_all_en.2782425034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.1154142938
Short name T414
Test name
Test status
Simulation time 823768000 ps
CPU time 94.19 seconds
Started Sep 24 06:47:37 PM UTC 24
Finished Sep 24 06:49:13 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154142938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1154142938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.4109699919
Short name T761
Test name
Test status
Simulation time 29569300 ps
CPU time 134.48 seconds
Started Sep 24 06:46:06 PM UTC 24
Finished Sep 24 06:48:24 PM UTC 24
Peak memory 287372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109699919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.4109699919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1114749921
Short name T777
Test name
Test status
Simulation time 3884248200 ps
CPU time 200.44 seconds
Started Sep 24 06:46:28 PM UTC 24
Finished Sep 24 06:49:52 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1114749921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.1114749921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.3444936817
Short name T115
Test name
Test status
Simulation time 414738500 ps
CPU time 20.43 seconds
Started Sep 24 05:54:20 PM UTC 24
Finished Sep 24 05:54:42 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444936817 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3444936817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.979905355
Short name T218
Test name
Test status
Simulation time 93099700 ps
CPU time 25.63 seconds
Started Sep 24 05:53:57 PM UTC 24
Finished Sep 24 05:54:24 PM UTC 24
Peak memory 275096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979905355 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.979905355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.3808467968
Short name T25
Test name
Test status
Simulation time 16089200 ps
CPU time 27.58 seconds
Started Sep 24 05:53:30 PM UTC 24
Finished Sep 24 05:54:00 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808467968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3808467968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3245722513
Short name T432
Test name
Test status
Simulation time 90844700 ps
CPU time 42.41 seconds
Started Sep 24 05:53:00 PM UTC 24
Finished Sep 24 05:53:44 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3245722513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_disable.3245722513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.3778770258
Short name T276
Test name
Test status
Simulation time 4060436500 ps
CPU time 3023.12 seconds
Started Sep 24 05:50:58 PM UTC 24
Finished Sep 24 06:41:54 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778770258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3778770258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1668222792
Short name T280
Test name
Test status
Simulation time 701282300 ps
CPU time 1353.78 seconds
Started Sep 24 05:50:49 PM UTC 24
Finished Sep 24 06:13:38 PM UTC 24
Peak memory 285400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668222792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1668222792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2188212943
Short name T299
Test name
Test status
Simulation time 477136300 ps
CPU time 44.53 seconds
Started Sep 24 05:53:40 PM UTC 24
Finished Sep 24 05:54:26 PM UTC 24
Peak memory 273184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188212
943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f
s_sup.2188212943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1148318706
Short name T165
Test name
Test status
Simulation time 119348576800 ps
CPU time 3629.11 seconds
Started Sep 24 05:50:48 PM UTC 24
Finished Sep 24 06:52:01 PM UTC 24
Peak memory 277816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148318706 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.1148318706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2475859283
Short name T304
Test name
Test status
Simulation time 65753200 ps
CPU time 42.18 seconds
Started Sep 24 05:54:19 PM UTC 24
Finished Sep 24 05:55:03 PM UTC 24
Peak memory 285372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247585928
3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho
st_addr_infection.2475859283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2976340361
Short name T183
Test name
Test status
Simulation time 430706862500 ps
CPU time 2738.11 seconds
Started Sep 24 05:50:40 PM UTC 24
Finished Sep 24 06:36:49 PM UTC 24
Peak memory 277996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976340361 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.2976340361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3806384170
Short name T192
Test name
Test status
Simulation time 93735300 ps
CPU time 51.33 seconds
Started Sep 24 05:50:31 PM UTC 24
Finished Sep 24 05:51:24 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806384170 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3806384170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.711811764
Short name T168
Test name
Test status
Simulation time 10015682100 ps
CPU time 106.01 seconds
Started Sep 24 05:54:18 PM UTC 24
Finished Sep 24 05:56:06 PM UTC 24
Peak memory 341080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=711811764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.711811764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3569575202
Short name T85
Test name
Test status
Simulation time 26051700 ps
CPU time 19.93 seconds
Started Sep 24 05:54:16 PM UTC 24
Finished Sep 24 05:54:37 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3569575202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_hw_read_seed_err.3569575202
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.3733289587
Short name T139
Test name
Test status
Simulation time 100821303300 ps
CPU time 1975.14 seconds
Started Sep 24 05:50:38 PM UTC 24
Finished Sep 24 06:23:57 PM UTC 24
Peak memory 277760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733289587
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.3733289587
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2943389973
Short name T141
Test name
Test status
Simulation time 160179352500 ps
CPU time 848.52 seconds
Started Sep 24 05:50:38 PM UTC 24
Finished Sep 24 06:04:58 PM UTC 24
Peak memory 275168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943389973
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.2943389973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.3605073807
Short name T120
Test name
Test status
Simulation time 2798715700 ps
CPU time 98.72 seconds
Started Sep 24 05:50:32 PM UTC 24
Finished Sep 24 05:52:13 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605073807 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.3605073807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.4165118054
Short name T467
Test name
Test status
Simulation time 31145588600 ps
CPU time 561.04 seconds
Started Sep 24 05:52:10 PM UTC 24
Finished Sep 24 06:01:39 PM UTC 24
Peak memory 343072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4165118054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr
ity.4165118054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2452813865
Short name T349
Test name
Test status
Simulation time 7361422700 ps
CPU time 231.54 seconds
Started Sep 24 05:52:14 PM UTC 24
Finished Sep 24 05:56:10 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452813865 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.2452813865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.892091350
Short name T343
Test name
Test status
Simulation time 107098561700 ps
CPU time 539.02 seconds
Started Sep 24 05:52:22 PM UTC 24
Finished Sep 24 06:01:29 PM UTC 24
Peak memory 301608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=892091350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_rd_slow_flash.892091350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.1721317647
Short name T446
Test name
Test status
Simulation time 8028198300 ps
CPU time 71.33 seconds
Started Sep 24 05:52:21 PM UTC 24
Finished Sep 24 05:53:35 PM UTC 24
Peak memory 275520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721317647 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.1721317647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1487852928
Short name T295
Test name
Test status
Simulation time 27644557100 ps
CPU time 248.5 seconds
Started Sep 24 05:52:22 PM UTC 24
Finished Sep 24 05:56:35 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487852928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1487852928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2306027351
Short name T87
Test name
Test status
Simulation time 3061122200 ps
CPU time 88.96 seconds
Started Sep 24 05:50:59 PM UTC 24
Finished Sep 24 05:52:30 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306027351 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2306027351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3629317574
Short name T175
Test name
Test status
Simulation time 15072800 ps
CPU time 16.71 seconds
Started Sep 24 05:54:06 PM UTC 24
Finished Sep 24 05:54:24 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3629317574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_lcmgr_intg.3629317574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.2597156408
Short name T61
Test name
Test status
Simulation time 2562509700 ps
CPU time 118.47 seconds
Started Sep 24 05:51:01 PM UTC 24
Finished Sep 24 05:53:02 PM UTC 24
Peak memory 272924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597156408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2597156408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.551077392
Short name T91
Test name
Test status
Simulation time 78592800 ps
CPU time 170.54 seconds
Started Sep 24 05:50:39 PM UTC 24
Finished Sep 24 05:53:34 PM UTC 24
Peak memory 271100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551077392 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.551077392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1281148589
Short name T205
Test name
Test status
Simulation time 1450748800 ps
CPU time 168.52 seconds
Started Sep 24 05:52:04 PM UTC 24
Finished Sep 24 05:54:57 PM UTC 24
Peak memory 292016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1281148589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_oversize_error.1281148589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.4221239487
Short name T195
Test name
Test status
Simulation time 15180900 ps
CPU time 24.87 seconds
Started Sep 24 05:53:55 PM UTC 24
Finished Sep 24 05:54:21 PM UTC 24
Peak memory 273524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221239487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.4221239487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.3785872129
Short name T228
Test name
Test status
Simulation time 238176800 ps
CPU time 291.49 seconds
Started Sep 24 05:50:32 PM UTC 24
Finished Sep 24 05:55:27 PM UTC 24
Peak memory 275336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785872129 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3785872129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1417261459
Short name T449
Test name
Test status
Simulation time 4602762700 ps
CPU time 256.58 seconds
Started Sep 24 05:52:22 PM UTC 24
Finished Sep 24 05:56:44 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417261459 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.1417261459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.3884545570
Short name T145
Test name
Test status
Simulation time 829723500 ps
CPU time 1021.15 seconds
Started Sep 24 05:50:24 PM UTC 24
Finished Sep 24 06:07:37 PM UTC 24
Peak memory 295752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884545570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3884545570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.591602483
Short name T35
Test name
Test status
Simulation time 2918833300 ps
CPU time 173.19 seconds
Started Sep 24 05:50:31 PM UTC 24
Finished Sep 24 05:53:27 PM UTC 24
Peak memory 273092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591602483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.591602483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.219612467
Short name T293
Test name
Test status
Simulation time 65993800 ps
CPU time 44.19 seconds
Started Sep 24 05:53:35 PM UTC 24
Finished Sep 24 05:54:21 PM UTC 24
Peak memory 285728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219612467
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.219612467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2578636364
Short name T264
Test name
Test status
Simulation time 80299100 ps
CPU time 65.28 seconds
Started Sep 24 05:52:32 PM UTC 24
Finished Sep 24 05:53:39 PM UTC 24
Peak memory 287876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578636364 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.2578636364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.1986713145
Short name T151
Test name
Test status
Simulation time 18416800 ps
CPU time 33.69 seconds
Started Sep 24 05:51:47 PM UTC 24
Finished Sep 24 05:52:22 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1986713145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_derr.1986713145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.216284972
Short name T420
Test name
Test status
Simulation time 58926600 ps
CPU time 36.43 seconds
Started Sep 24 05:51:09 PM UTC 24
Finished Sep 24 05:51:47 PM UTC 24
Peak memory 275336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216284972 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.216284972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2136616269
Short name T104
Test name
Test status
Simulation time 167198609600 ps
CPU time 1226.63 seconds
Started Sep 24 05:54:01 PM UTC 24
Finished Sep 24 06:14:43 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2136616269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_rma_err.2136616269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3294383121
Short name T153
Test name
Test status
Simulation time 2536990600 ps
CPU time 112.77 seconds
Started Sep 24 05:51:04 PM UTC 24
Finished Sep 24 05:52:59 PM UTC 24
Peak memory 291720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3294383121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.3294383121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1704146909
Short name T238
Test name
Test status
Simulation time 1393268400 ps
CPU time 148.3 seconds
Started Sep 24 05:51:48 PM UTC 24
Finished Sep 24 05:54:19 PM UTC 24
Peak memory 292028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704146909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1704146909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.495331339
Short name T227
Test name
Test status
Simulation time 8925102000 ps
CPU time 175.49 seconds
Started Sep 24 05:51:19 PM UTC 24
Finished Sep 24 05:54:17 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=495331339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_
ctrl_ro_serr.495331339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.3666410872
Short name T461
Test name
Test status
Simulation time 21242427700 ps
CPU time 549.48 seconds
Started Sep 24 05:51:05 PM UTC 24
Finished Sep 24 06:00:22 PM UTC 24
Peak memory 320536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666410872 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.3666410872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4001754285
Short name T444
Test name
Test status
Simulation time 10096348700 ps
CPU time 242.65 seconds
Started Sep 24 05:51:48 PM UTC 24
Finished Sep 24 05:55:55 PM UTC 24
Peak memory 300080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=4001754285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rw_derr.4001754285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1430605081
Short name T303
Test name
Test status
Simulation time 44695600 ps
CPU time 60.83 seconds
Started Sep 24 05:52:31 PM UTC 24
Finished Sep 24 05:53:33 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430605081 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.1430605081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.3419525404
Short name T263
Test name
Test status
Simulation time 105307600 ps
CPU time 56.22 seconds
Started Sep 24 05:52:32 PM UTC 24
Finished Sep 24 05:53:30 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3419525404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw_evict_all_en.3419525404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3833657648
Short name T422
Test name
Test status
Simulation time 6461169500 ps
CPU time 250.16 seconds
Started Sep 24 05:51:21 PM UTC 24
Finished Sep 24 05:55:35 PM UTC 24
Peak memory 306360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3833657648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.3833657648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.2580544934
Short name T64
Test name
Test status
Simulation time 4570065200 ps
CPU time 7393.6 seconds
Started Sep 24 05:53:03 PM UTC 24
Finished Sep 24 07:57:39 PM UTC 24
Peak memory 314212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580544934 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2580544934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.626996382
Short name T424
Test name
Test status
Simulation time 1785716000 ps
CPU time 97.99 seconds
Started Sep 24 05:51:37 PM UTC 24
Finished Sep 24 05:53:17 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626
996382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr
_address.626996382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1267335614
Short name T152
Test name
Test status
Simulation time 1127042000 ps
CPU time 63.17 seconds
Started Sep 24 05:51:25 PM UTC 24
Finished Sep 24 05:52:30 PM UTC 24
Peak memory 275460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12
67335614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se
rr_counter.1267335614
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.2269938862
Short name T222
Test name
Test status
Simulation time 38598500 ps
CPU time 202.74 seconds
Started Sep 24 05:50:21 PM UTC 24
Finished Sep 24 05:53:48 PM UTC 24
Peak memory 278800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269938862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2269938862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1277199260
Short name T445
Test name
Test status
Simulation time 16466700 ps
CPU time 34.42 seconds
Started Sep 24 05:50:22 PM UTC 24
Finished Sep 24 05:50:58 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277199260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1277199260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.1089012470
Short name T464
Test name
Test status
Simulation time 111047000 ps
CPU time 452.85 seconds
Started Sep 24 05:53:27 PM UTC 24
Finished Sep 24 06:01:06 PM UTC 24
Peak memory 287696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089012470 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.1089012470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3260132340
Short name T190
Test name
Test status
Simulation time 51741700 ps
CPU time 28.66 seconds
Started Sep 24 05:50:30 PM UTC 24
Finished Sep 24 05:51:00 PM UTC 24
Peak memory 272904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260132340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3260132340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.752957548
Short name T423
Test name
Test status
Simulation time 11344721900 ps
CPU time 189.58 seconds
Started Sep 24 05:51:02 PM UTC 24
Finished Sep 24 05:54:15 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=752957548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.752957548
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2236677233
Short name T21
Test name
Test status
Simulation time 124770100 ps
CPU time 17.74 seconds
Started Sep 24 05:53:35 PM UTC 24
Finished Sep 24 05:53:54 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2236677233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_wr_intg.2236677233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1834926105
Short name T769
Test name
Test status
Simulation time 38175800 ps
CPU time 25.68 seconds
Started Sep 24 06:48:53 PM UTC 24
Finished Sep 24 06:49:20 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834926105 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1834926105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.268760855
Short name T768
Test name
Test status
Simulation time 50784700 ps
CPU time 27.81 seconds
Started Sep 24 06:48:51 PM UTC 24
Finished Sep 24 06:49:20 PM UTC 24
Peak memory 284812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268760855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.268760855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.2963325623
Short name T767
Test name
Test status
Simulation time 11961300 ps
CPU time 32.01 seconds
Started Sep 24 06:48:37 PM UTC 24
Finished Sep 24 06:49:11 PM UTC 24
Peak memory 285452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2963325623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_
ctrl_disable.2963325623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2837919539
Short name T788
Test name
Test status
Simulation time 13021431700 ps
CPU time 143.16 seconds
Started Sep 24 06:48:11 PM UTC 24
Finished Sep 24 06:50:37 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837919539 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.2837919539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.2033483213
Short name T377
Test name
Test status
Simulation time 2539211000 ps
CPU time 241.48 seconds
Started Sep 24 06:48:14 PM UTC 24
Finished Sep 24 06:52:19 PM UTC 24
Peak memory 301932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033483213 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.2033483213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2282109945
Short name T796
Test name
Test status
Simulation time 5785702600 ps
CPU time 152.41 seconds
Started Sep 24 06:48:16 PM UTC 24
Finished Sep 24 06:50:51 PM UTC 24
Peak memory 303876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2282109945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.flash_ctrl_intr_rd_slow_flash.2282109945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3705625304
Short name T428
Test name
Test status
Simulation time 217519400 ps
CPU time 167.63 seconds
Started Sep 24 06:48:12 PM UTC 24
Finished Sep 24 06:51:02 PM UTC 24
Peak memory 275512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705625304 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.3705625304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.3954717894
Short name T765
Test name
Test status
Simulation time 18569500 ps
CPU time 27.09 seconds
Started Sep 24 06:48:23 PM UTC 24
Finished Sep 24 06:48:51 PM UTC 24
Peak memory 275388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954717894 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.3954717894
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.121551778
Short name T373
Test name
Test status
Simulation time 54821400 ps
CPU time 43.61 seconds
Started Sep 24 06:48:24 PM UTC 24
Finished Sep 24 06:49:09 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121551778 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.121551778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3404997325
Short name T779
Test name
Test status
Simulation time 2248058400 ps
CPU time 67.39 seconds
Started Sep 24 06:48:49 PM UTC 24
Finished Sep 24 06:49:59 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404997325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3404997325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.965032786
Short name T797
Test name
Test status
Simulation time 52907200 ps
CPU time 167.98 seconds
Started Sep 24 06:48:05 PM UTC 24
Finished Sep 24 06:50:56 PM UTC 24
Peak memory 287492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965032786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.965032786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.2116330528
Short name T778
Test name
Test status
Simulation time 99562700 ps
CPU time 21.89 seconds
Started Sep 24 06:49:33 PM UTC 24
Finished Sep 24 06:49:56 PM UTC 24
Peak memory 269064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116330528 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.2116330528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1449926797
Short name T775
Test name
Test status
Simulation time 26841400 ps
CPU time 18.37 seconds
Started Sep 24 06:49:28 PM UTC 24
Finished Sep 24 06:49:48 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449926797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1449926797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.4185355102
Short name T782
Test name
Test status
Simulation time 10211200 ps
CPU time 45.01 seconds
Started Sep 24 06:49:24 PM UTC 24
Finished Sep 24 06:50:10 PM UTC 24
Peak memory 285756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4185355102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_
ctrl_disable.4185355102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.742821454
Short name T785
Test name
Test status
Simulation time 3821817200 ps
CPU time 59.4 seconds
Started Sep 24 06:49:10 PM UTC 24
Finished Sep 24 06:50:11 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742821454 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.742821454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.3168074867
Short name T826
Test name
Test status
Simulation time 877389600 ps
CPU time 191.44 seconds
Started Sep 24 06:49:14 PM UTC 24
Finished Sep 24 06:52:29 PM UTC 24
Peak memory 293740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168074867 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.3168074867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3413984954
Short name T819
Test name
Test status
Simulation time 21264949000 ps
CPU time 169.95 seconds
Started Sep 24 06:49:18 PM UTC 24
Finished Sep 24 06:52:11 PM UTC 24
Peak memory 303852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3413984954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.flash_ctrl_intr_rd_slow_flash.3413984954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.373952408
Short name T820
Test name
Test status
Simulation time 330165400 ps
CPU time 176.37 seconds
Started Sep 24 06:49:12 PM UTC 24
Finished Sep 24 06:52:12 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373952408 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.373952408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.42051805
Short name T774
Test name
Test status
Simulation time 41225800 ps
CPU time 23.98 seconds
Started Sep 24 06:49:20 PM UTC 24
Finished Sep 24 06:49:46 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42051805 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.42051805
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.3957761897
Short name T784
Test name
Test status
Simulation time 98035100 ps
CPU time 48.68 seconds
Started Sep 24 06:49:20 PM UTC 24
Finished Sep 24 06:50:11 PM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957761897 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.3957761897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.113690583
Short name T780
Test name
Test status
Simulation time 27238100 ps
CPU time 42.64 seconds
Started Sep 24 06:49:23 PM UTC 24
Finished Sep 24 06:50:07 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113690583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ct
rl_rw_evict_all_en.113690583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3662293480
Short name T795
Test name
Test status
Simulation time 2717118800 ps
CPU time 82.41 seconds
Started Sep 24 06:49:25 PM UTC 24
Finished Sep 24 06:50:50 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662293480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3662293480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.3747804528
Short name T790
Test name
Test status
Simulation time 16666900 ps
CPU time 91.82 seconds
Started Sep 24 06:49:04 PM UTC 24
Finished Sep 24 06:50:38 PM UTC 24
Peak memory 285576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747804528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3747804528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3259778986
Short name T792
Test name
Test status
Simulation time 60467500 ps
CPU time 30.41 seconds
Started Sep 24 06:50:12 PM UTC 24
Finished Sep 24 06:50:44 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259778986 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.3259778986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.2878329578
Short name T794
Test name
Test status
Simulation time 15764800 ps
CPU time 32.78 seconds
Started Sep 24 06:50:12 PM UTC 24
Finished Sep 24 06:50:46 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878329578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2878329578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.836404854
Short name T789
Test name
Test status
Simulation time 24740600 ps
CPU time 26.73 seconds
Started Sep 24 06:50:09 PM UTC 24
Finished Sep 24 06:50:37 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=836404854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c
trl_disable.836404854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.1979987080
Short name T835
Test name
Test status
Simulation time 706500700 ps
CPU time 185.67 seconds
Started Sep 24 06:49:50 PM UTC 24
Finished Sep 24 06:52:59 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979987080 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.1979987080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1555907500
Short name T921
Test name
Test status
Simulation time 24202609800 ps
CPU time 434.99 seconds
Started Sep 24 06:49:53 PM UTC 24
Finished Sep 24 06:57:14 PM UTC 24
Peak memory 303848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1555907500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.flash_ctrl_intr_rd_slow_flash.1555907500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2292054134
Short name T836
Test name
Test status
Simulation time 40031300 ps
CPU time 187.75 seconds
Started Sep 24 06:49:49 PM UTC 24
Finished Sep 24 06:53:00 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292054134 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.2292054134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3443940823
Short name T786
Test name
Test status
Simulation time 18253600 ps
CPU time 17.75 seconds
Started Sep 24 06:49:57 PM UTC 24
Finished Sep 24 06:50:16 PM UTC 24
Peak memory 271048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443940823 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3443940823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.1243914937
Short name T798
Test name
Test status
Simulation time 31150700 ps
CPU time 60.68 seconds
Started Sep 24 06:49:59 PM UTC 24
Finished Sep 24 06:51:02 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243914937 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.1243914937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.1499649517
Short name T793
Test name
Test status
Simulation time 61960300 ps
CPU time 36.53 seconds
Started Sep 24 06:50:07 PM UTC 24
Finished Sep 24 06:50:46 PM UTC 24
Peak memory 287932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1499649517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c
trl_rw_evict_all_en.1499649517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.3721553027
Short name T860
Test name
Test status
Simulation time 74447000 ps
CPU time 275.23 seconds
Started Sep 24 06:49:37 PM UTC 24
Finished Sep 24 06:54:16 PM UTC 24
Peak memory 289416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721553027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3721553027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.2990487872
Short name T804
Test name
Test status
Simulation time 215761500 ps
CPU time 24.25 seconds
Started Sep 24 06:50:54 PM UTC 24
Finished Sep 24 06:51:20 PM UTC 24
Peak memory 269176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990487872 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.2990487872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1067736572
Short name T805
Test name
Test status
Simulation time 48704000 ps
CPU time 29.49 seconds
Started Sep 24 06:50:54 PM UTC 24
Finished Sep 24 06:51:25 PM UTC 24
Peak memory 294928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067736572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1067736572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.2060955213
Short name T807
Test name
Test status
Simulation time 10162500 ps
CPU time 31.52 seconds
Started Sep 24 06:50:54 PM UTC 24
Finished Sep 24 06:51:27 PM UTC 24
Peak memory 285596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2060955213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_
ctrl_disable.2060955213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2281442099
Short name T821
Test name
Test status
Simulation time 4629673200 ps
CPU time 115.91 seconds
Started Sep 24 06:50:18 PM UTC 24
Finished Sep 24 06:52:17 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281442099 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.2281442099
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.2842869349
Short name T870
Test name
Test status
Simulation time 3014603500 ps
CPU time 246.4 seconds
Started Sep 24 06:50:37 PM UTC 24
Finished Sep 24 06:54:48 PM UTC 24
Peak memory 301972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842869349 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.2842869349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.654797298
Short name T868
Test name
Test status
Simulation time 12160824300 ps
CPU time 240.32 seconds
Started Sep 24 06:50:38 PM UTC 24
Finished Sep 24 06:54:43 PM UTC 24
Peak memory 305964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=654797298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 23.flash_ctrl_intr_rd_slow_flash.654797298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3483068751
Short name T180
Test name
Test status
Simulation time 71296800 ps
CPU time 168.95 seconds
Started Sep 24 06:50:37 PM UTC 24
Finished Sep 24 06:53:29 PM UTC 24
Peak memory 273248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483068751 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.3483068751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.2557103281
Short name T799
Test name
Test status
Simulation time 19975200 ps
CPU time 17.61 seconds
Started Sep 24 06:50:43 PM UTC 24
Finished Sep 24 06:51:02 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557103281 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.2557103281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3773022964
Short name T806
Test name
Test status
Simulation time 76413600 ps
CPU time 39.32 seconds
Started Sep 24 06:50:45 PM UTC 24
Finished Sep 24 06:51:25 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773022964 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.3773022964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.2835351737
Short name T809
Test name
Test status
Simulation time 26696200 ps
CPU time 41.47 seconds
Started Sep 24 06:50:54 PM UTC 24
Finished Sep 24 06:51:37 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2835351737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c
trl_rw_evict_all_en.2835351737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.826660194
Short name T822
Test name
Test status
Simulation time 2051408700 ps
CPU time 82.27 seconds
Started Sep 24 06:50:54 PM UTC 24
Finished Sep 24 06:52:18 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826660194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.826660194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.312846276
Short name T872
Test name
Test status
Simulation time 2983546200 ps
CPU time 273.9 seconds
Started Sep 24 06:50:17 PM UTC 24
Finished Sep 24 06:54:55 PM UTC 24
Peak memory 291464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312846276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.312846276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.966780824
Short name T812
Test name
Test status
Simulation time 68588300 ps
CPU time 18.66 seconds
Started Sep 24 06:51:27 PM UTC 24
Finished Sep 24 06:51:46 PM UTC 24
Peak memory 269256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966780824 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.966780824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.730196231
Short name T816
Test name
Test status
Simulation time 16930400 ps
CPU time 28.49 seconds
Started Sep 24 06:51:25 PM UTC 24
Finished Sep 24 06:51:55 PM UTC 24
Peak memory 284812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730196231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.730196231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.1112283159
Short name T811
Test name
Test status
Simulation time 19938100 ps
CPU time 31.66 seconds
Started Sep 24 06:51:13 PM UTC 24
Finished Sep 24 06:51:46 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1112283159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_
ctrl_disable.1112283159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.4271147086
Short name T313
Test name
Test status
Simulation time 1819054800 ps
CPU time 91.49 seconds
Started Sep 24 06:50:57 PM UTC 24
Finished Sep 24 06:52:31 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271147086 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.4271147086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.19031681
Short name T841
Test name
Test status
Simulation time 5953294900 ps
CPU time 136.62 seconds
Started Sep 24 06:51:04 PM UTC 24
Finished Sep 24 06:53:23 PM UTC 24
Peak memory 303840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=19031681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.flash_ctrl_intr_rd_slow_flash.19031681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.506505332
Short name T850
Test name
Test status
Simulation time 39830500 ps
CPU time 168.62 seconds
Started Sep 24 06:51:02 PM UTC 24
Finished Sep 24 06:53:54 PM UTC 24
Peak memory 271220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506505332 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.506505332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.3688006897
Short name T808
Test name
Test status
Simulation time 34680600 ps
CPU time 24.24 seconds
Started Sep 24 06:51:08 PM UTC 24
Finished Sep 24 06:51:33 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688006897 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.3688006897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3752297121
Short name T815
Test name
Test status
Simulation time 62998200 ps
CPU time 44.65 seconds
Started Sep 24 06:51:08 PM UTC 24
Finished Sep 24 06:51:54 PM UTC 24
Peak memory 283840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752297121 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.3752297121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.2688961541
Short name T813
Test name
Test status
Simulation time 68275900 ps
CPU time 39.73 seconds
Started Sep 24 06:51:09 PM UTC 24
Finished Sep 24 06:51:50 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2688961541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_rw_evict_all_en.2688961541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.1612196883
Short name T830
Test name
Test status
Simulation time 1202716900 ps
CPU time 78.37 seconds
Started Sep 24 06:51:20 PM UTC 24
Finished Sep 24 06:52:41 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612196883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1612196883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.1761667702
Short name T859
Test name
Test status
Simulation time 28861100 ps
CPU time 195.25 seconds
Started Sep 24 06:50:55 PM UTC 24
Finished Sep 24 06:54:14 PM UTC 24
Peak memory 287372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761667702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1761667702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1143758463
Short name T825
Test name
Test status
Simulation time 182411000 ps
CPU time 26.64 seconds
Started Sep 24 06:51:56 PM UTC 24
Finished Sep 24 06:52:24 PM UTC 24
Peak memory 269320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143758463 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.1143758463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1051982465
Short name T824
Test name
Test status
Simulation time 13487500 ps
CPU time 27.68 seconds
Started Sep 24 06:51:55 PM UTC 24
Finished Sep 24 06:52:24 PM UTC 24
Peak memory 295056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051982465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1051982465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3798436946
Short name T829
Test name
Test status
Simulation time 12616300 ps
CPU time 43.88 seconds
Started Sep 24 06:51:51 PM UTC 24
Finished Sep 24 06:52:37 PM UTC 24
Peak memory 285436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3798436946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_
ctrl_disable.3798436946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.848265220
Short name T314
Test name
Test status
Simulation time 5234608400 ps
CPU time 133.39 seconds
Started Sep 24 06:51:29 PM UTC 24
Finished Sep 24 06:53:45 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848265220 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.848265220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3796249862
Short name T854
Test name
Test status
Simulation time 498546300 ps
CPU time 140.64 seconds
Started Sep 24 06:51:38 PM UTC 24
Finished Sep 24 06:54:01 PM UTC 24
Peak memory 306352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796249862 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.3796249862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.853087852
Short name T871
Test name
Test status
Simulation time 69960100 ps
CPU time 194.9 seconds
Started Sep 24 06:51:34 PM UTC 24
Finished Sep 24 06:54:52 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853087852 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.853087852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.3597920495
Short name T817
Test name
Test status
Simulation time 175990000 ps
CPU time 16.77 seconds
Started Sep 24 06:51:41 PM UTC 24
Finished Sep 24 06:51:59 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597920495 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.3597920495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.1311965666
Short name T828
Test name
Test status
Simulation time 78126800 ps
CPU time 46.41 seconds
Started Sep 24 06:51:47 PM UTC 24
Finished Sep 24 06:52:35 PM UTC 24
Peak memory 287712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311965666 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.1311965666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3698348041
Short name T827
Test name
Test status
Simulation time 46587800 ps
CPU time 42.15 seconds
Started Sep 24 06:51:47 PM UTC 24
Finished Sep 24 06:52:31 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3698348041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_rw_evict_all_en.3698348041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1398562859
Short name T845
Test name
Test status
Simulation time 624874000 ps
CPU time 102.81 seconds
Started Sep 24 06:51:53 PM UTC 24
Finished Sep 24 06:53:38 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398562859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1398562859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1504606625
Short name T846
Test name
Test status
Simulation time 29539300 ps
CPU time 129.29 seconds
Started Sep 24 06:51:28 PM UTC 24
Finished Sep 24 06:53:39 PM UTC 24
Peak memory 287568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504606625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1504606625
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.997593633
Short name T833
Test name
Test status
Simulation time 125407600 ps
CPU time 25.65 seconds
Started Sep 24 06:52:27 PM UTC 24
Finished Sep 24 06:52:54 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997593633 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.997593633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1995136251
Short name T832
Test name
Test status
Simulation time 35938700 ps
CPU time 21.29 seconds
Started Sep 24 06:52:27 PM UTC 24
Finished Sep 24 06:52:50 PM UTC 24
Peak memory 284880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995136251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1995136251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.2503883566
Short name T834
Test name
Test status
Simulation time 20585200 ps
CPU time 35.28 seconds
Started Sep 24 06:52:20 PM UTC 24
Finished Sep 24 06:52:57 PM UTC 24
Peak memory 285436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2503883566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_
ctrl_disable.2503883566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.2671193662
Short name T895
Test name
Test status
Simulation time 10018953900 ps
CPU time 214.75 seconds
Started Sep 24 06:52:10 PM UTC 24
Finished Sep 24 06:55:48 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671193662 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.2671193662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.847676490
Short name T857
Test name
Test status
Simulation time 653329500 ps
CPU time 116.56 seconds
Started Sep 24 06:52:12 PM UTC 24
Finished Sep 24 06:54:12 PM UTC 24
Peak memory 306128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847676490 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.847676490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2095824045
Short name T924
Test name
Test status
Simulation time 11995506400 ps
CPU time 303.82 seconds
Started Sep 24 06:52:13 PM UTC 24
Finished Sep 24 06:57:21 PM UTC 24
Peak memory 301800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2095824045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.flash_ctrl_intr_rd_slow_flash.2095824045
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.1981868434
Short name T904
Test name
Test status
Simulation time 298287600 ps
CPU time 241.44 seconds
Started Sep 24 06:52:11 PM UTC 24
Finished Sep 24 06:56:17 PM UTC 24
Peak memory 271332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981868434 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.1981868434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.4276217153
Short name T831
Test name
Test status
Simulation time 36861600 ps
CPU time 25.73 seconds
Started Sep 24 06:52:18 PM UTC 24
Finished Sep 24 06:52:45 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276217153 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.4276217153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.3039623879
Short name T837
Test name
Test status
Simulation time 28634500 ps
CPU time 45.66 seconds
Started Sep 24 06:52:19 PM UTC 24
Finished Sep 24 06:53:06 PM UTC 24
Peak memory 287936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039623879 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.3039623879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.176145270
Short name T839
Test name
Test status
Simulation time 80174600 ps
CPU time 57.54 seconds
Started Sep 24 06:52:19 PM UTC 24
Finished Sep 24 06:53:18 PM UTC 24
Peak memory 287604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=176145270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ct
rl_rw_evict_all_en.176145270
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1787111464
Short name T848
Test name
Test status
Simulation time 2071465600 ps
CPU time 83.03 seconds
Started Sep 24 06:52:26 PM UTC 24
Finished Sep 24 06:53:51 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787111464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1787111464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.2870091455
Short name T873
Test name
Test status
Simulation time 52989300 ps
CPU time 172.46 seconds
Started Sep 24 06:52:00 PM UTC 24
Finished Sep 24 06:54:55 PM UTC 24
Peak memory 277128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870091455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2870091455
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1443197279
Short name T843
Test name
Test status
Simulation time 73917300 ps
CPU time 27.37 seconds
Started Sep 24 06:53:01 PM UTC 24
Finished Sep 24 06:53:30 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443197279 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.1443197279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3683600082
Short name T840
Test name
Test status
Simulation time 18415300 ps
CPU time 20.56 seconds
Started Sep 24 06:53:00 PM UTC 24
Finished Sep 24 06:53:21 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683600082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3683600082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.1267746819
Short name T434
Test name
Test status
Simulation time 10602300 ps
CPU time 43.79 seconds
Started Sep 24 06:52:55 PM UTC 24
Finished Sep 24 06:53:41 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1267746819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_
ctrl_disable.1267746819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.2461602229
Short name T884
Test name
Test status
Simulation time 7144667000 ps
CPU time 163.47 seconds
Started Sep 24 06:52:32 PM UTC 24
Finished Sep 24 06:55:18 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461602229 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.2461602229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.133395724
Short name T889
Test name
Test status
Simulation time 2826932400 ps
CPU time 172.28 seconds
Started Sep 24 06:52:36 PM UTC 24
Finished Sep 24 06:55:31 PM UTC 24
Peak memory 306124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133395724 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.133395724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3919414419
Short name T887
Test name
Test status
Simulation time 29571713500 ps
CPU time 164.69 seconds
Started Sep 24 06:52:38 PM UTC 24
Finished Sep 24 06:55:26 PM UTC 24
Peak memory 303848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3919414419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.flash_ctrl_intr_rd_slow_flash.3919414419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.995827747
Short name T170
Test name
Test status
Simulation time 38909000 ps
CPU time 230.63 seconds
Started Sep 24 06:52:32 PM UTC 24
Finished Sep 24 06:56:26 PM UTC 24
Peak memory 271136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995827747 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.995827747
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2007015023
Short name T896
Test name
Test status
Simulation time 9525703000 ps
CPU time 183.43 seconds
Started Sep 24 06:52:42 PM UTC 24
Finished Sep 24 06:55:49 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007015023 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2007015023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.1512764932
Short name T842
Test name
Test status
Simulation time 42735100 ps
CPU time 35.41 seconds
Started Sep 24 06:52:46 PM UTC 24
Finished Sep 24 06:53:23 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512764932 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.1512764932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.325533556
Short name T847
Test name
Test status
Simulation time 78617100 ps
CPU time 50.58 seconds
Started Sep 24 06:52:50 PM UTC 24
Finished Sep 24 06:53:43 PM UTC 24
Peak memory 285756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=325533556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ct
rl_rw_evict_all_en.325533556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2282385023
Short name T876
Test name
Test status
Simulation time 12210583000 ps
CPU time 118.32 seconds
Started Sep 24 06:52:58 PM UTC 24
Finished Sep 24 06:54:58 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282385023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2282385023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.2699003015
Short name T851
Test name
Test status
Simulation time 32575700 ps
CPU time 83.31 seconds
Started Sep 24 06:52:29 PM UTC 24
Finished Sep 24 06:53:55 PM UTC 24
Peak memory 287368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699003015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2699003015
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.1588472116
Short name T852
Test name
Test status
Simulation time 68627700 ps
CPU time 18.04 seconds
Started Sep 24 06:53:40 PM UTC 24
Finished Sep 24 06:54:00 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588472116 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.1588472116
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.1317252980
Short name T856
Test name
Test status
Simulation time 26038800 ps
CPU time 24.28 seconds
Started Sep 24 06:53:39 PM UTC 24
Finished Sep 24 06:54:05 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317252980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1317252980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3247002684
Short name T853
Test name
Test status
Simulation time 13714300 ps
CPU time 28.82 seconds
Started Sep 24 06:53:31 PM UTC 24
Finished Sep 24 06:54:01 PM UTC 24
Peak memory 285580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3247002684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_
ctrl_disable.3247002684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.830003960
Short name T874
Test name
Test status
Simulation time 1980107800 ps
CPU time 100.62 seconds
Started Sep 24 06:53:13 PM UTC 24
Finished Sep 24 06:54:56 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830003960 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.830003960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.1601439736
Short name T894
Test name
Test status
Simulation time 2811952800 ps
CPU time 141.12 seconds
Started Sep 24 06:53:19 PM UTC 24
Finished Sep 24 06:55:43 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601439736 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.1601439736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.658211322
Short name T941
Test name
Test status
Simulation time 62940459900 ps
CPU time 278.2 seconds
Started Sep 24 06:53:23 PM UTC 24
Finished Sep 24 06:58:05 PM UTC 24
Peak memory 301804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=658211322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 28.flash_ctrl_intr_rd_slow_flash.658211322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.3756391464
Short name T900
Test name
Test status
Simulation time 40557100 ps
CPU time 170.27 seconds
Started Sep 24 06:53:14 PM UTC 24
Finished Sep 24 06:56:07 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756391464 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.3756391464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.1208377795
Short name T849
Test name
Test status
Simulation time 452217600 ps
CPU time 26.61 seconds
Started Sep 24 06:53:24 PM UTC 24
Finished Sep 24 06:53:52 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208377795 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.1208377795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.1571830066
Short name T855
Test name
Test status
Simulation time 31327700 ps
CPU time 37.67 seconds
Started Sep 24 06:53:24 PM UTC 24
Finished Sep 24 06:54:03 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571830066 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.1571830066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.1758362965
Short name T858
Test name
Test status
Simulation time 121939500 ps
CPU time 41.56 seconds
Started Sep 24 06:53:30 PM UTC 24
Finished Sep 24 06:54:13 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1758362965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c
trl_rw_evict_all_en.1758362965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.1209175700
Short name T880
Test name
Test status
Simulation time 1777044900 ps
CPU time 91.66 seconds
Started Sep 24 06:53:35 PM UTC 24
Finished Sep 24 06:55:09 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209175700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1209175700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.2036469430
Short name T950
Test name
Test status
Simulation time 30787700 ps
CPU time 313.93 seconds
Started Sep 24 06:53:07 PM UTC 24
Finished Sep 24 06:58:26 PM UTC 24
Peak memory 291460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036469430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2036469430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.2983450307
Short name T864
Test name
Test status
Simulation time 51930200 ps
CPU time 24.44 seconds
Started Sep 24 06:54:06 PM UTC 24
Finished Sep 24 06:54:32 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983450307 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.2983450307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.4170046459
Short name T863
Test name
Test status
Simulation time 16524700 ps
CPU time 25.06 seconds
Started Sep 24 06:54:04 PM UTC 24
Finished Sep 24 06:54:30 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170046459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.4170046459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.826324770
Short name T865
Test name
Test status
Simulation time 34822500 ps
CPU time 33.56 seconds
Started Sep 24 06:54:03 PM UTC 24
Finished Sep 24 06:54:38 PM UTC 24
Peak memory 285448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=826324770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_disable.826324770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.1872242060
Short name T885
Test name
Test status
Simulation time 8858748000 ps
CPU time 92.36 seconds
Started Sep 24 06:53:44 PM UTC 24
Finished Sep 24 06:55:18 PM UTC 24
Peak memory 270988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872242060 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.1872242060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.3526136884
Short name T931
Test name
Test status
Simulation time 1679366100 ps
CPU time 216.35 seconds
Started Sep 24 06:53:52 PM UTC 24
Finished Sep 24 06:57:32 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526136884 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.3526136884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1367892513
Short name T957
Test name
Test status
Simulation time 22118289500 ps
CPU time 285.55 seconds
Started Sep 24 06:53:52 PM UTC 24
Finished Sep 24 06:58:42 PM UTC 24
Peak memory 293604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1367892513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.flash_ctrl_intr_rd_slow_flash.1367892513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.646511150
Short name T918
Test name
Test status
Simulation time 147904100 ps
CPU time 200.16 seconds
Started Sep 24 06:53:46 PM UTC 24
Finished Sep 24 06:57:09 PM UTC 24
Peak memory 271544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646511150 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.646511150
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.1193360274
Short name T862
Test name
Test status
Simulation time 73843500 ps
CPU time 27.86 seconds
Started Sep 24 06:53:55 PM UTC 24
Finished Sep 24 06:54:25 PM UTC 24
Peak memory 271084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193360274 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.1193360274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.1777474665
Short name T866
Test name
Test status
Simulation time 38756600 ps
CPU time 40.85 seconds
Started Sep 24 06:53:56 PM UTC 24
Finished Sep 24 06:54:39 PM UTC 24
Peak memory 283840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777474665 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.1777474665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.1928783011
Short name T867
Test name
Test status
Simulation time 31942000 ps
CPU time 38.2 seconds
Started Sep 24 06:54:00 PM UTC 24
Finished Sep 24 06:54:40 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1928783011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_rw_evict_all_en.1928783011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.2866584452
Short name T882
Test name
Test status
Simulation time 1533961200 ps
CPU time 71.24 seconds
Started Sep 24 06:54:03 PM UTC 24
Finished Sep 24 06:55:16 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866584452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2866584452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.1698815866
Short name T878
Test name
Test status
Simulation time 49535400 ps
CPU time 81.54 seconds
Started Sep 24 06:53:42 PM UTC 24
Finished Sep 24 06:55:05 PM UTC 24
Peak memory 285320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698815866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1698815866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3645403021
Short name T463
Test name
Test status
Simulation time 38860300 ps
CPU time 27 seconds
Started Sep 24 06:00:22 PM UTC 24
Finished Sep 24 06:00:51 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645403021 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3645403021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1392459281
Short name T394
Test name
Test status
Simulation time 84941900 ps
CPU time 26.47 seconds
Started Sep 24 06:00:02 PM UTC 24
Finished Sep 24 06:00:35 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392459281 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.1392459281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2518393383
Short name T409
Test name
Test status
Simulation time 50657300 ps
CPU time 25.42 seconds
Started Sep 24 05:59:38 PM UTC 24
Finished Sep 24 06:00:05 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518393383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2518393383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.4205476346
Short name T242
Test name
Test status
Simulation time 1452851200 ps
CPU time 498.37 seconds
Started Sep 24 05:54:38 PM UTC 24
Finished Sep 24 06:03:03 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205476346 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.4205476346
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1386317934
Short name T802
Test name
Test status
Simulation time 13416717700 ps
CPU time 3295.03 seconds
Started Sep 24 05:55:36 PM UTC 24
Finished Sep 24 06:51:08 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386317934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1386317934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1238261370
Short name T520
Test name
Test status
Simulation time 340349900 ps
CPU time 1120.52 seconds
Started Sep 24 05:55:28 PM UTC 24
Finished Sep 24 06:14:22 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238261370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1238261370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2653692689
Short name T67
Test name
Test status
Simulation time 933725200 ps
CPU time 37.24 seconds
Started Sep 24 05:55:08 PM UTC 24
Finished Sep 24 05:55:46 PM UTC 24
Peak memory 273092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
53692689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc
h_code.2653692689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2814983772
Short name T357
Test name
Test status
Simulation time 1592664300 ps
CPU time 49.03 seconds
Started Sep 24 05:59:46 PM UTC 24
Finished Sep 24 06:00:36 PM UTC 24
Peak memory 273188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814983
772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f
s_sup.2814983772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.4259819609
Short name T216
Test name
Test status
Simulation time 48914286300 ps
CPU time 4045.74 seconds
Started Sep 24 05:55:12 PM UTC 24
Finished Sep 24 07:03:23 PM UTC 24
Peak memory 277816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259819609 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.4259819609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.959781890
Short name T265
Test name
Test status
Simulation time 122953300 ps
CPU time 177.78 seconds
Started Sep 24 05:54:25 PM UTC 24
Finished Sep 24 05:57:25 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959781890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.959781890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2851490673
Short name T184
Test name
Test status
Simulation time 10012725100 ps
CPU time 148.75 seconds
Started Sep 24 06:00:15 PM UTC 24
Finished Sep 24 06:02:48 PM UTC 24
Peak memory 291884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2851490673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2851490673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3257177010
Short name T268
Test name
Test status
Simulation time 15419400 ps
CPU time 22.11 seconds
Started Sep 24 06:00:10 PM UTC 24
Finished Sep 24 06:00:33 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3257177010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_hw_read_seed_err.3257177010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.3075100635
Short name T186
Test name
Test status
Simulation time 160169531700 ps
CPU time 947.91 seconds
Started Sep 24 05:54:43 PM UTC 24
Finished Sep 24 06:10:42 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075100635
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.3075100635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1426939786
Short name T294
Test name
Test status
Simulation time 3965471300 ps
CPU time 115.92 seconds
Started Sep 24 05:54:38 PM UTC 24
Finished Sep 24 05:56:36 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426939786 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.1426939786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.3834027701
Short name T489
Test name
Test status
Simulation time 4067909400 ps
CPU time 591.79 seconds
Started Sep 24 05:57:26 PM UTC 24
Finished Sep 24 06:07:26 PM UTC 24
Peak memory 345384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3834027701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr
ity.3834027701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2729617334
Short name T310
Test name
Test status
Simulation time 8532270800 ps
CPU time 260 seconds
Started Sep 24 05:57:40 PM UTC 24
Finished Sep 24 06:02:04 PM UTC 24
Peak memory 301800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2729617334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_intr_rd_slow_flash.2729617334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.3656763318
Short name T456
Test name
Test status
Simulation time 4205491500 ps
CPU time 99.08 seconds
Started Sep 24 05:57:35 PM UTC 24
Finished Sep 24 05:59:17 PM UTC 24
Peak memory 275324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656763318 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.3656763318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2522806411
Short name T297
Test name
Test status
Simulation time 23954776700 ps
CPU time 237.32 seconds
Started Sep 24 05:58:05 PM UTC 24
Finished Sep 24 06:02:07 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522806411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2522806411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.71836350
Short name T157
Test name
Test status
Simulation time 23913697100 ps
CPU time 78.7 seconds
Started Sep 24 05:55:42 PM UTC 24
Finished Sep 24 05:57:03 PM UTC 24
Peak memory 275268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71836350 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.71836350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.3212967505
Short name T273
Test name
Test status
Simulation time 46964800 ps
CPU time 24.06 seconds
Started Sep 24 06:00:08 PM UTC 24
Finished Sep 24 06:00:33 PM UTC 24
Peak memory 275292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3212967505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_lcmgr_intg.3212967505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.4163315222
Short name T86
Test name
Test status
Simulation time 32700544000 ps
CPU time 457.05 seconds
Started Sep 24 05:55:03 PM UTC 24
Finished Sep 24 06:02:47 PM UTC 24
Peak memory 283564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4163315222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_mp_regions.4163315222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.446714774
Short name T136
Test name
Test status
Simulation time 149513500 ps
CPU time 184.45 seconds
Started Sep 24 05:54:57 PM UTC 24
Finished Sep 24 05:58:05 PM UTC 24
Peak memory 271356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446714774 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.446714774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1659998129
Short name T460
Test name
Test status
Simulation time 4689158300 ps
CPU time 190.61 seconds
Started Sep 24 05:57:07 PM UTC 24
Finished Sep 24 06:00:21 PM UTC 24
Peak memory 302084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1659998129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_oversize_error.1659998129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1270706133
Short name T65
Test name
Test status
Simulation time 24994500 ps
CPU time 24.34 seconds
Started Sep 24 06:00:00 PM UTC 24
Finished Sep 24 06:00:31 PM UTC 24
Peak memory 293188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270706133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1270706133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1360333944
Short name T241
Test name
Test status
Simulation time 1456667400 ps
CPU time 472.96 seconds
Started Sep 24 05:54:27 PM UTC 24
Finished Sep 24 06:02:27 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360333944 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1360333944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.442097301
Short name T300
Test name
Test status
Simulation time 62064000 ps
CPU time 25.87 seconds
Started Sep 24 05:58:08 PM UTC 24
Finished Sep 24 05:58:35 PM UTC 24
Peak memory 271288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442097301 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.442097301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1047511104
Short name T159
Test name
Test status
Simulation time 141846500 ps
CPU time 765.09 seconds
Started Sep 24 05:54:25 PM UTC 24
Finished Sep 24 06:07:19 PM UTC 24
Peak memory 291464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047511104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1047511104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.606927269
Short name T240
Test name
Test status
Simulation time 2921582200 ps
CPU time 184.04 seconds
Started Sep 24 05:54:27 PM UTC 24
Finished Sep 24 05:57:34 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606927269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.606927269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.2932800093
Short name T158
Test name
Test status
Simulation time 63887600 ps
CPU time 46.35 seconds
Started Sep 24 05:59:01 PM UTC 24
Finished Sep 24 05:59:49 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932800093 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.2932800093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3977577110
Short name T452
Test name
Test status
Simulation time 24022100 ps
CPU time 38.49 seconds
Started Sep 24 05:56:45 PM UTC 24
Finished Sep 24 05:57:26 PM UTC 24
Peak memory 275320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3977577110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_read_word_sweep_derr.3977577110
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.496835880
Short name T450
Test name
Test status
Simulation time 76321400 ps
CPU time 32.95 seconds
Started Sep 24 05:56:10 PM UTC 24
Finished Sep 24 05:56:45 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496835880 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.496835880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.683957779
Short name T213
Test name
Test status
Simulation time 8390875400 ps
CPU time 148.17 seconds
Started Sep 24 05:55:55 PM UTC 24
Finished Sep 24 05:58:26 PM UTC 24
Peak memory 304048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=683957779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.683957779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.153880060
Short name T457
Test name
Test status
Simulation time 1012017300 ps
CPU time 156.72 seconds
Started Sep 24 05:56:56 PM UTC 24
Finished Sep 24 05:59:35 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153880060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.153880060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2168468444
Short name T458
Test name
Test status
Simulation time 738973800 ps
CPU time 190.96 seconds
Started Sep 24 05:56:32 PM UTC 24
Finished Sep 24 05:59:47 PM UTC 24
Peak memory 306176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2168468444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_ro_serr.2168468444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.3930351066
Short name T476
Test name
Test status
Simulation time 5033334600 ps
CPU time 523.58 seconds
Started Sep 24 05:56:07 PM UTC 24
Finished Sep 24 06:04:58 PM UTC 24
Peak memory 330944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930351066 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.3930351066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1683833794
Short name T462
Test name
Test status
Simulation time 3172310000 ps
CPU time 214.29 seconds
Started Sep 24 05:56:57 PM UTC 24
Finished Sep 24 06:00:34 PM UTC 24
Peak memory 296032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1683833794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_rw_derr.1683833794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2563557008
Short name T296
Test name
Test status
Simulation time 40280500 ps
CPU time 60.43 seconds
Started Sep 24 05:58:36 PM UTC 24
Finished Sep 24 05:59:38 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2563557008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw_evict_all_en.2563557008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.400315836
Short name T459
Test name
Test status
Simulation time 3667660900 ps
CPU time 199.5 seconds
Started Sep 24 05:56:36 PM UTC 24
Finished Sep 24 05:59:59 PM UTC 24
Peak memory 306176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=400315836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.400315836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1936971138
Short name T15
Test name
Test status
Simulation time 7339369700 ps
CPU time 6587.28 seconds
Started Sep 24 05:59:19 PM UTC 24
Finished Sep 24 07:50:19 PM UTC 24
Peak memory 314212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936971138 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1936971138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.4041324350
Short name T306
Test name
Test status
Simulation time 5893230500 ps
CPU time 79.48 seconds
Started Sep 24 05:59:23 PM UTC 24
Finished Sep 24 06:00:45 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041324350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.4041324350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1663318011
Short name T454
Test name
Test status
Simulation time 1737582700 ps
CPU time 79.86 seconds
Started Sep 24 05:56:44 PM UTC 24
Finished Sep 24 05:58:06 PM UTC 24
Peak memory 275388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166
3318011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser
r_address.1663318011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.83382820
Short name T453
Test name
Test status
Simulation time 626332700 ps
CPU time 60.35 seconds
Started Sep 24 05:56:37 PM UTC 24
Finished Sep 24 05:57:39 PM UTC 24
Peak memory 275464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83
382820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr
_counter.83382820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3682744448
Short name T451
Test name
Test status
Simulation time 77140400 ps
CPU time 151.42 seconds
Started Sep 24 05:54:21 PM UTC 24
Finished Sep 24 05:56:56 PM UTC 24
Peak memory 287376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682744448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3682744448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1434833700
Short name T448
Test name
Test status
Simulation time 56552100 ps
CPU time 46.45 seconds
Started Sep 24 05:54:23 PM UTC 24
Finished Sep 24 05:55:11 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434833700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1434833700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.568220539
Short name T322
Test name
Test status
Simulation time 6004794900 ps
CPU time 1449.02 seconds
Started Sep 24 05:59:36 PM UTC 24
Finished Sep 24 06:24:02 PM UTC 24
Peak memory 295628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568220539 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.568220539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3419356635
Short name T447
Test name
Test status
Simulation time 36534300 ps
CPU time 31.63 seconds
Started Sep 24 05:54:25 PM UTC 24
Finished Sep 24 05:54:58 PM UTC 24
Peak memory 272912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419356635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3419356635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1717266197
Short name T455
Test name
Test status
Simulation time 7504271500 ps
CPU time 189.64 seconds
Started Sep 24 05:55:47 PM UTC 24
Finished Sep 24 05:59:00 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1717266197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.1717266197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.714926922
Short name T877
Test name
Test status
Simulation time 99645000 ps
CPU time 19.88 seconds
Started Sep 24 06:54:41 PM UTC 24
Finished Sep 24 06:55:02 PM UTC 24
Peak memory 269064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714926922 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.714926922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.4262680126
Short name T881
Test name
Test status
Simulation time 49070000 ps
CPU time 31.39 seconds
Started Sep 24 06:54:40 PM UTC 24
Finished Sep 24 06:55:13 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262680126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.4262680126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.661004984
Short name T879
Test name
Test status
Simulation time 24819600 ps
CPU time 31.58 seconds
Started Sep 24 06:54:33 PM UTC 24
Finished Sep 24 06:55:06 PM UTC 24
Peak memory 285552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=661004984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c
trl_disable.661004984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.1649467066
Short name T886
Test name
Test status
Simulation time 1081939500 ps
CPU time 65.66 seconds
Started Sep 24 06:54:14 PM UTC 24
Finished Sep 24 06:55:22 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649467066 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.1649467066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.1305529301
Short name T969
Test name
Test status
Simulation time 6002274900 ps
CPU time 286.94 seconds
Started Sep 24 06:54:17 PM UTC 24
Finished Sep 24 06:59:09 PM UTC 24
Peak memory 293744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305529301 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.1305529301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3278659604
Short name T925
Test name
Test status
Simulation time 17191822700 ps
CPU time 181.41 seconds
Started Sep 24 06:54:18 PM UTC 24
Finished Sep 24 06:57:23 PM UTC 24
Peak memory 304044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3278659604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.flash_ctrl_intr_rd_slow_flash.3278659604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.59102197
Short name T923
Test name
Test status
Simulation time 76840200 ps
CPU time 182.31 seconds
Started Sep 24 06:54:15 PM UTC 24
Finished Sep 24 06:57:20 PM UTC 24
Peak memory 270888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59102197 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.59102197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.260257056
Short name T888
Test name
Test status
Simulation time 38259300 ps
CPU time 59.81 seconds
Started Sep 24 06:54:26 PM UTC 24
Finished Sep 24 06:55:27 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260257056 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.260257056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.231224660
Short name T883
Test name
Test status
Simulation time 39738200 ps
CPU time 45.7 seconds
Started Sep 24 06:54:31 PM UTC 24
Finished Sep 24 06:55:18 PM UTC 24
Peak memory 287708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=231224660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ct
rl_rw_evict_all_en.231224660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1827834653
Short name T905
Test name
Test status
Simulation time 2681162900 ps
CPU time 100.81 seconds
Started Sep 24 06:54:39 PM UTC 24
Finished Sep 24 06:56:22 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827834653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1827834653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.2419209001
Short name T875
Test name
Test status
Simulation time 48093000 ps
CPU time 159.94 seconds
Started Sep 24 06:54:13 PM UTC 24
Finished Sep 24 06:56:56 PM UTC 24
Peak memory 287628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419209001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2419209001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.4214982720
Short name T891
Test name
Test status
Simulation time 224078400 ps
CPU time 25.66 seconds
Started Sep 24 06:55:07 PM UTC 24
Finished Sep 24 06:55:34 PM UTC 24
Peak memory 275464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214982720 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.4214982720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.3201025298
Short name T890
Test name
Test status
Simulation time 13664000 ps
CPU time 25.44 seconds
Started Sep 24 06:55:06 PM UTC 24
Finished Sep 24 06:55:33 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201025298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3201025298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1880979865
Short name T893
Test name
Test status
Simulation time 10235700 ps
CPU time 38.56 seconds
Started Sep 24 06:55:00 PM UTC 24
Finished Sep 24 06:55:40 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1880979865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_
ctrl_disable.1880979865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.34661132
Short name T911
Test name
Test status
Simulation time 11410373000 ps
CPU time 111.5 seconds
Started Sep 24 06:54:46 PM UTC 24
Finished Sep 24 06:56:40 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34661132 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.34661132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.1673277717
Short name T961
Test name
Test status
Simulation time 7271959500 ps
CPU time 230.58 seconds
Started Sep 24 06:54:53 PM UTC 24
Finished Sep 24 06:58:47 PM UTC 24
Peak memory 301928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673277717 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.1673277717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.45809494
Short name T964
Test name
Test status
Simulation time 64483093400 ps
CPU time 239.46 seconds
Started Sep 24 06:54:56 PM UTC 24
Finished Sep 24 06:58:59 PM UTC 24
Peak memory 305964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=45809494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.flash_ctrl_intr_rd_slow_flash.45809494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.4015237106
Short name T935
Test name
Test status
Simulation time 46609700 ps
CPU time 168.85 seconds
Started Sep 24 06:54:49 PM UTC 24
Finished Sep 24 06:57:41 PM UTC 24
Peak memory 275512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015237106 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.4015237106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.996930037
Short name T892
Test name
Test status
Simulation time 65881900 ps
CPU time 39.47 seconds
Started Sep 24 06:54:56 PM UTC 24
Finished Sep 24 06:55:37 PM UTC 24
Peak memory 285852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996930037 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.996930037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.1881552359
Short name T898
Test name
Test status
Simulation time 30083900 ps
CPU time 56.89 seconds
Started Sep 24 06:54:58 PM UTC 24
Finished Sep 24 06:55:56 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1881552359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_rw_evict_all_en.1881552359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.2547569117
Short name T411
Test name
Test status
Simulation time 1674580200 ps
CPU time 60.49 seconds
Started Sep 24 06:55:03 PM UTC 24
Finished Sep 24 06:56:05 PM UTC 24
Peak memory 275280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547569117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2547569117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.172589018
Short name T914
Test name
Test status
Simulation time 30418900 ps
CPU time 127.96 seconds
Started Sep 24 06:54:43 PM UTC 24
Finished Sep 24 06:56:54 PM UTC 24
Peak memory 287564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172589018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.172589018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.1883309964
Short name T899
Test name
Test status
Simulation time 61666100 ps
CPU time 26.25 seconds
Started Sep 24 06:55:32 PM UTC 24
Finished Sep 24 06:55:59 PM UTC 24
Peak memory 269048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883309964 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.1883309964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.367447154
Short name T897
Test name
Test status
Simulation time 45865800 ps
CPU time 25.5 seconds
Started Sep 24 06:55:28 PM UTC 24
Finished Sep 24 06:55:54 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367447154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.367447154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.722649314
Short name T901
Test name
Test status
Simulation time 17203800 ps
CPU time 44.88 seconds
Started Sep 24 06:55:22 PM UTC 24
Finished Sep 24 06:56:09 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=722649314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c
trl_disable.722649314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.683514454
Short name T930
Test name
Test status
Simulation time 2168640100 ps
CPU time 134.27 seconds
Started Sep 24 06:55:12 PM UTC 24
Finished Sep 24 06:57:29 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683514454 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.683514454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.3764331340
Short name T932
Test name
Test status
Simulation time 1021280200 ps
CPU time 135.67 seconds
Started Sep 24 06:55:17 PM UTC 24
Finished Sep 24 06:57:35 PM UTC 24
Peak memory 302000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764331340 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.3764331340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.660774880
Short name T971
Test name
Test status
Simulation time 15719350600 ps
CPU time 227.79 seconds
Started Sep 24 06:55:19 PM UTC 24
Finished Sep 24 06:59:11 PM UTC 24
Peak memory 303848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=660774880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 32.flash_ctrl_intr_rd_slow_flash.660774880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2168841102
Short name T943
Test name
Test status
Simulation time 215480900 ps
CPU time 169.97 seconds
Started Sep 24 06:55:14 PM UTC 24
Finished Sep 24 06:58:06 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168841102 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.2168841102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.3095435095
Short name T902
Test name
Test status
Simulation time 53846400 ps
CPU time 51.16 seconds
Started Sep 24 06:55:19 PM UTC 24
Finished Sep 24 06:56:12 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095435095 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.3095435095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.316648426
Short name T367
Test name
Test status
Simulation time 118650700 ps
CPU time 39 seconds
Started Sep 24 06:55:19 PM UTC 24
Finished Sep 24 06:56:00 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=316648426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ct
rl_rw_evict_all_en.316648426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.1088615097
Short name T912
Test name
Test status
Simulation time 2076152900 ps
CPU time 73.85 seconds
Started Sep 24 06:55:26 PM UTC 24
Finished Sep 24 06:56:42 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088615097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1088615097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.448513810
Short name T903
Test name
Test status
Simulation time 219606000 ps
CPU time 63.04 seconds
Started Sep 24 06:55:09 PM UTC 24
Finished Sep 24 06:56:14 PM UTC 24
Peak memory 285324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448513810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.448513810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.3734412398
Short name T908
Test name
Test status
Simulation time 42424900 ps
CPU time 31.4 seconds
Started Sep 24 06:56:01 PM UTC 24
Finished Sep 24 06:56:34 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734412398 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.3734412398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.3257314139
Short name T907
Test name
Test status
Simulation time 14799900 ps
CPU time 24.36 seconds
Started Sep 24 06:56:00 PM UTC 24
Finished Sep 24 06:56:26 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257314139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3257314139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.958787913
Short name T909
Test name
Test status
Simulation time 92755400 ps
CPU time 36.7 seconds
Started Sep 24 06:55:56 PM UTC 24
Finished Sep 24 06:56:34 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=958787913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_disable.958787913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.3509863303
Short name T323
Test name
Test status
Simulation time 7281385700 ps
CPU time 128.12 seconds
Started Sep 24 06:55:35 PM UTC 24
Finished Sep 24 06:57:45 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509863303 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.3509863303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.766045462
Short name T953
Test name
Test status
Simulation time 749670100 ps
CPU time 174.34 seconds
Started Sep 24 06:55:40 PM UTC 24
Finished Sep 24 06:58:37 PM UTC 24
Peak memory 304080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766045462 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.766045462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4035250058
Short name T1023
Test name
Test status
Simulation time 12178709500 ps
CPU time 327.83 seconds
Started Sep 24 06:55:44 PM UTC 24
Finished Sep 24 07:01:17 PM UTC 24
Peak memory 303852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4035250058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.flash_ctrl_intr_rd_slow_flash.4035250058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.3955561713
Short name T959
Test name
Test status
Simulation time 37588800 ps
CPU time 184.01 seconds
Started Sep 24 06:55:38 PM UTC 24
Finished Sep 24 06:58:45 PM UTC 24
Peak memory 271140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955561713 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.3955561713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.3324953307
Short name T910
Test name
Test status
Simulation time 28658500 ps
CPU time 44.12 seconds
Started Sep 24 06:55:50 PM UTC 24
Finished Sep 24 06:56:36 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324953307 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.3324953307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.3470622730
Short name T913
Test name
Test status
Simulation time 73547800 ps
CPU time 55.76 seconds
Started Sep 24 06:55:51 PM UTC 24
Finished Sep 24 06:56:48 PM UTC 24
Peak memory 287840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3470622730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_rw_evict_all_en.3470622730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1979547801
Short name T440
Test name
Test status
Simulation time 1265337200 ps
CPU time 65.78 seconds
Started Sep 24 06:55:57 PM UTC 24
Finished Sep 24 06:57:04 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979547801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1979547801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3274515984
Short name T922
Test name
Test status
Simulation time 47171700 ps
CPU time 98.83 seconds
Started Sep 24 06:55:34 PM UTC 24
Finished Sep 24 06:57:15 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274515984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3274515984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2018671154
Short name T783
Test name
Test status
Simulation time 101512500 ps
CPU time 24.74 seconds
Started Sep 24 06:56:34 PM UTC 24
Finished Sep 24 06:57:00 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018671154 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.2018671154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.1158766057
Short name T915
Test name
Test status
Simulation time 18983300 ps
CPU time 27.4 seconds
Started Sep 24 06:56:27 PM UTC 24
Finished Sep 24 06:56:56 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158766057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1158766057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.1051400041
Short name T917
Test name
Test status
Simulation time 10848100 ps
CPU time 36.49 seconds
Started Sep 24 06:56:25 PM UTC 24
Finished Sep 24 06:57:03 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1051400041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_
ctrl_disable.1051400041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.1982091259
Short name T972
Test name
Test status
Simulation time 17116437600 ps
CPU time 179.2 seconds
Started Sep 24 06:56:08 PM UTC 24
Finished Sep 24 06:59:11 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982091259 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.1982091259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.1961923108
Short name T978
Test name
Test status
Simulation time 2728364000 ps
CPU time 186.53 seconds
Started Sep 24 06:56:12 PM UTC 24
Finished Sep 24 06:59:22 PM UTC 24
Peak memory 304048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961923108 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.1961923108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3925484425
Short name T1020
Test name
Test status
Simulation time 24327910900 ps
CPU time 287.78 seconds
Started Sep 24 06:56:15 PM UTC 24
Finished Sep 24 07:01:07 PM UTC 24
Peak memory 303872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3925484425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.flash_ctrl_intr_rd_slow_flash.3925484425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.3153567700
Short name T984
Test name
Test status
Simulation time 140974300 ps
CPU time 212.19 seconds
Started Sep 24 06:56:09 PM UTC 24
Finished Sep 24 06:59:45 PM UTC 24
Peak memory 274980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153567700 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.3153567700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.3362216461
Short name T916
Test name
Test status
Simulation time 44447600 ps
CPU time 43.54 seconds
Started Sep 24 06:56:18 PM UTC 24
Finished Sep 24 06:57:03 PM UTC 24
Peak memory 283512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362216461 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.3362216461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1221134343
Short name T927
Test name
Test status
Simulation time 410506500 ps
CPU time 57.27 seconds
Started Sep 24 06:56:26 PM UTC 24
Finished Sep 24 06:57:25 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221134343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1221134343
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.3993322197
Short name T926
Test name
Test status
Simulation time 27147000 ps
CPU time 74.93 seconds
Started Sep 24 06:56:06 PM UTC 24
Finished Sep 24 06:57:23 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993322197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3993322197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.909638662
Short name T928
Test name
Test status
Simulation time 78405700 ps
CPU time 21.55 seconds
Started Sep 24 06:57:04 PM UTC 24
Finished Sep 24 06:57:27 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909638662 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.909638662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.3947479327
Short name T929
Test name
Test status
Simulation time 17317000 ps
CPU time 22 seconds
Started Sep 24 06:57:04 PM UTC 24
Finished Sep 24 06:57:27 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947479327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3947479327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.1477565311
Short name T934
Test name
Test status
Simulation time 20723400 ps
CPU time 41.13 seconds
Started Sep 24 06:56:57 PM UTC 24
Finished Sep 24 06:57:40 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1477565311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_
ctrl_disable.1477565311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.4164300372
Short name T951
Test name
Test status
Simulation time 3953507200 ps
CPU time 116.24 seconds
Started Sep 24 06:56:37 PM UTC 24
Finished Sep 24 06:58:35 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164300372 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.4164300372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.2104609461
Short name T970
Test name
Test status
Simulation time 529747200 ps
CPU time 144.11 seconds
Started Sep 24 06:56:43 PM UTC 24
Finished Sep 24 06:59:10 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104609461 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.2104609461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2480800308
Short name T113
Test name
Test status
Simulation time 12713068700 ps
CPU time 329.73 seconds
Started Sep 24 06:56:49 PM UTC 24
Finished Sep 24 07:02:24 PM UTC 24
Peak memory 304108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2480800308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.flash_ctrl_intr_rd_slow_flash.2480800308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.231872980
Short name T983
Test name
Test status
Simulation time 38002000 ps
CPU time 181.15 seconds
Started Sep 24 06:56:41 PM UTC 24
Finished Sep 24 06:59:45 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231872980 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.231872980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.2930044409
Short name T936
Test name
Test status
Simulation time 128280400 ps
CPU time 45.13 seconds
Started Sep 24 06:56:55 PM UTC 24
Finished Sep 24 06:57:42 PM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930044409 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.2930044409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3236056629
Short name T933
Test name
Test status
Simulation time 100313600 ps
CPU time 42.04 seconds
Started Sep 24 06:56:56 PM UTC 24
Finished Sep 24 06:57:40 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3236056629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_rw_evict_all_en.3236056629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.777652620
Short name T441
Test name
Test status
Simulation time 638562300 ps
CPU time 70.7 seconds
Started Sep 24 06:57:02 PM UTC 24
Finished Sep 24 06:58:14 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777652620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.777652620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.1859094271
Short name T962
Test name
Test status
Simulation time 62924400 ps
CPU time 131.73 seconds
Started Sep 24 06:56:35 PM UTC 24
Finished Sep 24 06:58:49 PM UTC 24
Peak memory 287372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859094271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1859094271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.979660985
Short name T937
Test name
Test status
Simulation time 117709200 ps
CPU time 17.73 seconds
Started Sep 24 06:57:26 PM UTC 24
Finished Sep 24 06:57:45 PM UTC 24
Peak memory 269244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979660985 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.979660985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.1878799300
Short name T939
Test name
Test status
Simulation time 49785000 ps
CPU time 32.08 seconds
Started Sep 24 06:57:24 PM UTC 24
Finished Sep 24 06:57:58 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878799300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1878799300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.1401142525
Short name T938
Test name
Test status
Simulation time 10376700 ps
CPU time 32.68 seconds
Started Sep 24 06:57:22 PM UTC 24
Finished Sep 24 06:57:56 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1401142525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_
ctrl_disable.1401142525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.772405313
Short name T1021
Test name
Test status
Simulation time 3318040300 ps
CPU time 239.98 seconds
Started Sep 24 06:57:10 PM UTC 24
Finished Sep 24 07:01:14 PM UTC 24
Peak memory 273228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772405313 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.772405313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.222901818
Short name T1009
Test name
Test status
Simulation time 3456130600 ps
CPU time 204.77 seconds
Started Sep 24 06:57:14 PM UTC 24
Finished Sep 24 07:00:42 PM UTC 24
Peak memory 301960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222901818 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.222901818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.205233468
Short name T997
Test name
Test status
Simulation time 22963083800 ps
CPU time 177.15 seconds
Started Sep 24 06:57:15 PM UTC 24
Finished Sep 24 07:00:15 PM UTC 24
Peak memory 302060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=205233468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.flash_ctrl_intr_rd_slow_flash.205233468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.243012523
Short name T1000
Test name
Test status
Simulation time 137372700 ps
CPU time 184.47 seconds
Started Sep 24 06:57:11 PM UTC 24
Finished Sep 24 07:00:19 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243012523 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.243012523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.1147479650
Short name T940
Test name
Test status
Simulation time 74079900 ps
CPU time 40.82 seconds
Started Sep 24 06:57:16 PM UTC 24
Finished Sep 24 06:57:58 PM UTC 24
Peak memory 287712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147479650 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.1147479650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.4040963090
Short name T942
Test name
Test status
Simulation time 70483500 ps
CPU time 41.81 seconds
Started Sep 24 06:57:22 PM UTC 24
Finished Sep 24 06:58:05 PM UTC 24
Peak memory 285920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4040963090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c
trl_rw_evict_all_en.4040963090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.3795185658
Short name T960
Test name
Test status
Simulation time 4372375400 ps
CPU time 80.43 seconds
Started Sep 24 06:57:24 PM UTC 24
Finished Sep 24 06:58:46 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795185658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3795185658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.2738340058
Short name T1032
Test name
Test status
Simulation time 26578300 ps
CPU time 262.02 seconds
Started Sep 24 06:57:05 PM UTC 24
Finished Sep 24 07:01:31 PM UTC 24
Peak memory 291456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738340058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2738340058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1483093059
Short name T944
Test name
Test status
Simulation time 53406700 ps
CPU time 22.54 seconds
Started Sep 24 06:57:46 PM UTC 24
Finished Sep 24 06:58:09 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483093059 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.1483093059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.3923123737
Short name T945
Test name
Test status
Simulation time 103270200 ps
CPU time 27.25 seconds
Started Sep 24 06:57:42 PM UTC 24
Finished Sep 24 06:58:11 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923123737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3923123737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.3530203699
Short name T947
Test name
Test status
Simulation time 25868800 ps
CPU time 38.08 seconds
Started Sep 24 06:57:41 PM UTC 24
Finished Sep 24 06:58:21 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3530203699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_
ctrl_disable.3530203699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.2231917615
Short name T324
Test name
Test status
Simulation time 13267943900 ps
CPU time 120.16 seconds
Started Sep 24 06:57:27 PM UTC 24
Finished Sep 24 06:59:30 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231917615 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.2231917615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.2308128283
Short name T1010
Test name
Test status
Simulation time 1615505200 ps
CPU time 187.76 seconds
Started Sep 24 06:57:33 PM UTC 24
Finished Sep 24 07:00:44 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308128283 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.2308128283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1506351250
Short name T1002
Test name
Test status
Simulation time 10276129600 ps
CPU time 163.45 seconds
Started Sep 24 06:57:36 PM UTC 24
Finished Sep 24 07:00:22 PM UTC 24
Peak memory 304072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1506351250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.flash_ctrl_intr_rd_slow_flash.1506351250
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.898775598
Short name T1018
Test name
Test status
Simulation time 34526300 ps
CPU time 208.92 seconds
Started Sep 24 06:57:31 PM UTC 24
Finished Sep 24 07:01:03 PM UTC 24
Peak memory 271256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898775598 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.898775598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.1275877022
Short name T948
Test name
Test status
Simulation time 65511100 ps
CPU time 42.59 seconds
Started Sep 24 06:57:37 PM UTC 24
Finished Sep 24 06:58:21 PM UTC 24
Peak memory 287808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275877022 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.1275877022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.3195021478
Short name T949
Test name
Test status
Simulation time 29924600 ps
CPU time 40 seconds
Started Sep 24 06:57:41 PM UTC 24
Finished Sep 24 06:58:23 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3195021478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c
trl_rw_evict_all_en.3195021478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.4253834858
Short name T963
Test name
Test status
Simulation time 8705264600 ps
CPU time 73.47 seconds
Started Sep 24 06:57:41 PM UTC 24
Finished Sep 24 06:58:57 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253834858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.4253834858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.634856693
Short name T965
Test name
Test status
Simulation time 66582200 ps
CPU time 90.66 seconds
Started Sep 24 06:57:27 PM UTC 24
Finished Sep 24 06:59:00 PM UTC 24
Peak memory 285324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634856693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.634856693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3987456713
Short name T954
Test name
Test status
Simulation time 30122000 ps
CPU time 19.35 seconds
Started Sep 24 06:58:18 PM UTC 24
Finished Sep 24 06:58:38 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987456713 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.3987456713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2344401845
Short name T956
Test name
Test status
Simulation time 18627400 ps
CPU time 24.4 seconds
Started Sep 24 06:58:15 PM UTC 24
Finished Sep 24 06:58:40 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344401845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2344401845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.3266376390
Short name T955
Test name
Test status
Simulation time 11189900 ps
CPU time 27.56 seconds
Started Sep 24 06:58:11 PM UTC 24
Finished Sep 24 06:58:40 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3266376390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_
ctrl_disable.3266376390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.1764023711
Short name T1031
Test name
Test status
Simulation time 4359089200 ps
CPU time 209.92 seconds
Started Sep 24 06:57:57 PM UTC 24
Finished Sep 24 07:01:31 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764023711 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.1764023711
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.2803291821
Short name T1037
Test name
Test status
Simulation time 3217587300 ps
CPU time 214.8 seconds
Started Sep 24 06:57:59 PM UTC 24
Finished Sep 24 07:01:37 PM UTC 24
Peak memory 301936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803291821 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.2803291821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3002072207
Short name T1050
Test name
Test status
Simulation time 41103576600 ps
CPU time 232.11 seconds
Started Sep 24 06:58:05 PM UTC 24
Finished Sep 24 07:02:01 PM UTC 24
Peak memory 303876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3002072207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.flash_ctrl_intr_rd_slow_flash.3002072207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.3151788804
Short name T1019
Test name
Test status
Simulation time 71326600 ps
CPU time 182.03 seconds
Started Sep 24 06:57:58 PM UTC 24
Finished Sep 24 07:01:03 PM UTC 24
Peak memory 271352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151788804 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.3151788804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.2796460068
Short name T375
Test name
Test status
Simulation time 261965400 ps
CPU time 39.82 seconds
Started Sep 24 06:58:06 PM UTC 24
Finished Sep 24 06:58:48 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796460068 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.2796460068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.1570352668
Short name T967
Test name
Test status
Simulation time 288757900 ps
CPU time 56.25 seconds
Started Sep 24 06:58:07 PM UTC 24
Finished Sep 24 06:59:05 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1570352668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c
trl_rw_evict_all_en.1570352668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.1405113707
Short name T990
Test name
Test status
Simulation time 116637700 ps
CPU time 130.54 seconds
Started Sep 24 06:57:47 PM UTC 24
Finished Sep 24 07:00:00 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405113707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1405113707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.717841978
Short name T974
Test name
Test status
Simulation time 550196300 ps
CPU time 29.88 seconds
Started Sep 24 06:58:43 PM UTC 24
Finished Sep 24 06:59:15 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717841978 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.717841978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.3668371731
Short name T966
Test name
Test status
Simulation time 15701000 ps
CPU time 18.09 seconds
Started Sep 24 06:58:41 PM UTC 24
Finished Sep 24 06:59:00 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668371731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3668371731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.2104230465
Short name T968
Test name
Test status
Simulation time 25221200 ps
CPU time 28.03 seconds
Started Sep 24 06:58:39 PM UTC 24
Finished Sep 24 06:59:08 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2104230465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_
ctrl_disable.2104230465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.890629750
Short name T982
Test name
Test status
Simulation time 3349632000 ps
CPU time 79.67 seconds
Started Sep 24 06:58:22 PM UTC 24
Finished Sep 24 06:59:44 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890629750 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.890629750
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.1881547335
Short name T1011
Test name
Test status
Simulation time 8263334300 ps
CPU time 135.23 seconds
Started Sep 24 06:58:26 PM UTC 24
Finished Sep 24 07:00:44 PM UTC 24
Peak memory 306288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881547335 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.1881547335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3403961529
Short name T1096
Test name
Test status
Simulation time 12221930000 ps
CPU time 313.36 seconds
Started Sep 24 06:58:37 PM UTC 24
Finished Sep 24 07:03:55 PM UTC 24
Peak memory 304136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3403961529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.flash_ctrl_intr_rd_slow_flash.3403961529
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.304745983
Short name T1025
Test name
Test status
Simulation time 39017500 ps
CPU time 172.66 seconds
Started Sep 24 06:58:23 PM UTC 24
Finished Sep 24 07:01:19 PM UTC 24
Peak memory 271076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304745983 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.304745983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.2216164442
Short name T975
Test name
Test status
Simulation time 31287300 ps
CPU time 38.49 seconds
Started Sep 24 06:58:37 PM UTC 24
Finished Sep 24 06:59:16 PM UTC 24
Peak memory 287712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216164442 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.2216164442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.4093910431
Short name T977
Test name
Test status
Simulation time 26083300 ps
CPU time 39.18 seconds
Started Sep 24 06:58:39 PM UTC 24
Finished Sep 24 06:59:19 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4093910431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c
trl_rw_evict_all_en.4093910431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.195371404
Short name T992
Test name
Test status
Simulation time 587437900 ps
CPU time 79.81 seconds
Started Sep 24 06:58:40 PM UTC 24
Finished Sep 24 07:00:02 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195371404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.195371404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.1875082449
Short name T1026
Test name
Test status
Simulation time 36134600 ps
CPU time 178.32 seconds
Started Sep 24 06:58:22 PM UTC 24
Finished Sep 24 07:01:23 PM UTC 24
Peak memory 289420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875082449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1875082449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.3268274336
Short name T485
Test name
Test status
Simulation time 30802200 ps
CPU time 22.64 seconds
Started Sep 24 06:06:39 PM UTC 24
Finished Sep 24 06:07:03 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268274336 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3268274336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.510555023
Short name T483
Test name
Test status
Simulation time 71753100 ps
CPU time 16.45 seconds
Started Sep 24 06:06:20 PM UTC 24
Finished Sep 24 06:06:38 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510555023 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.510555023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.277363803
Short name T121
Test name
Test status
Simulation time 12410400 ps
CPU time 39.8 seconds
Started Sep 24 06:05:27 PM UTC 24
Finished Sep 24 06:06:08 PM UTC 24
Peak memory 285432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=277363803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_disable.277363803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2412760385
Short name T309
Test name
Test status
Simulation time 223276000 ps
CPU time 389.82 seconds
Started Sep 24 06:00:37 PM UTC 24
Finished Sep 24 06:07:12 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412760385 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2412760385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.4263405124
Short name T991
Test name
Test status
Simulation time 9331910000 ps
CPU time 3445.27 seconds
Started Sep 24 06:01:57 PM UTC 24
Finished Sep 24 07:00:00 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263405124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.4263405124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2053165005
Short name T580
Test name
Test status
Simulation time 2461004100 ps
CPU time 1468.44 seconds
Started Sep 24 06:01:47 PM UTC 24
Finished Sep 24 06:26:32 PM UTC 24
Peak memory 285400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053165005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2053165005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2961573161
Short name T58
Test name
Test status
Simulation time 901650800 ps
CPU time 32.3 seconds
Started Sep 24 06:01:22 PM UTC 24
Finished Sep 24 06:01:56 PM UTC 24
Peak memory 273352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
61573161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc
h_code.2961573161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.3927519243
Short name T262
Test name
Test status
Simulation time 325119700 ps
CPU time 60.68 seconds
Started Sep 24 06:06:08 PM UTC 24
Finished Sep 24 06:07:10 PM UTC 24
Peak memory 273216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927519
243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f
s_sup.3927519243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.3428859605
Short name T443
Test name
Test status
Simulation time 79843918100 ps
CPU time 2918.74 seconds
Started Sep 24 06:01:30 PM UTC 24
Finished Sep 24 06:50:45 PM UTC 24
Peak memory 277824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428859605 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.3428859605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3118920805
Short name T743
Test name
Test status
Simulation time 399616256100 ps
CPU time 2684.01 seconds
Started Sep 24 06:01:07 PM UTC 24
Finished Sep 24 06:46:20 PM UTC 24
Peak memory 277988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118920805 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3118920805
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1752081208
Short name T261
Test name
Test status
Simulation time 33007300 ps
CPU time 97.13 seconds
Started Sep 24 06:00:35 PM UTC 24
Finished Sep 24 06:02:14 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752081208 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1752081208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2818201198
Short name T484
Test name
Test status
Simulation time 15924300 ps
CPU time 16.54 seconds
Started Sep 24 06:06:38 PM UTC 24
Finished Sep 24 06:06:56 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2818201198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_hw_read_seed_err.2818201198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1470881039
Short name T188
Test name
Test status
Simulation time 40129508900 ps
CPU time 869.37 seconds
Started Sep 24 06:00:45 PM UTC 24
Finished Sep 24 06:15:25 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470881039
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.1470881039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1047988647
Short name T471
Test name
Test status
Simulation time 7539000900 ps
CPU time 191.21 seconds
Started Sep 24 06:00:36 PM UTC 24
Finished Sep 24 06:03:50 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047988647 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.1047988647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2978633358
Short name T528
Test name
Test status
Simulation time 8412737300 ps
CPU time 683.89 seconds
Started Sep 24 06:04:12 PM UTC 24
Finished Sep 24 06:15:45 PM UTC 24
Peak memory 349196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2978633358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr
ity.2978633358
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1693782937
Short name T308
Test name
Test status
Simulation time 2712982100 ps
CPU time 187.52 seconds
Started Sep 24 06:04:15 PM UTC 24
Finished Sep 24 06:07:26 PM UTC 24
Peak memory 301968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693782937 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.1693782937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.851971270
Short name T487
Test name
Test status
Simulation time 15318181600 ps
CPU time 137.25 seconds
Started Sep 24 06:04:51 PM UTC 24
Finished Sep 24 06:07:10 PM UTC 24
Peak memory 304140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=851971270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_rd_slow_flash.851971270
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1518206202
Short name T482
Test name
Test status
Simulation time 3683311300 ps
CPU time 88.51 seconds
Started Sep 24 06:04:49 PM UTC 24
Finished Sep 24 06:06:19 PM UTC 24
Peak memory 271184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518206202 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.1518206202
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1289387036
Short name T502
Test name
Test status
Simulation time 80443242300 ps
CPU time 345.22 seconds
Started Sep 24 06:04:59 PM UTC 24
Finished Sep 24 06:10:49 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289387036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1289387036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.2494219199
Short name T166
Test name
Test status
Simulation time 1870215500 ps
CPU time 53.51 seconds
Started Sep 24 06:02:05 PM UTC 24
Finished Sep 24 06:03:00 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494219199 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2494219199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3045499222
Short name T274
Test name
Test status
Simulation time 16046700 ps
CPU time 17.07 seconds
Started Sep 24 06:06:35 PM UTC 24
Finished Sep 24 06:06:54 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3045499222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_lcmgr_intg.3045499222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1882277932
Short name T89
Test name
Test status
Simulation time 819793700 ps
CPU time 78.41 seconds
Started Sep 24 06:02:07 PM UTC 24
Finished Sep 24 06:03:27 PM UTC 24
Peak memory 272924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882277932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1882277932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1971944437
Short name T435
Test name
Test status
Simulation time 75869500 ps
CPU time 200.01 seconds
Started Sep 24 06:00:51 PM UTC 24
Finished Sep 24 06:04:14 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971944437 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1971944437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.4222343087
Short name T488
Test name
Test status
Simulation time 6596862400 ps
CPU time 193.97 seconds
Started Sep 24 06:04:07 PM UTC 24
Finished Sep 24 06:07:24 PM UTC 24
Peak memory 292016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=4222343087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_oversize_error.4222343087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3143309305
Short name T196
Test name
Test status
Simulation time 15153200 ps
CPU time 24.38 seconds
Started Sep 24 06:06:16 PM UTC 24
Finished Sep 24 06:06:42 PM UTC 24
Peak memory 273760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143309305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3143309305
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3228734457
Short name T493
Test name
Test status
Simulation time 1913224000 ps
CPU time 540.62 seconds
Started Sep 24 06:00:35 PM UTC 24
Finished Sep 24 06:09:43 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228734457 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3228734457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.179765599
Short name T479
Test name
Test status
Simulation time 18194900 ps
CPU time 25.93 seconds
Started Sep 24 06:04:59 PM UTC 24
Finished Sep 24 06:05:26 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179765599 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.179765599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1429575300
Short name T167
Test name
Test status
Simulation time 173901300 ps
CPU time 337.14 seconds
Started Sep 24 06:00:33 PM UTC 24
Finished Sep 24 06:06:15 PM UTC 24
Peak memory 289612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429575300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1429575300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.810669283
Short name T473
Test name
Test status
Simulation time 2428900200 ps
CPU time 207.92 seconds
Started Sep 24 06:00:35 PM UTC 24
Finished Sep 24 06:04:06 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810669283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.810669283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.962515986
Short name T356
Test name
Test status
Simulation time 83442200 ps
CPU time 45.06 seconds
Started Sep 24 06:05:26 PM UTC 24
Finished Sep 24 06:06:13 PM UTC 24
Peak memory 287900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962515986 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.962515986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3803868362
Short name T474
Test name
Test status
Simulation time 18617600 ps
CPU time 41.84 seconds
Started Sep 24 06:03:28 PM UTC 24
Finished Sep 24 06:04:11 PM UTC 24
Peak memory 275316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3803868362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_derr.3803868362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3287898603
Short name T469
Test name
Test status
Simulation time 24359000 ps
CPU time 35.52 seconds
Started Sep 24 06:02:48 PM UTC 24
Finished Sep 24 06:03:25 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287898603 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.3287898603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1425695591
Short name T214
Test name
Test status
Simulation time 1167265400 ps
CPU time 139.02 seconds
Started Sep 24 06:02:28 PM UTC 24
Finished Sep 24 06:04:50 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1425695591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.1425695591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.390799489
Short name T480
Test name
Test status
Simulation time 2259578100 ps
CPU time 175.95 seconds
Started Sep 24 06:02:54 PM UTC 24
Finished Sep 24 06:05:53 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=390799489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_
ctrl_ro_serr.390799489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3157261298
Short name T497
Test name
Test status
Simulation time 6398709300 ps
CPU time 436.01 seconds
Started Sep 24 06:02:48 PM UTC 24
Finished Sep 24 06:10:10 PM UTC 24
Peak memory 330788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157261298 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.3157261298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.1541534920
Short name T486
Test name
Test status
Simulation time 2881496500 ps
CPU time 195.28 seconds
Started Sep 24 06:03:51 PM UTC 24
Finished Sep 24 06:07:10 PM UTC 24
Peak memory 295960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1541534920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_rw_derr.1541534920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.551353865
Short name T481
Test name
Test status
Simulation time 227607000 ps
CPU time 56.58 seconds
Started Sep 24 06:05:06 PM UTC 24
Finished Sep 24 06:06:04 PM UTC 24
Peak memory 281532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551353865 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.551353865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1406552365
Short name T328
Test name
Test status
Simulation time 191719500 ps
CPU time 54.67 seconds
Started Sep 24 06:05:11 PM UTC 24
Finished Sep 24 06:06:07 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1406552365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw_evict_all_en.1406552365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.1597373148
Short name T472
Test name
Test status
Simulation time 5233977100 ps
CPU time 248.31 seconds
Started Sep 24 06:03:01 PM UTC 24
Finished Sep 24 06:07:14 PM UTC 24
Peak memory 306380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1597373148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.1597373148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2110299957
Short name T404
Test name
Test status
Simulation time 1864535700 ps
CPU time 108.24 seconds
Started Sep 24 06:05:54 PM UTC 24
Finished Sep 24 06:07:45 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110299957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2110299957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1385810907
Short name T477
Test name
Test status
Simulation time 1106560700 ps
CPU time 97.48 seconds
Started Sep 24 06:03:26 PM UTC 24
Finished Sep 24 06:05:05 PM UTC 24
Peak memory 275580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138
5810907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser
r_address.1385810907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.3905901641
Short name T475
Test name
Test status
Simulation time 1707486600 ps
CPU time 101.73 seconds
Started Sep 24 06:03:03 PM UTC 24
Finished Sep 24 06:04:48 PM UTC 24
Peak memory 285676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
05901641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se
rr_counter.3905901641
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2441915882
Short name T470
Test name
Test status
Simulation time 37095800 ps
CPU time 180.03 seconds
Started Sep 24 06:00:23 PM UTC 24
Finished Sep 24 06:03:26 PM UTC 24
Peak memory 287376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441915882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2441915882
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2175284405
Short name T466
Test name
Test status
Simulation time 31077900 ps
CPU time 47.13 seconds
Started Sep 24 06:00:32 PM UTC 24
Finished Sep 24 06:01:21 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175284405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2175284405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3259631899
Short name T776
Test name
Test status
Simulation time 696451100 ps
CPU time 2593.94 seconds
Started Sep 24 06:06:06 PM UTC 24
Finished Sep 24 06:49:49 PM UTC 24
Peak memory 304552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259631899 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.3259631899
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3389158229
Short name T465
Test name
Test status
Simulation time 36388000 ps
CPU time 41.7 seconds
Started Sep 24 06:00:35 PM UTC 24
Finished Sep 24 06:01:18 PM UTC 24
Peak memory 272900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389158229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3389158229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.3205115799
Short name T478
Test name
Test status
Simulation time 15276290800 ps
CPU time 186.96 seconds
Started Sep 24 06:02:15 PM UTC 24
Finished Sep 24 06:05:25 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3205115799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.3205115799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.3241387545
Short name T976
Test name
Test status
Simulation time 33933300 ps
CPU time 20.73 seconds
Started Sep 24 06:58:57 PM UTC 24
Finished Sep 24 06:59:19 PM UTC 24
Peak memory 269064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241387545 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.3241387545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.2058446290
Short name T973
Test name
Test status
Simulation time 14242400 ps
CPU time 22.72 seconds
Started Sep 24 06:58:50 PM UTC 24
Finished Sep 24 06:59:14 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058446290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2058446290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.1610716031
Short name T979
Test name
Test status
Simulation time 29469400 ps
CPU time 36.85 seconds
Started Sep 24 06:58:48 PM UTC 24
Finished Sep 24 06:59:26 PM UTC 24
Peak memory 285436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1610716031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_
ctrl_disable.1610716031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.773878382
Short name T321
Test name
Test status
Simulation time 18285196700 ps
CPU time 154.86 seconds
Started Sep 24 06:58:46 PM UTC 24
Finished Sep 24 07:01:23 PM UTC 24
Peak memory 273224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773878382 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.773878382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.3104945373
Short name T1030
Test name
Test status
Simulation time 40215400 ps
CPU time 160.87 seconds
Started Sep 24 06:58:47 PM UTC 24
Finished Sep 24 07:01:30 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104945373 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.3104945373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.3280106968
Short name T995
Test name
Test status
Simulation time 3666369100 ps
CPU time 74.73 seconds
Started Sep 24 06:58:49 PM UTC 24
Finished Sep 24 07:00:06 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280106968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3280106968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.791970907
Short name T1098
Test name
Test status
Simulation time 37970400 ps
CPU time 309.51 seconds
Started Sep 24 06:58:46 PM UTC 24
Finished Sep 24 07:04:00 PM UTC 24
Peak memory 289420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791970907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.791970907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3954306340
Short name T981
Test name
Test status
Simulation time 50097200 ps
CPU time 20.72 seconds
Started Sep 24 06:59:11 PM UTC 24
Finished Sep 24 06:59:33 PM UTC 24
Peak memory 269048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954306340 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3954306340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.2722473214
Short name T980
Test name
Test status
Simulation time 15832700 ps
CPU time 19.74 seconds
Started Sep 24 06:59:10 PM UTC 24
Finished Sep 24 06:59:31 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722473214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2722473214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.3231205508
Short name T985
Test name
Test status
Simulation time 17787300 ps
CPU time 39.21 seconds
Started Sep 24 06:59:07 PM UTC 24
Finished Sep 24 06:59:47 PM UTC 24
Peak memory 285436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3231205508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_
ctrl_disable.3231205508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.289463906
Short name T1003
Test name
Test status
Simulation time 3319354900 ps
CPU time 80.36 seconds
Started Sep 24 06:59:02 PM UTC 24
Finished Sep 24 07:00:24 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289463906 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.289463906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.909004056
Short name T1052
Test name
Test status
Simulation time 150171600 ps
CPU time 179.51 seconds
Started Sep 24 06:59:02 PM UTC 24
Finished Sep 24 07:02:04 PM UTC 24
Peak memory 271540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909004056 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.909004056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.2887148871
Short name T1014
Test name
Test status
Simulation time 1453356100 ps
CPU time 97.56 seconds
Started Sep 24 06:59:09 PM UTC 24
Finished Sep 24 07:00:49 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887148871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2887148871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.3152028261
Short name T1024
Test name
Test status
Simulation time 29498900 ps
CPU time 133.9 seconds
Started Sep 24 06:59:00 PM UTC 24
Finished Sep 24 07:01:17 PM UTC 24
Peak memory 287376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152028261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3152028261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.2479839170
Short name T986
Test name
Test status
Simulation time 82264400 ps
CPU time 25.77 seconds
Started Sep 24 06:59:21 PM UTC 24
Finished Sep 24 06:59:48 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479839170 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.2479839170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.936558562
Short name T988
Test name
Test status
Simulation time 14156000 ps
CPU time 27.81 seconds
Started Sep 24 06:59:20 PM UTC 24
Finished Sep 24 06:59:49 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936558562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.936558562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.327916154
Short name T987
Test name
Test status
Simulation time 10228000 ps
CPU time 31.24 seconds
Started Sep 24 06:59:16 PM UTC 24
Finished Sep 24 06:59:48 PM UTC 24
Peak memory 285840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=327916154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_c
trl_disable.327916154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.3287041163
Short name T1004
Test name
Test status
Simulation time 3530683900 ps
CPU time 69.93 seconds
Started Sep 24 06:59:12 PM UTC 24
Finished Sep 24 07:00:24 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287041163 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.3287041163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.2113424032
Short name T1074
Test name
Test status
Simulation time 41392000 ps
CPU time 202.77 seconds
Started Sep 24 06:59:15 PM UTC 24
Finished Sep 24 07:02:42 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113424032 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.2113424032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.4018769974
Short name T1013
Test name
Test status
Simulation time 1107315400 ps
CPU time 86.78 seconds
Started Sep 24 06:59:18 PM UTC 24
Finished Sep 24 07:00:47 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018769974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.4018769974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3597583454
Short name T1038
Test name
Test status
Simulation time 258096100 ps
CPU time 146.06 seconds
Started Sep 24 06:59:11 PM UTC 24
Finished Sep 24 07:01:40 PM UTC 24
Peak memory 287376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597583454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3597583454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.996758903
Short name T994
Test name
Test status
Simulation time 43283900 ps
CPU time 17.9 seconds
Started Sep 24 06:59:45 PM UTC 24
Finished Sep 24 07:00:04 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996758903 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.996758903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.493394563
Short name T989
Test name
Test status
Simulation time 29502800 ps
CPU time 17.63 seconds
Started Sep 24 06:59:38 PM UTC 24
Finished Sep 24 06:59:56 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493394563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.493394563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.565946348
Short name T996
Test name
Test status
Simulation time 28394700 ps
CPU time 33.53 seconds
Started Sep 24 06:59:32 PM UTC 24
Finished Sep 24 07:00:07 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=565946348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_c
trl_disable.565946348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.300895887
Short name T1039
Test name
Test status
Simulation time 14824502900 ps
CPU time 130.83 seconds
Started Sep 24 06:59:27 PM UTC 24
Finished Sep 24 07:01:40 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300895887 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.300895887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1007481404
Short name T1056
Test name
Test status
Simulation time 78275000 ps
CPU time 153.83 seconds
Started Sep 24 06:59:31 PM UTC 24
Finished Sep 24 07:02:08 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007481404 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.1007481404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.2261601175
Short name T439
Test name
Test status
Simulation time 1573334600 ps
CPU time 93.74 seconds
Started Sep 24 06:59:33 PM UTC 24
Finished Sep 24 07:01:09 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261601175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2261601175
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.465659695
Short name T1061
Test name
Test status
Simulation time 19021400 ps
CPU time 167.47 seconds
Started Sep 24 06:59:23 PM UTC 24
Finished Sep 24 07:02:13 PM UTC 24
Peak memory 289604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465659695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.465659695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1656303821
Short name T1001
Test name
Test status
Simulation time 105122800 ps
CPU time 19.69 seconds
Started Sep 24 06:59:58 PM UTC 24
Finished Sep 24 07:00:19 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656303821 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1656303821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.566899381
Short name T999
Test name
Test status
Simulation time 47265400 ps
CPU time 25.2 seconds
Started Sep 24 06:59:50 PM UTC 24
Finished Sep 24 07:00:17 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566899381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.566899381
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.994987328
Short name T1005
Test name
Test status
Simulation time 10006200 ps
CPU time 35.48 seconds
Started Sep 24 06:59:49 PM UTC 24
Finished Sep 24 07:00:26 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=994987328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_c
trl_disable.994987328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.495849583
Short name T1058
Test name
Test status
Simulation time 5156239000 ps
CPU time 142.05 seconds
Started Sep 24 06:59:46 PM UTC 24
Finished Sep 24 07:02:11 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495849583 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.495849583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.1711622783
Short name T1062
Test name
Test status
Simulation time 84889700 ps
CPU time 146.52 seconds
Started Sep 24 06:59:48 PM UTC 24
Finished Sep 24 07:02:18 PM UTC 24
Peak memory 270884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711622783 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.1711622783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.3767190859
Short name T1016
Test name
Test status
Simulation time 420309500 ps
CPU time 67.43 seconds
Started Sep 24 06:59:49 PM UTC 24
Finished Sep 24 07:00:59 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767190859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3767190859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.1164236242
Short name T1091
Test name
Test status
Simulation time 104123400 ps
CPU time 230.47 seconds
Started Sep 24 06:59:46 PM UTC 24
Finished Sep 24 07:03:40 PM UTC 24
Peak memory 289420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164236242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1164236242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.3057616966
Short name T1006
Test name
Test status
Simulation time 88395400 ps
CPU time 22.57 seconds
Started Sep 24 07:00:08 PM UTC 24
Finished Sep 24 07:00:34 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057616966 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.3057616966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.3089452147
Short name T1008
Test name
Test status
Simulation time 27336800 ps
CPU time 31.09 seconds
Started Sep 24 07:00:07 PM UTC 24
Finished Sep 24 07:00:40 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089452147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3089452147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2778067532
Short name T1007
Test name
Test status
Simulation time 10656700 ps
CPU time 28.94 seconds
Started Sep 24 07:00:07 PM UTC 24
Finished Sep 24 07:00:38 PM UTC 24
Peak memory 285100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2778067532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_
ctrl_disable.2778067532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.3102086752
Short name T1092
Test name
Test status
Simulation time 3173857000 ps
CPU time 211.61 seconds
Started Sep 24 07:00:01 PM UTC 24
Finished Sep 24 07:03:41 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102086752 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.3102086752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.1830414456
Short name T1083
Test name
Test status
Simulation time 36852500 ps
CPU time 174.65 seconds
Started Sep 24 07:00:07 PM UTC 24
Finished Sep 24 07:03:05 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830414456 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.1830414456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.1664011036
Short name T1033
Test name
Test status
Simulation time 6908479300 ps
CPU time 83.92 seconds
Started Sep 24 07:00:07 PM UTC 24
Finished Sep 24 07:01:34 PM UTC 24
Peak memory 274700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664011036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1664011036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1824909201
Short name T1085
Test name
Test status
Simulation time 72452000 ps
CPU time 178.6 seconds
Started Sep 24 07:00:01 PM UTC 24
Finished Sep 24 07:03:08 PM UTC 24
Peak memory 289372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824909201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1824909201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.994280049
Short name T1015
Test name
Test status
Simulation time 71332600 ps
CPU time 31.75 seconds
Started Sep 24 07:00:24 PM UTC 24
Finished Sep 24 07:00:58 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994280049 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.994280049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.4262678028
Short name T1012
Test name
Test status
Simulation time 26942300 ps
CPU time 21.72 seconds
Started Sep 24 07:00:23 PM UTC 24
Finished Sep 24 07:00:46 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262678028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.4262678028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.93652602
Short name T1044
Test name
Test status
Simulation time 2083445800 ps
CPU time 93.2 seconds
Started Sep 24 07:00:17 PM UTC 24
Finished Sep 24 07:01:52 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93652602 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.93652602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.646912699
Short name T1094
Test name
Test status
Simulation time 157508000 ps
CPU time 209.74 seconds
Started Sep 24 07:00:18 PM UTC 24
Finished Sep 24 07:03:51 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646912699 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.646912699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.1103055959
Short name T1060
Test name
Test status
Simulation time 36660348600 ps
CPU time 111.46 seconds
Started Sep 24 07:00:19 PM UTC 24
Finished Sep 24 07:02:13 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103055959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1103055959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.2505546041
Short name T1076
Test name
Test status
Simulation time 47065800 ps
CPU time 147.04 seconds
Started Sep 24 07:00:16 PM UTC 24
Finished Sep 24 07:02:45 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505546041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2505546041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.2440546651
Short name T1017
Test name
Test status
Simulation time 80630400 ps
CPU time 16.58 seconds
Started Sep 24 07:00:44 PM UTC 24
Finished Sep 24 07:01:02 PM UTC 24
Peak memory 269304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440546651 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.2440546651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.336374942
Short name T1022
Test name
Test status
Simulation time 25194400 ps
CPU time 28.88 seconds
Started Sep 24 07:00:43 PM UTC 24
Finished Sep 24 07:01:14 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336374942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.336374942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.1255491603
Short name T407
Test name
Test status
Simulation time 14213800 ps
CPU time 36.56 seconds
Started Sep 24 07:00:39 PM UTC 24
Finished Sep 24 07:01:17 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1255491603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_
ctrl_disable.1255491603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.3705088018
Short name T1099
Test name
Test status
Simulation time 13626223700 ps
CPU time 215.39 seconds
Started Sep 24 07:00:28 PM UTC 24
Finished Sep 24 07:04:07 PM UTC 24
Peak memory 273032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705088018 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.3705088018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2753208820
Short name T1080
Test name
Test status
Simulation time 70763300 ps
CPU time 132.91 seconds
Started Sep 24 07:00:35 PM UTC 24
Finished Sep 24 07:02:50 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753208820 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.2753208820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.3473309855
Short name T1048
Test name
Test status
Simulation time 1072066200 ps
CPU time 76.46 seconds
Started Sep 24 07:00:41 PM UTC 24
Finished Sep 24 07:02:00 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473309855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3473309855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3571471505
Short name T1046
Test name
Test status
Simulation time 28686300 ps
CPU time 92.47 seconds
Started Sep 24 07:00:25 PM UTC 24
Finished Sep 24 07:01:59 PM UTC 24
Peak memory 277136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571471505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3571471505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.2719142588
Short name T1028
Test name
Test status
Simulation time 53675300 ps
CPU time 21.8 seconds
Started Sep 24 07:01:03 PM UTC 24
Finished Sep 24 07:01:27 PM UTC 24
Peak memory 269176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719142588 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.2719142588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.2924631276
Short name T1027
Test name
Test status
Simulation time 111491000 ps
CPU time 22.73 seconds
Started Sep 24 07:00:59 PM UTC 24
Finished Sep 24 07:01:23 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924631276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2924631276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.905337016
Short name T1029
Test name
Test status
Simulation time 28049000 ps
CPU time 37.18 seconds
Started Sep 24 07:00:49 PM UTC 24
Finished Sep 24 07:01:28 PM UTC 24
Peak memory 285576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=905337016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_c
trl_disable.905337016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.2339065703
Short name T1077
Test name
Test status
Simulation time 1361316300 ps
CPU time 117.24 seconds
Started Sep 24 07:00:47 PM UTC 24
Finished Sep 24 07:02:46 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339065703 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.2339065703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.844155385
Short name T1090
Test name
Test status
Simulation time 77764100 ps
CPU time 162.2 seconds
Started Sep 24 07:00:48 PM UTC 24
Finished Sep 24 07:03:33 PM UTC 24
Peak memory 270884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844155385 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.844155385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.2062643862
Short name T415
Test name
Test status
Simulation time 1694338700 ps
CPU time 81.81 seconds
Started Sep 24 07:00:58 PM UTC 24
Finished Sep 24 07:02:22 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062643862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2062643862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.658282474
Short name T1100
Test name
Test status
Simulation time 33559400 ps
CPU time 201.24 seconds
Started Sep 24 07:00:46 PM UTC 24
Finished Sep 24 07:04:10 PM UTC 24
Peak memory 289424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658282474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.658282474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1189946931
Short name T1041
Test name
Test status
Simulation time 81858500 ps
CPU time 30.47 seconds
Started Sep 24 07:01:14 PM UTC 24
Finished Sep 24 07:01:46 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189946931 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.1189946931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.2963645229
Short name T1034
Test name
Test status
Simulation time 54175700 ps
CPU time 19.07 seconds
Started Sep 24 07:01:14 PM UTC 24
Finished Sep 24 07:01:35 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963645229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2963645229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1231252577
Short name T1035
Test name
Test status
Simulation time 10274800 ps
CPU time 25.81 seconds
Started Sep 24 07:01:08 PM UTC 24
Finished Sep 24 07:01:35 PM UTC 24
Peak memory 285716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1231252577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_
ctrl_disable.1231252577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.1667313765
Short name T1071
Test name
Test status
Simulation time 2413854900 ps
CPU time 91.6 seconds
Started Sep 24 07:01:05 PM UTC 24
Finished Sep 24 07:02:38 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667313765 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.1667313765
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1928870891
Short name T1095
Test name
Test status
Simulation time 132540100 ps
CPU time 167.06 seconds
Started Sep 24 07:01:05 PM UTC 24
Finished Sep 24 07:03:55 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928870891 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.1928870891
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.120483876
Short name T1066
Test name
Test status
Simulation time 596003900 ps
CPU time 74.99 seconds
Started Sep 24 07:01:10 PM UTC 24
Finished Sep 24 07:02:27 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120483876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.120483876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.1689674115
Short name T1126
Test name
Test status
Simulation time 145432500 ps
CPU time 271.15 seconds
Started Sep 24 07:01:05 PM UTC 24
Finished Sep 24 07:05:40 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689674115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1689674115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2877239806
Short name T503
Test name
Test status
Simulation time 24710400 ps
CPU time 19.33 seconds
Started Sep 24 06:10:34 PM UTC 24
Finished Sep 24 06:10:54 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877239806 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2877239806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1272465710
Short name T501
Test name
Test status
Simulation time 43282900 ps
CPU time 27.61 seconds
Started Sep 24 06:10:14 PM UTC 24
Finished Sep 24 06:10:43 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272465710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1272465710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1442683096
Short name T185
Test name
Test status
Simulation time 58826500 ps
CPU time 29.67 seconds
Started Sep 24 06:10:07 PM UTC 24
Finished Sep 24 06:10:38 PM UTC 24
Peak memory 285812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1442683096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c
trl_disable.1442683096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.1182445546
Short name T946
Test name
Test status
Simulation time 19208248800 ps
CPU time 3029.17 seconds
Started Sep 24 06:07:13 PM UTC 24
Finished Sep 24 06:58:17 PM UTC 24
Peak memory 277860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182445546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.1182445546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.1848803225
Short name T599
Test name
Test status
Simulation time 1042456100 ps
CPU time 1294.12 seconds
Started Sep 24 06:07:12 PM UTC 24
Finished Sep 24 06:29:01 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848803225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1848803225
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.628605288
Short name T59
Test name
Test status
Simulation time 3753480400 ps
CPU time 35.33 seconds
Started Sep 24 06:07:11 PM UTC 24
Finished Sep 24 06:07:47 PM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62
8605288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch
_code.628605288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2426377316
Short name T187
Test name
Test status
Simulation time 10012579800 ps
CPU time 118.33 seconds
Started Sep 24 06:10:24 PM UTC 24
Finished Sep 24 06:12:24 PM UTC 24
Peak memory 324692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2426377316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2426377316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.2578715996
Short name T266
Test name
Test status
Simulation time 15506300 ps
CPU time 26.66 seconds
Started Sep 24 06:10:22 PM UTC 24
Finished Sep 24 06:10:51 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2578715996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_hw_read_seed_err.2578715996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.2830116140
Short name T556
Test name
Test status
Simulation time 60141139700 ps
CPU time 838.46 seconds
Started Sep 24 06:07:05 PM UTC 24
Finished Sep 24 06:21:14 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830116140
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.2830116140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3411188508
Short name T350
Test name
Test status
Simulation time 33260248200 ps
CPU time 225.39 seconds
Started Sep 24 06:08:43 PM UTC 24
Finished Sep 24 06:12:32 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411188508 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.3411188508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3728848672
Short name T331
Test name
Test status
Simulation time 24389165200 ps
CPU time 192.72 seconds
Started Sep 24 06:08:57 PM UTC 24
Finished Sep 24 06:12:13 PM UTC 24
Peak memory 303872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3728848672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_intr_rd_slow_flash.3728848672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.592306642
Short name T499
Test name
Test status
Simulation time 8674207300 ps
CPU time 91.24 seconds
Started Sep 24 06:08:49 PM UTC 24
Finished Sep 24 06:10:22 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592306642 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.592306642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2869539140
Short name T514
Test name
Test status
Simulation time 92944307700 ps
CPU time 225.72 seconds
Started Sep 24 06:09:16 PM UTC 24
Finished Sep 24 06:13:04 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869539140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2869539140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.2559436607
Short name T491
Test name
Test status
Simulation time 3147150600 ps
CPU time 98.66 seconds
Started Sep 24 06:07:15 PM UTC 24
Finished Sep 24 06:08:56 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559436607 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2559436607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3483054703
Short name T315
Test name
Test status
Simulation time 44505200 ps
CPU time 18.59 seconds
Started Sep 24 06:10:16 PM UTC 24
Finished Sep 24 06:10:36 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3483054703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_lcmgr_intg.3483054703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.366223906
Short name T239
Test name
Test status
Simulation time 8010036200 ps
CPU time 239.47 seconds
Started Sep 24 06:07:11 PM UTC 24
Finished Sep 24 06:11:14 PM UTC 24
Peak memory 274828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=366223906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_mp_regions.366223906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3005841545
Short name T171
Test name
Test status
Simulation time 81868900 ps
CPU time 187.99 seconds
Started Sep 24 06:07:11 PM UTC 24
Finished Sep 24 06:10:22 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005841545 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.3005841545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.3100810193
Short name T517
Test name
Test status
Simulation time 55674700 ps
CPU time 409.03 seconds
Started Sep 24 06:06:57 PM UTC 24
Finished Sep 24 06:13:51 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100810193 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3100810193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.2987295065
Short name T496
Test name
Test status
Simulation time 18066000 ps
CPU time 20.44 seconds
Started Sep 24 06:09:44 PM UTC 24
Finished Sep 24 06:10:06 PM UTC 24
Peak memory 271124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987295065 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.2987295065
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3497994657
Short name T609
Test name
Test status
Simulation time 449537000 ps
CPU time 1403.35 seconds
Started Sep 24 06:06:55 PM UTC 24
Finished Sep 24 06:30:34 PM UTC 24
Peak memory 293704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497994657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3497994657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.2799178239
Short name T505
Test name
Test status
Simulation time 87656100 ps
CPU time 61.37 seconds
Started Sep 24 06:10:06 PM UTC 24
Finished Sep 24 06:11:09 PM UTC 24
Peak memory 287612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799178239 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.2799178239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3860402454
Short name T494
Test name
Test status
Simulation time 747527200 ps
CPU time 144.44 seconds
Started Sep 24 06:07:25 PM UTC 24
Finished Sep 24 06:09:53 PM UTC 24
Peak memory 291868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3860402454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.3860402454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.14265136
Short name T498
Test name
Test status
Simulation time 638944200 ps
CPU time 146.77 seconds
Started Sep 24 06:07:46 PM UTC 24
Finished Sep 24 06:10:15 PM UTC 24
Peak memory 291836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14265136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.14265136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.4158795357
Short name T495
Test name
Test status
Simulation time 518074700 ps
CPU time 154.37 seconds
Started Sep 24 06:07:27 PM UTC 24
Finished Sep 24 06:10:05 PM UTC 24
Peak memory 306172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4158795357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_ro_serr.4158795357
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3475873678
Short name T370
Test name
Test status
Simulation time 4277796300 ps
CPU time 548.63 seconds
Started Sep 24 06:07:26 PM UTC 24
Finished Sep 24 06:16:43 PM UTC 24
Peak memory 320536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475873678 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.3475873678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3252013066
Short name T512
Test name
Test status
Simulation time 7044953700 ps
CPU time 288.03 seconds
Started Sep 24 06:07:49 PM UTC 24
Finished Sep 24 06:12:41 PM UTC 24
Peak memory 300064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3252013066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_rw_derr.3252013066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3792705790
Short name T500
Test name
Test status
Simulation time 44411500 ps
CPU time 37.76 seconds
Started Sep 24 06:09:54 PM UTC 24
Finished Sep 24 06:10:33 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792705790 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.3792705790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3389906347
Short name T504
Test name
Test status
Simulation time 179244200 ps
CPU time 54.46 seconds
Started Sep 24 06:10:05 PM UTC 24
Finished Sep 24 06:11:01 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3389906347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw_evict_all_en.3389906347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.3468966759
Short name T506
Test name
Test status
Simulation time 5698003400 ps
CPU time 221.19 seconds
Started Sep 24 06:07:39 PM UTC 24
Finished Sep 24 06:11:24 PM UTC 24
Peak memory 306168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3468966759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.3468966759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3076094918
Short name T403
Test name
Test status
Simulation time 3780133400 ps
CPU time 119.51 seconds
Started Sep 24 06:10:11 PM UTC 24
Finished Sep 24 06:12:13 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076094918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3076094918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.3092197733
Short name T492
Test name
Test status
Simulation time 177866500 ps
CPU time 150.07 seconds
Started Sep 24 06:06:43 PM UTC 24
Finished Sep 24 06:09:15 PM UTC 24
Peak memory 289412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092197733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.3092197733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.4099468291
Short name T508
Test name
Test status
Simulation time 9928508300 ps
CPU time 271.7 seconds
Started Sep 24 06:07:20 PM UTC 24
Finished Sep 24 06:11:56 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4099468291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.4099468291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.3204555323
Short name T1040
Test name
Test status
Simulation time 17223000 ps
CPU time 21.78 seconds
Started Sep 24 07:01:17 PM UTC 24
Finished Sep 24 07:01:41 PM UTC 24
Peak memory 284816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204555323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3204555323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.82534004
Short name T1093
Test name
Test status
Simulation time 79766300 ps
CPU time 147.96 seconds
Started Sep 24 07:01:17 PM UTC 24
Finished Sep 24 07:03:48 PM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82534004 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.82534004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.1848023778
Short name T1043
Test name
Test status
Simulation time 89854400 ps
CPU time 30.02 seconds
Started Sep 24 07:01:20 PM UTC 24
Finished Sep 24 07:01:51 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848023778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1848023778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.288089516
Short name T1103
Test name
Test status
Simulation time 72189500 ps
CPU time 184.36 seconds
Started Sep 24 07:01:19 PM UTC 24
Finished Sep 24 07:04:26 PM UTC 24
Peak memory 275300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288089516 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.288089516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.540378013
Short name T1042
Test name
Test status
Simulation time 42463600 ps
CPU time 25.13 seconds
Started Sep 24 07:01:24 PM UTC 24
Finished Sep 24 07:01:51 PM UTC 24
Peak memory 284812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540378013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.540378013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3047895508
Short name T1097
Test name
Test status
Simulation time 76831300 ps
CPU time 149.13 seconds
Started Sep 24 07:01:24 PM UTC 24
Finished Sep 24 07:03:56 PM UTC 24
Peak memory 271672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047895508 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.3047895508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.105342775
Short name T1051
Test name
Test status
Simulation time 13682200 ps
CPU time 32.79 seconds
Started Sep 24 07:01:27 PM UTC 24
Finished Sep 24 07:02:02 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105342775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.105342775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.763325017
Short name T1104
Test name
Test status
Simulation time 65365600 ps
CPU time 179.77 seconds
Started Sep 24 07:01:24 PM UTC 24
Finished Sep 24 07:04:28 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763325017 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.763325017
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.4167152714
Short name T1049
Test name
Test status
Simulation time 14072800 ps
CPU time 27.03 seconds
Started Sep 24 07:01:32 PM UTC 24
Finished Sep 24 07:02:00 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167152714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.4167152714
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3132562681
Short name T1108
Test name
Test status
Simulation time 38307700 ps
CPU time 186.35 seconds
Started Sep 24 07:01:28 PM UTC 24
Finished Sep 24 07:04:38 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132562681 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.3132562681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.1503063611
Short name T1047
Test name
Test status
Simulation time 45153800 ps
CPU time 24.57 seconds
Started Sep 24 07:01:33 PM UTC 24
Finished Sep 24 07:01:59 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503063611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1503063611
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1087208008
Short name T1115
Test name
Test status
Simulation time 43035200 ps
CPU time 190.89 seconds
Started Sep 24 07:01:32 PM UTC 24
Finished Sep 24 07:04:46 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087208008 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.1087208008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.2954357822
Short name T1053
Test name
Test status
Simulation time 132743800 ps
CPU time 28.23 seconds
Started Sep 24 07:01:35 PM UTC 24
Finished Sep 24 07:02:05 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954357822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2954357822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3066850153
Short name T1106
Test name
Test status
Simulation time 41059100 ps
CPU time 172.79 seconds
Started Sep 24 07:01:35 PM UTC 24
Finished Sep 24 07:04:31 PM UTC 24
Peak memory 275768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066850153 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.3066850153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.4093241776
Short name T1045
Test name
Test status
Simulation time 28549000 ps
CPU time 18.53 seconds
Started Sep 24 07:01:36 PM UTC 24
Finished Sep 24 07:01:56 PM UTC 24
Peak memory 284616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093241776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.4093241776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.3124777286
Short name T1111
Test name
Test status
Simulation time 722619400 ps
CPU time 183.28 seconds
Started Sep 24 07:01:36 PM UTC 24
Finished Sep 24 07:04:43 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124777286 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.3124777286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.3500377266
Short name T1055
Test name
Test status
Simulation time 28164100 ps
CPU time 24.02 seconds
Started Sep 24 07:01:41 PM UTC 24
Finished Sep 24 07:02:06 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500377266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3500377266
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3730981221
Short name T1116
Test name
Test status
Simulation time 72045300 ps
CPU time 187.34 seconds
Started Sep 24 07:01:38 PM UTC 24
Finished Sep 24 07:04:49 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730981221 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.3730981221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.627631457
Short name T1057
Test name
Test status
Simulation time 54134100 ps
CPU time 26.82 seconds
Started Sep 24 07:01:41 PM UTC 24
Finished Sep 24 07:02:09 PM UTC 24
Peak memory 294856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627631457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.627631457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.541829249
Short name T1109
Test name
Test status
Simulation time 81574800 ps
CPU time 177.66 seconds
Started Sep 24 07:01:41 PM UTC 24
Finished Sep 24 07:04:42 PM UTC 24
Peak memory 271200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541829249 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.541829249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4075376783
Short name T524
Test name
Test status
Simulation time 205785100 ps
CPU time 25.76 seconds
Started Sep 24 06:14:13 PM UTC 24
Finished Sep 24 06:14:40 PM UTC 24
Peak memory 269236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075376783 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4075376783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.584315368
Short name T521
Test name
Test status
Simulation time 14907300 ps
CPU time 31.07 seconds
Started Sep 24 06:13:53 PM UTC 24
Finished Sep 24 06:14:25 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584315368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.584315368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1696828755
Short name T77
Test name
Test status
Simulation time 31849700 ps
CPU time 31.36 seconds
Started Sep 24 06:13:39 PM UTC 24
Finished Sep 24 06:14:12 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1696828755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c
trl_disable.1696828755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2139555653
Short name T605
Test name
Test status
Simulation time 4377162500 ps
CPU time 1086.51 seconds
Started Sep 24 06:11:10 PM UTC 24
Finished Sep 24 06:29:28 PM UTC 24
Peak memory 285460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139555653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2139555653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.716357546
Short name T507
Test name
Test status
Simulation time 599725800 ps
CPU time 49.71 seconds
Started Sep 24 06:11:01 PM UTC 24
Finished Sep 24 06:11:53 PM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71
6357546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch
_code.716357546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.802495073
Short name T109
Test name
Test status
Simulation time 10011936300 ps
CPU time 330.81 seconds
Started Sep 24 06:14:13 PM UTC 24
Finished Sep 24 06:19:49 PM UTC 24
Peak memory 340744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=802495073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.802495073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3008975129
Short name T522
Test name
Test status
Simulation time 15319200 ps
CPU time 24.21 seconds
Started Sep 24 06:14:01 PM UTC 24
Finished Sep 24 06:14:26 PM UTC 24
Peak memory 275444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3008975129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_hw_read_seed_err.3008975129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1737454311
Short name T613
Test name
Test status
Simulation time 480322671400 ps
CPU time 1211.25 seconds
Started Sep 24 06:10:49 PM UTC 24
Finished Sep 24 06:31:15 PM UTC 24
Peak memory 275104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737454311
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.1737454311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.705144834
Short name T511
Test name
Test status
Simulation time 4209506400 ps
CPU time 112.88 seconds
Started Sep 24 06:10:44 PM UTC 24
Finished Sep 24 06:12:39 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705144834 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.705144834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2828046739
Short name T347
Test name
Test status
Simulation time 1436642500 ps
CPU time 151.45 seconds
Started Sep 24 06:12:33 PM UTC 24
Finished Sep 24 06:15:08 PM UTC 24
Peak memory 306100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828046739 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.2828046739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3004347465
Short name T533
Test name
Test status
Simulation time 12342721400 ps
CPU time 288.67 seconds
Started Sep 24 06:12:41 PM UTC 24
Finished Sep 24 06:17:34 PM UTC 24
Peak memory 303876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3004347465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_intr_rd_slow_flash.3004347465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1401885980
Short name T518
Test name
Test status
Simulation time 5392516500 ps
CPU time 75.07 seconds
Started Sep 24 06:12:40 PM UTC 24
Finished Sep 24 06:13:57 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401885980 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.1401885980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3690516612
Short name T535
Test name
Test status
Simulation time 38354938800 ps
CPU time 291.82 seconds
Started Sep 24 06:12:42 PM UTC 24
Finished Sep 24 06:17:38 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690516612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3690516612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.2908880948
Short name T510
Test name
Test status
Simulation time 1596089700 ps
CPU time 80.54 seconds
Started Sep 24 06:11:16 PM UTC 24
Finished Sep 24 06:12:39 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908880948 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2908880948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.374323421
Short name T329
Test name
Test status
Simulation time 26182000 ps
CPU time 24.11 seconds
Started Sep 24 06:13:58 PM UTC 24
Finished Sep 24 06:14:23 PM UTC 24
Peak memory 271208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=374323421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_lcmgr_intg.374323421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.2472521397
Short name T147
Test name
Test status
Simulation time 9170916500 ps
CPU time 700.05 seconds
Started Sep 24 06:10:55 PM UTC 24
Finished Sep 24 06:22:44 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2472521397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_mp_regions.2472521397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2715245397
Short name T92
Test name
Test status
Simulation time 345268900 ps
CPU time 163.13 seconds
Started Sep 24 06:10:51 PM UTC 24
Finished Sep 24 06:13:37 PM UTC 24
Peak memory 275440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715245397 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.2715245397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3869996960
Short name T529
Test name
Test status
Simulation time 336948100 ps
CPU time 334.48 seconds
Started Sep 24 06:10:43 PM UTC 24
Finished Sep 24 06:16:22 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869996960 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3869996960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1738076501
Short name T515
Test name
Test status
Simulation time 18410400 ps
CPU time 25.32 seconds
Started Sep 24 06:12:58 PM UTC 24
Finished Sep 24 06:13:25 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738076501 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.1738076501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.2395149360
Short name T513
Test name
Test status
Simulation time 37963100 ps
CPU time 135.47 seconds
Started Sep 24 06:10:39 PM UTC 24
Finished Sep 24 06:12:57 PM UTC 24
Peak memory 279180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395149360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2395149360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.1203287273
Short name T523
Test name
Test status
Simulation time 88245400 ps
CPU time 56.85 seconds
Started Sep 24 06:13:38 PM UTC 24
Finished Sep 24 06:14:37 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203287273 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.1203287273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.175610675
Short name T318
Test name
Test status
Simulation time 628635900 ps
CPU time 136.03 seconds
Started Sep 24 06:11:54 PM UTC 24
Finished Sep 24 06:14:12 PM UTC 24
Peak memory 302072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=175610675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.175610675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.1468751158
Short name T525
Test name
Test status
Simulation time 5745557300 ps
CPU time 162.52 seconds
Started Sep 24 06:12:16 PM UTC 24
Finished Sep 24 06:15:02 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468751158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1468751158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1770812655
Short name T527
Test name
Test status
Simulation time 877440400 ps
CPU time 194.19 seconds
Started Sep 24 06:12:14 PM UTC 24
Finished Sep 24 06:15:32 PM UTC 24
Peak memory 291856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1770812655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_ro_serr.1770812655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2129813034
Short name T566
Test name
Test status
Simulation time 16198711800 ps
CPU time 691.07 seconds
Started Sep 24 06:11:57 PM UTC 24
Finished Sep 24 06:23:37 PM UTC 24
Peak memory 320516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129813034 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.2129813034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.3916463550
Short name T530
Test name
Test status
Simulation time 10859113700 ps
CPU time 256.32 seconds
Started Sep 24 06:12:25 PM UTC 24
Finished Sep 24 06:16:46 PM UTC 24
Peak memory 302072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3916463550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_rw_derr.3916463550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1612607001
Short name T519
Test name
Test status
Simulation time 154477100 ps
CPU time 53.41 seconds
Started Sep 24 06:13:05 PM UTC 24
Finished Sep 24 06:14:00 PM UTC 24
Peak memory 287812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612607001 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.1612607001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.199113933
Short name T532
Test name
Test status
Simulation time 7955446400 ps
CPU time 284.89 seconds
Started Sep 24 06:12:14 PM UTC 24
Finished Sep 24 06:17:04 PM UTC 24
Peak memory 306444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=199113933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.199113933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3509174855
Short name T442
Test name
Test status
Simulation time 2641116300 ps
CPU time 86.54 seconds
Started Sep 24 06:13:41 PM UTC 24
Finished Sep 24 06:15:09 PM UTC 24
Peak memory 275352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509174855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3509174855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2145770627
Short name T509
Test name
Test status
Simulation time 96483700 ps
CPU time 96.01 seconds
Started Sep 24 06:10:37 PM UTC 24
Finished Sep 24 06:12:15 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145770627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2145770627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.2300937663
Short name T516
Test name
Test status
Simulation time 3835293700 ps
CPU time 132.56 seconds
Started Sep 24 06:11:25 PM UTC 24
Finished Sep 24 06:13:40 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2300937663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.2300937663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.4062202241
Short name T1054
Test name
Test status
Simulation time 14575800 ps
CPU time 17.4 seconds
Started Sep 24 07:01:47 PM UTC 24
Finished Sep 24 07:02:06 PM UTC 24
Peak memory 294852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062202241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.4062202241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3144865458
Short name T1110
Test name
Test status
Simulation time 75741500 ps
CPU time 176.92 seconds
Started Sep 24 07:01:42 PM UTC 24
Finished Sep 24 07:04:42 PM UTC 24
Peak memory 275512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144865458 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.3144865458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.2270366478
Short name T1059
Test name
Test status
Simulation time 25416500 ps
CPU time 18.39 seconds
Started Sep 24 07:01:53 PM UTC 24
Finished Sep 24 07:02:12 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270366478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2270366478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1490967706
Short name T1105
Test name
Test status
Simulation time 69494700 ps
CPU time 154.99 seconds
Started Sep 24 07:01:51 PM UTC 24
Finished Sep 24 07:04:29 PM UTC 24
Peak memory 274980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490967706 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.1490967706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.1035728872
Short name T1063
Test name
Test status
Simulation time 73679400 ps
CPU time 20.3 seconds
Started Sep 24 07:01:57 PM UTC 24
Finished Sep 24 07:02:18 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035728872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1035728872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1912525423
Short name T1101
Test name
Test status
Simulation time 55070100 ps
CPU time 137.87 seconds
Started Sep 24 07:01:53 PM UTC 24
Finished Sep 24 07:04:13 PM UTC 24
Peak memory 271544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912525423 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.1912525423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.4151512505
Short name T1064
Test name
Test status
Simulation time 42078000 ps
CPU time 21.79 seconds
Started Sep 24 07:02:00 PM UTC 24
Finished Sep 24 07:02:23 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151512505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.4151512505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1299968971
Short name T1117
Test name
Test status
Simulation time 42637200 ps
CPU time 179.16 seconds
Started Sep 24 07:02:00 PM UTC 24
Finished Sep 24 07:05:02 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299968971 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.1299968971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.3621136048
Short name T1065
Test name
Test status
Simulation time 38559900 ps
CPU time 22.98 seconds
Started Sep 24 07:02:01 PM UTC 24
Finished Sep 24 07:02:25 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621136048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3621136048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1411095654
Short name T1107
Test name
Test status
Simulation time 82056300 ps
CPU time 152.02 seconds
Started Sep 24 07:02:01 PM UTC 24
Finished Sep 24 07:04:36 PM UTC 24
Peak memory 271200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411095654 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.1411095654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.4130126088
Short name T1067
Test name
Test status
Simulation time 15022100 ps
CPU time 25.14 seconds
Started Sep 24 07:02:02 PM UTC 24
Finished Sep 24 07:02:29 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130126088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.4130126088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1290485627
Short name T1118
Test name
Test status
Simulation time 146826800 ps
CPU time 182.94 seconds
Started Sep 24 07:02:02 PM UTC 24
Finished Sep 24 07:05:08 PM UTC 24
Peak memory 271332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290485627 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.1290485627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.3930814269
Short name T1068
Test name
Test status
Simulation time 47615200 ps
CPU time 22.82 seconds
Started Sep 24 07:02:05 PM UTC 24
Finished Sep 24 07:02:29 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930814269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3930814269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3675928055
Short name T1114
Test name
Test status
Simulation time 79171400 ps
CPU time 157.59 seconds
Started Sep 24 07:02:05 PM UTC 24
Finished Sep 24 07:04:46 PM UTC 24
Peak memory 271608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675928055 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.3675928055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3154148767
Short name T1069
Test name
Test status
Simulation time 26222600 ps
CPU time 22.22 seconds
Started Sep 24 07:02:08 PM UTC 24
Finished Sep 24 07:02:31 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154148767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3154148767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.491404732
Short name T1113
Test name
Test status
Simulation time 41961300 ps
CPU time 155.91 seconds
Started Sep 24 07:02:07 PM UTC 24
Finished Sep 24 07:04:45 PM UTC 24
Peak memory 271348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491404732 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.491404732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3439834233
Short name T1070
Test name
Test status
Simulation time 42872600 ps
CPU time 21 seconds
Started Sep 24 07:02:10 PM UTC 24
Finished Sep 24 07:02:32 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439834233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3439834233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4228350682
Short name T1122
Test name
Test status
Simulation time 42052900 ps
CPU time 194.23 seconds
Started Sep 24 07:02:09 PM UTC 24
Finished Sep 24 07:05:27 PM UTC 24
Peak memory 275440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228350682 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.4228350682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.3865288557
Short name T1075
Test name
Test status
Simulation time 15756900 ps
CPU time 28.1 seconds
Started Sep 24 07:02:13 PM UTC 24
Finished Sep 24 07:02:43 PM UTC 24
Peak memory 294928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865288557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3865288557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3013968484
Short name T1112
Test name
Test status
Simulation time 40298300 ps
CPU time 149.1 seconds
Started Sep 24 07:02:12 PM UTC 24
Finished Sep 24 07:04:44 PM UTC 24
Peak memory 275512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013968484 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.3013968484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1864769972
Short name T546
Test name
Test status
Simulation time 173962500 ps
CPU time 22.85 seconds
Started Sep 24 06:18:43 PM UTC 24
Finished Sep 24 06:19:07 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864769972 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1864769972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1290682816
Short name T106
Test name
Test status
Simulation time 14231500 ps
CPU time 27.38 seconds
Started Sep 24 06:18:12 PM UTC 24
Finished Sep 24 06:18:42 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290682816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1290682816
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1782654776
Short name T125
Test name
Test status
Simulation time 10790700 ps
CPU time 35.07 seconds
Started Sep 24 06:18:04 PM UTC 24
Finished Sep 24 06:18:41 PM UTC 24
Peak memory 285484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1782654776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c
trl_disable.1782654776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.553439336
Short name T1102
Test name
Test status
Simulation time 4840237100 ps
CPU time 2915.2 seconds
Started Sep 24 06:15:09 PM UTC 24
Finished Sep 24 07:04:17 PM UTC 24
Peak memory 275884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553439336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.553439336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.20986414
Short name T663
Test name
Test status
Simulation time 1363538200 ps
CPU time 1312.61 seconds
Started Sep 24 06:15:03 PM UTC 24
Finished Sep 24 06:37:11 PM UTC 24
Peak memory 283344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20986414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/fla
sh_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.20986414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3755125869
Short name T526
Test name
Test status
Simulation time 1612271300 ps
CPU time 25.8 seconds
Started Sep 24 06:14:44 PM UTC 24
Finished Sep 24 06:15:11 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37
55125869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc
h_code.3755125869
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.358754576
Short name T553
Test name
Test status
Simulation time 10017865100 ps
CPU time 119.01 seconds
Started Sep 24 06:18:42 PM UTC 24
Finished Sep 24 06:20:43 PM UTC 24
Peak memory 341080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=358754576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.358754576
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1134793832
Short name T544
Test name
Test status
Simulation time 25086400 ps
CPU time 23.97 seconds
Started Sep 24 06:18:26 PM UTC 24
Finished Sep 24 06:18:52 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1134793832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_hw_read_seed_err.1134793832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1480488141
Short name T615
Test name
Test status
Simulation time 100150674400 ps
CPU time 997.86 seconds
Started Sep 24 06:14:27 PM UTC 24
Finished Sep 24 06:31:18 PM UTC 24
Peak memory 274976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480488141
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.1480488141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3677163002
Short name T538
Test name
Test status
Simulation time 2009491500 ps
CPU time 207.81 seconds
Started Sep 24 06:14:26 PM UTC 24
Finished Sep 24 06:17:58 PM UTC 24
Peak memory 273040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677163002 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.3677163002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3293896694
Short name T348
Test name
Test status
Simulation time 2937147200 ps
CPU time 197.88 seconds
Started Sep 24 06:16:58 PM UTC 24
Finished Sep 24 06:20:19 PM UTC 24
Peak memory 304052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293896694 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.3293896694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1748130907
Short name T555
Test name
Test status
Simulation time 63473305100 ps
CPU time 200.46 seconds
Started Sep 24 06:17:34 PM UTC 24
Finished Sep 24 06:20:58 PM UTC 24
Peak memory 303868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1748130907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_intr_rd_slow_flash.1748130907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2500303415
Short name T542
Test name
Test status
Simulation time 4460786900 ps
CPU time 94.93 seconds
Started Sep 24 06:17:04 PM UTC 24
Finished Sep 24 06:18:41 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500303415 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.2500303415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2350385271
Short name T558
Test name
Test status
Simulation time 22398119400 ps
CPU time 223.98 seconds
Started Sep 24 06:17:35 PM UTC 24
Finished Sep 24 06:21:23 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350385271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2350385271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2917237056
Short name T531
Test name
Test status
Simulation time 2682732500 ps
CPU time 104.82 seconds
Started Sep 24 06:15:10 PM UTC 24
Finished Sep 24 06:16:57 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917237056 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2917237056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.1662754246
Short name T543
Test name
Test status
Simulation time 45410400 ps
CPU time 24.91 seconds
Started Sep 24 06:18:24 PM UTC 24
Finished Sep 24 06:18:51 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1662754246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_lcmgr_intg.1662754246
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.267496970
Short name T146
Test name
Test status
Simulation time 12522018700 ps
CPU time 465.51 seconds
Started Sep 24 06:14:41 PM UTC 24
Finished Sep 24 06:22:33 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=267496970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_mp_regions.267496970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.4071850871
Short name T179
Test name
Test status
Simulation time 38645500 ps
CPU time 224.38 seconds
Started Sep 24 06:14:37 PM UTC 24
Finished Sep 24 06:18:26 PM UTC 24
Peak memory 271344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071850871 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.4071850871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1862221531
Short name T557
Test name
Test status
Simulation time 167463600 ps
CPU time 406.52 seconds
Started Sep 24 06:14:24 PM UTC 24
Finished Sep 24 06:21:16 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862221531 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1862221531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.885407850
Short name T539
Test name
Test status
Simulation time 35808600 ps
CPU time 29.85 seconds
Started Sep 24 06:17:40 PM UTC 24
Finished Sep 24 06:18:11 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885407850 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.885407850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1750342350
Short name T567
Test name
Test status
Simulation time 244549700 ps
CPU time 553.94 seconds
Started Sep 24 06:14:23 PM UTC 24
Finished Sep 24 06:23:45 PM UTC 24
Peak memory 291656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750342350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1750342350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1137654051
Short name T545
Test name
Test status
Simulation time 227681500 ps
CPU time 57.09 seconds
Started Sep 24 06:17:59 PM UTC 24
Finished Sep 24 06:18:58 PM UTC 24
Peak memory 287936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137654051 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.1137654051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.4061460160
Short name T534
Test name
Test status
Simulation time 1792642400 ps
CPU time 125.78 seconds
Started Sep 24 06:15:26 PM UTC 24
Finished Sep 24 06:17:35 PM UTC 24
Peak memory 302116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4061460160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.4061460160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.1393992121
Short name T550
Test name
Test status
Simulation time 2508334700 ps
CPU time 192.04 seconds
Started Sep 24 06:16:44 PM UTC 24
Finished Sep 24 06:19:59 PM UTC 24
Peak memory 291836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393992121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1393992121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.425983230
Short name T537
Test name
Test status
Simulation time 627515700 ps
CPU time 113.65 seconds
Started Sep 24 06:15:45 PM UTC 24
Finished Sep 24 06:17:41 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=425983230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_
ctrl_ro_serr.425983230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.2116699759
Short name T573
Test name
Test status
Simulation time 14206299300 ps
CPU time 568.24 seconds
Started Sep 24 06:15:32 PM UTC 24
Finished Sep 24 06:25:08 PM UTC 24
Peak memory 330948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116699759 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.2116699759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4082141632
Short name T552
Test name
Test status
Simulation time 1805960500 ps
CPU time 221.96 seconds
Started Sep 24 06:16:47 PM UTC 24
Finished Sep 24 06:20:32 PM UTC 24
Peak memory 296140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=4082141632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_rw_derr.4082141632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.377007790
Short name T541
Test name
Test status
Simulation time 39527000 ps
CPU time 40.27 seconds
Started Sep 24 06:17:42 PM UTC 24
Finished Sep 24 06:18:24 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=377007790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctr
l_rw_evict_all_en.377007790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.652974040
Short name T559
Test name
Test status
Simulation time 6083477300 ps
CPU time 329.28 seconds
Started Sep 24 06:16:23 PM UTC 24
Finished Sep 24 06:21:57 PM UTC 24
Peak memory 306176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=652974040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.652974040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.1061796758
Short name T548
Test name
Test status
Simulation time 1958616200 ps
CPU time 78.16 seconds
Started Sep 24 06:18:11 PM UTC 24
Finished Sep 24 06:19:31 PM UTC 24
Peak memory 275352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061796758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1061796758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.3165450070
Short name T540
Test name
Test status
Simulation time 24593900 ps
CPU time 225.61 seconds
Started Sep 24 06:14:22 PM UTC 24
Finished Sep 24 06:18:11 PM UTC 24
Peak memory 289404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165450070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3165450070
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.3565644114
Short name T547
Test name
Test status
Simulation time 4674499700 ps
CPU time 231.92 seconds
Started Sep 24 06:15:12 PM UTC 24
Finished Sep 24 06:19:08 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3565644114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.3565644114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.768116736
Short name T1072
Test name
Test status
Simulation time 14079200 ps
CPU time 23.63 seconds
Started Sep 24 07:02:15 PM UTC 24
Finished Sep 24 07:02:39 PM UTC 24
Peak memory 284812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768116736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.768116736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2079507650
Short name T1121
Test name
Test status
Simulation time 552243700 ps
CPU time 188.63 seconds
Started Sep 24 07:02:15 PM UTC 24
Finished Sep 24 07:05:26 PM UTC 24
Peak memory 271396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079507650 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.2079507650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.3082515454
Short name T1073
Test name
Test status
Simulation time 16062900 ps
CPU time 20.23 seconds
Started Sep 24 07:02:19 PM UTC 24
Finished Sep 24 07:02:40 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082515454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3082515454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3758492319
Short name T1119
Test name
Test status
Simulation time 105350800 ps
CPU time 175.65 seconds
Started Sep 24 07:02:19 PM UTC 24
Finished Sep 24 07:05:18 PM UTC 24
Peak memory 271140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758492319 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.3758492319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.869914228
Short name T1078
Test name
Test status
Simulation time 47878700 ps
CPU time 23.87 seconds
Started Sep 24 07:02:24 PM UTC 24
Finished Sep 24 07:02:49 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869914228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.869914228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.373611504
Short name T1123
Test name
Test status
Simulation time 42250400 ps
CPU time 180.91 seconds
Started Sep 24 07:02:23 PM UTC 24
Finished Sep 24 07:05:27 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373611504 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.373611504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.750983626
Short name T1079
Test name
Test status
Simulation time 28734000 ps
CPU time 22.55 seconds
Started Sep 24 07:02:26 PM UTC 24
Finished Sep 24 07:02:50 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750983626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.750983626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.4148219447
Short name T1127
Test name
Test status
Simulation time 143173300 ps
CPU time 198.96 seconds
Started Sep 24 07:02:24 PM UTC 24
Finished Sep 24 07:05:46 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148219447 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.4148219447
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.784533504
Short name T1081
Test name
Test status
Simulation time 41364100 ps
CPU time 23.98 seconds
Started Sep 24 07:02:30 PM UTC 24
Finished Sep 24 07:02:55 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784533504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.784533504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3527310474
Short name T1120
Test name
Test status
Simulation time 139369900 ps
CPU time 168.36 seconds
Started Sep 24 07:02:27 PM UTC 24
Finished Sep 24 07:05:19 PM UTC 24
Peak memory 270884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527310474 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.3527310474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.95895117
Short name T1082
Test name
Test status
Simulation time 45124600 ps
CPU time 28.17 seconds
Started Sep 24 07:02:32 PM UTC 24
Finished Sep 24 07:03:01 PM UTC 24
Peak memory 294856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95895117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.95895117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2571718938
Short name T1124
Test name
Test status
Simulation time 74684100 ps
CPU time 177.82 seconds
Started Sep 24 07:02:31 PM UTC 24
Finished Sep 24 07:05:32 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571718938 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.2571718938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.2608411830
Short name T1084
Test name
Test status
Simulation time 38279400 ps
CPU time 24.85 seconds
Started Sep 24 07:02:39 PM UTC 24
Finished Sep 24 07:03:05 PM UTC 24
Peak memory 284688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608411830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.2608411830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3657930383
Short name T1125
Test name
Test status
Simulation time 70726200 ps
CPU time 177.71 seconds
Started Sep 24 07:02:33 PM UTC 24
Finished Sep 24 07:05:34 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657930383 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.3657930383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.365428682
Short name T1087
Test name
Test status
Simulation time 25121000 ps
CPU time 25.72 seconds
Started Sep 24 07:02:41 PM UTC 24
Finished Sep 24 07:03:08 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365428682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.365428682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2870584351
Short name T1129
Test name
Test status
Simulation time 137406800 ps
CPU time 187.23 seconds
Started Sep 24 07:02:40 PM UTC 24
Finished Sep 24 07:05:51 PM UTC 24
Peak memory 271544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870584351 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.2870584351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.439308444
Short name T1088
Test name
Test status
Simulation time 14645700 ps
CPU time 25.31 seconds
Started Sep 24 07:02:44 PM UTC 24
Finished Sep 24 07:03:10 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439308444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.439308444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2071299833
Short name T1128
Test name
Test status
Simulation time 75122200 ps
CPU time 183.04 seconds
Started Sep 24 07:02:43 PM UTC 24
Finished Sep 24 07:05:49 PM UTC 24
Peak memory 275364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071299833 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.2071299833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.1949814904
Short name T1086
Test name
Test status
Simulation time 54137600 ps
CPU time 20.17 seconds
Started Sep 24 07:02:47 PM UTC 24
Finished Sep 24 07:03:08 PM UTC 24
Peak memory 284620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949814904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1949814904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.4214820563
Short name T429
Test name
Test status
Simulation time 168470200 ps
CPU time 169.57 seconds
Started Sep 24 07:02:46 PM UTC 24
Finished Sep 24 07:05:38 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214820563 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.4214820563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3161144689
Short name T565
Test name
Test status
Simulation time 134742900 ps
CPU time 16.73 seconds
Started Sep 24 06:23:11 PM UTC 24
Finished Sep 24 06:23:29 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161144689 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3161144689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3179496362
Short name T564
Test name
Test status
Simulation time 73523900 ps
CPU time 26.13 seconds
Started Sep 24 06:22:43 PM UTC 24
Finished Sep 24 06:23:10 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179496362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3179496362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2609158310
Short name T124
Test name
Test status
Simulation time 13066000 ps
CPU time 39.09 seconds
Started Sep 24 06:22:35 PM UTC 24
Finished Sep 24 06:23:15 PM UTC 24
Peak memory 285448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2609158310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c
trl_disable.2609158310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3078997009
Short name T1130
Test name
Test status
Simulation time 18229218900 ps
CPU time 2971.27 seconds
Started Sep 24 06:19:46 PM UTC 24
Finished Sep 24 07:09:51 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078997009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3078997009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1052712491
Short name T676
Test name
Test status
Simulation time 659675700 ps
CPU time 1133.91 seconds
Started Sep 24 06:19:32 PM UTC 24
Finished Sep 24 06:38:39 PM UTC 24
Peak memory 285400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052712491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1052712491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3777150823
Short name T549
Test name
Test status
Simulation time 142324700 ps
CPU time 35.31 seconds
Started Sep 24 06:19:08 PM UTC 24
Finished Sep 24 06:19:45 PM UTC 24
Peak memory 275336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37
77150823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc
h_code.3777150823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1714360636
Short name T267
Test name
Test status
Simulation time 67081900 ps
CPU time 23.77 seconds
Started Sep 24 06:22:53 PM UTC 24
Finished Sep 24 06:23:18 PM UTC 24
Peak memory 269256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1714360636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_hw_read_seed_err.1714360636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.433871737
Short name T635
Test name
Test status
Simulation time 80136806400 ps
CPU time 842.59 seconds
Started Sep 24 06:18:59 PM UTC 24
Finished Sep 24 06:33:12 PM UTC 24
Peak memory 274976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433871737 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.433871737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.3045102601
Short name T560
Test name
Test status
Simulation time 18266775900 ps
CPU time 181.37 seconds
Started Sep 24 06:18:53 PM UTC 24
Finished Sep 24 06:21:57 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045102601 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.3045102601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1879029771
Short name T578
Test name
Test status
Simulation time 11912519500 ps
CPU time 301.7 seconds
Started Sep 24 06:21:17 PM UTC 24
Finished Sep 24 06:26:23 PM UTC 24
Peak memory 303880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1879029771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_intr_rd_slow_flash.1879029771
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.357875932
Short name T575
Test name
Test status
Simulation time 43964455300 ps
CPU time 268.7 seconds
Started Sep 24 06:21:23 PM UTC 24
Finished Sep 24 06:25:56 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357875932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.357875932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3729602785
Short name T554
Test name
Test status
Simulation time 5264914600 ps
CPU time 63.4 seconds
Started Sep 24 06:19:50 PM UTC 24
Finished Sep 24 06:20:55 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729602785 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3729602785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3672297100
Short name T148
Test name
Test status
Simulation time 11652855000 ps
CPU time 324.32 seconds
Started Sep 24 06:19:07 PM UTC 24
Finished Sep 24 06:24:36 PM UTC 24
Peak memory 285400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3672297100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_mp_regions.3672297100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1843864330
Short name T93
Test name
Test status
Simulation time 37475400 ps
CPU time 168.15 seconds
Started Sep 24 06:19:03 PM UTC 24
Finished Sep 24 06:21:54 PM UTC 24
Peak memory 271348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843864330 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.1843864330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.852808787
Short name T582
Test name
Test status
Simulation time 136447500 ps
CPU time 471.93 seconds
Started Sep 24 06:18:52 PM UTC 24
Finished Sep 24 06:26:50 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852808787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.852808787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1231280465
Short name T90
Test name
Test status
Simulation time 39047300 ps
CPU time 24.94 seconds
Started Sep 24 06:21:55 PM UTC 24
Finished Sep 24 06:22:22 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231280465 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.1231280465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3561789001
Short name T632
Test name
Test status
Simulation time 169454300 ps
CPU time 822.21 seconds
Started Sep 24 06:18:44 PM UTC 24
Finished Sep 24 06:32:36 PM UTC 24
Peak memory 291528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561789001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3561789001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3529245202
Short name T563
Test name
Test status
Simulation time 57304700 ps
CPU time 45.29 seconds
Started Sep 24 06:22:23 PM UTC 24
Finished Sep 24 06:23:10 PM UTC 24
Peak memory 287708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529245202 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.3529245202
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.897384082
Short name T319
Test name
Test status
Simulation time 979747500 ps
CPU time 140.03 seconds
Started Sep 24 06:20:16 PM UTC 24
Finished Sep 24 06:22:39 PM UTC 24
Peak memory 302284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=897384082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.897384082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1048661434
Short name T569
Test name
Test status
Simulation time 1438950500 ps
CPU time 188.21 seconds
Started Sep 24 06:20:56 PM UTC 24
Finished Sep 24 06:24:07 PM UTC 24
Peak memory 291836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048661434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1048661434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1474196056
Short name T561
Test name
Test status
Simulation time 558634000 ps
CPU time 126.02 seconds
Started Sep 24 06:20:33 PM UTC 24
Finished Sep 24 06:22:42 PM UTC 24
Peak memory 306184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1474196056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_ro_serr.1474196056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2252233713
Short name T590
Test name
Test status
Simulation time 12189366600 ps
CPU time 420.74 seconds
Started Sep 24 06:20:20 PM UTC 24
Finished Sep 24 06:27:27 PM UTC 24
Peak memory 324652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252233713 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.2252233713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3657724887
Short name T376
Test name
Test status
Simulation time 29806900 ps
CPU time 53.26 seconds
Started Sep 24 06:21:58 PM UTC 24
Finished Sep 24 06:22:52 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657724887 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3657724887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1966922382
Short name T562
Test name
Test status
Simulation time 29374900 ps
CPU time 52.65 seconds
Started Sep 24 06:21:59 PM UTC 24
Finished Sep 24 06:22:53 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1966922382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw_evict_all_en.1966922382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.1114818408
Short name T568
Test name
Test status
Simulation time 6410638800 ps
CPU time 178.31 seconds
Started Sep 24 06:20:43 PM UTC 24
Finished Sep 24 06:23:45 PM UTC 24
Peak memory 306188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1114818408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.1114818408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2208973073
Short name T436
Test name
Test status
Simulation time 1687228600 ps
CPU time 96.28 seconds
Started Sep 24 06:22:40 PM UTC 24
Finished Sep 24 06:24:18 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208973073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2208973073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3499086740
Short name T551
Test name
Test status
Simulation time 22620200 ps
CPU time 90.84 seconds
Started Sep 24 06:18:43 PM UTC 24
Finished Sep 24 06:20:16 PM UTC 24
Peak memory 285328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499086740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3499086740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3766289429
Short name T570
Test name
Test status
Simulation time 17837024000 ps
CPU time 249.38 seconds
Started Sep 24 06:20:00 PM UTC 24
Finished Sep 24 06:24:14 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3766289429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.3766289429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2177101261
Short name T588
Test name
Test status
Simulation time 98606500 ps
CPU time 22.96 seconds
Started Sep 24 06:26:53 PM UTC 24
Finished Sep 24 06:27:17 PM UTC 24
Peak memory 269052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177101261 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2177101261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2661269279
Short name T584
Test name
Test status
Simulation time 15316800 ps
CPU time 18.81 seconds
Started Sep 24 06:26:39 PM UTC 24
Finished Sep 24 06:27:00 PM UTC 24
Peak memory 284616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661269279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2661269279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2546933966
Short name T425
Test name
Test status
Simulation time 34441500 ps
CPU time 24.97 seconds
Started Sep 24 06:26:28 PM UTC 24
Finished Sep 24 06:26:54 PM UTC 24
Peak memory 285356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2546933966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c
trl_disable.2546933966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1513770976
Short name T1131
Test name
Test status
Simulation time 36820898000 ps
CPU time 3049.31 seconds
Started Sep 24 06:23:58 PM UTC 24
Finished Sep 24 07:15:22 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513770976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1513770976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.417246480
Short name T720
Test name
Test status
Simulation time 371496700 ps
CPU time 1209.9 seconds
Started Sep 24 06:23:52 PM UTC 24
Finished Sep 24 06:44:16 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417246480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.417246480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2600654740
Short name T572
Test name
Test status
Simulation time 1897118500 ps
CPU time 34.57 seconds
Started Sep 24 06:23:45 PM UTC 24
Finished Sep 24 06:24:22 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
00654740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc
h_code.2600654740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1881202566
Short name T592
Test name
Test status
Simulation time 10028180800 ps
CPU time 62.25 seconds
Started Sep 24 06:26:51 PM UTC 24
Finished Sep 24 06:27:55 PM UTC 24
Peak memory 291664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1881202566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1881202566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1627848223
Short name T586
Test name
Test status
Simulation time 15328500 ps
CPU time 21.38 seconds
Started Sep 24 06:26:49 PM UTC 24
Finished Sep 24 06:27:11 PM UTC 24
Peak memory 275328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1627848223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_hw_read_seed_err.1627848223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.1489879345
Short name T311
Test name
Test status
Simulation time 698756400 ps
CPU time 41.48 seconds
Started Sep 24 06:23:19 PM UTC 24
Finished Sep 24 06:24:02 PM UTC 24
Peak memory 273036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489879345 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.1489879345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1109647348
Short name T351
Test name
Test status
Simulation time 1303059900 ps
CPU time 154.41 seconds
Started Sep 24 06:24:38 PM UTC 24
Finished Sep 24 06:27:15 PM UTC 24
Peak memory 302228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109647348 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.1109647348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3355648384
Short name T595
Test name
Test status
Simulation time 51447568900 ps
CPU time 192.65 seconds
Started Sep 24 06:25:10 PM UTC 24
Finished Sep 24 06:28:27 PM UTC 24
Peak memory 303872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3355648384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_intr_rd_slow_flash.3355648384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2220672717
Short name T330
Test name
Test status
Simulation time 2346283000 ps
CPU time 95.36 seconds
Started Sep 24 06:25:09 PM UTC 24
Finished Sep 24 06:26:48 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220672717 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2220672717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1369491648
Short name T316
Test name
Test status
Simulation time 72045672800 ps
CPU time 294.63 seconds
Started Sep 24 06:25:19 PM UTC 24
Finished Sep 24 06:30:18 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369491648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1369491648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.4040654632
Short name T574
Test name
Test status
Simulation time 2021879300 ps
CPU time 73.17 seconds
Started Sep 24 06:24:03 PM UTC 24
Finished Sep 24 06:25:18 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040654632 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.4040654632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.147568231
Short name T585
Test name
Test status
Simulation time 121262400 ps
CPU time 15.35 seconds
Started Sep 24 06:26:49 PM UTC 24
Finished Sep 24 06:27:05 PM UTC 24
Peak memory 275300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=147568231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_lcmgr_intg.147568231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1782821853
Short name T149
Test name
Test status
Simulation time 23530691800 ps
CPU time 277.1 seconds
Started Sep 24 06:23:45 PM UTC 24
Finished Sep 24 06:28:27 PM UTC 24
Peak memory 283376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1782821853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_mp_regions.1782821853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1920923077
Short name T327
Test name
Test status
Simulation time 147547600 ps
CPU time 525.62 seconds
Started Sep 24 06:23:16 PM UTC 24
Finished Sep 24 06:32:08 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920923077 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1920923077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3911706750
Short name T576
Test name
Test status
Simulation time 27366600 ps
CPU time 15.82 seconds
Started Sep 24 06:25:57 PM UTC 24
Finished Sep 24 06:26:14 PM UTC 24
Peak memory 271096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911706750 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.3911706750
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3384305547
Short name T604
Test name
Test status
Simulation time 73464600 ps
CPU time 368.38 seconds
Started Sep 24 06:23:13 PM UTC 24
Finished Sep 24 06:29:27 PM UTC 24
Peak memory 289416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384305547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3384305547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3434509366
Short name T354
Test name
Test status
Simulation time 271975600 ps
CPU time 40.65 seconds
Started Sep 24 06:26:24 PM UTC 24
Finished Sep 24 06:27:06 PM UTC 24
Peak memory 283584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434509366 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.3434509366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1766176926
Short name T579
Test name
Test status
Simulation time 541472600 ps
CPU time 135.97 seconds
Started Sep 24 06:24:08 PM UTC 24
Finished Sep 24 06:26:27 PM UTC 24
Peak memory 302344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1766176926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1766176926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3430506013
Short name T589
Test name
Test status
Simulation time 619784300 ps
CPU time 175.9 seconds
Started Sep 24 06:24:22 PM UTC 24
Finished Sep 24 06:27:22 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430506013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3430506013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2366557825
Short name T581
Test name
Test status
Simulation time 5624990700 ps
CPU time 145.73 seconds
Started Sep 24 06:24:19 PM UTC 24
Finished Sep 24 06:26:48 PM UTC 24
Peak memory 302288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2366557825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_ro_serr.2366557825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.506664300
Short name T649
Test name
Test status
Simulation time 22017849200 ps
CPU time 648.77 seconds
Started Sep 24 06:24:15 PM UTC 24
Finished Sep 24 06:35:12 PM UTC 24
Peak memory 330828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506664300 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.506664300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.992970446
Short name T587
Test name
Test status
Simulation time 4200409400 ps
CPU time 166.93 seconds
Started Sep 24 06:24:24 PM UTC 24
Finished Sep 24 06:27:14 PM UTC 24
Peak memory 292028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=992970446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_rw_derr.992970446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.959723924
Short name T583
Test name
Test status
Simulation time 30800400 ps
CPU time 36.05 seconds
Started Sep 24 06:26:15 PM UTC 24
Finished Sep 24 06:26:53 PM UTC 24
Peak memory 287604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959723924 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.959723924
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1219361876
Short name T591
Test name
Test status
Simulation time 14212312800 ps
CPU time 191.51 seconds
Started Sep 24 06:24:21 PM UTC 24
Finished Sep 24 06:27:36 PM UTC 24
Peak memory 302068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1219361876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.1219361876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.321201040
Short name T418
Test name
Test status
Simulation time 2505685100 ps
CPU time 81.37 seconds
Started Sep 24 06:26:33 PM UTC 24
Finished Sep 24 06:27:56 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321201040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.321201040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.1079783068
Short name T571
Test name
Test status
Simulation time 27286000 ps
CPU time 67.66 seconds
Started Sep 24 06:23:11 PM UTC 24
Finished Sep 24 06:24:20 PM UTC 24
Peak memory 285516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079783068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1079783068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.340592615
Short name T577
Test name
Test status
Simulation time 6877178100 ps
CPU time 137.07 seconds
Started Sep 24 06:24:03 PM UTC 24
Finished Sep 24 06:26:22 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=340592615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.340592615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest
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