| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.1164236242 |
|
|
Sep 24 06:59:46 PM UTC 24 |
Sep 24 07:03:40 PM UTC 24 |
104123400 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.3102086752 |
|
|
Sep 24 07:00:01 PM UTC 24 |
Sep 24 07:03:41 PM UTC 24 |
3173857000 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.82534004 |
|
|
Sep 24 07:01:17 PM UTC 24 |
Sep 24 07:03:48 PM UTC 24 |
79766300 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.646912699 |
|
|
Sep 24 07:00:18 PM UTC 24 |
Sep 24 07:03:51 PM UTC 24 |
157508000 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1928870891 |
|
|
Sep 24 07:01:05 PM UTC 24 |
Sep 24 07:03:55 PM UTC 24 |
132540100 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3403961529 |
|
|
Sep 24 06:58:37 PM UTC 24 |
Sep 24 07:03:55 PM UTC 24 |
12221930000 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3047895508 |
|
|
Sep 24 07:01:24 PM UTC 24 |
Sep 24 07:03:56 PM UTC 24 |
76831300 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.791970907 |
|
|
Sep 24 06:58:46 PM UTC 24 |
Sep 24 07:04:00 PM UTC 24 |
37970400 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.3705088018 |
|
|
Sep 24 07:00:28 PM UTC 24 |
Sep 24 07:04:07 PM UTC 24 |
13626223700 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.658282474 |
|
|
Sep 24 07:00:46 PM UTC 24 |
Sep 24 07:04:10 PM UTC 24 |
33559400 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1912525423 |
|
|
Sep 24 07:01:53 PM UTC 24 |
Sep 24 07:04:13 PM UTC 24 |
55070100 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.553439336 |
|
|
Sep 24 06:15:09 PM UTC 24 |
Sep 24 07:04:17 PM UTC 24 |
4840237100 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.288089516 |
|
|
Sep 24 07:01:19 PM UTC 24 |
Sep 24 07:04:26 PM UTC 24 |
72189500 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.763325017 |
|
|
Sep 24 07:01:24 PM UTC 24 |
Sep 24 07:04:28 PM UTC 24 |
65365600 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1490967706 |
|
|
Sep 24 07:01:51 PM UTC 24 |
Sep 24 07:04:29 PM UTC 24 |
69494700 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3066850153 |
|
|
Sep 24 07:01:35 PM UTC 24 |
Sep 24 07:04:31 PM UTC 24 |
41059100 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1411095654 |
|
|
Sep 24 07:02:01 PM UTC 24 |
Sep 24 07:04:36 PM UTC 24 |
82056300 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3132562681 |
|
|
Sep 24 07:01:28 PM UTC 24 |
Sep 24 07:04:38 PM UTC 24 |
38307700 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.541829249 |
|
|
Sep 24 07:01:41 PM UTC 24 |
Sep 24 07:04:42 PM UTC 24 |
81574800 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.3144865458 |
|
|
Sep 24 07:01:42 PM UTC 24 |
Sep 24 07:04:42 PM UTC 24 |
75741500 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.3124777286 |
|
|
Sep 24 07:01:36 PM UTC 24 |
Sep 24 07:04:43 PM UTC 24 |
722619400 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3013968484 |
|
|
Sep 24 07:02:12 PM UTC 24 |
Sep 24 07:04:44 PM UTC 24 |
40298300 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.491404732 |
|
|
Sep 24 07:02:07 PM UTC 24 |
Sep 24 07:04:45 PM UTC 24 |
41961300 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3675928055 |
|
|
Sep 24 07:02:05 PM UTC 24 |
Sep 24 07:04:46 PM UTC 24 |
79171400 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1087208008 |
|
|
Sep 24 07:01:32 PM UTC 24 |
Sep 24 07:04:46 PM UTC 24 |
43035200 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3730981221 |
|
|
Sep 24 07:01:38 PM UTC 24 |
Sep 24 07:04:49 PM UTC 24 |
72045300 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1299968971 |
|
|
Sep 24 07:02:00 PM UTC 24 |
Sep 24 07:05:02 PM UTC 24 |
42637200 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1290485627 |
|
|
Sep 24 07:02:02 PM UTC 24 |
Sep 24 07:05:08 PM UTC 24 |
146826800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3758492319 |
|
|
Sep 24 07:02:19 PM UTC 24 |
Sep 24 07:05:18 PM UTC 24 |
105350800 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3527310474 |
|
|
Sep 24 07:02:27 PM UTC 24 |
Sep 24 07:05:19 PM UTC 24 |
139369900 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2079507650 |
|
|
Sep 24 07:02:15 PM UTC 24 |
Sep 24 07:05:26 PM UTC 24 |
552243700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4228350682 |
|
|
Sep 24 07:02:09 PM UTC 24 |
Sep 24 07:05:27 PM UTC 24 |
42052900 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.373611504 |
|
|
Sep 24 07:02:23 PM UTC 24 |
Sep 24 07:05:27 PM UTC 24 |
42250400 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2571718938 |
|
|
Sep 24 07:02:31 PM UTC 24 |
Sep 24 07:05:32 PM UTC 24 |
74684100 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3657930383 |
|
|
Sep 24 07:02:33 PM UTC 24 |
Sep 24 07:05:34 PM UTC 24 |
70726200 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.4214820563 |
|
|
Sep 24 07:02:46 PM UTC 24 |
Sep 24 07:05:38 PM UTC 24 |
168470200 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.1689674115 |
|
|
Sep 24 07:01:05 PM UTC 24 |
Sep 24 07:05:40 PM UTC 24 |
145432500 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.4148219447 |
|
|
Sep 24 07:02:24 PM UTC 24 |
Sep 24 07:05:46 PM UTC 24 |
143173300 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2071299833 |
|
|
Sep 24 07:02:43 PM UTC 24 |
Sep 24 07:05:49 PM UTC 24 |
75122200 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2870584351 |
|
|
Sep 24 07:02:40 PM UTC 24 |
Sep 24 07:05:51 PM UTC 24 |
137406800 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3078997009 |
|
|
Sep 24 06:19:46 PM UTC 24 |
Sep 24 07:09:51 PM UTC 24 |
18229218900 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1513770976 |
|
|
Sep 24 06:23:58 PM UTC 24 |
Sep 24 07:15:22 PM UTC 24 |
36820898000 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.3201989184 |
|
|
Sep 24 05:47:02 PM UTC 24 |
Sep 24 07:41:43 PM UTC 24 |
6744563000 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.160713910 |
|
|
Sep 24 05:49:33 PM UTC 24 |
Sep 24 07:47:04 PM UTC 24 |
1323141700 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1936971138 |
|
|
Sep 24 05:59:19 PM UTC 24 |
Sep 24 07:50:19 PM UTC 24 |
7339369700 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.2580544934 |
|
|
Sep 24 05:53:03 PM UTC 24 |
Sep 24 07:57:39 PM UTC 24 |
4570065200 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.630002329 |
|
|
Sep 24 06:05:43 PM UTC 24 |
Sep 24 08:00:36 PM UTC 24 |
1356581900 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.46590317 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
29963500 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.113780352 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
158580200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2195842778 |
|
|
Sep 24 05:24:40 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
31392700 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2130145065 |
|
|
Sep 24 05:24:40 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
111311600 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1418661720 |
|
|
Sep 24 05:24:40 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
21856500 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1204968092 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:56 PM UTC 24 |
27085600 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.915332006 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
38404600 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3197972301 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
43466700 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1713893013 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
111581900 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.491300834 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
148269700 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3192048414 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
13804200 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2041517744 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:24:59 PM UTC 24 |
37298100 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3125585898 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:00 PM UTC 24 |
155114000 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3994668390 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:02 PM UTC 24 |
63885800 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.640734185 |
|
|
Sep 24 05:24:46 PM UTC 24 |
Sep 24 05:25:33 PM UTC 24 |
29270900 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.899713353 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:06 PM UTC 24 |
52404500 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.88299362 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:07 PM UTC 24 |
24039700 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1972574699 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:07 PM UTC 24 |
60554700 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.43309609 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:07 PM UTC 24 |
27744100 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2083594517 |
|
|
Sep 24 05:24:47 PM UTC 24 |
Sep 24 05:25:08 PM UTC 24 |
131317200 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.908467134 |
|
|
Sep 24 05:24:47 PM UTC 24 |
Sep 24 05:25:08 PM UTC 24 |
58155400 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2808788001 |
|
|
Sep 24 05:24:49 PM UTC 24 |
Sep 24 05:25:11 PM UTC 24 |
211223400 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3361719491 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:11 PM UTC 24 |
92218900 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3269337234 |
|
|
Sep 24 05:24:46 PM UTC 24 |
Sep 24 05:25:12 PM UTC 24 |
17773800 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3697627031 |
|
|
Sep 24 05:24:46 PM UTC 24 |
Sep 24 05:25:13 PM UTC 24 |
16786300 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2065355660 |
|
|
Sep 24 05:24:46 PM UTC 24 |
Sep 24 05:25:13 PM UTC 24 |
33050800 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2768232224 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:14 PM UTC 24 |
22745300 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2600986237 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:14 PM UTC 24 |
116165000 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2305450158 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:14 PM UTC 24 |
333173900 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.439865730 |
|
|
Sep 24 05:24:55 PM UTC 24 |
Sep 24 05:25:15 PM UTC 24 |
12302900 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3889921127 |
|
|
Sep 24 05:24:57 PM UTC 24 |
Sep 24 05:25:15 PM UTC 24 |
52200500 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1519204694 |
|
|
Sep 24 05:24:46 PM UTC 24 |
Sep 24 05:25:16 PM UTC 24 |
19743600 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4170086698 |
|
|
Sep 24 05:24:48 PM UTC 24 |
Sep 24 05:25:16 PM UTC 24 |
53239500 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4010421421 |
|
|
Sep 24 05:24:57 PM UTC 24 |
Sep 24 05:25:16 PM UTC 24 |
53036000 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1262159553 |
|
|
Sep 24 05:24:55 PM UTC 24 |
Sep 24 05:25:16 PM UTC 24 |
37221300 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3371068114 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:18 PM UTC 24 |
64268400 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3470462807 |
|
|
Sep 24 05:24:57 PM UTC 24 |
Sep 24 05:25:18 PM UTC 24 |
115068000 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3175364354 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:19 PM UTC 24 |
83643300 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.826995235 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:20 PM UTC 24 |
15023400 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2659009147 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:21 PM UTC 24 |
71274800 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.389499450 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:21 PM UTC 24 |
217812400 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3914466704 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:21 PM UTC 24 |
40544900 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2617474165 |
|
|
Sep 24 05:24:58 PM UTC 24 |
Sep 24 05:25:22 PM UTC 24 |
304517300 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1515106630 |
|
|
Sep 24 05:24:57 PM UTC 24 |
Sep 24 05:25:23 PM UTC 24 |
57358100 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1112532041 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:24 PM UTC 24 |
32454000 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1352079828 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:24 PM UTC 24 |
237044400 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.580065013 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:25 PM UTC 24 |
17209200 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2022799605 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:26 PM UTC 24 |
1144849000 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3979719508 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:26 PM UTC 24 |
440215000 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3541128655 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:26 PM UTC 24 |
1036833600 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.6138832 |
|
|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:25:27 PM UTC 24 |
111792200 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1189252165 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:28 PM UTC 24 |
25270900 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2764530200 |
|
|
Sep 24 05:25:08 PM UTC 24 |
Sep 24 05:25:28 PM UTC 24 |
12626200 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1163958287 |
|
|
Sep 24 05:24:43 PM UTC 24 |
Sep 24 05:25:28 PM UTC 24 |
62194100 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.548096241 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:29 PM UTC 24 |
1458166400 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3758391604 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:30 PM UTC 24 |
210735400 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3166691523 |
|
|
Sep 24 05:24:47 PM UTC 24 |
Sep 24 05:25:32 PM UTC 24 |
669977800 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3533939725 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:32 PM UTC 24 |
289974500 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3057162696 |
|
|
Sep 24 05:25:17 PM UTC 24 |
Sep 24 05:25:39 PM UTC 24 |
191867000 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1210386974 |
|
|
Sep 24 05:25:09 PM UTC 24 |
Sep 24 05:25:32 PM UTC 24 |
29734300 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2058909664 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:33 PM UTC 24 |
25305500 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.816054762 |
|
|
Sep 24 05:24:57 PM UTC 24 |
Sep 24 05:25:33 PM UTC 24 |
20772100 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.672262632 |
|
|
Sep 24 05:25:02 PM UTC 24 |
Sep 24 05:25:33 PM UTC 24 |
90251600 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.861619972 |
|
|
Sep 24 05:25:09 PM UTC 24 |
Sep 24 05:25:33 PM UTC 24 |
29332600 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1346503047 |
|
|
Sep 24 05:25:09 PM UTC 24 |
Sep 24 05:25:34 PM UTC 24 |
17383900 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.508548111 |
|
|
Sep 24 05:25:15 PM UTC 24 |
Sep 24 05:25:34 PM UTC 24 |
22789900 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1304079523 |
|
|
Sep 24 05:24:39 PM UTC 24 |
Sep 24 05:25:35 PM UTC 24 |
5078606000 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3295583107 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:35 PM UTC 24 |
1023686700 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2218896308 |
|
|
Sep 24 05:25:08 PM UTC 24 |
Sep 24 05:25:35 PM UTC 24 |
113988900 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.801555598 |
|
|
Sep 24 05:25:12 PM UTC 24 |
Sep 24 05:25:36 PM UTC 24 |
107098900 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.520693336 |
|
|
Sep 24 05:25:12 PM UTC 24 |
Sep 24 05:25:37 PM UTC 24 |
164828600 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4250901472 |
|
|
Sep 24 05:25:19 PM UTC 24 |
Sep 24 05:25:37 PM UTC 24 |
34520600 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1982556426 |
|
|
Sep 24 05:25:15 PM UTC 24 |
Sep 24 05:25:38 PM UTC 24 |
29707300 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2795464206 |
|
|
Sep 24 05:25:15 PM UTC 24 |
Sep 24 05:25:40 PM UTC 24 |
147636300 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2103132326 |
|
|
Sep 24 05:25:14 PM UTC 24 |
Sep 24 05:25:38 PM UTC 24 |
15918500 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.925220799 |
|
|
Sep 24 05:25:18 PM UTC 24 |
Sep 24 05:25:39 PM UTC 24 |
44159600 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1859277984 |
|
|
Sep 24 05:25:22 PM UTC 24 |
Sep 24 05:25:39 PM UTC 24 |
42202200 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2400877734 |
|
|
Sep 24 05:25:18 PM UTC 24 |
Sep 24 05:25:40 PM UTC 24 |
24366700 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1985398841 |
|
|
Sep 24 05:24:47 PM UTC 24 |
Sep 24 05:25:41 PM UTC 24 |
1083225600 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3968502086 |
|
|
Sep 24 05:25:13 PM UTC 24 |
Sep 24 05:25:41 PM UTC 24 |
71213500 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.501307191 |
|
|
Sep 24 05:25:19 PM UTC 24 |
Sep 24 05:25:41 PM UTC 24 |
30817900 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2853675495 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:42 PM UTC 24 |
33837600 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1092895315 |
|
|
Sep 24 05:25:17 PM UTC 24 |
Sep 24 05:25:43 PM UTC 24 |
80795300 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3640938623 |
|
|
Sep 24 05:25:21 PM UTC 24 |
Sep 24 05:25:43 PM UTC 24 |
737473600 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1203954236 |
|
|
Sep 24 05:25:25 PM UTC 24 |
Sep 24 05:25:45 PM UTC 24 |
18663900 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3426110416 |
|
|
Sep 24 05:25:23 PM UTC 24 |
Sep 24 05:25:47 PM UTC 24 |
12154100 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.589649198 |
|
|
Sep 24 05:25:57 PM UTC 24 |
Sep 24 05:26:21 PM UTC 24 |
32123500 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3449723333 |
|
|
Sep 24 05:25:20 PM UTC 24 |
Sep 24 05:25:47 PM UTC 24 |
2721293700 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4111578730 |
|
|
Sep 24 05:25:22 PM UTC 24 |
Sep 24 05:25:48 PM UTC 24 |
94982200 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1093670672 |
|
|
Sep 24 05:25:25 PM UTC 24 |
Sep 24 05:25:48 PM UTC 24 |
54494400 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1110383327 |
|
|
Sep 24 05:25:30 PM UTC 24 |
Sep 24 05:25:48 PM UTC 24 |
13717500 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2354227168 |
|
|
Sep 24 05:24:41 PM UTC 24 |
Sep 24 05:25:49 PM UTC 24 |
473206600 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3100476999 |
|
|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:25:50 PM UTC 24 |
36363600 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3168892401 |
|
|
Sep 24 05:24:58 PM UTC 24 |
Sep 24 05:25:51 PM UTC 24 |
818553300 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2423153126 |
|
|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:25:51 PM UTC 24 |
26695800 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2327695477 |
|
|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:25:51 PM UTC 24 |
26157200 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.197097384 |
|
|
Sep 24 05:25:30 PM UTC 24 |
Sep 24 05:25:52 PM UTC 24 |
31654800 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.804034057 |
|
|
Sep 24 05:25:34 PM UTC 24 |
Sep 24 05:25:52 PM UTC 24 |
18387900 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.39185148 |
|
|
Sep 24 05:25:29 PM UTC 24 |
Sep 24 05:25:52 PM UTC 24 |
335043500 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2514165084 |
|
|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:25:52 PM UTC 24 |
43445400 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1362316168 |
|
|
Sep 24 05:25:33 PM UTC 24 |
Sep 24 05:25:53 PM UTC 24 |
23500900 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2542925421 |
|
|
Sep 24 05:25:36 PM UTC 24 |
Sep 24 05:25:54 PM UTC 24 |
158623300 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4189737833 |
|
|
Sep 24 05:25:33 PM UTC 24 |
Sep 24 05:25:54 PM UTC 24 |
12879400 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3579496591 |
|
|
Sep 24 05:25:33 PM UTC 24 |
Sep 24 05:25:54 PM UTC 24 |
37246200 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.184403427 |
|
|
Sep 24 05:25:29 PM UTC 24 |
Sep 24 05:25:55 PM UTC 24 |
85716800 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3077112738 |
|
|
Sep 24 05:25:34 PM UTC 24 |
Sep 24 05:25:57 PM UTC 24 |
96097000 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1394936726 |
|
|
Sep 24 05:25:33 PM UTC 24 |
Sep 24 05:25:57 PM UTC 24 |
102208500 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.173832673 |
|
|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:25:58 PM UTC 24 |
273568200 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2852661661 |
|
|
Sep 24 05:25:38 PM UTC 24 |
Sep 24 05:25:58 PM UTC 24 |
73088100 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1197052049 |
|
|
Sep 24 05:25:36 PM UTC 24 |
Sep 24 05:25:58 PM UTC 24 |
10938500 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.616381240 |
|
|
Sep 24 05:25:16 PM UTC 24 |
Sep 24 05:25:58 PM UTC 24 |
872509000 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3309031454 |
|
|
Sep 24 05:25:39 PM UTC 24 |
Sep 24 05:25:59 PM UTC 24 |
14510200 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2031874952 |
|
|
Sep 24 05:25:36 PM UTC 24 |
Sep 24 05:25:59 PM UTC 24 |
81786200 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1918366455 |
|
|
Sep 24 05:25:36 PM UTC 24 |
Sep 24 05:26:01 PM UTC 24 |
542246700 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2001207803 |
|
|
Sep 24 05:25:37 PM UTC 24 |
Sep 24 05:26:01 PM UTC 24 |
160108100 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.648117330 |
|
|
Sep 24 05:25:34 PM UTC 24 |
Sep 24 05:26:02 PM UTC 24 |
51324700 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1950611755 |
|
|
Sep 24 05:25:44 PM UTC 24 |
Sep 24 05:26:03 PM UTC 24 |
53163100 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4198713970 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:03 PM UTC 24 |
48917400 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.797844386 |
|
|
Sep 24 05:25:39 PM UTC 24 |
Sep 24 05:26:05 PM UTC 24 |
29724300 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4057512609 |
|
|
Sep 24 05:25:44 PM UTC 24 |
Sep 24 05:26:05 PM UTC 24 |
38516000 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1948702166 |
|
|
Sep 24 05:25:44 PM UTC 24 |
Sep 24 05:26:05 PM UTC 24 |
127417600 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3568794644 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:06 PM UTC 24 |
98731700 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.257558582 |
|
|
Sep 24 05:25:49 PM UTC 24 |
Sep 24 05:26:06 PM UTC 24 |
32568700 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1700683310 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:07 PM UTC 24 |
28860800 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3671354568 |
|
|
Sep 24 05:25:48 PM UTC 24 |
Sep 24 05:26:07 PM UTC 24 |
28233100 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.59482063 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:20 PM UTC 24 |
549934100 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4194439029 |
|
|
Sep 24 05:25:47 PM UTC 24 |
Sep 24 05:26:08 PM UTC 24 |
242531600 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2293948642 |
|
|
Sep 24 05:25:25 PM UTC 24 |
Sep 24 05:26:08 PM UTC 24 |
983366500 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.305374076 |
|
|
Sep 24 05:25:49 PM UTC 24 |
Sep 24 05:26:09 PM UTC 24 |
22734300 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.482516569 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:10 PM UTC 24 |
74876800 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3925661791 |
|
|
Sep 24 05:25:50 PM UTC 24 |
Sep 24 05:26:11 PM UTC 24 |
37881100 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1689616567 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:11 PM UTC 24 |
662026700 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2202624615 |
|
|
Sep 24 05:25:49 PM UTC 24 |
Sep 24 05:26:11 PM UTC 24 |
17181200 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1072640685 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:12 PM UTC 24 |
85327700 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3608711239 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:12 PM UTC 24 |
15877600 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2304277928 |
|
|
Sep 24 05:25:45 PM UTC 24 |
Sep 24 05:26:13 PM UTC 24 |
43579600 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.4007853895 |
|
|
Sep 24 05:25:56 PM UTC 24 |
Sep 24 05:26:15 PM UTC 24 |
53988000 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.688043910 |
|
|
Sep 24 05:25:51 PM UTC 24 |
Sep 24 05:26:15 PM UTC 24 |
54895900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.431695593 |
|
|
Sep 24 05:25:51 PM UTC 24 |
Sep 24 05:26:16 PM UTC 24 |
33452700 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1514026260 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:17 PM UTC 24 |
24105900 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1889520218 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:17 PM UTC 24 |
384946600 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1497715045 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:18 PM UTC 24 |
47929200 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1201113340 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:18 PM UTC 24 |
13453500 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3120860467 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:20 PM UTC 24 |
11176400 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2447256368 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:20 PM UTC 24 |
46529600 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2484741424 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:21 PM UTC 24 |
40250600 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1332261824 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:23 PM UTC 24 |
23053900 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.825653988 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:24 PM UTC 24 |
390778000 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2363893140 |
|
|
Sep 24 05:25:55 PM UTC 24 |
Sep 24 05:26:25 PM UTC 24 |
479093300 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.11617142 |
|
|
Sep 24 05:26:04 PM UTC 24 |
Sep 24 05:26:25 PM UTC 24 |
12993400 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.431942691 |
|
|
Sep 24 05:26:06 PM UTC 24 |
Sep 24 05:26:25 PM UTC 24 |
55145200 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4019694420 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:25 PM UTC 24 |
124254400 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2495704560 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:26 PM UTC 24 |
91340900 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3697451290 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:26 PM UTC 24 |
13752700 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3827703362 |
|
|
Sep 24 05:26:03 PM UTC 24 |
Sep 24 05:26:26 PM UTC 24 |
83294900 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2264492064 |
|
|
Sep 24 05:26:08 PM UTC 24 |
Sep 24 05:26:26 PM UTC 24 |
45415500 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1295266631 |
|
|
Sep 24 05:26:08 PM UTC 24 |
Sep 24 05:26:26 PM UTC 24 |
24111600 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2097418974 |
|
|
Sep 24 05:26:03 PM UTC 24 |
Sep 24 05:26:27 PM UTC 24 |
31627700 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2876473520 |
|
|
Sep 24 05:26:02 PM UTC 24 |
Sep 24 05:26:27 PM UTC 24 |
103134600 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.1757181263 |
|
|
Sep 24 05:26:09 PM UTC 24 |
Sep 24 05:26:28 PM UTC 24 |
19861400 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1492711798 |
|
|
Sep 24 05:26:06 PM UTC 24 |
Sep 24 05:26:29 PM UTC 24 |
177175800 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3404072719 |
|
|
Sep 24 05:25:34 PM UTC 24 |
Sep 24 05:26:30 PM UTC 24 |
1192980300 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2561057632 |
|
|
Sep 24 05:26:12 PM UTC 24 |
Sep 24 05:26:30 PM UTC 24 |
17296900 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3455779095 |
|
|
Sep 24 05:26:09 PM UTC 24 |
Sep 24 05:26:30 PM UTC 24 |
16033800 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3446430143 |
|
|
Sep 24 05:26:12 PM UTC 24 |
Sep 24 05:26:30 PM UTC 24 |
36413400 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3307656850 |
|
|
Sep 24 05:26:00 PM UTC 24 |
Sep 24 05:26:31 PM UTC 24 |
142248500 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3935364220 |
|
|
Sep 24 05:26:10 PM UTC 24 |
Sep 24 05:26:31 PM UTC 24 |
50290300 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.1029323662 |
|
|
Sep 24 05:26:06 PM UTC 24 |
Sep 24 05:26:32 PM UTC 24 |
42068100 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.1176373845 |
|
|
Sep 24 05:26:13 PM UTC 24 |
Sep 24 05:26:33 PM UTC 24 |
50492900 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1566217618 |
|
|
Sep 24 05:26:07 PM UTC 24 |
Sep 24 05:26:33 PM UTC 24 |
219583100 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.2577553935 |
|
|
Sep 24 05:26:15 PM UTC 24 |
Sep 24 05:26:34 PM UTC 24 |
17030200 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1237837050 |
|
|
Sep 24 05:26:16 PM UTC 24 |
Sep 24 05:26:34 PM UTC 24 |
31854300 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2071444579 |
|
|
Sep 24 05:26:13 PM UTC 24 |
Sep 24 05:26:34 PM UTC 24 |
79726300 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3076874350 |
|
|
Sep 24 05:26:07 PM UTC 24 |
Sep 24 05:26:35 PM UTC 24 |
168459600 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2729456039 |
|
|
Sep 24 05:25:44 PM UTC 24 |
Sep 24 05:26:35 PM UTC 24 |
480912200 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.1937035054 |
|
|
Sep 24 05:26:12 PM UTC 24 |
Sep 24 05:26:36 PM UTC 24 |
270266100 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3940107236 |
|
|
Sep 24 05:26:18 PM UTC 24 |
Sep 24 05:26:37 PM UTC 24 |
16432000 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2056729418 |
|
|
Sep 24 05:26:17 PM UTC 24 |
Sep 24 05:26:37 PM UTC 24 |
17576800 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.267490429 |
|
|
Sep 24 05:26:13 PM UTC 24 |
Sep 24 05:26:37 PM UTC 24 |
45208000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2865508005 |
|
|
Sep 24 05:26:12 PM UTC 24 |
Sep 24 05:26:37 PM UTC 24 |
17152200 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1240798298 |
|
|
Sep 24 05:26:21 PM UTC 24 |
Sep 24 05:26:39 PM UTC 24 |
56995000 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.4155026306 |
|
|
Sep 24 05:26:21 PM UTC 24 |
Sep 24 05:26:40 PM UTC 24 |
44246800 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.4019639182 |
|
|
Sep 24 05:26:17 PM UTC 24 |
Sep 24 05:26:40 PM UTC 24 |
61402000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1537926465 |
|
|
Sep 24 05:26:22 PM UTC 24 |
Sep 24 05:26:41 PM UTC 24 |
18619700 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3871983414 |
|
|
Sep 24 05:26:24 PM UTC 24 |
Sep 24 05:26:42 PM UTC 24 |
54704400 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.2290756310 |
|
|
Sep 24 05:26:24 PM UTC 24 |
Sep 24 05:26:42 PM UTC 24 |
15270700 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1996475855 |
|
|
Sep 24 05:26:25 PM UTC 24 |
Sep 24 05:26:43 PM UTC 24 |
21904000 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1748975744 |
|
|
Sep 24 05:26:20 PM UTC 24 |
Sep 24 05:26:43 PM UTC 24 |
21703200 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.954552288 |
|
|
Sep 24 05:26:22 PM UTC 24 |
Sep 24 05:26:43 PM UTC 24 |
43553400 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1864878007 |
|
|
Sep 24 05:26:18 PM UTC 24 |
Sep 24 05:26:44 PM UTC 24 |
14504300 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2714667066 |
|
|
Sep 24 05:26:22 PM UTC 24 |
Sep 24 05:26:44 PM UTC 24 |
56303700 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1816379672 |
|
|
Sep 24 05:26:26 PM UTC 24 |
Sep 24 05:26:45 PM UTC 24 |
42666300 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2776534960 |
|
|
Sep 24 05:24:58 PM UTC 24 |
Sep 24 05:26:45 PM UTC 24 |
9240748300 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3201284658 |
|
|
Sep 24 05:26:26 PM UTC 24 |
Sep 24 05:26:45 PM UTC 24 |
25168100 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.2438776868 |
|
|
Sep 24 05:26:26 PM UTC 24 |
Sep 24 05:26:46 PM UTC 24 |
15174700 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1340615893 |
|
|
Sep 24 05:24:49 PM UTC 24 |
Sep 24 05:33:46 PM UTC 24 |
822438900 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2546107588 |
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|
Sep 24 05:25:31 PM UTC 24 |
Sep 24 05:33:55 PM UTC 24 |
1499236300 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3491210556 |
|
|
Sep 24 05:25:30 PM UTC 24 |
Sep 24 05:34:56 PM UTC 24 |
418131600 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2380738126 |
|
|
Sep 24 05:25:38 PM UTC 24 |
Sep 24 05:35:33 PM UTC 24 |
423659700 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1954714571 |
|
|
Sep 24 05:25:08 PM UTC 24 |
Sep 24 05:35:56 PM UTC 24 |
353715300 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2089148233 |
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|
Sep 24 05:25:00 PM UTC 24 |
Sep 24 05:36:22 PM UTC 24 |
260744100 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.459630617 |
|
|
Sep 24 05:25:34 PM UTC 24 |
Sep 24 05:36:33 PM UTC 24 |
714820700 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1964929622 |
|
|
Sep 24 05:25:51 PM UTC 24 |
Sep 24 05:36:39 PM UTC 24 |
400824500 ps |