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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.23 93.90 98.31 92.52 97.14 97.08 98.15


Total test records in report: 1262
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T183 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2976340361 Sep 24 05:50:40 PM UTC 24 Sep 24 06:36:49 PM UTC 24 430706862500 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3966460129 Sep 24 06:29:29 PM UTC 24 Sep 24 06:36:51 PM UTC 24 34720696200 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.343630472 Sep 24 06:35:21 PM UTC 24 Sep 24 06:36:52 PM UTC 24 555198700 ps
T663 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.20986414 Sep 24 06:15:03 PM UTC 24 Sep 24 06:37:11 PM UTC 24 1363538200 ps
T664 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2563305571 Sep 24 06:36:53 PM UTC 24 Sep 24 06:37:23 PM UTC 24 23931900 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.589313749 Sep 24 06:34:31 PM UTC 24 Sep 24 06:37:24 PM UTC 24 2551070900 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.54946753 Sep 24 06:31:44 PM UTC 24 Sep 24 06:37:25 PM UTC 24 192752000 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.828672708 Sep 24 06:33:45 PM UTC 24 Sep 24 06:37:30 PM UTC 24 76637400 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3609267405 Sep 24 06:33:47 PM UTC 24 Sep 24 06:37:32 PM UTC 24 2793756500 ps
T667 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.746323817 Sep 24 06:36:22 PM UTC 24 Sep 24 06:37:40 PM UTC 24 4037466900 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.2551815769 Sep 24 06:37:11 PM UTC 24 Sep 24 06:37:55 PM UTC 24 28080500 ps
T668 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1461578490 Sep 24 06:37:24 PM UTC 24 Sep 24 06:38:01 PM UTC 24 185108700 ps
T669 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.1171142754 Sep 24 06:37:34 PM UTC 24 Sep 24 06:38:02 PM UTC 24 28959700 ps
T670 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.985017790 Sep 24 06:37:42 PM UTC 24 Sep 24 06:38:03 PM UTC 24 44295900 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1765726887 Sep 24 06:37:26 PM UTC 24 Sep 24 06:38:08 PM UTC 24 11597600 ps
T671 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.259030438 Sep 24 06:35:55 PM UTC 24 Sep 24 06:38:11 PM UTC 24 10013330200 ps
T672 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.1863095953 Sep 24 06:37:56 PM UTC 24 Sep 24 06:38:15 PM UTC 24 60880900 ps
T673 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3227167487 Sep 24 06:36:03 PM UTC 24 Sep 24 06:38:16 PM UTC 24 47694700 ps
T674 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.2068538782 Sep 24 06:37:25 PM UTC 24 Sep 24 06:38:30 PM UTC 24 84556200 ps
T675 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.1890826049 Sep 24 06:38:03 PM UTC 24 Sep 24 06:38:31 PM UTC 24 224639900 ps
T676 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1052712491 Sep 24 06:19:32 PM UTC 24 Sep 24 06:38:39 PM UTC 24 659675700 ps
T677 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.167435292 Sep 24 06:36:08 PM UTC 24 Sep 24 06:38:39 PM UTC 24 6889803600 ps
T678 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.221584678 Sep 24 06:30:19 PM UTC 24 Sep 24 06:38:39 PM UTC 24 6798579600 ps
T679 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.3553394840 Sep 24 06:36:07 PM UTC 24 Sep 24 06:38:53 PM UTC 24 1379222700 ps
T680 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1389716839 Sep 24 06:34:40 PM UTC 24 Sep 24 06:38:59 PM UTC 24 29924962300 ps
T681 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.4082979666 Sep 24 06:36:39 PM UTC 24 Sep 24 06:39:00 PM UTC 24 2141848100 ps
T682 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.1913168935 Sep 24 06:37:31 PM UTC 24 Sep 24 06:39:08 PM UTC 24 6139213800 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3455453286 Sep 24 06:23:29 PM UTC 24 Sep 24 06:39:14 PM UTC 24 80138005200 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3847988118 Sep 24 06:36:09 PM UTC 24 Sep 24 06:39:14 PM UTC 24 42030400 ps
T683 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3747823508 Sep 24 06:38:02 PM UTC 24 Sep 24 06:39:16 PM UTC 24 10057602200 ps
T684 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.482296658 Sep 24 06:29:18 PM UTC 24 Sep 24 06:39:19 PM UTC 24 70882800 ps
T685 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.4105405464 Sep 24 06:36:05 PM UTC 24 Sep 24 06:39:33 PM UTC 24 173090800 ps
T686 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1669771569 Sep 24 06:39:10 PM UTC 24 Sep 24 06:39:42 PM UTC 24 30274800 ps
T687 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3205420806 Sep 24 06:36:23 PM UTC 24 Sep 24 06:40:00 PM UTC 24 5388891600 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2974675941 Sep 24 06:39:17 PM UTC 24 Sep 24 06:40:02 PM UTC 24 16443200 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.2227980590 Sep 24 06:39:33 PM UTC 24 Sep 24 06:40:03 PM UTC 24 54443900 ps
T688 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.4213372020 Sep 24 06:39:10 PM UTC 24 Sep 24 06:40:08 PM UTC 24 42277800 ps
T689 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1289344123 Sep 24 06:39:15 PM UTC 24 Sep 24 06:40:10 PM UTC 24 72968400 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1514027984 Sep 24 06:36:50 PM UTC 24 Sep 24 06:40:11 PM UTC 24 954579200 ps
T690 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2484819012 Sep 24 06:39:42 PM UTC 24 Sep 24 06:40:14 PM UTC 24 15183000 ps
T691 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1805367950 Sep 24 06:39:15 PM UTC 24 Sep 24 06:40:16 PM UTC 24 250970000 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2823511955 Sep 24 06:31:50 PM UTC 24 Sep 24 06:40:16 PM UTC 24 191831616800 ps
T692 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.325336984 Sep 24 06:40:01 PM UTC 24 Sep 24 06:40:26 PM UTC 24 15592300 ps
T693 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1620183601 Sep 24 06:38:40 PM UTC 24 Sep 24 06:40:29 PM UTC 24 891044500 ps
T694 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3699454743 Sep 24 06:40:04 PM UTC 24 Sep 24 06:40:33 PM UTC 24 62596900 ps
T695 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.1456174864 Sep 24 06:39:19 PM UTC 24 Sep 24 06:40:36 PM UTC 24 3230212600 ps
T696 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.614320752 Sep 24 06:38:15 PM UTC 24 Sep 24 06:40:47 PM UTC 24 3087086600 ps
T697 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1030816167 Sep 24 06:31:44 PM UTC 24 Sep 24 06:40:48 PM UTC 24 294601400 ps
T698 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.2401883708 Sep 24 06:40:09 PM UTC 24 Sep 24 06:41:09 PM UTC 24 33951900 ps
T699 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3821006523 Sep 24 06:36:53 PM UTC 24 Sep 24 06:41:09 PM UTC 24 32598317100 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.2525846262 Sep 24 06:31:56 PM UTC 24 Sep 24 06:41:11 PM UTC 24 3551891700 ps
T700 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1821053101 Sep 24 06:40:03 PM UTC 24 Sep 24 06:41:14 PM UTC 24 10120807000 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.2823184923 Sep 24 06:38:31 PM UTC 24 Sep 24 06:41:31 PM UTC 24 37048400 ps
T701 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.2008836722 Sep 24 06:41:10 PM UTC 24 Sep 24 06:41:32 PM UTC 24 57454800 ps
T702 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.2960327258 Sep 24 06:38:40 PM UTC 24 Sep 24 06:41:42 PM UTC 24 8820855600 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.3778770258 Sep 24 05:50:58 PM UTC 24 Sep 24 06:41:54 PM UTC 24 4060436500 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2778364161 Sep 24 06:41:33 PM UTC 24 Sep 24 06:41:58 PM UTC 24 17459800 ps
T703 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2133543654 Sep 24 06:34:25 PM UTC 24 Sep 24 06:41:59 PM UTC 24 3331264300 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3675163354 Sep 24 06:41:15 PM UTC 24 Sep 24 06:42:01 PM UTC 24 30282400 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1015915434 Sep 24 06:41:12 PM UTC 24 Sep 24 06:42:06 PM UTC 24 28452700 ps
T704 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.1721253683 Sep 24 06:40:30 PM UTC 24 Sep 24 06:42:07 PM UTC 24 3099685800 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.3560194009 Sep 24 06:36:12 PM UTC 24 Sep 24 06:42:17 PM UTC 24 25641782500 ps
T705 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.2394678175 Sep 24 06:41:31 PM UTC 24 Sep 24 06:42:23 PM UTC 24 72469800 ps
T706 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1319241645 Sep 24 06:41:56 PM UTC 24 Sep 24 06:42:25 PM UTC 24 16990100 ps
T707 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.2134946333 Sep 24 06:41:59 PM UTC 24 Sep 24 06:42:26 PM UTC 24 26616500 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3955324966 Sep 24 06:42:00 PM UTC 24 Sep 24 06:42:30 PM UTC 24 45212800 ps
T708 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2916364178 Sep 24 06:38:11 PM UTC 24 Sep 24 06:42:30 PM UTC 24 186398100 ps
T709 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.1598401709 Sep 24 06:40:36 PM UTC 24 Sep 24 06:42:32 PM UTC 24 930294500 ps
T710 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3124946557 Sep 24 06:42:07 PM UTC 24 Sep 24 06:42:33 PM UTC 24 75754200 ps
T711 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.4221212473 Sep 24 06:40:15 PM UTC 24 Sep 24 06:42:39 PM UTC 24 3858646800 ps
T712 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.3415690604 Sep 24 06:38:04 PM UTC 24 Sep 24 06:42:52 PM UTC 24 30566600 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3027745162 Sep 24 06:41:44 PM UTC 24 Sep 24 06:42:53 PM UTC 24 513772600 ps
T713 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.4077826211 Sep 24 06:38:59 PM UTC 24 Sep 24 06:42:58 PM UTC 24 5768041000 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.2199860745 Sep 24 05:46:50 PM UTC 24 Sep 24 06:43:00 PM UTC 24 4493324500 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.873180895 Sep 24 06:40:18 PM UTC 24 Sep 24 06:43:05 PM UTC 24 43759800 ps
T714 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.2560261360 Sep 24 06:43:01 PM UTC 24 Sep 24 06:43:31 PM UTC 24 140528200 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.3935058719 Sep 24 06:27:08 PM UTC 24 Sep 24 06:43:32 PM UTC 24 80154955200 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2943329779 Sep 24 06:42:02 PM UTC 24 Sep 24 06:43:34 PM UTC 24 10019070600 ps
T715 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.842501836 Sep 24 06:39:01 PM UTC 24 Sep 24 06:43:41 PM UTC 24 11436592400 ps
T716 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.4098969336 Sep 24 06:40:27 PM UTC 24 Sep 24 06:43:52 PM UTC 24 8131596200 ps
T717 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.4079059799 Sep 24 06:40:34 PM UTC 24 Sep 24 06:43:53 PM UTC 24 28842636300 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.342067025 Sep 24 06:43:05 PM UTC 24 Sep 24 06:43:56 PM UTC 24 28864300 ps
T718 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1695950301 Sep 24 06:43:35 PM UTC 24 Sep 24 06:44:02 PM UTC 24 10245000 ps
T719 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.2841654806 Sep 24 06:42:33 PM UTC 24 Sep 24 06:44:02 PM UTC 24 8526133900 ps
T720 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.417246480 Sep 24 06:23:52 PM UTC 24 Sep 24 06:44:16 PM UTC 24 371496700 ps
T721 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.465192558 Sep 24 06:42:24 PM UTC 24 Sep 24 06:44:18 PM UTC 24 279719100 ps
T722 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3255516385 Sep 24 06:40:50 PM UTC 24 Sep 24 06:44:18 PM UTC 24 1233997800 ps
T723 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.2809318698 Sep 24 06:42:40 PM UTC 24 Sep 24 06:44:19 PM UTC 24 489956000 ps
T724 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1708682030 Sep 24 06:43:54 PM UTC 24 Sep 24 06:44:19 PM UTC 24 38222400 ps
T725 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.975514478 Sep 24 06:43:53 PM UTC 24 Sep 24 06:44:19 PM UTC 24 24163800 ps
T726 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.3740667197 Sep 24 06:43:31 PM UTC 24 Sep 24 06:44:20 PM UTC 24 68230400 ps
T727 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.188147591 Sep 24 06:42:31 PM UTC 24 Sep 24 06:44:20 PM UTC 24 1185949200 ps
T728 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.905260174 Sep 24 06:43:58 PM UTC 24 Sep 24 06:44:21 PM UTC 24 96166300 ps
T729 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.738638511 Sep 24 06:43:33 PM UTC 24 Sep 24 06:44:23 PM UTC 24 129085100 ps
T730 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1025965409 Sep 24 06:44:03 PM UTC 24 Sep 24 06:44:31 PM UTC 24 22140300 ps
T731 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.2119589703 Sep 24 06:40:12 PM UTC 24 Sep 24 06:44:37 PM UTC 24 187491600 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.1440067127 Sep 24 06:36:50 PM UTC 24 Sep 24 06:44:54 PM UTC 24 60845755300 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.4088601516 Sep 24 06:42:26 PM UTC 24 Sep 24 06:44:57 PM UTC 24 6749898100 ps
T732 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1001749494 Sep 24 06:42:54 PM UTC 24 Sep 24 06:45:05 PM UTC 24 886154400 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1802284760 Sep 24 06:43:42 PM UTC 24 Sep 24 06:45:17 PM UTC 24 488019700 ps
T733 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.3428241685 Sep 24 06:42:34 PM UTC 24 Sep 24 06:45:27 PM UTC 24 7036860500 ps
T734 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.2630642533 Sep 24 06:44:58 PM UTC 24 Sep 24 06:45:28 PM UTC 24 19358000 ps
T735 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.3091861433 Sep 24 06:42:08 PM UTC 24 Sep 24 06:45:36 PM UTC 24 42325700 ps
T736 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.3782549080 Sep 24 06:44:22 PM UTC 24 Sep 24 06:45:46 PM UTC 24 6244383400 ps
T737 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.2438425967 Sep 24 06:29:27 PM UTC 24 Sep 24 06:45:47 PM UTC 24 160172020200 ps
T738 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3752802262 Sep 24 06:33:35 PM UTC 24 Sep 24 06:45:48 PM UTC 24 2967146500 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.789360535 Sep 24 06:45:06 PM UTC 24 Sep 24 06:46:01 PM UTC 24 30664800 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1562114543 Sep 24 06:45:29 PM UTC 24 Sep 24 06:46:03 PM UTC 24 15324700 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.4133740201 Sep 24 06:45:27 PM UTC 24 Sep 24 06:46:06 PM UTC 24 119760000 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.4253871373 Sep 24 06:42:31 PM UTC 24 Sep 24 06:46:11 PM UTC 24 139870900 ps
T739 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2843143720 Sep 24 06:45:48 PM UTC 24 Sep 24 06:46:13 PM UTC 24 136708300 ps
T740 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.933733033 Sep 24 06:45:47 PM UTC 24 Sep 24 06:46:13 PM UTC 24 51265200 ps
T741 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.711477628 Sep 24 06:45:18 PM UTC 24 Sep 24 06:46:14 PM UTC 24 28246400 ps
T742 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.174241941 Sep 24 06:45:49 PM UTC 24 Sep 24 06:46:16 PM UTC 24 16710000 ps
T743 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3118920805 Sep 24 06:01:07 PM UTC 24 Sep 24 06:46:20 PM UTC 24 399616256100 ps
T744 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.185014035 Sep 24 06:44:17 PM UTC 24 Sep 24 06:46:25 PM UTC 24 22332000 ps
T745 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1262679026 Sep 24 06:41:10 PM UTC 24 Sep 24 06:46:28 PM UTC 24 48856666800 ps
T746 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1640991709 Sep 24 06:46:04 PM UTC 24 Sep 24 06:46:31 PM UTC 24 41471400 ps
T747 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.4012053745 Sep 24 06:44:22 PM UTC 24 Sep 24 06:47:01 PM UTC 24 1884181500 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.1839670860 Sep 24 06:45:38 PM UTC 24 Sep 24 06:47:09 PM UTC 24 6031833100 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.2233278167 Sep 24 06:38:32 PM UTC 24 Sep 24 06:47:12 PM UTC 24 21574280700 ps
T748 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.3684161688 Sep 24 06:44:24 PM UTC 24 Sep 24 06:47:13 PM UTC 24 656401200 ps
T749 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3500070137 Sep 24 06:44:19 PM UTC 24 Sep 24 06:47:24 PM UTC 24 2453568800 ps
T750 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.1641005598 Sep 24 06:31:49 PM UTC 24 Sep 24 06:47:25 PM UTC 24 40120394300 ps
T751 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.3843490363 Sep 24 06:44:22 PM UTC 24 Sep 24 06:47:27 PM UTC 24 9035120200 ps
T752 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3908958260 Sep 24 06:46:25 PM UTC 24 Sep 24 06:47:43 PM UTC 24 5863351700 ps
T753 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.3794382163 Sep 24 06:44:20 PM UTC 24 Sep 24 06:47:44 PM UTC 24 135763400 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2682229864 Sep 24 05:54:58 PM UTC 24 Sep 24 06:47:47 PM UTC 24 264530947100 ps
T754 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.3526505290 Sep 24 06:47:13 PM UTC 24 Sep 24 06:47:48 PM UTC 24 712362800 ps
T755 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.2782425034 Sep 24 06:47:25 PM UTC 24 Sep 24 06:48:04 PM UTC 24 109350700 ps
T756 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.1785907702 Sep 24 06:47:28 PM UTC 24 Sep 24 06:48:05 PM UTC 24 11766300 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2685033651 Sep 24 06:47:25 PM UTC 24 Sep 24 06:48:10 PM UTC 24 132438100 ps
T757 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.2310090462 Sep 24 06:47:45 PM UTC 24 Sep 24 06:48:11 PM UTC 24 153253800 ps
T758 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.2598262787 Sep 24 06:47:47 PM UTC 24 Sep 24 06:48:13 PM UTC 24 47418800 ps
T759 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.3048150727 Sep 24 06:47:44 PM UTC 24 Sep 24 06:48:15 PM UTC 24 17160200 ps
T760 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.422688686 Sep 24 06:47:14 PM UTC 24 Sep 24 06:48:22 PM UTC 24 41789700 ps
T761 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.4109699919 Sep 24 06:46:06 PM UTC 24 Sep 24 06:48:24 PM UTC 24 29569300 ps
T762 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.3375743009 Sep 24 06:40:11 PM UTC 24 Sep 24 06:48:32 PM UTC 24 47984700 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1468629301 Sep 24 06:48:05 PM UTC 24 Sep 24 06:48:37 PM UTC 24 90920900 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2283448269 Sep 24 06:46:02 PM UTC 24 Sep 24 06:48:48 PM UTC 24 10019148200 ps
T764 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.731211269 Sep 24 06:44:38 PM UTC 24 Sep 24 06:48:49 PM UTC 24 1450063100 ps
T765 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.3954717894 Sep 24 06:48:23 PM UTC 24 Sep 24 06:48:51 PM UTC 24 18569500 ps
T766 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3040841886 Sep 24 06:44:56 PM UTC 24 Sep 24 06:49:03 PM UTC 24 43005940400 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.121551778 Sep 24 06:48:24 PM UTC 24 Sep 24 06:49:09 PM UTC 24 54821400 ps
T767 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.2963325623 Sep 24 06:48:37 PM UTC 24 Sep 24 06:49:11 PM UTC 24 11961300 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.1154142938 Sep 24 06:47:37 PM UTC 24 Sep 24 06:49:13 PM UTC 24 823768000 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.229565885 Sep 24 06:46:17 PM UTC 24 Sep 24 06:49:18 PM UTC 24 172567100 ps
T768 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.268760855 Sep 24 06:48:51 PM UTC 24 Sep 24 06:49:20 PM UTC 24 50784700 ps
T769 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1834926105 Sep 24 06:48:53 PM UTC 24 Sep 24 06:49:20 PM UTC 24 38175800 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1879587790 Sep 24 06:46:14 PM UTC 24 Sep 24 06:49:22 PM UTC 24 9971412000 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.1724027245 Sep 24 06:48:33 PM UTC 24 Sep 24 06:49:23 PM UTC 24 68205300 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1962129919 Sep 24 06:46:21 PM UTC 24 Sep 24 06:49:24 PM UTC 24 6047658100 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.10774645 Sep 24 06:44:03 PM UTC 24 Sep 24 06:49:28 PM UTC 24 10012213900 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.4277152015 Sep 24 06:40:49 PM UTC 24 Sep 24 06:49:32 PM UTC 24 6326640300 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1116015565 Sep 24 06:47:06 PM UTC 24 Sep 24 06:49:36 PM UTC 24 1542533500 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.42051805 Sep 24 06:49:20 PM UTC 24 Sep 24 06:49:46 PM UTC 24 41225800 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1449926797 Sep 24 06:49:28 PM UTC 24 Sep 24 06:49:48 PM UTC 24 26841400 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3259631899 Sep 24 06:06:06 PM UTC 24 Sep 24 06:49:49 PM UTC 24 696451100 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1114749921 Sep 24 06:46:28 PM UTC 24 Sep 24 06:49:52 PM UTC 24 3884248200 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.2116330528 Sep 24 06:49:33 PM UTC 24 Sep 24 06:49:56 PM UTC 24 99562700 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3404997325 Sep 24 06:48:49 PM UTC 24 Sep 24 06:49:59 PM UTC 24 2248058400 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.113690583 Sep 24 06:49:23 PM UTC 24 Sep 24 06:50:07 PM UTC 24 27238100 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.1270013963 Sep 24 06:38:53 PM UTC 24 Sep 24 06:50:08 PM UTC 24 50080362500 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.4185355102 Sep 24 06:49:24 PM UTC 24 Sep 24 06:50:10 PM UTC 24 10211200 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2018671154 Sep 24 06:56:34 PM UTC 24 Sep 24 06:57:00 PM UTC 24 101512500 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.3957761897 Sep 24 06:49:20 PM UTC 24 Sep 24 06:50:11 PM UTC 24 98035100 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.742821454 Sep 24 06:49:10 PM UTC 24 Sep 24 06:50:11 PM UTC 24 3821817200 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3443940823 Sep 24 06:49:57 PM UTC 24 Sep 24 06:50:16 PM UTC 24 18253600 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.857551165 Sep 24 06:42:59 PM UTC 24 Sep 24 06:50:16 PM UTC 24 12945663300 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2837919539 Sep 24 06:48:11 PM UTC 24 Sep 24 06:50:37 PM UTC 24 13021431700 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.836404854 Sep 24 06:50:09 PM UTC 24 Sep 24 06:50:37 PM UTC 24 24740600 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.3747804528 Sep 24 06:49:04 PM UTC 24 Sep 24 06:50:38 PM UTC 24 16666900 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1164753622 Sep 24 06:47:48 PM UTC 24 Sep 24 06:50:43 PM UTC 24 10019604700 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3259778986 Sep 24 06:50:12 PM UTC 24 Sep 24 06:50:44 PM UTC 24 60467500 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.3428859605 Sep 24 06:01:30 PM UTC 24 Sep 24 06:50:45 PM UTC 24 79843918100 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.1499649517 Sep 24 06:50:07 PM UTC 24 Sep 24 06:50:46 PM UTC 24 61960300 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.2878329578 Sep 24 06:50:12 PM UTC 24 Sep 24 06:50:46 PM UTC 24 15764800 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3662293480 Sep 24 06:49:25 PM UTC 24 Sep 24 06:50:50 PM UTC 24 2717118800 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2282109945 Sep 24 06:48:16 PM UTC 24 Sep 24 06:50:51 PM UTC 24 5785702600 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.965032786 Sep 24 06:48:05 PM UTC 24 Sep 24 06:50:56 PM UTC 24 52907200 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.1243914937 Sep 24 06:49:59 PM UTC 24 Sep 24 06:51:02 PM UTC 24 31150700 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3705625304 Sep 24 06:48:12 PM UTC 24 Sep 24 06:51:02 PM UTC 24 217519400 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.2557103281 Sep 24 06:50:43 PM UTC 24 Sep 24 06:51:02 PM UTC 24 19975200 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.2445215654 Sep 24 06:42:53 PM UTC 24 Sep 24 06:51:07 PM UTC 24 4232687100 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1127140633 Sep 24 06:44:18 PM UTC 24 Sep 24 06:51:07 PM UTC 24 250790800 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1386317934 Sep 24 05:55:36 PM UTC 24 Sep 24 06:51:08 PM UTC 24 13416717700 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.3220157200 Sep 24 06:33:38 PM UTC 24 Sep 24 06:51:12 PM UTC 24 40126210000 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.2990487872 Sep 24 06:50:54 PM UTC 24 Sep 24 06:51:20 PM UTC 24 215761500 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1067736572 Sep 24 06:50:54 PM UTC 24 Sep 24 06:51:25 PM UTC 24 48704000 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3773022964 Sep 24 06:50:45 PM UTC 24 Sep 24 06:51:25 PM UTC 24 76413600 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.2060955213 Sep 24 06:50:54 PM UTC 24 Sep 24 06:51:27 PM UTC 24 10162500 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.3435663367 Sep 24 06:49:47 PM UTC 24 Sep 24 06:51:28 PM UTC 24 5752521000 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.3688006897 Sep 24 06:51:08 PM UTC 24 Sep 24 06:51:33 PM UTC 24 34680600 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.2835351737 Sep 24 06:50:54 PM UTC 24 Sep 24 06:51:37 PM UTC 24 26696200 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1394083666 Sep 24 06:38:17 PM UTC 24 Sep 24 06:51:39 PM UTC 24 90142717300 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.2632142554 Sep 24 06:50:12 PM UTC 24 Sep 24 06:51:40 PM UTC 24 6472335600 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.1112283159 Sep 24 06:51:13 PM UTC 24 Sep 24 06:51:46 PM UTC 24 19938100 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.966780824 Sep 24 06:51:27 PM UTC 24 Sep 24 06:51:46 PM UTC 24 68588300 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.2688961541 Sep 24 06:51:09 PM UTC 24 Sep 24 06:51:50 PM UTC 24 68275900 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.994897625 Sep 24 06:36:08 PM UTC 24 Sep 24 06:51:52 PM UTC 24 80135121500 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3752297121 Sep 24 06:51:08 PM UTC 24 Sep 24 06:51:54 PM UTC 24 62998200 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.730196231 Sep 24 06:51:25 PM UTC 24 Sep 24 06:51:55 PM UTC 24 16930400 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.3597920495 Sep 24 06:51:41 PM UTC 24 Sep 24 06:51:59 PM UTC 24 175990000 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1148318706 Sep 24 05:50:48 PM UTC 24 Sep 24 06:52:01 PM UTC 24 119348576800 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3099637653 Sep 24 06:33:34 PM UTC 24 Sep 24 06:52:10 PM UTC 24 230118300 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3413984954 Sep 24 06:49:18 PM UTC 24 Sep 24 06:52:11 PM UTC 24 21264949000 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.373952408 Sep 24 06:49:12 PM UTC 24 Sep 24 06:52:12 PM UTC 24 330165400 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2281442099 Sep 24 06:50:18 PM UTC 24 Sep 24 06:52:17 PM UTC 24 4629673200 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.826660194 Sep 24 06:50:54 PM UTC 24 Sep 24 06:52:18 PM UTC 24 2051408700 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3660629906 Sep 24 06:47:09 PM UTC 24 Sep 24 06:52:18 PM UTC 24 13216702900 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.2033483213 Sep 24 06:48:14 PM UTC 24 Sep 24 06:52:19 PM UTC 24 2539211000 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.1542157120 Sep 24 05:46:47 PM UTC 24 Sep 24 06:52:21 PM UTC 24 54782485600 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1051982465 Sep 24 06:51:55 PM UTC 24 Sep 24 06:52:24 PM UTC 24 13487500 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1143758463 Sep 24 06:51:56 PM UTC 24 Sep 24 06:52:24 PM UTC 24 182411000 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.3168074867 Sep 24 06:49:14 PM UTC 24 Sep 24 06:52:29 PM UTC 24 877389600 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.4271147086 Sep 24 06:50:57 PM UTC 24 Sep 24 06:52:31 PM UTC 24 1819054800 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3698348041 Sep 24 06:51:47 PM UTC 24 Sep 24 06:52:31 PM UTC 24 46587800 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.1311965666 Sep 24 06:51:47 PM UTC 24 Sep 24 06:52:35 PM UTC 24 78126800 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3798436946 Sep 24 06:51:51 PM UTC 24 Sep 24 06:52:37 PM UTC 24 12616300 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.1612196883 Sep 24 06:51:20 PM UTC 24 Sep 24 06:52:41 PM UTC 24 1202716900 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.4276217153 Sep 24 06:52:18 PM UTC 24 Sep 24 06:52:45 PM UTC 24 36861600 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1995136251 Sep 24 06:52:27 PM UTC 24 Sep 24 06:52:50 PM UTC 24 35938700 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.997593633 Sep 24 06:52:27 PM UTC 24 Sep 24 06:52:54 PM UTC 24 125407600 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.2503883566 Sep 24 06:52:20 PM UTC 24 Sep 24 06:52:57 PM UTC 24 20585200 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.1979987080 Sep 24 06:49:50 PM UTC 24 Sep 24 06:52:59 PM UTC 24 706500700 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2292054134 Sep 24 06:49:49 PM UTC 24 Sep 24 06:53:00 PM UTC 24 40031300 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.3039623879 Sep 24 06:52:19 PM UTC 24 Sep 24 06:53:06 PM UTC 24 28634500 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3190757122 Sep 24 06:46:14 PM UTC 24 Sep 24 06:53:14 PM UTC 24 736732100 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.176145270 Sep 24 06:52:19 PM UTC 24 Sep 24 06:53:18 PM UTC 24 80174600 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3683600082 Sep 24 06:53:00 PM UTC 24 Sep 24 06:53:21 PM UTC 24 18415300 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.19031681 Sep 24 06:51:04 PM UTC 24 Sep 24 06:53:23 PM UTC 24 5953294900 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.1512764932 Sep 24 06:52:46 PM UTC 24 Sep 24 06:53:23 PM UTC 24 42735100 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3483068751 Sep 24 06:50:37 PM UTC 24 Sep 24 06:53:29 PM UTC 24 71296800 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1443197279 Sep 24 06:53:01 PM UTC 24 Sep 24 06:53:30 PM UTC 24 73917300 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2683149640 Sep 24 06:46:13 PM UTC 24 Sep 24 06:53:34 PM UTC 24 118359200 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1398562859 Sep 24 06:51:53 PM UTC 24 Sep 24 06:53:38 PM UTC 24 624874000 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1504606625 Sep 24 06:51:28 PM UTC 24 Sep 24 06:53:39 PM UTC 24 29539300 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.1267746819 Sep 24 06:52:55 PM UTC 24 Sep 24 06:53:41 PM UTC 24 10602300 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.325533556 Sep 24 06:52:50 PM UTC 24 Sep 24 06:53:43 PM UTC 24 78617100 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.848265220 Sep 24 06:51:29 PM UTC 24 Sep 24 06:53:45 PM UTC 24 5234608400 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1787111464 Sep 24 06:52:26 PM UTC 24 Sep 24 06:53:51 PM UTC 24 2071465600 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.1208377795 Sep 24 06:53:24 PM UTC 24 Sep 24 06:53:52 PM UTC 24 452217600 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.506505332 Sep 24 06:51:02 PM UTC 24 Sep 24 06:53:54 PM UTC 24 39830500 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.2699003015 Sep 24 06:52:29 PM UTC 24 Sep 24 06:53:55 PM UTC 24 32575700 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.1588472116 Sep 24 06:53:40 PM UTC 24 Sep 24 06:54:00 PM UTC 24 68627700 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3247002684 Sep 24 06:53:31 PM UTC 24 Sep 24 06:54:01 PM UTC 24 13714300 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3796249862 Sep 24 06:51:38 PM UTC 24 Sep 24 06:54:01 PM UTC 24 498546300 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.1571830066 Sep 24 06:53:24 PM UTC 24 Sep 24 06:54:03 PM UTC 24 31327700 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.1317252980 Sep 24 06:53:39 PM UTC 24 Sep 24 06:54:05 PM UTC 24 26038800 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.847676490 Sep 24 06:52:12 PM UTC 24 Sep 24 06:54:12 PM UTC 24 653329500 ps
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