FLASH_CTRL Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.232m	30.788us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	49.600s	19.601us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	39.330s	33.838us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.756m	9.241ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	53.650s	5.079ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	26.680s	83.643us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
		flash_ctrl_csr_aliasing	53.650s	5.079ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	16.650s	52.200us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	19.710s	115.068us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	41.700s	36.388us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.963m	122.953us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.317m	105.224ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.188m	480.323ms	20	20	100.00
		flash_ctrl_lcmgr_intg	30.330s	15.183us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	52.232m	264.531ms	4	5	80.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.851m	11.706ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.276m	4.603ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.249h	271.946ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.465m	2.429ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.105m	41.790us	40	40	100.00
		flash_ctrl_rw_evict_all_en	1.007m	40.281us	38	40	95.00
		flash_ctrl_re_evict	1.099m	105.919us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	12.074m	2.967ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	12.074m	2.967ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.667m	9.171ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	49.710s	599.726us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	31.963m	664.885us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	57.421m	9.332ms	9	10	90.00
V2	error_prog_win	flash_ctrl_error_prog_win	24.474m	2.461ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.470m	1.264ms	2	5	40.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.970s	45.213us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.464m	2.441ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.010s	10.211us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.790s	13.682us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	44.321m	3.727ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.229m	3.077ms	50	50	100.00
		flash_ctrl_otp_reset	4.024m	298.288us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.317m	105.224ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.782m	6.002ms	39	40	97.50
		flash_ctrl_intr_wr	1.651m	4.205ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	8.984m	107.099ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	13.832m	352.753ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.876m	3.499ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.974m	2.563ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	41.840s	18.618us	5	5	100.00
		flash_ctrl_ro_derr	3.201m	2.508ms	10	10	100.00
		flash_ctrl_rw_derr	4.800m	7.045ms	10	10	100.00
		flash_ctrl_derr_detect	4.824m	11.548ms	2	5	40.00
		flash_ctrl_integrity	11.398m	8.413ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	47.530s	56.409us	5	5	100.00
		flash_ctrl_ro_serr	3.236m	877.440us	10	10	100.00
		flash_ctrl_rw_serr	5.488m	6.083ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.801m	3.232ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.730m	3.325ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.528m	9.929ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.460s	61.929us	1	1	100.00
		flash_ctrl_read_word_sweep	18.220s	44.840us	1	1	100.00
		flash_ctrl_ro	2.753m	656.401us	18	20	90.00
		flash_ctrl_rw	11.518m	16.199ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.030m	2.355ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.444m	167.199ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.513m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	31.750s	71.333us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	24.460s	14.504us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	26.540s	71.213us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	26.540s	71.213us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	39.330s	33.838us	5	5	100.00
		flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
		flash_ctrl_csr_aliasing	53.650s	5.079ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.900s	1.193ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	39.330s	33.838us	5	5	100.00
		flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
		flash_ctrl_csr_aliasing	53.650s	5.079ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.900s	1.193ms	20	20	100.00
V2		TOTAL			997	1013	98.42
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	25.180s	85.328us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
		flash_ctrl_tl_intg_err	20.191m	1.394ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	20.191m	1.394ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	20.191m	1.394ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	44.190s	65.994us	3	3	100.00
		flash_ctrl_wr_intg	30.140s	111.858us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.232m	30.788us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.024m	298.288us	80	80	100.00
		flash_ctrl_disable	45.010s	10.211us	50	50	100.00
		flash_ctrl_sec_info_access	2.228m	9.683ms	50	50	100.00
		flash_ctrl_connect	32.790s	13.682us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	28.030s	19.625us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	29.370s	142.249us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	23.330s	11.176us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.010s	10.211us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	44.190s	65.994us	3	3	100.00
		flash_ctrl_access_after_disable	27.560s	23.802us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	48.490s	39.577us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.010s	10.211us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	49.710s	599.726us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.518m	16.199ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	5.488m	6.083ms	10	10	100.00
		flash_ctrl_rw_derr	4.800m	7.045ms	10	10	100.00
		flash_ctrl_integrity	11.398m	8.413ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.317m	105.224ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	40.610s	857.844us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	28.530s	19.841us	2	5	40.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	27.880s	32.702us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.054h	4.570ms	5	5	100.00
V2S		TOTAL			144	147	97.96
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.194m	109.478us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1262	1281	98.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	95.23	93.90	98.31	92.52	97.14	97.08	98.15

Failure Buckets

Job timed out after * minutes has 7 failures:
- Test flash_ctrl_host_ctrl_arb has 1 failures.
  - 1.flash_ctrl_host_ctrl_arb.66150879066114181530141798485004293968482767677629682727316143355145727871935
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_error_prog_type has 3 failures.
  - 2.flash_ctrl_error_prog_type.70156907829034631127418842153108394816171863859976076454155017519892721609351
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.flash_ctrl_error_prog_type.35809698528226900792161428034622163337127665499928089340109236021462043826673
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test flash_ctrl_error_mp has 1 failures.
  - 6.flash_ctrl_error_mp.107260542119613809194794942962188299203652368718969379907748837888498620900894
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 8.flash_ctrl_intr_wr.36166295980553624984692266337591421765612409211102606180199762565748214065171
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw has 1 failures.
  - 19.flash_ctrl_rw.19857292163818912889600325784823207010814101595893784056107232669953860186822
    Log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test flash_ctrl_derr_detect has 2 failures.

0.flash_ctrl_derr_detect.45984141565925560453551862799467835662796324746789706446433638199403009793749
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 37124.1 ns: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 37124.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_derr_detect.63703546089470602230258777560970720378122139564451833414987630340227745472824
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 32332.8 ns: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 32332.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 2 failures:
- Test flash_ctrl_phy_host_grant_err has 2 failures.
  - 2.flash_ctrl_phy_host_grant_err.47765930102763108091274861281348897080965402220376632259639107047587045042
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 19841.0 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 19841.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.flash_ctrl_phy_host_grant_err.45066201414719406163236217891044531340931827468658377014930800200880083692453
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 21963.4 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 21963.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 6.flash_ctrl_rw_evict_all_en.83927685889185468773628371573662882448970708422189359623978644727352565049708
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 24497.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24497.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.flash_ctrl_rw_evict_all_en.98665990311443431205719949783270299536929107344352336706804771304512561338181
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 9962.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 9962.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.43949282036077147214255740202438526378084257397487328837561902868301438266378
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 4.flash_ctrl_phy_host_grant_err.37181537258642528375673327813739084128567534805556871328117375403064070569671
    Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
```
  UVM_ERROR @ 6888.7 ns: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6888.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 8.flash_ctrl_lcmgr_intg.105529804062202796380731391948011685032941743052982707594358555947307506660002
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 62769.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 62769.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 15.flash_ctrl_ro.88761927899057036753667258997049005452163351720657889260126346210599821153431
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 46261.0 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 46261.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 19.flash_ctrl_ro.4181640425478014872021311545157291711421140218583849792811976141908648847732
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 85929.5 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 85929.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c400178_c7a68570:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 24.flash_ctrl_intr_rd.91267277342827645524232460058822997897635431866173394955182835971842229925915
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 783102.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    8c400178_c7a68570:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 783102.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```