FLASH_CTRL Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	6.702m	3.574ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	46.620s	16.453us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.151m	78.588us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.224m	5.688ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.207m	1.351ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	28.590s	237.322us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
		flash_ctrl_csr_aliasing	1.207m	1.351ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	21.980s	43.175us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	23.830s	15.069us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	46.360s	82.491us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.894m	65.254us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.999m	543.604ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.195m	480.367ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.480s	27.000us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	57.485m	267.917ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	11.664m	4.167ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.902m	8.032ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.151h	99.778ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.696m	702.203us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.029m	127.508us	37	40	92.50
		flash_ctrl_rw_evict_all_en	1.054m	42.781us	39	40	97.50
		flash_ctrl_re_evict	1.034m	269.696us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	13.838m	2.852ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	13.838m	2.852ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.379m	59.471ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	54.760s	1.771ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.942m	76.968us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	56.267m	4.375ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	24.926m	792.648us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	58.657m	3.801ms	3	5	60.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.500s	15.120us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.093m	4.507ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	44.180s	26.087us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.490s	49.451us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.796m	309.983us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.349m	2.988ms	50	50	100.00
		flash_ctrl_otp_reset	4.104m	130.711us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.999m	543.604ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.080m	1.670ms	36	40	90.00
		flash_ctrl_intr_wr	1.882m	5.080ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.757m	86.579ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.850m	305.046ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.892m	3.430ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.043m	645.965us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	33.420s	32.516us	5	5	100.00
		flash_ctrl_ro_derr	3.098m	1.270ms	10	10	100.00
		flash_ctrl_rw_derr	5.098m	5.065ms	10	10	100.00
		flash_ctrl_derr_detect	17.907m	200.000ms	1	5	20.00
		flash_ctrl_integrity	11.335m	17.024ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	33.550s	39.282us	5	5	100.00
		flash_ctrl_ro_serr	2.930m	1.316ms	10	10	100.00
		flash_ctrl_rw_serr	4.576m	6.945ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.926m	3.060ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.859m	3.445ms	5	5	100.00
V2	scramble	flash_ctrl_wo	5.927m	25.528ms	19	20	95.00
		flash_ctrl_write_word_sweep	23.550s	41.623us	1	1	100.00
		flash_ctrl_read_word_sweep	21.530s	29.607us	1	1	100.00
		flash_ctrl_ro	2.627m	2.216ms	20	20	100.00
		flash_ctrl_rw	10.282m	12.001ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.125m	1.703ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.138m	159.306ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	6.252m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	28.640s	100.639us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	22.750s	24.915us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	31.130s	69.283us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	31.130s	69.283us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.151m	78.588us	5	5	100.00
		flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
		flash_ctrl_csr_aliasing	1.207m	1.351ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	46.530s	311.365us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.151m	78.588us	5	5	100.00
		flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
		flash_ctrl_csr_aliasing	1.207m	1.351ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	46.530s	311.365us	20	20	100.00
V2		TOTAL			995	1013	98.22
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	27.420s	42.239us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
		flash_ctrl_tl_intg_err	18.838m	718.239us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	18.838m	718.239us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	18.838m	718.239us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	50.540s	69.157us	3	3	100.00
		flash_ctrl_wr_intg	30.340s	69.923us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	6.702m	3.574ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.104m	130.711us	80	80	100.00
		flash_ctrl_disable	44.180s	26.087us	50	50	100.00
		flash_ctrl_sec_info_access	2.066m	16.727ms	50	50	100.00
		flash_ctrl_connect	32.490s	49.451us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	28.790s	96.973us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	28.710s	35.500us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	24.070us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	44.180s	26.087us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	50.540s	69.157us	3	3	100.00
		flash_ctrl_access_after_disable	26.200s	38.458us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	55.740s	98.249us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	44.180s	26.087us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	54.760s	1.771ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.282m	12.001ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.576m	6.945ms	9	10	90.00
		flash_ctrl_rw_derr	5.098m	5.065ms	10	10	100.00
		flash_ctrl_integrity	11.335m	17.024ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.999m	543.604ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	37.530s	835.255us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	25.830s	44.518us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.982m	200.000ms	2	5	40.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.058h	3.941ms	5	5	100.00
V2S		TOTAL			142	147	96.60
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.111m	99.627us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1258	1281	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	11	84.62
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.02	95.22	93.82	98.31	92.52	97.12	96.99	98.15

Failure Buckets

Job timed out after * minutes has 5 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 0.flash_ctrl_intr_wr_slow_flash.45226923776564211271144445657602549469417480176532553129257227669706783763545
    Log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_error_prog_type has 2 failures.
  - 2.flash_ctrl_error_prog_type.68385045226294049238183903784190744202930746487838073412210765282030527517631
    Log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.flash_ctrl_error_prog_type.72098692671045743364255165513785845882557155564003527761204746507920028434305
    Log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_wo has 1 failures.
  - 5.flash_ctrl_wo.95532159001539673751382050119712283244878802486940193801788120436122420801573
    Log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw has 1 failures.
  - 7.flash_ctrl_rw.62586827821006931007846690741616403052511479176204101606845003869965156871662
    Log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test flash_ctrl_derr_detect has 3 failures.

0.flash_ctrl_derr_detect.33457698722015104835174026023958685064882553912137841107695082551728511184917
Line 96, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 33877.0 ns: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 33877.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_derr_detect.30149837926482080251549875375415519003118005574241742068392697542400771786068
Line 96, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 5200.7 ns: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5200.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 3 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 0.flash_ctrl_phy_host_grant_err.49663755115497128872863041001647070353210880138237035653350364890836218993847
    Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log
```
  UVM_ERROR @ 27328.8 ns: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 27328.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_phy_ack_consistency has 2 failures.
  - 0.flash_ctrl_phy_ack_consistency.106178218051581712506071721946318748799997527847232649423040606968272236513441
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 14948.4 ns: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 14948.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_phy_ack_consistency.30377109357795565171105966109621638125065178327344336609309677618528166960990
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 15211.1 ns: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 15211.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 10.flash_ctrl_rw_evict.51414741222925707850806217229598459466392859223959101109970793887059959354263
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 30982.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 30982.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.flash_ctrl_rw_evict.53679089506621370400844582889387211578586330436730451586538478766784201227425
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 11828.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 11828.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 38.flash_ctrl_rw_evict_all_en.27251380315480966715600549783769311039708538423462009964698080554376714900048
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 19115.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 19115.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue has 2 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.15189622354310265467685292101229676903915150726602979328601001320054160465957
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 3.flash_ctrl_phy_ack_consistency.32787956146735686005465405559369565522843702198896146753521539381486387573258
    Line 99, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 2.flash_ctrl_phy_host_grant_err.87249007765142145200362221092007338686272748734505299772255075927130305539832
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 5395.3 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 5395.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:572) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 4.flash_ctrl_rw_serr.66089100309116776756804696785636127358922921354806630288587616916749445802087
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 7886919.4 ns: (flash_ctrl_otf_scoreboard.sv:572) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (40307030067534985531572 [0x8890c6912a00c0190b4] vs 40306741837158833819828 [0x889086912a00c0190b4])
  UVM_INFO @ 7886919.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 4.flash_ctrl_rw_evict.94595909892964718748153580600487328728256941123362906768145032895981675144913
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 42166.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 42166.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c2a3ee4_1143ad1a:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 5.flash_ctrl_intr_rd.62434504147521161512836105372958861918046873667165048181854436395168313057613
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1217608.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    3c2a3ee4_1143ad1a:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1217608.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b176b7ae_464ce42b:ffffffff_464ce42b mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 12.flash_ctrl_intr_rd.70901865988683896808901369700172054711318189523657589157817491802062385866198
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 11512.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    b176b7ae_464ce42b:ffffffff_464ce42b  mismatch!!
  UVM_INFO @ 11512.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f18_af89a9e2:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 15.flash_ctrl_intr_rd.36539081666384921241010629552596029758181122267419164516432561849541344216033
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3274205.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    27143f18_af89a9e2:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3274205.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ca483e_d5fa4028:ffffffff_d5fa* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 23.flash_ctrl_intr_rd.16768917715914235236204505106889450853085857003330339430822620839755120858363
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 9897718.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    25ca483e_d5fa4028:ffffffff_d5fa4028  mismatch!!
  UVM_INFO @ 9897718.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```