| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3191800685 |
|
|
Oct 09 08:24:11 PM UTC 24 |
Oct 09 08:43:33 PM UTC 24 |
58694781700 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.1831928516 |
|
|
Oct 09 08:38:57 PM UTC 24 |
Oct 09 08:43:34 PM UTC 24 |
6227552000 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.946209834 |
|
|
Oct 09 08:43:11 PM UTC 24 |
Oct 09 08:43:35 PM UTC 24 |
39938900 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3368101299 |
|
|
Oct 09 08:43:15 PM UTC 24 |
Oct 09 08:43:36 PM UTC 24 |
15739700 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3152434781 |
|
|
Oct 09 08:43:08 PM UTC 24 |
Oct 09 08:43:36 PM UTC 24 |
21162800 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.470224696 |
|
|
Oct 09 08:43:11 PM UTC 24 |
Oct 09 08:43:38 PM UTC 24 |
16702900 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3877427352 |
|
|
Oct 09 08:41:00 PM UTC 24 |
Oct 09 08:43:43 PM UTC 24 |
269035400 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.2073534829 |
|
|
Oct 09 08:43:25 PM UTC 24 |
Oct 09 08:43:52 PM UTC 24 |
92000900 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.3130563412 |
|
|
Oct 09 08:43:26 PM UTC 24 |
Oct 09 08:43:55 PM UTC 24 |
20758400 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.824142048 |
|
|
Oct 09 08:38:31 PM UTC 24 |
Oct 09 08:44:00 PM UTC 24 |
31972312000 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.122548704 |
|
|
Oct 09 08:40:36 PM UTC 24 |
Oct 09 08:44:14 PM UTC 24 |
1807382500 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2950502268 |
|
|
Oct 09 08:41:20 PM UTC 24 |
Oct 09 08:44:22 PM UTC 24 |
148163100 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.4281212117 |
|
|
Oct 09 08:41:55 PM UTC 24 |
Oct 09 08:44:38 PM UTC 24 |
302794400 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.2483453042 |
|
|
Oct 09 08:41:57 PM UTC 24 |
Oct 09 08:44:39 PM UTC 24 |
69077100 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2850623635 |
|
|
Oct 09 08:41:38 PM UTC 24 |
Oct 09 08:44:42 PM UTC 24 |
574412200 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.2781544299 |
|
|
Oct 09 08:41:11 PM UTC 24 |
Oct 09 08:44:42 PM UTC 24 |
50931300 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.32474880 |
|
|
Oct 09 08:41:40 PM UTC 24 |
Oct 09 08:44:47 PM UTC 24 |
37572500 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.913839940 |
|
|
Oct 09 08:41:32 PM UTC 24 |
Oct 09 08:44:47 PM UTC 24 |
39475200 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1242677548 |
|
|
Oct 09 08:41:32 PM UTC 24 |
Oct 09 08:44:50 PM UTC 24 |
89374700 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.504655096 |
|
|
Oct 09 08:42:02 PM UTC 24 |
Oct 09 08:44:59 PM UTC 24 |
139754500 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2561425468 |
|
|
Oct 09 08:42:45 PM UTC 24 |
Oct 09 08:45:02 PM UTC 24 |
78247000 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.1592657661 |
|
|
Oct 09 08:42:04 PM UTC 24 |
Oct 09 08:45:13 PM UTC 24 |
138507000 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.485730332 |
|
|
Oct 09 08:41:56 PM UTC 24 |
Oct 09 08:45:16 PM UTC 24 |
284502200 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2802938378 |
|
|
Oct 09 08:40:02 PM UTC 24 |
Oct 09 08:45:19 PM UTC 24 |
26357600 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3963991837 |
|
|
Oct 09 08:42:30 PM UTC 24 |
Oct 09 08:45:22 PM UTC 24 |
40201800 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2380870573 |
|
|
Oct 09 08:42:08 PM UTC 24 |
Oct 09 08:45:25 PM UTC 24 |
148970800 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.977964086 |
|
|
Oct 09 08:43:08 PM UTC 24 |
Oct 09 08:45:28 PM UTC 24 |
147698000 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3852979114 |
|
|
Oct 09 08:42:25 PM UTC 24 |
Oct 09 08:45:30 PM UTC 24 |
46129300 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.778365749 |
|
|
Oct 09 08:42:25 PM UTC 24 |
Oct 09 08:45:33 PM UTC 24 |
85910600 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2561958826 |
|
|
Oct 09 08:42:17 PM UTC 24 |
Oct 09 08:45:34 PM UTC 24 |
142445700 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3637648075 |
|
|
Oct 09 08:42:31 PM UTC 24 |
Oct 09 08:45:37 PM UTC 24 |
142819600 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.138852741 |
|
|
Oct 09 08:42:41 PM UTC 24 |
Oct 09 08:45:40 PM UTC 24 |
75747900 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1644010403 |
|
|
Oct 09 08:43:25 PM UTC 24 |
Oct 09 08:45:50 PM UTC 24 |
112524700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.165307756 |
|
|
Oct 09 08:42:35 PM UTC 24 |
Oct 09 08:45:51 PM UTC 24 |
151419700 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.1952057711 |
|
|
Oct 09 08:42:43 PM UTC 24 |
Oct 09 08:45:51 PM UTC 24 |
73142100 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1335064043 |
|
|
Oct 09 08:42:49 PM UTC 24 |
Oct 09 08:45:54 PM UTC 24 |
82382600 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.2568090509 |
|
|
Oct 09 07:53:04 PM UTC 24 |
Oct 09 08:46:00 PM UTC 24 |
5809744800 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1322109126 |
|
|
Oct 09 08:43:13 PM UTC 24 |
Oct 09 08:46:02 PM UTC 24 |
243143600 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2285423491 |
|
|
Oct 09 08:42:50 PM UTC 24 |
Oct 09 08:46:06 PM UTC 24 |
39923700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3628329976 |
|
|
Oct 09 08:38:59 PM UTC 24 |
Oct 09 08:46:09 PM UTC 24 |
171418782500 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1860209463 |
|
|
Oct 09 07:36:23 PM UTC 24 |
Oct 09 08:46:11 PM UTC 24 |
52828500000 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2808721340 |
|
|
Oct 09 08:42:56 PM UTC 24 |
Oct 09 08:46:17 PM UTC 24 |
56303800 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1909927149 |
|
|
Oct 09 08:42:58 PM UTC 24 |
Oct 09 08:46:19 PM UTC 24 |
75133900 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.459243404 |
|
|
Oct 09 08:43:09 PM UTC 24 |
Oct 09 08:46:20 PM UTC 24 |
64077400 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1881614329 |
|
|
Oct 09 08:43:11 PM UTC 24 |
Oct 09 08:46:26 PM UTC 24 |
41139200 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.9710619 |
|
|
Oct 09 08:43:03 PM UTC 24 |
Oct 09 08:46:29 PM UTC 24 |
78415900 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.968087817 |
|
|
Oct 09 08:43:21 PM UTC 24 |
Oct 09 08:46:35 PM UTC 24 |
75952500 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2080749663 |
|
|
Oct 09 08:24:01 PM UTC 24 |
Oct 09 08:47:44 PM UTC 24 |
267331500 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3595638032 |
|
|
Oct 09 08:00:38 PM UTC 24 |
Oct 09 08:48:56 PM UTC 24 |
11721783100 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.512667526 |
|
|
Oct 09 07:57:18 PM UTC 24 |
Oct 09 08:49:25 PM UTC 24 |
14748559200 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1784409282 |
|
|
Oct 09 08:05:17 PM UTC 24 |
Oct 09 08:53:47 PM UTC 24 |
8561326400 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.2425619295 |
|
|
Oct 09 08:25:41 PM UTC 24 |
Oct 09 08:53:51 PM UTC 24 |
1089359400 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1096308674 |
|
|
Oct 09 08:27:16 PM UTC 24 |
Oct 09 08:58:16 PM UTC 24 |
929679900 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1102801878 |
|
|
Oct 09 07:14:44 PM UTC 24 |
Oct 09 09:08:41 PM UTC 24 |
25038612800 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3103814433 |
|
|
Oct 09 07:28:59 PM UTC 24 |
Oct 09 09:17:41 PM UTC 24 |
13645378400 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.857854815 |
|
|
Oct 09 07:38:15 PM UTC 24 |
Oct 09 09:23:50 PM UTC 24 |
10603076800 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2457377875 |
|
|
Oct 09 07:47:36 PM UTC 24 |
Oct 09 09:29:25 PM UTC 24 |
5525817400 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.2607194195 |
|
|
Oct 09 07:42:30 PM UTC 24 |
Oct 09 09:36:02 PM UTC 24 |
1549477900 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3650965293 |
|
|
Oct 09 06:10:50 PM UTC 24 |
Oct 09 06:11:08 PM UTC 24 |
22163100 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1512480181 |
|
|
Oct 09 06:10:46 PM UTC 24 |
Oct 09 06:11:11 PM UTC 24 |
61306200 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2052465029 |
|
|
Oct 09 06:10:50 PM UTC 24 |
Oct 09 06:11:14 PM UTC 24 |
45552000 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.129456065 |
|
|
Oct 09 06:10:50 PM UTC 24 |
Oct 09 06:11:16 PM UTC 24 |
53222900 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2759118574 |
|
|
Oct 09 06:10:50 PM UTC 24 |
Oct 09 06:11:18 PM UTC 24 |
14123000 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2008148022 |
|
|
Oct 09 06:10:48 PM UTC 24 |
Oct 09 06:11:19 PM UTC 24 |
17652300 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1812661974 |
|
|
Oct 09 06:10:51 PM UTC 24 |
Oct 09 06:11:29 PM UTC 24 |
40326300 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2790801569 |
|
|
Oct 09 06:11:08 PM UTC 24 |
Oct 09 06:11:34 PM UTC 24 |
68918000 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1933302241 |
|
|
Oct 09 06:11:18 PM UTC 24 |
Oct 09 06:11:41 PM UTC 24 |
34649700 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2073982273 |
|
|
Oct 09 06:11:26 PM UTC 24 |
Oct 09 06:11:43 PM UTC 24 |
35053400 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.899855900 |
|
|
Oct 09 06:11:17 PM UTC 24 |
Oct 09 06:11:46 PM UTC 24 |
39606300 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.705704815 |
|
|
Oct 09 06:11:16 PM UTC 24 |
Oct 09 06:11:47 PM UTC 24 |
163101000 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2262135525 |
|
|
Oct 09 06:11:29 PM UTC 24 |
Oct 09 06:11:56 PM UTC 24 |
17025800 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3999043237 |
|
|
Oct 09 06:11:25 PM UTC 24 |
Oct 09 06:11:57 PM UTC 24 |
33195200 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1776693992 |
|
|
Oct 09 06:11:34 PM UTC 24 |
Oct 09 06:11:57 PM UTC 24 |
100736100 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2256600070 |
|
|
Oct 09 06:11:43 PM UTC 24 |
Oct 09 06:12:05 PM UTC 24 |
119427100 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3471938198 |
|
|
Oct 09 06:11:13 PM UTC 24 |
Oct 09 06:12:10 PM UTC 24 |
1527989500 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1256011416 |
|
|
Oct 09 06:11:47 PM UTC 24 |
Oct 09 06:12:17 PM UTC 24 |
36649400 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2697596500 |
|
|
Oct 09 06:11:45 PM UTC 24 |
Oct 09 06:12:23 PM UTC 24 |
55037400 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.512064308 |
|
|
Oct 09 06:11:58 PM UTC 24 |
Oct 09 06:12:28 PM UTC 24 |
209821700 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2333718495 |
|
|
Oct 09 06:11:58 PM UTC 24 |
Oct 09 06:12:33 PM UTC 24 |
43514300 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.869286020 |
|
|
Oct 09 06:12:12 PM UTC 24 |
Oct 09 06:12:35 PM UTC 24 |
24222900 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.238937663 |
|
|
Oct 09 06:11:15 PM UTC 24 |
Oct 09 06:12:39 PM UTC 24 |
4941430500 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.801329107 |
|
|
Oct 09 06:12:15 PM UTC 24 |
Oct 09 06:12:42 PM UTC 24 |
18031600 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2349802355 |
|
|
Oct 09 06:12:18 PM UTC 24 |
Oct 09 06:12:45 PM UTC 24 |
52105400 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4083512645 |
|
|
Oct 09 06:12:28 PM UTC 24 |
Oct 09 06:12:49 PM UTC 24 |
32013900 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4055272104 |
|
|
Oct 09 06:12:24 PM UTC 24 |
Oct 09 06:12:50 PM UTC 24 |
57651000 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1493859641 |
|
|
Oct 09 06:12:34 PM UTC 24 |
Oct 09 06:13:02 PM UTC 24 |
41561400 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.678673626 |
|
|
Oct 09 06:12:43 PM UTC 24 |
Oct 09 06:13:03 PM UTC 24 |
54776700 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1270972986 |
|
|
Oct 09 06:11:57 PM UTC 24 |
Oct 09 06:13:04 PM UTC 24 |
258852400 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1840762525 |
|
|
Oct 09 06:14:09 PM UTC 24 |
Oct 09 06:14:40 PM UTC 24 |
469343700 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2002567710 |
|
|
Oct 09 06:12:29 PM UTC 24 |
Oct 09 06:13:07 PM UTC 24 |
34455500 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3691700571 |
|
|
Oct 09 06:12:40 PM UTC 24 |
Oct 09 06:13:11 PM UTC 24 |
87810900 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2076755704 |
|
|
Oct 09 06:12:50 PM UTC 24 |
Oct 09 06:13:13 PM UTC 24 |
12346000 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.873453842 |
|
|
Oct 09 06:12:46 PM UTC 24 |
Oct 09 06:13:20 PM UTC 24 |
138555700 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.973697166 |
|
|
Oct 09 06:13:03 PM UTC 24 |
Oct 09 06:13:23 PM UTC 24 |
17777500 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.559512635 |
|
|
Oct 09 06:13:01 PM UTC 24 |
Oct 09 06:13:29 PM UTC 24 |
11760800 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2993308989 |
|
|
Oct 09 06:13:08 PM UTC 24 |
Oct 09 06:13:30 PM UTC 24 |
174776300 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2271770408 |
|
|
Oct 09 06:13:02 PM UTC 24 |
Oct 09 06:13:31 PM UTC 24 |
16661100 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3170439631 |
|
|
Oct 09 06:13:04 PM UTC 24 |
Oct 09 06:13:31 PM UTC 24 |
30255700 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2543278269 |
|
|
Oct 09 06:11:48 PM UTC 24 |
Oct 09 06:13:31 PM UTC 24 |
2465939700 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2624806056 |
|
|
Oct 09 06:11:49 PM UTC 24 |
Oct 09 06:13:35 PM UTC 24 |
1558361600 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2224193782 |
|
|
Oct 09 06:12:37 PM UTC 24 |
Oct 09 06:13:43 PM UTC 24 |
1284740800 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2279317171 |
|
|
Oct 09 06:12:38 PM UTC 24 |
Oct 09 06:13:43 PM UTC 24 |
3004482000 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1397819241 |
|
|
Oct 09 06:13:20 PM UTC 24 |
Oct 09 06:13:44 PM UTC 24 |
64714100 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3086832474 |
|
|
Oct 09 06:13:14 PM UTC 24 |
Oct 09 06:13:44 PM UTC 24 |
846787800 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1897572022 |
|
|
Oct 09 06:13:24 PM UTC 24 |
Oct 09 06:13:53 PM UTC 24 |
394934700 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.3883354854 |
|
|
Oct 09 06:13:32 PM UTC 24 |
Oct 09 06:13:54 PM UTC 24 |
25714200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2350638315 |
|
|
Oct 09 06:13:33 PM UTC 24 |
Oct 09 06:13:57 PM UTC 24 |
80090900 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2125970582 |
|
|
Oct 09 06:13:32 PM UTC 24 |
Oct 09 06:14:00 PM UTC 24 |
126030500 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.529313317 |
|
|
Oct 09 06:13:31 PM UTC 24 |
Oct 09 06:14:02 PM UTC 24 |
11857600 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2664815344 |
|
|
Oct 09 06:13:36 PM UTC 24 |
Oct 09 06:14:03 PM UTC 24 |
48339200 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3729947830 |
|
|
Oct 09 06:13:45 PM UTC 24 |
Oct 09 06:14:08 PM UTC 24 |
269586400 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1409860262 |
|
|
Oct 09 06:13:44 PM UTC 24 |
Oct 09 06:14:08 PM UTC 24 |
94523600 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1881616889 |
|
|
Oct 09 06:13:14 PM UTC 24 |
Oct 09 06:14:08 PM UTC 24 |
842714100 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.359417751 |
|
|
Oct 09 06:13:12 PM UTC 24 |
Oct 09 06:14:13 PM UTC 24 |
1466239100 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.925824312 |
|
|
Oct 09 06:13:49 PM UTC 24 |
Oct 09 06:14:25 PM UTC 24 |
209524900 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1950783523 |
|
|
Oct 09 06:13:58 PM UTC 24 |
Oct 09 06:14:27 PM UTC 24 |
12764800 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.3305970915 |
|
|
Oct 09 06:14:03 PM UTC 24 |
Oct 09 06:14:31 PM UTC 24 |
51715200 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4259583150 |
|
|
Oct 09 06:14:01 PM UTC 24 |
Oct 09 06:14:31 PM UTC 24 |
18512800 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2529016188 |
|
|
Oct 09 06:13:05 PM UTC 24 |
Oct 09 06:14:31 PM UTC 24 |
118005200 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4270136559 |
|
|
Oct 09 06:13:55 PM UTC 24 |
Oct 09 06:14:34 PM UTC 24 |
61630100 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4041254882 |
|
|
Oct 09 06:14:04 PM UTC 24 |
Oct 09 06:14:34 PM UTC 24 |
29804700 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2510398797 |
|
|
Oct 09 06:14:09 PM UTC 24 |
Oct 09 06:14:39 PM UTC 24 |
48049500 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1857417979 |
|
|
Oct 09 06:14:08 PM UTC 24 |
Oct 09 06:14:45 PM UTC 24 |
587469700 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3634584399 |
|
|
Oct 09 06:13:42 PM UTC 24 |
Oct 09 06:14:46 PM UTC 24 |
20370800 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3889455785 |
|
|
Oct 09 06:13:45 PM UTC 24 |
Oct 09 06:14:53 PM UTC 24 |
440193800 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.500686222 |
|
|
Oct 09 06:14:26 PM UTC 24 |
Oct 09 06:14:54 PM UTC 24 |
21692300 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2339735580 |
|
|
Oct 09 06:14:32 PM UTC 24 |
Oct 09 06:14:55 PM UTC 24 |
251959100 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1821057704 |
|
|
Oct 09 06:14:32 PM UTC 24 |
Oct 09 06:14:58 PM UTC 24 |
101888700 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3649964107 |
|
|
Oct 09 06:14:34 PM UTC 24 |
Oct 09 06:14:59 PM UTC 24 |
29366200 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1912140488 |
|
|
Oct 09 06:14:28 PM UTC 24 |
Oct 09 06:15:00 PM UTC 24 |
13892800 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3367921172 |
|
|
Oct 09 06:14:34 PM UTC 24 |
Oct 09 06:15:05 PM UTC 24 |
150416700 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3131093019 |
|
|
Oct 09 06:14:32 PM UTC 24 |
Oct 09 06:15:06 PM UTC 24 |
739672100 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.552300123 |
|
|
Oct 09 06:14:40 PM UTC 24 |
Oct 09 06:15:07 PM UTC 24 |
11996800 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.793886230 |
|
|
Oct 09 06:13:44 PM UTC 24 |
Oct 09 06:15:07 PM UTC 24 |
662475200 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4023004903 |
|
|
Oct 09 06:14:40 PM UTC 24 |
Oct 09 06:15:08 PM UTC 24 |
16663100 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2101526747 |
|
|
Oct 09 06:14:41 PM UTC 24 |
Oct 09 06:15:08 PM UTC 24 |
14515100 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1634693549 |
|
|
Oct 09 06:14:47 PM UTC 24 |
Oct 09 06:15:10 PM UTC 24 |
216386300 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.34266709 |
|
|
Oct 09 06:14:46 PM UTC 24 |
Oct 09 06:15:16 PM UTC 24 |
149547700 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.536534173 |
|
|
Oct 09 06:15:00 PM UTC 24 |
Oct 09 06:15:21 PM UTC 24 |
12067800 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3554810832 |
|
|
Oct 09 06:14:54 PM UTC 24 |
Oct 09 06:15:25 PM UTC 24 |
36214600 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.688889669 |
|
|
Oct 09 06:15:01 PM UTC 24 |
Oct 09 06:15:26 PM UTC 24 |
14241400 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1105218529 |
|
|
Oct 09 06:14:54 PM UTC 24 |
Oct 09 06:15:28 PM UTC 24 |
203496400 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.889859013 |
|
|
Oct 09 06:14:58 PM UTC 24 |
Oct 09 06:15:31 PM UTC 24 |
11633900 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1414981188 |
|
|
Oct 09 06:15:06 PM UTC 24 |
Oct 09 06:15:34 PM UTC 24 |
56607900 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.656015702 |
|
|
Oct 09 06:15:10 PM UTC 24 |
Oct 09 06:15:34 PM UTC 24 |
32017800 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3902977826 |
|
|
Oct 09 06:15:08 PM UTC 24 |
Oct 09 06:15:34 PM UTC 24 |
80536600 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1637842293 |
|
|
Oct 09 06:15:07 PM UTC 24 |
Oct 09 06:15:38 PM UTC 24 |
1673835000 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1006418668 |
|
|
Oct 09 06:15:12 PM UTC 24 |
Oct 09 06:15:41 PM UTC 24 |
15592500 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3422563594 |
|
|
Oct 09 06:15:09 PM UTC 24 |
Oct 09 06:15:41 PM UTC 24 |
22693600 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1946912091 |
|
|
Oct 09 06:15:08 PM UTC 24 |
Oct 09 06:15:44 PM UTC 24 |
44367600 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3459981754 |
|
|
Oct 09 06:15:17 PM UTC 24 |
Oct 09 06:15:48 PM UTC 24 |
127513900 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3450009315 |
|
|
Oct 09 06:15:25 PM UTC 24 |
Oct 09 06:15:51 PM UTC 24 |
227493000 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3426513390 |
|
|
Oct 09 06:15:34 PM UTC 24 |
Oct 09 06:15:54 PM UTC 24 |
55386700 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3215832573 |
|
|
Oct 09 06:15:26 PM UTC 24 |
Oct 09 06:15:54 PM UTC 24 |
74490800 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.650175879 |
|
|
Oct 09 06:15:21 PM UTC 24 |
Oct 09 06:15:58 PM UTC 24 |
751352400 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2973077682 |
|
|
Oct 09 06:15:32 PM UTC 24 |
Oct 09 06:15:59 PM UTC 24 |
23509300 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3927234032 |
|
|
Oct 09 06:15:33 PM UTC 24 |
Oct 09 06:16:04 PM UTC 24 |
34074500 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.275219823 |
|
|
Oct 09 06:15:40 PM UTC 24 |
Oct 09 06:16:06 PM UTC 24 |
107955000 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3304878682 |
|
|
Oct 09 06:15:35 PM UTC 24 |
Oct 09 06:16:10 PM UTC 24 |
47220400 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2446257709 |
|
|
Oct 09 06:15:42 PM UTC 24 |
Oct 09 06:16:11 PM UTC 24 |
33032300 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3713111317 |
|
|
Oct 09 06:15:45 PM UTC 24 |
Oct 09 06:16:12 PM UTC 24 |
29320700 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1224320092 |
|
|
Oct 09 06:15:39 PM UTC 24 |
Oct 09 06:16:14 PM UTC 24 |
146153200 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3763036335 |
|
|
Oct 09 06:15:45 PM UTC 24 |
Oct 09 06:16:16 PM UTC 24 |
36736000 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1455779649 |
|
|
Oct 09 06:15:49 PM UTC 24 |
Oct 09 06:16:17 PM UTC 24 |
31942500 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1711156427 |
|
|
Oct 09 06:15:35 PM UTC 24 |
Oct 09 06:16:18 PM UTC 24 |
60512000 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4025212101 |
|
|
Oct 09 06:15:55 PM UTC 24 |
Oct 09 06:16:24 PM UTC 24 |
39052400 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2190873186 |
|
|
Oct 09 06:15:52 PM UTC 24 |
Oct 09 06:16:25 PM UTC 24 |
463646000 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1362145319 |
|
|
Oct 09 06:16:05 PM UTC 24 |
Oct 09 06:16:26 PM UTC 24 |
17633600 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.506229404 |
|
|
Oct 09 06:15:54 PM UTC 24 |
Oct 09 06:16:27 PM UTC 24 |
84636000 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2942082612 |
|
|
Oct 09 06:15:59 PM UTC 24 |
Oct 09 06:16:32 PM UTC 24 |
35765600 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2646743265 |
|
|
Oct 09 06:16:12 PM UTC 24 |
Oct 09 06:16:34 PM UTC 24 |
28071100 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2457249081 |
|
|
Oct 09 06:16:04 PM UTC 24 |
Oct 09 06:16:36 PM UTC 24 |
12234300 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.797136953 |
|
|
Oct 09 06:16:16 PM UTC 24 |
Oct 09 06:16:41 PM UTC 24 |
38949000 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2077910283 |
|
|
Oct 09 06:16:07 PM UTC 24 |
Oct 09 06:16:42 PM UTC 24 |
58212900 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.519892475 |
|
|
Oct 09 06:16:12 PM UTC 24 |
Oct 09 06:16:45 PM UTC 24 |
229264100 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1049053074 |
|
|
Oct 09 06:16:20 PM UTC 24 |
Oct 09 06:16:46 PM UTC 24 |
23849100 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3218632157 |
|
|
Oct 09 06:16:17 PM UTC 24 |
Oct 09 06:16:48 PM UTC 24 |
14898600 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4096782280 |
|
|
Oct 09 06:16:26 PM UTC 24 |
Oct 09 06:16:49 PM UTC 24 |
296667100 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3007274801 |
|
|
Oct 09 06:16:25 PM UTC 24 |
Oct 09 06:16:49 PM UTC 24 |
26438200 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1481287739 |
|
|
Oct 09 06:16:29 PM UTC 24 |
Oct 09 06:16:57 PM UTC 24 |
87610200 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4226615415 |
|
|
Oct 09 06:16:29 PM UTC 24 |
Oct 09 06:16:57 PM UTC 24 |
414398300 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2348925060 |
|
|
Oct 09 06:16:33 PM UTC 24 |
Oct 09 06:17:00 PM UTC 24 |
68256000 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.168373182 |
|
|
Oct 09 06:16:35 PM UTC 24 |
Oct 09 06:17:01 PM UTC 24 |
14654300 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1003107681 |
|
|
Oct 09 06:16:40 PM UTC 24 |
Oct 09 06:17:02 PM UTC 24 |
36696700 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.161091762 |
|
|
Oct 09 06:16:39 PM UTC 24 |
Oct 09 06:17:08 PM UTC 24 |
46593900 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1472613526 |
|
|
Oct 09 06:16:10 PM UTC 24 |
Oct 09 06:17:08 PM UTC 24 |
704850300 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2859925417 |
|
|
Oct 09 06:16:45 PM UTC 24 |
Oct 09 06:17:08 PM UTC 24 |
49144000 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2039753927 |
|
|
Oct 09 06:16:47 PM UTC 24 |
Oct 09 06:17:11 PM UTC 24 |
41792900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3479437595 |
|
|
Oct 09 06:16:50 PM UTC 24 |
Oct 09 06:17:11 PM UTC 24 |
222127100 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.964109675 |
|
|
Oct 09 06:16:50 PM UTC 24 |
Oct 09 06:17:13 PM UTC 24 |
59081800 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3063852157 |
|
|
Oct 09 06:16:43 PM UTC 24 |
Oct 09 06:17:14 PM UTC 24 |
53201200 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3778990787 |
|
|
Oct 09 06:16:58 PM UTC 24 |
Oct 09 06:17:21 PM UTC 24 |
36392500 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3333063085 |
|
|
Oct 09 06:16:49 PM UTC 24 |
Oct 09 06:17:21 PM UTC 24 |
34217100 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2761831356 |
|
|
Oct 09 06:17:03 PM UTC 24 |
Oct 09 06:17:27 PM UTC 24 |
21298200 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1490999548 |
|
|
Oct 09 06:17:01 PM UTC 24 |
Oct 09 06:17:28 PM UTC 24 |
52408200 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.941776563 |
|
|
Oct 09 06:17:10 PM UTC 24 |
Oct 09 06:17:29 PM UTC 24 |
28205500 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3286660148 |
|
|
Oct 09 06:17:09 PM UTC 24 |
Oct 09 06:17:30 PM UTC 24 |
23518500 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2880493284 |
|
|
Oct 09 06:17:08 PM UTC 24 |
Oct 09 06:17:34 PM UTC 24 |
103692100 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.410666125 |
|
|
Oct 09 06:17:22 PM UTC 24 |
Oct 09 06:17:42 PM UTC 24 |
36900000 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.234138626 |
|
|
Oct 09 06:16:42 PM UTC 24 |
Oct 09 06:17:45 PM UTC 24 |
112609500 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3146753768 |
|
|
Oct 09 06:17:14 PM UTC 24 |
Oct 09 06:17:45 PM UTC 24 |
38130600 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4282497327 |
|
|
Oct 09 06:16:57 PM UTC 24 |
Oct 09 06:17:46 PM UTC 24 |
722563800 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.468362451 |
|
|
Oct 09 06:17:12 PM UTC 24 |
Oct 09 06:17:47 PM UTC 24 |
35020300 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.3004062839 |
|
|
Oct 09 06:17:28 PM UTC 24 |
Oct 09 06:17:48 PM UTC 24 |
28444400 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.446977277 |
|
|
Oct 09 06:17:22 PM UTC 24 |
Oct 09 06:17:49 PM UTC 24 |
84084100 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1348740199 |
|
|
Oct 09 06:17:12 PM UTC 24 |
Oct 09 06:17:50 PM UTC 24 |
947707300 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.993983658 |
|
|
Oct 09 06:17:29 PM UTC 24 |
Oct 09 06:17:53 PM UTC 24 |
568804700 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2870457579 |
|
|
Oct 09 06:17:29 PM UTC 24 |
Oct 09 06:17:53 PM UTC 24 |
95440400 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2999394717 |
|
|
Oct 09 06:17:31 PM UTC 24 |
Oct 09 06:18:04 PM UTC 24 |
137117700 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.156862794 |
|
|
Oct 09 06:17:45 PM UTC 24 |
Oct 09 06:18:05 PM UTC 24 |
16096700 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3080698499 |
|
|
Oct 09 06:17:47 PM UTC 24 |
Oct 09 06:18:06 PM UTC 24 |
213810500 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1573926709 |
|
|
Oct 09 06:17:30 PM UTC 24 |
Oct 09 06:18:06 PM UTC 24 |
414076400 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3019318089 |
|
|
Oct 09 06:17:47 PM UTC 24 |
Oct 09 06:18:13 PM UTC 24 |
15593200 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3331103763 |
|
|
Oct 09 06:17:42 PM UTC 24 |
Oct 09 06:18:13 PM UTC 24 |
17093700 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2592317791 |
|
|
Oct 09 06:17:54 PM UTC 24 |
Oct 09 06:18:17 PM UTC 24 |
167452600 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3427160051 |
|
|
Oct 09 06:17:49 PM UTC 24 |
Oct 09 06:18:18 PM UTC 24 |
72620100 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4068666418 |
|
|
Oct 09 06:17:54 PM UTC 24 |
Oct 09 06:18:18 PM UTC 24 |
124706000 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.477582030 |
|
|
Oct 09 06:17:50 PM UTC 24 |
Oct 09 06:18:21 PM UTC 24 |
57799100 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.56824946 |
|
|
Oct 09 06:17:48 PM UTC 24 |
Oct 09 06:18:23 PM UTC 24 |
125569500 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3081607254 |
|
|
Oct 09 06:18:04 PM UTC 24 |
Oct 09 06:18:27 PM UTC 24 |
104750500 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.148085099 |
|
|
Oct 09 06:18:07 PM UTC 24 |
Oct 09 06:18:29 PM UTC 24 |
237647500 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4036287095 |
|
|
Oct 09 06:18:06 PM UTC 24 |
Oct 09 06:18:35 PM UTC 24 |
20055000 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2353637158 |
|
|
Oct 09 06:18:14 PM UTC 24 |
Oct 09 06:18:35 PM UTC 24 |
14906100 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1075292118 |
|
|
Oct 09 06:18:14 PM UTC 24 |
Oct 09 06:18:36 PM UTC 24 |
54252500 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3964254921 |
|
|
Oct 09 06:18:06 PM UTC 24 |
Oct 09 06:18:38 PM UTC 24 |
68678500 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3047425539 |
|
|
Oct 09 06:18:18 PM UTC 24 |
Oct 09 06:18:39 PM UTC 24 |
17063400 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.430579259 |
|
|
Oct 09 06:18:13 PM UTC 24 |
Oct 09 06:18:40 PM UTC 24 |
16986100 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1053093966 |
|
|
Oct 09 06:18:21 PM UTC 24 |
Oct 09 06:18:44 PM UTC 24 |
32184700 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1485610573 |
|
|
Oct 09 06:18:19 PM UTC 24 |
Oct 09 06:18:45 PM UTC 24 |
18381000 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2282489077 |
|
|
Oct 09 06:18:19 PM UTC 24 |
Oct 09 06:18:45 PM UTC 24 |
52682500 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2035721249 |
|
|
Oct 09 06:18:28 PM UTC 24 |
Oct 09 06:18:47 PM UTC 24 |
69582200 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1703845720 |
|
|
Oct 09 06:18:23 PM UTC 24 |
Oct 09 06:18:49 PM UTC 24 |
31576100 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.2958961092 |
|
|
Oct 09 06:18:37 PM UTC 24 |
Oct 09 06:18:54 PM UTC 24 |
18306600 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.3710278607 |
|
|
Oct 09 06:18:30 PM UTC 24 |
Oct 09 06:18:56 PM UTC 24 |
214499800 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2917909072 |
|
|
Oct 09 06:18:40 PM UTC 24 |
Oct 09 06:19:02 PM UTC 24 |
58236100 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3422312795 |
|
|
Oct 09 06:18:45 PM UTC 24 |
Oct 09 06:19:03 PM UTC 24 |
14461600 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.601934501 |
|
|
Oct 09 06:18:36 PM UTC 24 |
Oct 09 06:19:05 PM UTC 24 |
55196300 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1385588494 |
|
|
Oct 09 06:18:36 PM UTC 24 |
Oct 09 06:19:05 PM UTC 24 |
17928100 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.857695660 |
|
|
Oct 09 06:18:38 PM UTC 24 |
Oct 09 06:19:06 PM UTC 24 |
15764000 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2609869801 |
|
|
Oct 09 06:18:40 PM UTC 24 |
Oct 09 06:19:08 PM UTC 24 |
42479100 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.119469974 |
|
|
Oct 09 06:18:45 PM UTC 24 |
Oct 09 06:19:09 PM UTC 24 |
25912400 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2504695825 |
|
|
Oct 09 06:18:50 PM UTC 24 |
Oct 09 06:19:10 PM UTC 24 |
16911000 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3433586202 |
|
|
Oct 09 06:18:44 PM UTC 24 |
Oct 09 06:19:12 PM UTC 24 |
252952800 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.738406293 |
|
|
Oct 09 06:18:48 PM UTC 24 |
Oct 09 06:19:13 PM UTC 24 |
19057900 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.386409569 |
|
|
Oct 09 06:18:55 PM UTC 24 |
Oct 09 06:19:16 PM UTC 24 |
56325300 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2716708537 |
|
|
Oct 09 06:18:54 PM UTC 24 |
Oct 09 06:19:21 PM UTC 24 |
25427300 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.4169281364 |
|
|
Oct 09 06:18:56 PM UTC 24 |
Oct 09 06:19:23 PM UTC 24 |
56523100 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.3428869335 |
|
|
Oct 09 06:19:07 PM UTC 24 |
Oct 09 06:19:24 PM UTC 24 |
58605000 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.4111700634 |
|
|
Oct 09 06:19:06 PM UTC 24 |
Oct 09 06:19:26 PM UTC 24 |
79448400 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.741492437 |
|
|
Oct 09 06:19:02 PM UTC 24 |
Oct 09 06:19:28 PM UTC 24 |
51797100 ps |