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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 95.23 93.83 98.31 92.52 97.16 97.27 98.18


Total test records in report: 1273
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T1271 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3804012416 Oct 09 06:19:06 PM UTC 24 Oct 09 06:19:28 PM UTC 24 46532600 ps
T1272 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1559389413 Oct 09 06:19:04 PM UTC 24 Oct 09 06:19:29 PM UTC 24 27934300 ps
T1273 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.1288402651 Oct 09 06:19:09 PM UTC 24 Oct 09 06:19:31 PM UTC 24 57147900 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1323793419 Oct 09 06:13:31 PM UTC 24 Oct 09 06:23:55 PM UTC 24 351267400 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2224669346 Oct 09 06:16:30 PM UTC 24 Oct 09 06:26:04 PM UTC 24 337762500 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1371820280 Oct 09 06:14:38 PM UTC 24 Oct 09 06:26:24 PM UTC 24 462740400 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.994759811 Oct 09 06:15:41 PM UTC 24 Oct 09 06:26:42 PM UTC 24 503167700 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2991581569 Oct 09 06:15:58 PM UTC 24 Oct 09 06:27:02 PM UTC 24 855721900 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2410528150 Oct 09 06:14:55 PM UTC 24 Oct 09 06:27:11 PM UTC 24 322169400 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.339892800 Oct 09 06:17:51 PM UTC 24 Oct 09 06:27:58 PM UTC 24 367618000 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.705571605 Oct 09 06:16:46 PM UTC 24 Oct 09 06:28:27 PM UTC 24 1272159400 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.730818602 Oct 09 06:10:48 PM UTC 24 Oct 09 06:28:44 PM UTC 24 501108700 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.474657974 Oct 09 06:17:02 PM UTC 24 Oct 09 06:29:18 PM UTC 24 446828800 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1094185655 Oct 09 06:17:35 PM UTC 24 Oct 09 06:29:40 PM UTC 24 795435400 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.681164675 Oct 09 06:11:20 PM UTC 24 Oct 09 06:33:45 PM UTC 24 1393566400 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2209494581 Oct 09 06:12:05 PM UTC 24 Oct 09 06:33:52 PM UTC 24 1308910800 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.843200529 Oct 09 06:12:50 PM UTC 24 Oct 09 06:34:38 PM UTC 24 1378696200 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3703002999 Oct 09 06:17:15 PM UTC 24 Oct 09 06:37:08 PM UTC 24 714804700 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3101015994 Oct 09 06:13:55 PM UTC 24 Oct 09 06:37:37 PM UTC 24 1030620900 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3243665048 Oct 09 06:14:14 PM UTC 24 Oct 09 06:38:11 PM UTC 24 4817186700 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.323937220 Oct 09 06:15:09 PM UTC 24 Oct 09 06:38:25 PM UTC 24 749435900 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1644769515 Oct 09 06:15:30 PM UTC 24 Oct 09 06:39:38 PM UTC 24 670749700 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1744604183 Oct 09 06:16:15 PM UTC 24 Oct 09 06:40:49 PM UTC 24 665371500 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3271395311
Short name T12
Test name
Test status
Simulation time 1396902700 ps
CPU time 31.76 seconds
Started Oct 09 07:06:31 PM UTC 24
Finished Oct 09 07:07:04 PM UTC 24
Peak memory 275392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32
71395311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc
h_code.3271395311
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3309074478
Short name T11
Test name
Test status
Simulation time 8645530900 ps
CPU time 115.74 seconds
Started Oct 09 07:08:38 PM UTC 24
Finished Oct 09 07:10:37 PM UTC 24
Peak memory 271192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309074478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3309074478
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2291773828
Short name T4
Test name
Test status
Simulation time 72422100 ps
CPU time 210.3 seconds
Started Oct 09 07:05:19 PM UTC 24
Finished Oct 09 07:08:54 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291773828 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.2291773828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.899855900
Short name T77
Test name
Test status
Simulation time 39606300 ps
CPU time 27.85 seconds
Started Oct 09 06:11:17 PM UTC 24
Finished Oct 09 06:11:46 PM UTC 24
Peak memory 286644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=899855900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.899855900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3693167144
Short name T50
Test name
Test status
Simulation time 2534812200 ps
CPU time 215.1 seconds
Started Oct 09 07:10:31 PM UTC 24
Finished Oct 09 07:14:11 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3693167144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.3693167144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.211846843
Short name T29
Test name
Test status
Simulation time 15385712500 ps
CPU time 534.09 seconds
Started Oct 09 07:05:41 PM UTC 24
Finished Oct 09 07:14:44 PM UTC 24
Peak memory 283520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=211846843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_mp_regions.211846843
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2624806056
Short name T276
Test name
Test status
Simulation time 1558361600 ps
CPU time 103.49 seconds
Started Oct 09 06:11:49 PM UTC 24
Finished Oct 09 06:13:35 PM UTC 24
Peak memory 274300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624806056 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.2624806056
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.857854815
Short name T16
Test name
Test status
Simulation time 10603076800 ps
CPU time 6268.84 seconds
Started Oct 09 07:38:15 PM UTC 24
Finished Oct 09 09:23:50 PM UTC 24
Peak memory 316240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857854815 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.857854815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1468251436
Short name T99
Test name
Test status
Simulation time 168993621600 ps
CPU time 1986.99 seconds
Started Oct 09 07:04:43 PM UTC 24
Finished Oct 09 07:38:19 PM UTC 24
Peak memory 277828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468251436
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.1468251436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.2032973229
Short name T81
Test name
Test status
Simulation time 1257708500 ps
CPU time 104.84 seconds
Started Oct 09 07:36:27 PM UTC 24
Finished Oct 09 07:38:15 PM UTC 24
Peak memory 270936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032973229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2032973229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.539359560
Short name T46
Test name
Test status
Simulation time 12507093600 ps
CPU time 374.6 seconds
Started Oct 09 07:13:11 PM UTC 24
Finished Oct 09 07:19:33 PM UTC 24
Peak memory 304168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=539359560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_rd_slow_flash.539359560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2543278269
Short name T291
Test name
Test status
Simulation time 2465939700 ps
CPU time 101.08 seconds
Started Oct 09 06:11:48 PM UTC 24
Finished Oct 09 06:13:31 PM UTC 24
Peak memory 274236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543278269 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.2543278269
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3123452590
Short name T7
Test name
Test status
Simulation time 46648400 ps
CPU time 24.64 seconds
Started Oct 09 07:15:10 PM UTC 24
Finished Oct 09 07:15:36 PM UTC 24
Peak memory 271444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3123452590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_wr_intg.3123452590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1526949047
Short name T114
Test name
Test status
Simulation time 73224578700 ps
CPU time 195.98 seconds
Started Oct 09 07:17:05 PM UTC 24
Finished Oct 09 07:20:24 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526949047 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.1526949047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.246293378
Short name T788
Test name
Test status
Simulation time 71967200 ps
CPU time 183.58 seconds
Started Oct 09 08:27:23 PM UTC 24
Finished Oct 09 08:30:30 PM UTC 24
Peak memory 271408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246293378 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.246293378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2052465029
Short name T225
Test name
Test status
Simulation time 45552000 ps
CPU time 22.71 seconds
Started Oct 09 06:10:50 PM UTC 24
Finished Oct 09 06:11:14 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052465029 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2052465029
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.730818602
Short name T345
Test name
Test status
Simulation time 501108700 ps
CPU time 1062.22 seconds
Started Oct 09 06:10:48 PM UTC 24
Finished Oct 09 06:28:44 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730818602 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.730818602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1672408646
Short name T172
Test name
Test status
Simulation time 51787500 ps
CPU time 184.11 seconds
Started Oct 09 08:30:02 PM UTC 24
Finished Oct 09 08:33:09 PM UTC 24
Peak memory 275636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672408646 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.1672408646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1433692496
Short name T62
Test name
Test status
Simulation time 1204431100 ps
CPU time 206.63 seconds
Started Oct 09 07:11:39 PM UTC 24
Finished Oct 09 07:15:09 PM UTC 24
Peak memory 296200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1433692496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rw_derr.1433692496
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.27970573
Short name T40
Test name
Test status
Simulation time 1625275100 ps
CPU time 93.53 seconds
Started Oct 09 07:14:45 PM UTC 24
Finished Oct 09 07:16:21 PM UTC 24
Peak memory 275120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27970573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.27970573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1512480181
Short name T125
Test name
Test status
Simulation time 61306200 ps
CPU time 24.22 seconds
Started Oct 09 06:10:46 PM UTC 24
Finished Oct 09 06:11:11 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512480181 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1512480181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2983213037
Short name T98
Test name
Test status
Simulation time 165690267800 ps
CPU time 1043.88 seconds
Started Oct 09 07:15:57 PM UTC 24
Finished Oct 09 07:33:36 PM UTC 24
Peak memory 275748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2983213037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_rma_err.2983213037
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4264466975
Short name T32
Test name
Test status
Simulation time 916197700 ps
CPU time 95.87 seconds
Started Oct 09 07:08:31 PM UTC 24
Finished Oct 09 07:10:10 PM UTC 24
Peak memory 275012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264466975 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4264466975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.4172461997
Short name T110
Test name
Test status
Simulation time 34312600 ps
CPU time 22.52 seconds
Started Oct 09 07:16:20 PM UTC 24
Finished Oct 09 07:16:44 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172461997 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.4172461997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.3869979625
Short name T927
Test name
Test status
Simulation time 144936300 ps
CPU time 164.43 seconds
Started Oct 09 08:34:41 PM UTC 24
Finished Oct 09 08:37:28 PM UTC 24
Peak memory 271196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869979625 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.3869979625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.418732840
Short name T78
Test name
Test status
Simulation time 671980400 ps
CPU time 142.86 seconds
Started Oct 09 07:40:29 PM UTC 24
Finished Oct 09 07:42:55 PM UTC 24
Peak memory 270940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418732840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.418732840
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1566856621
Short name T133
Test name
Test status
Simulation time 269232861000 ps
CPU time 3183.18 seconds
Started Oct 09 07:05:19 PM UTC 24
Finished Oct 09 07:59:03 PM UTC 24
Peak memory 278184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566856621 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.1566856621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3295579308
Short name T67
Test name
Test status
Simulation time 858247300 ps
CPU time 107.22 seconds
Started Oct 09 07:20:26 PM UTC 24
Finished Oct 09 07:22:16 PM UTC 24
Peak memory 270936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295579308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3295579308
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1812661974
Short name T75
Test name
Test status
Simulation time 40326300 ps
CPU time 36.28 seconds
Started Oct 09 06:10:51 PM UTC 24
Finished Oct 09 06:11:29 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812661974 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.1812661974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2664815344
Short name T255
Test name
Test status
Simulation time 48339200 ps
CPU time 25.87 seconds
Started Oct 09 06:13:36 PM UTC 24
Finished Oct 09 06:14:03 PM UTC 24
Peak memory 276272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664815344 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.2664815344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2746212022
Short name T401
Test name
Test status
Simulation time 75415900 ps
CPU time 45.72 seconds
Started Oct 09 07:55:45 PM UTC 24
Finished Oct 09 07:56:32 PM UTC 24
Peak memory 289720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746212022 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2746212022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.222485653
Short name T183
Test name
Test status
Simulation time 7990950500 ps
CPU time 590.36 seconds
Started Oct 09 07:12:42 PM UTC 24
Finished Oct 09 07:22:42 PM UTC 24
Peak memory 324716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=222485653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integrity.222485653
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3096148659
Short name T168
Test name
Test status
Simulation time 25952300 ps
CPU time 20.97 seconds
Started Oct 09 07:39:25 PM UTC 24
Finished Oct 09 07:39:47 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3096148659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_lcmgr_intg.3096148659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.824791906
Short name T85
Test name
Test status
Simulation time 890026800 ps
CPU time 25.84 seconds
Started Oct 09 07:15:29 PM UTC 24
Finished Oct 09 07:15:56 PM UTC 24
Peak memory 275716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=824791906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.824791906
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3215832573
Short name T238
Test name
Test status
Simulation time 74490800 ps
CPU time 25.87 seconds
Started Oct 09 06:15:26 PM UTC 24
Finished Oct 09 06:15:54 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215832573 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.3215832573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2271770408
Short name T317
Test name
Test status
Simulation time 16661100 ps
CPU time 26.86 seconds
Started Oct 09 06:13:02 PM UTC 24
Finished Oct 09 06:13:31 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271770408 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2271770408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.151454981
Short name T325
Test name
Test status
Simulation time 2552579200 ps
CPU time 153.9 seconds
Started Oct 09 08:16:13 PM UTC 24
Finished Oct 09 08:18:49 PM UTC 24
Peak memory 308428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151454981 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.151454981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2582298280
Short name T213
Test name
Test status
Simulation time 764134700 ps
CPU time 1555.91 seconds
Started Oct 09 07:07:25 PM UTC 24
Finished Oct 09 07:33:44 PM UTC 24
Peak memory 288184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582298280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2582298280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.850961464
Short name T762
Test name
Test status
Simulation time 10019541500 ps
CPU time 112.87 seconds
Started Oct 09 08:27:05 PM UTC 24
Finished Oct 09 08:29:01 PM UTC 24
Peak memory 322388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=850961464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.850961464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.114296725
Short name T82
Test name
Test status
Simulation time 20083285100 ps
CPU time 292.75 seconds
Started Oct 09 07:34:28 PM UTC 24
Finished Oct 09 07:39:26 PM UTC 24
Peak memory 283368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=114296725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_mp_regions.114296725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2822490423
Short name T264
Test name
Test status
Simulation time 44615700 ps
CPU time 15.26 seconds
Started Oct 09 07:48:13 PM UTC 24
Finished Oct 09 07:48:29 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2822490423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_hw_read_seed_err.2822490423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2209494581
Short name T346
Test name
Test status
Simulation time 1308910800 ps
CPU time 1289.41 seconds
Started Oct 09 06:12:05 PM UTC 24
Finished Oct 09 06:33:52 PM UTC 24
Peak memory 276476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209494581 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.2209494581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2297181189
Short name T770
Test name
Test status
Simulation time 5986848800 ps
CPU time 177.62 seconds
Started Oct 09 08:26:26 PM UTC 24
Finished Oct 09 08:29:26 PM UTC 24
Peak memory 306156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2297181189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_intr_rd_slow_flash.2297181189
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3630797958
Short name T51
Test name
Test status
Simulation time 68012400 ps
CPU time 47.22 seconds
Started Oct 09 07:28:13 PM UTC 24
Finished Oct 09 07:29:02 PM UTC 24
Peak memory 287708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3630797958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw_evict_all_en.3630797958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.1895808236
Short name T90
Test name
Test status
Simulation time 28752400 ps
CPU time 29.15 seconds
Started Oct 09 07:39:04 PM UTC 24
Finished Oct 09 07:39:35 PM UTC 24
Peak memory 275560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1895808236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1895808236
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.1878051512
Short name T188
Test name
Test status
Simulation time 15255800 ps
CPU time 38.61 seconds
Started Oct 09 08:34:57 PM UTC 24
Finished Oct 09 08:35:37 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1878051512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_
ctrl_disable.1878051512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3650965293
Short name T256
Test name
Test status
Simulation time 22163100 ps
CPU time 16.64 seconds
Started Oct 09 06:10:50 PM UTC 24
Finished Oct 09 06:11:08 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650965293 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.3650965293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2802181661
Short name T6
Test name
Test status
Simulation time 41637400 ps
CPU time 20.65 seconds
Started Oct 09 07:15:11 PM UTC 24
Finished Oct 09 07:15:33 PM UTC 24
Peak memory 273508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2802181661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2802181661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.695312467
Short name T68
Test name
Test status
Simulation time 25374400 ps
CPU time 21.86 seconds
Started Oct 09 07:15:37 PM UTC 24
Finished Oct 09 07:16:01 PM UTC 24
Peak memory 293056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695312467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.695312467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1990668777
Short name T123
Test name
Test status
Simulation time 27047300 ps
CPU time 20.7 seconds
Started Oct 09 07:16:02 PM UTC 24
Finished Oct 09 07:16:24 PM UTC 24
Peak memory 269204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1990668777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_hw_read_seed_err.1990668777
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2448742554
Short name T406
Test name
Test status
Simulation time 112912600 ps
CPU time 50.9 seconds
Started Oct 09 08:14:35 PM UTC 24
Finished Oct 09 08:15:28 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2448742554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw_evict_all_en.2448742554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.282977819
Short name T52
Test name
Test status
Simulation time 1317774300 ps
CPU time 39.36 seconds
Started Oct 09 07:17:59 PM UTC 24
Finished Oct 09 07:18:40 PM UTC 24
Peak memory 273356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
2977819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch
_code.282977819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.3578542770
Short name T190
Test name
Test status
Simulation time 987016100 ps
CPU time 73.91 seconds
Started Oct 09 07:29:02 PM UTC 24
Finished Oct 09 07:30:18 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578542770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3578542770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3524004431
Short name T105
Test name
Test status
Simulation time 10018990500 ps
CPU time 179.62 seconds
Started Oct 09 08:13:09 PM UTC 24
Finished Oct 09 08:16:12 PM UTC 24
Peak memory 299912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3524004431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3524004431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1744604183
Short name T246
Test name
Test status
Simulation time 665371500 ps
CPU time 1452.78 seconds
Started Oct 09 06:16:15 PM UTC 24
Finished Oct 09 06:40:49 PM UTC 24
Peak memory 276572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744604183 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.1744604183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2905396212
Short name T677
Test name
Test status
Simulation time 47468100 ps
CPU time 23.27 seconds
Started Oct 09 08:21:36 PM UTC 24
Finished Oct 09 08:22:01 PM UTC 24
Peak memory 271304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2905396212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_lcmgr_intg.2905396212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.323937220
Short name T347
Test name
Test status
Simulation time 749435900 ps
CPU time 1376.39 seconds
Started Oct 09 06:15:09 PM UTC 24
Finished Oct 09 06:38:25 PM UTC 24
Peak memory 276572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323937220 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.323937220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3797731304
Short name T28
Test name
Test status
Simulation time 3674015700 ps
CPU time 505.34 seconds
Started Oct 09 07:04:37 PM UTC 24
Finished Oct 09 07:13:10 PM UTC 24
Peak memory 276060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797731304 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3797731304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2813496145
Short name T157
Test name
Test status
Simulation time 10080040100 ps
CPU time 58.61 seconds
Started Oct 09 07:31:15 PM UTC 24
Finished Oct 09 07:32:15 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2813496145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2813496145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.595097547
Short name T27
Test name
Test status
Simulation time 23900700 ps
CPU time 25.58 seconds
Started Oct 09 07:38:44 PM UTC 24
Finished Oct 09 07:39:12 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595097547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.595097547
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.4133571024
Short name T420
Test name
Test status
Simulation time 263934400 ps
CPU time 57.21 seconds
Started Oct 09 07:47:20 PM UTC 24
Finished Oct 09 07:48:19 PM UTC 24
Peak memory 289728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133571024 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.4133571024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3078863227
Short name T109
Test name
Test status
Simulation time 2997568200 ps
CPU time 3101.91 seconds
Started Oct 09 07:36:26 PM UTC 24
Finished Oct 09 08:28:43 PM UTC 24
Peak memory 277932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30
78863227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_error_prog_type.3078863227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2638224347
Short name T131
Test name
Test status
Simulation time 40122601200 ps
CPU time 897.52 seconds
Started Oct 09 07:17:20 PM UTC 24
Finished Oct 09 07:32:31 PM UTC 24
Peak memory 277828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638224347
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.2638224347
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3908942252
Short name T63
Test name
Test status
Simulation time 287805100 ps
CPU time 47.4 seconds
Started Oct 09 07:15:06 PM UTC 24
Finished Oct 09 07:15:55 PM UTC 24
Peak memory 287544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390894225
2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.3908942252
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3703002999
Short name T243
Test name
Test status
Simulation time 714804700 ps
CPU time 1175.82 seconds
Started Oct 09 06:17:15 PM UTC 24
Finished Oct 09 06:37:08 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703002999 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.3703002999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3219943824
Short name T397
Test name
Test status
Simulation time 299277400 ps
CPU time 46.84 seconds
Started Oct 09 07:38:52 PM UTC 24
Finished Oct 09 07:39:41 PM UTC 24
Peak memory 275300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219943
824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f
s_sup.3219943824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1477801494
Short name T515
Test name
Test status
Simulation time 3323897100 ps
CPU time 447.21 seconds
Started Oct 09 07:49:35 PM UTC 24
Finished Oct 09 07:57:08 PM UTC 24
Peak memory 320612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477801494 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.1477801494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.2568866877
Short name T304
Test name
Test status
Simulation time 160196104000 ps
CPU time 909.42 seconds
Started Oct 09 08:08:42 PM UTC 24
Finished Oct 09 08:24:03 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568866877
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res
et.2568866877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2224193782
Short name T293
Test name
Test status
Simulation time 1284740800 ps
CPU time 64.22 seconds
Started Oct 09 06:12:37 PM UTC 24
Finished Oct 09 06:13:43 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224193782 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.2224193782
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1061873531
Short name T652
Test name
Test status
Simulation time 19287603500 ps
CPU time 594.99 seconds
Started Oct 09 08:09:29 PM UTC 24
Finished Oct 09 08:19:31 PM UTC 24
Peak memory 330976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061873531 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.1061873531
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.1370456723
Short name T369
Test name
Test status
Simulation time 1135014600 ps
CPU time 100.1 seconds
Started Oct 09 08:10:39 PM UTC 24
Finished Oct 09 08:12:21 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370456723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1370456723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.2884263245
Short name T331
Test name
Test status
Simulation time 782013400 ps
CPU time 137.41 seconds
Started Oct 09 08:12:00 PM UTC 24
Finished Oct 09 08:14:20 PM UTC 24
Peak memory 306348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884263245 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.2884263245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.512064308
Short name T205
Test name
Test status
Simulation time 209821700 ps
CPU time 28.11 seconds
Started Oct 09 06:11:58 PM UTC 24
Finished Oct 09 06:12:28 PM UTC 24
Peak memory 276420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512064308 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.512064308
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2969828116
Short name T9
Test name
Test status
Simulation time 5000205200 ps
CPU time 61.89 seconds
Started Oct 09 07:04:37 PM UTC 24
Finished Oct 09 07:05:41 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969828116 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.2969828116
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.1725083833
Short name T94
Test name
Test status
Simulation time 665548900 ps
CPU time 26.06 seconds
Started Oct 09 07:30:37 PM UTC 24
Finished Oct 09 07:31:05 PM UTC 24
Peak memory 273400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1725083833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1725083833
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2771304498
Short name T120
Test name
Test status
Simulation time 27325500 ps
CPU time 38.24 seconds
Started Oct 09 08:10:31 PM UTC 24
Finished Oct 09 08:11:11 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2771304498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_
ctrl_disable.2771304498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3103814433
Short name T15
Test name
Test status
Simulation time 13645378400 ps
CPU time 6450.32 seconds
Started Oct 09 07:28:59 PM UTC 24
Finished Oct 09 09:17:41 PM UTC 24
Peak memory 316236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103814433 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3103814433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.2199420293
Short name T149
Test name
Test status
Simulation time 99781445700 ps
CPU time 4183.2 seconds
Started Oct 09 07:07:06 PM UTC 24
Finished Oct 09 08:17:42 PM UTC 24
Peak memory 277876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199420293 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.2199420293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3978076409
Short name T204
Test name
Test status
Simulation time 40760000 ps
CPU time 20.64 seconds
Started Oct 09 07:31:05 PM UTC 24
Finished Oct 09 07:31:27 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978076409 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.3978076409
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.175891237
Short name T396
Test name
Test status
Simulation time 11099241300 ps
CPU time 2989.23 seconds
Started Oct 09 07:44:14 PM UTC 24
Finished Oct 09 08:34:36 PM UTC 24
Peak memory 273284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175891237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.175891237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.977964086
Short name T390
Test name
Test status
Simulation time 147698000 ps
CPU time 137.12 seconds
Started Oct 09 08:43:08 PM UTC 24
Finished Oct 09 08:45:28 PM UTC 24
Peak memory 273460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977964086 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.977964086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.4080256851
Short name T96
Test name
Test status
Simulation time 906937300 ps
CPU time 29.21 seconds
Started Oct 09 07:47:49 PM UTC 24
Finished Oct 09 07:48:20 PM UTC 24
Peak memory 275644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4080256851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.4080256851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.4112167017
Short name T5
Test name
Test status
Simulation time 62710000 ps
CPU time 33.52 seconds
Started Oct 09 07:14:30 PM UTC 24
Finished Oct 09 07:15:05 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4112167017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_disable.4112167017
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3625139749
Short name T121
Test name
Test status
Simulation time 16253500 ps
CPU time 46.35 seconds
Started Oct 09 08:14:53 PM UTC 24
Finished Oct 09 08:15:40 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3625139749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_
ctrl_disable.3625139749
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3088292485
Short name T417
Test name
Test status
Simulation time 221779000 ps
CPU time 60.63 seconds
Started Oct 09 08:16:43 PM UTC 24
Finished Oct 09 08:17:46 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088292485 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3088292485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.1435780842
Short name T365
Test name
Test status
Simulation time 735682800 ps
CPU time 72.13 seconds
Started Oct 09 08:19:42 PM UTC 24
Finished Oct 09 08:20:56 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435780842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1435780842
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3170071005
Short name T392
Test name
Test status
Simulation time 104562900 ps
CPU time 38.34 seconds
Started Oct 09 08:28:10 PM UTC 24
Finished Oct 09 08:28:50 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3170071005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_
ctrl_disable.3170071005
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2885862967
Short name T323
Test name
Test status
Simulation time 3411027900 ps
CPU time 268.8 seconds
Started Oct 09 08:30:08 PM UTC 24
Finished Oct 09 08:34:41 PM UTC 24
Peak memory 293836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885862967 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.2885862967
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1485527172
Short name T370
Test name
Test status
Simulation time 5877409700 ps
CPU time 93 seconds
Started Oct 09 08:33:04 PM UTC 24
Finished Oct 09 08:34:40 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485527172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1485527172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.674120837
Short name T115
Test name
Test status
Simulation time 10181200 ps
CPU time 36.25 seconds
Started Oct 09 07:42:18 PM UTC 24
Finished Oct 09 07:42:56 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=674120837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_disable.674120837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3366051207
Short name T398
Test name
Test status
Simulation time 336921200 ps
CPU time 41.55 seconds
Started Oct 09 07:42:46 PM UTC 24
Finished Oct 09 07:43:29 PM UTC 24
Peak memory 273256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366051
207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f
s_sup.3366051207
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.3282843955
Short name T411
Test name
Test status
Simulation time 58651500 ps
CPU time 39.39 seconds
Started Oct 09 08:34:54 PM UTC 24
Finished Oct 09 08:35:35 PM UTC 24
Peak memory 285916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3282843955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c
trl_rw_evict_all_en.3282843955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1545417969
Short name T373
Test name
Test status
Simulation time 13416440900 ps
CPU time 95.18 seconds
Started Oct 09 08:34:58 PM UTC 24
Finished Oct 09 08:36:35 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545417969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1545417969
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.3378206144
Short name T366
Test name
Test status
Simulation time 2996378900 ps
CPU time 90.11 seconds
Started Oct 09 08:36:38 PM UTC 24
Finished Oct 09 08:38:10 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378206144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.3378206144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.804701948
Short name T357
Test name
Test status
Simulation time 18806000 ps
CPU time 35.35 seconds
Started Oct 09 08:40:05 PM UTC 24
Finished Oct 09 08:40:42 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=804701948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_c
trl_disable.804701948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3340791835
Short name T33
Test name
Test status
Simulation time 11156232200 ps
CPU time 99.55 seconds
Started Oct 09 07:13:01 PM UTC 24
Finished Oct 09 07:14:43 PM UTC 24
Peak memory 271400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340791835 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.3340791835
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3088385411
Short name T101
Test name
Test status
Simulation time 32092400 ps
CPU time 26.22 seconds
Started Oct 09 07:47:54 PM UTC 24
Finished Oct 09 07:48:21 PM UTC 24
Peak memory 275480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088385411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3088385411
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.238937663
Short name T227
Test name
Test status
Simulation time 4941430500 ps
CPU time 82.89 seconds
Started Oct 09 06:11:15 PM UTC 24
Finished Oct 09 06:12:39 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238937663 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.238937663
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.1202751435
Short name T682
Test name
Test status
Simulation time 11881508000 ps
CPU time 245.63 seconds
Started Oct 09 08:18:11 PM UTC 24
Finished Oct 09 08:22:20 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202751435 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.1202751435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.870045294
Short name T196
Test name
Test status
Simulation time 1172315400 ps
CPU time 144.15 seconds
Started Oct 09 07:36:38 PM UTC 24
Finished Oct 09 07:39:05 PM UTC 24
Peak memory 306176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=870045294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_
ctrl_ro_serr.870045294
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.1144880736
Short name T8
Test name
Test status
Simulation time 354441700 ps
CPU time 23.36 seconds
Started Oct 09 07:29:57 PM UTC 24
Finished Oct 09 07:30:22 PM UTC 24
Peak memory 275604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1144880736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_wr_intg.1144880736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3079738501
Short name T611
Test name
Test status
Simulation time 32966700 ps
CPU time 21.01 seconds
Started Oct 09 08:13:08 PM UTC 24
Finished Oct 09 08:13:30 PM UTC 24
Peak memory 271296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3079738501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_hw_read_seed_err.3079738501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2966745914
Short name T195
Test name
Test status
Simulation time 528875090900 ps
CPU time 2182.07 seconds
Started Oct 09 07:34:06 PM UTC 24
Finished Oct 09 08:10:53 PM UTC 24
Peak memory 275456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966745914 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.2966745914
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3893975513
Short name T97
Test name
Test status
Simulation time 876100400 ps
CPU time 42.31 seconds
Started Oct 09 07:42:47 PM UTC 24
Finished Oct 09 07:43:31 PM UTC 24
Peak memory 275524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3893975513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3893975513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.3946837004
Short name T189
Test name
Test status
Simulation time 148524000 ps
CPU time 196.71 seconds
Started Oct 09 08:36:43 PM UTC 24
Finished Oct 09 08:40:03 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946837004 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.3946837004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3471938198
Short name T207
Test name
Test status
Simulation time 1527989500 ps
CPU time 56.14 seconds
Started Oct 09 06:11:13 PM UTC 24
Finished Oct 09 06:12:10 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471938198 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.3471938198
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2790801569
Short name T76
Test name
Test status
Simulation time 68918000 ps
CPU time 23.93 seconds
Started Oct 09 06:11:08 PM UTC 24
Finished Oct 09 06:11:34 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790801569 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.2790801569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.129456065
Short name T1142
Test name
Test status
Simulation time 53222900 ps
CPU time 24.97 seconds
Started Oct 09 06:10:50 PM UTC 24
Finished Oct 09 06:11:16 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129456065 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.129456065
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.705704815
Short name T226
Test name
Test status
Simulation time 163101000 ps
CPU time 30.12 seconds
Started Oct 09 06:11:16 PM UTC 24
Finished Oct 09 06:11:47 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
705704815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_s
ame_csr_outstanding.705704815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2008148022
Short name T1144
Test name
Test status
Simulation time 17652300 ps
CPU time 29.99 seconds
Started Oct 09 06:10:48 PM UTC 24
Finished Oct 09 06:11:19 PM UTC 24
Peak memory 274160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200
8148022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha
dow_reg_errors.2008148022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2759118574
Short name T1143
Test name
Test status
Simulation time 14123000 ps
CPU time 26.44 seconds
Started Oct 09 06:10:50 PM UTC 24
Finished Oct 09 06:11:18 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2759118574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2759118574
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2697596500
Short name T231
Test name
Test status
Simulation time 55037400 ps
CPU time 36.82 seconds
Started Oct 09 06:11:45 PM UTC 24
Finished Oct 09 06:12:23 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697596500 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.2697596500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2333718495
Short name T126
Test name
Test status
Simulation time 43514300 ps
CPU time 32.8 seconds
Started Oct 09 06:11:58 PM UTC 24
Finished Oct 09 06:12:33 PM UTC 24
Peak memory 286584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2333718495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2333718495
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1256011416
Short name T229
Test name
Test status
Simulation time 36649400 ps
CPU time 28.57 seconds
Started Oct 09 06:11:47 PM UTC 24
Finished Oct 09 06:12:17 PM UTC 24
Peak memory 274296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256011416 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.1256011416
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2262135525
Short name T235
Test name
Test status
Simulation time 17025800 ps
CPU time 25.77 seconds
Started Oct 09 06:11:29 PM UTC 24
Finished Oct 09 06:11:56 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262135525 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2262135525
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2256600070
Short name T257
Test name
Test status
Simulation time 119427100 ps
CPU time 20.51 seconds
Started Oct 09 06:11:43 PM UTC 24
Finished Oct 09 06:12:05 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256600070 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.2256600070
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1776693992
Short name T1147
Test name
Test status
Simulation time 100736100 ps
CPU time 20.72 seconds
Started Oct 09 06:11:34 PM UTC 24
Finished Oct 09 06:11:57 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776693992 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.1776693992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1270972986
Short name T232
Test name
Test status
Simulation time 258852400 ps
CPU time 65.07 seconds
Started Oct 09 06:11:57 PM UTC 24
Finished Oct 09 06:13:04 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1270972986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
same_csr_outstanding.1270972986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3999043237
Short name T1146
Test name
Test status
Simulation time 33195200 ps
CPU time 30.39 seconds
Started Oct 09 06:11:25 PM UTC 24
Finished Oct 09 06:11:57 PM UTC 24
Peak memory 274160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399
9043237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha
dow_reg_errors.3999043237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2073982273
Short name T1145
Test name
Test status
Simulation time 35053400 ps
CPU time 15.99 seconds
Started Oct 09 06:11:26 PM UTC 24
Finished Oct 09 06:11:43 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2073982273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2073982273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1933302241
Short name T128
Test name
Test status
Simulation time 34649700 ps
CPU time 21.76 seconds
Started Oct 09 06:11:18 PM UTC 24
Finished Oct 09 06:11:41 PM UTC 24
Peak memory 276420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933302241 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1933302241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.681164675
Short name T342
Test name
Test status
Simulation time 1393566400 ps
CPU time 1326.4 seconds
Started Oct 09 06:11:20 PM UTC 24
Finished Oct 09 06:33:45 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681164675 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.681164675
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1224320092
Short name T1183
Test name
Test status
Simulation time 146153200 ps
CPU time 33.31 seconds
Started Oct 09 06:15:39 PM UTC 24
Finished Oct 09 06:16:14 PM UTC 24
Peak memory 286580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1224320092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1224320092
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3304878682
Short name T1180
Test name
Test status
Simulation time 47220400 ps
CPU time 32.05 seconds
Started Oct 09 06:15:35 PM UTC 24
Finished Oct 09 06:16:10 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304878682 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.3304878682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3426513390
Short name T1176
Test name
Test status
Simulation time 55386700 ps
CPU time 17.86 seconds
Started Oct 09 06:15:34 PM UTC 24
Finished Oct 09 06:15:54 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426513390 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.3426513390
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1711156427
Short name T1186
Test name
Test status
Simulation time 60512000 ps
CPU time 40.91 seconds
Started Oct 09 06:15:35 PM UTC 24
Finished Oct 09 06:16:18 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1711156427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_same_csr_outstanding.1711156427
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2973077682
Short name T1178
Test name
Test status
Simulation time 23509300 ps
CPU time 25.14 seconds
Started Oct 09 06:15:32 PM UTC 24
Finished Oct 09 06:15:59 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297
3077682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh
adow_reg_errors.2973077682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3927234032
Short name T1179
Test name
Test status
Simulation time 34074500 ps
CPU time 29.01 seconds
Started Oct 09 06:15:33 PM UTC 24
Finished Oct 09 06:16:04 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3927234032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3927234032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1644769515
Short name T339
Test name
Test status
Simulation time 670749700 ps
CPU time 1428.09 seconds
Started Oct 09 06:15:30 PM UTC 24
Finished Oct 09 06:39:38 PM UTC 24
Peak memory 276572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644769515 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.1644769515
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.506229404
Short name T1189
Test name
Test status
Simulation time 84636000 ps
CPU time 31.13 seconds
Started Oct 09 06:15:54 PM UTC 24
Finished Oct 09 06:16:27 PM UTC 24
Peak memory 286580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=506229404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.506229404
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1455779649
Short name T1185
Test name
Test status
Simulation time 31942500 ps
CPU time 26.56 seconds
Started Oct 09 06:15:49 PM UTC 24
Finished Oct 09 06:16:17 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455779649 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.1455779649
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3713111317
Short name T1182
Test name
Test status
Simulation time 29320700 ps
CPU time 25.57 seconds
Started Oct 09 06:15:45 PM UTC 24
Finished Oct 09 06:16:12 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713111317 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.3713111317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2190873186
Short name T1187
Test name
Test status
Simulation time 463646000 ps
CPU time 31.25 seconds
Started Oct 09 06:15:52 PM UTC 24
Finished Oct 09 06:16:25 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2190873186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_same_csr_outstanding.2190873186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2446257709
Short name T1181
Test name
Test status
Simulation time 33032300 ps
CPU time 27.08 seconds
Started Oct 09 06:15:42 PM UTC 24
Finished Oct 09 06:16:11 PM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244
6257709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh
adow_reg_errors.2446257709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3763036335
Short name T1184
Test name
Test status
Simulation time 36736000 ps
CPU time 29.31 seconds
Started Oct 09 06:15:45 PM UTC 24
Finished Oct 09 06:16:16 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3763036335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3763036335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.275219823
Short name T245
Test name
Test status
Simulation time 107955000 ps
CPU time 24.55 seconds
Started Oct 09 06:15:40 PM UTC 24
Finished Oct 09 06:16:06 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275219823 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.275219823
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.994759811
Short name T340
Test name
Test status
Simulation time 503167700 ps
CPU time 651.66 seconds
Started Oct 09 06:15:41 PM UTC 24
Finished Oct 09 06:26:42 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994759811 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.994759811
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2646743265
Short name T1191
Test name
Test status
Simulation time 28071100 ps
CPU time 20.4 seconds
Started Oct 09 06:16:12 PM UTC 24
Finished Oct 09 06:16:34 PM UTC 24
Peak memory 286580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2646743265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2646743265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2077910283
Short name T1194
Test name
Test status
Simulation time 58212900 ps
CPU time 33.1 seconds
Started Oct 09 06:16:07 PM UTC 24
Finished Oct 09 06:16:42 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077910283 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.2077910283
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1362145319
Short name T1188
Test name
Test status
Simulation time 17633600 ps
CPU time 19.84 seconds
Started Oct 09 06:16:05 PM UTC 24
Finished Oct 09 06:16:26 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362145319 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.1362145319
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1472613526
Short name T1206
Test name
Test status
Simulation time 704850300 ps
CPU time 56.22 seconds
Started Oct 09 06:16:10 PM UTC 24
Finished Oct 09 06:17:08 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1472613526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_same_csr_outstanding.1472613526
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2942082612
Short name T1190
Test name
Test status
Simulation time 35765600 ps
CPU time 30.83 seconds
Started Oct 09 06:15:59 PM UTC 24
Finished Oct 09 06:16:32 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294
2082612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh
adow_reg_errors.2942082612
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2457249081
Short name T1192
Test name
Test status
Simulation time 12234300 ps
CPU time 30.71 seconds
Started Oct 09 06:16:04 PM UTC 24
Finished Oct 09 06:16:36 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2457249081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2457249081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4025212101
Short name T241
Test name
Test status
Simulation time 39052400 ps
CPU time 27 seconds
Started Oct 09 06:15:55 PM UTC 24
Finished Oct 09 06:16:24 PM UTC 24
Peak memory 276220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025212101 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.4025212101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2991581569
Short name T337
Test name
Test status
Simulation time 855721900 ps
CPU time 654.16 seconds
Started Oct 09 06:15:58 PM UTC 24
Finished Oct 09 06:27:02 PM UTC 24
Peak memory 276476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991581569 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.2991581569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4226615415
Short name T1201
Test name
Test status
Simulation time 414398300 ps
CPU time 27.32 seconds
Started Oct 09 06:16:29 PM UTC 24
Finished Oct 09 06:16:57 PM UTC 24
Peak memory 286580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4226615415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.4226615415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3007274801
Short name T1199
Test name
Test status
Simulation time 26438200 ps
CPU time 23.3 seconds
Started Oct 09 06:16:25 PM UTC 24
Finished Oct 09 06:16:49 PM UTC 24
Peak memory 276272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007274801 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.3007274801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1049053074
Short name T1196
Test name
Test status
Simulation time 23849100 ps
CPU time 24.98 seconds
Started Oct 09 06:16:20 PM UTC 24
Finished Oct 09 06:16:46 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049053074 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1049053074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4096782280
Short name T1198
Test name
Test status
Simulation time 296667100 ps
CPU time 21.57 seconds
Started Oct 09 06:16:26 PM UTC 24
Finished Oct 09 06:16:49 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4096782280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_same_csr_outstanding.4096782280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.797136953
Short name T1193
Test name
Test status
Simulation time 38949000 ps
CPU time 23.18 seconds
Started Oct 09 06:16:16 PM UTC 24
Finished Oct 09 06:16:41 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797
136953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sha
dow_reg_errors.797136953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3218632157
Short name T1197
Test name
Test status
Simulation time 14898600 ps
CPU time 29.19 seconds
Started Oct 09 06:16:17 PM UTC 24
Finished Oct 09 06:16:48 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3218632157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3218632157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.519892475
Short name T1195
Test name
Test status
Simulation time 229264100 ps
CPU time 31.33 seconds
Started Oct 09 06:16:12 PM UTC 24
Finished Oct 09 06:16:45 PM UTC 24
Peak memory 276416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519892475 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.519892475
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3063852157
Short name T1211
Test name
Test status
Simulation time 53201200 ps
CPU time 29.62 seconds
Started Oct 09 06:16:43 PM UTC 24
Finished Oct 09 06:17:14 PM UTC 24
Peak memory 286576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3063852157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3063852157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1003107681
Short name T1204
Test name
Test status
Simulation time 36696700 ps
CPU time 21.25 seconds
Started Oct 09 06:16:40 PM UTC 24
Finished Oct 09 06:17:02 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003107681 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.1003107681
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.161091762
Short name T1205
Test name
Test status
Simulation time 46593900 ps
CPU time 26.92 seconds
Started Oct 09 06:16:39 PM UTC 24
Finished Oct 09 06:17:08 PM UTC 24
Peak memory 274096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161091762 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.161091762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.234138626
Short name T1220
Test name
Test status
Simulation time 112609500 ps
CPU time 61.39 seconds
Started Oct 09 06:16:42 PM UTC 24
Finished Oct 09 06:17:45 PM UTC 24
Peak memory 276476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
234138626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
same_csr_outstanding.234138626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2348925060
Short name T1202
Test name
Test status
Simulation time 68256000 ps
CPU time 25.6 seconds
Started Oct 09 06:16:33 PM UTC 24
Finished Oct 09 06:17:00 PM UTC 24
Peak memory 274296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234
8925060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh
adow_reg_errors.2348925060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.168373182
Short name T1203
Test name
Test status
Simulation time 14654300 ps
CPU time 24.62 seconds
Started Oct 09 06:16:35 PM UTC 24
Finished Oct 09 06:17:01 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=168373182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.168373182
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1481287739
Short name T1200
Test name
Test status
Simulation time 87610200 ps
CPU time 26.52 seconds
Started Oct 09 06:16:29 PM UTC 24
Finished Oct 09 06:16:57 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481287739 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.1481287739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2224669346
Short name T223
Test name
Test status
Simulation time 337762500 ps
CPU time 565.87 seconds
Started Oct 09 06:16:30 PM UTC 24
Finished Oct 09 06:26:04 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224669346 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2224669346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3778990787
Short name T1212
Test name
Test status
Simulation time 36392500 ps
CPU time 21.08 seconds
Started Oct 09 06:16:58 PM UTC 24
Finished Oct 09 06:17:21 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3778990787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3778990787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.964109675
Short name T1210
Test name
Test status
Simulation time 59081800 ps
CPU time 22.33 seconds
Started Oct 09 06:16:50 PM UTC 24
Finished Oct 09 06:17:13 PM UTC 24
Peak memory 274236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964109675 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.964109675
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3479437595
Short name T1209
Test name
Test status
Simulation time 222127100 ps
CPU time 20.27 seconds
Started Oct 09 06:16:50 PM UTC 24
Finished Oct 09 06:17:11 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479437595 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.3479437595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4282497327
Short name T1222
Test name
Test status
Simulation time 722563800 ps
CPU time 47.45 seconds
Started Oct 09 06:16:57 PM UTC 24
Finished Oct 09 06:17:46 PM UTC 24
Peak memory 276472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4282497327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_same_csr_outstanding.4282497327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2039753927
Short name T1208
Test name
Test status
Simulation time 41792900 ps
CPU time 23.07 seconds
Started Oct 09 06:16:47 PM UTC 24
Finished Oct 09 06:17:11 PM UTC 24
Peak memory 274232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203
9753927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh
adow_reg_errors.2039753927
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3333063085
Short name T1213
Test name
Test status
Simulation time 34217100 ps
CPU time 30.99 seconds
Started Oct 09 06:16:49 PM UTC 24
Finished Oct 09 06:17:21 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3333063085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3333063085
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2859925417
Short name T1207
Test name
Test status
Simulation time 49144000 ps
CPU time 21.78 seconds
Started Oct 09 06:16:45 PM UTC 24
Finished Oct 09 06:17:08 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859925417 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.2859925417
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.705571605
Short name T341
Test name
Test status
Simulation time 1272159400 ps
CPU time 691.52 seconds
Started Oct 09 06:16:46 PM UTC 24
Finished Oct 09 06:28:27 PM UTC 24
Peak memory 276476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705571605 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.705571605
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.468362451
Short name T1223
Test name
Test status
Simulation time 35020300 ps
CPU time 33.86 seconds
Started Oct 09 06:17:12 PM UTC 24
Finished Oct 09 06:17:47 PM UTC 24
Peak memory 290604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=468362451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.468362451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.941776563
Short name T1216
Test name
Test status
Simulation time 28205500 ps
CPU time 17.72 seconds
Started Oct 09 06:17:10 PM UTC 24
Finished Oct 09 06:17:29 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941776563 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.941776563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3286660148
Short name T1217
Test name
Test status
Simulation time 23518500 ps
CPU time 20.52 seconds
Started Oct 09 06:17:09 PM UTC 24
Finished Oct 09 06:17:30 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286660148 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.3286660148
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1348740199
Short name T1226
Test name
Test status
Simulation time 947707300 ps
CPU time 36.41 seconds
Started Oct 09 06:17:12 PM UTC 24
Finished Oct 09 06:17:50 PM UTC 24
Peak memory 276468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1348740199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_same_csr_outstanding.1348740199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2761831356
Short name T1214
Test name
Test status
Simulation time 21298200 ps
CPU time 22.16 seconds
Started Oct 09 06:17:03 PM UTC 24
Finished Oct 09 06:17:27 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276
1831356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh
adow_reg_errors.2761831356
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2880493284
Short name T1218
Test name
Test status
Simulation time 103692100 ps
CPU time 24.42 seconds
Started Oct 09 06:17:08 PM UTC 24
Finished Oct 09 06:17:34 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2880493284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2880493284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1490999548
Short name T1215
Test name
Test status
Simulation time 52408200 ps
CPU time 25.01 seconds
Started Oct 09 06:17:01 PM UTC 24
Finished Oct 09 06:17:28 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490999548 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.1490999548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.474657974
Short name T343
Test name
Test status
Simulation time 446828800 ps
CPU time 725.49 seconds
Started Oct 09 06:17:02 PM UTC 24
Finished Oct 09 06:29:18 PM UTC 24
Peak memory 276412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474657974 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.474657974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1573926709
Short name T1232
Test name
Test status
Simulation time 414076400 ps
CPU time 34.31 seconds
Started Oct 09 06:17:30 PM UTC 24
Finished Oct 09 06:18:06 PM UTC 24
Peak memory 286580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1573926709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1573926709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2870457579
Short name T1228
Test name
Test status
Simulation time 95440400 ps
CPU time 23.15 seconds
Started Oct 09 06:17:29 PM UTC 24
Finished Oct 09 06:17:53 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870457579 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.2870457579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.3004062839
Short name T1224
Test name
Test status
Simulation time 28444400 ps
CPU time 19.06 seconds
Started Oct 09 06:17:28 PM UTC 24
Finished Oct 09 06:17:48 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004062839 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.3004062839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.993983658
Short name T1227
Test name
Test status
Simulation time 568804700 ps
CPU time 22.56 seconds
Started Oct 09 06:17:29 PM UTC 24
Finished Oct 09 06:17:53 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
993983658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
same_csr_outstanding.993983658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.446977277
Short name T1225
Test name
Test status
Simulation time 84084100 ps
CPU time 25.34 seconds
Started Oct 09 06:17:22 PM UTC 24
Finished Oct 09 06:17:49 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446
977277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sha
dow_reg_errors.446977277
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.410666125
Short name T1219
Test name
Test status
Simulation time 36900000 ps
CPU time 18.5 seconds
Started Oct 09 06:17:22 PM UTC 24
Finished Oct 09 06:17:42 PM UTC 24
Peak memory 263916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=410666125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.410666125
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3146753768
Short name T1221
Test name
Test status
Simulation time 38130600 ps
CPU time 29.85 seconds
Started Oct 09 06:17:14 PM UTC 24
Finished Oct 09 06:17:45 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146753768 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.3146753768
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3427160051
Short name T1236
Test name
Test status
Simulation time 72620100 ps
CPU time 27.98 seconds
Started Oct 09 06:17:49 PM UTC 24
Finished Oct 09 06:18:18 PM UTC 24
Peak memory 292852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3427160051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3427160051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3080698499
Short name T1231
Test name
Test status
Simulation time 213810500 ps
CPU time 17.93 seconds
Started Oct 09 06:17:47 PM UTC 24
Finished Oct 09 06:18:06 PM UTC 24
Peak memory 274232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080698499 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.3080698499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3019318089
Short name T1233
Test name
Test status
Simulation time 15593200 ps
CPU time 25.31 seconds
Started Oct 09 06:17:47 PM UTC 24
Finished Oct 09 06:18:13 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019318089 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.3019318089
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.56824946
Short name T1239
Test name
Test status
Simulation time 125569500 ps
CPU time 33.31 seconds
Started Oct 09 06:17:48 PM UTC 24
Finished Oct 09 06:18:23 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
56824946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_s
ame_csr_outstanding.56824946
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3331103763
Short name T1234
Test name
Test status
Simulation time 17093700 ps
CPU time 29.58 seconds
Started Oct 09 06:17:42 PM UTC 24
Finished Oct 09 06:18:13 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333
1103763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh
adow_reg_errors.3331103763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.156862794
Short name T1230
Test name
Test status
Simulation time 16096700 ps
CPU time 18.79 seconds
Started Oct 09 06:17:45 PM UTC 24
Finished Oct 09 06:18:05 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=156862794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.156862794
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2999394717
Short name T1229
Test name
Test status
Simulation time 137117700 ps
CPU time 31.11 seconds
Started Oct 09 06:17:31 PM UTC 24
Finished Oct 09 06:18:04 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999394717 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.2999394717
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1094185655
Short name T350
Test name
Test status
Simulation time 795435400 ps
CPU time 713.92 seconds
Started Oct 09 06:17:35 PM UTC 24
Finished Oct 09 06:29:40 PM UTC 24
Peak memory 274300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094185655 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.1094185655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.148085099
Short name T1241
Test name
Test status
Simulation time 237647500 ps
CPU time 21.22 seconds
Started Oct 09 06:18:07 PM UTC 24
Finished Oct 09 06:18:29 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=148085099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.148085099
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4036287095
Short name T1242
Test name
Test status
Simulation time 20055000 ps
CPU time 27.45 seconds
Started Oct 09 06:18:06 PM UTC 24
Finished Oct 09 06:18:35 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036287095 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.4036287095
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3081607254
Short name T1240
Test name
Test status
Simulation time 104750500 ps
CPU time 21.32 seconds
Started Oct 09 06:18:04 PM UTC 24
Finished Oct 09 06:18:27 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081607254 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3081607254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3964254921
Short name T1245
Test name
Test status
Simulation time 68678500 ps
CPU time 29.83 seconds
Started Oct 09 06:18:06 PM UTC 24
Finished Oct 09 06:18:38 PM UTC 24
Peak memory 276336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3964254921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_same_csr_outstanding.3964254921
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2592317791
Short name T1235
Test name
Test status
Simulation time 167452600 ps
CPU time 21.6 seconds
Started Oct 09 06:17:54 PM UTC 24
Finished Oct 09 06:18:17 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259
2317791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh
adow_reg_errors.2592317791
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4068666418
Short name T1237
Test name
Test status
Simulation time 124706000 ps
CPU time 22.7 seconds
Started Oct 09 06:17:54 PM UTC 24
Finished Oct 09 06:18:18 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4068666418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f
lash_ctrl_shadow_reg_errors_with_csr_rw.4068666418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.477582030
Short name T1238
Test name
Test status
Simulation time 57799100 ps
CPU time 29.44 seconds
Started Oct 09 06:17:50 PM UTC 24
Finished Oct 09 06:18:21 PM UTC 24
Peak memory 276416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477582030 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.477582030
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.339892800
Short name T344
Test name
Test status
Simulation time 367618000 ps
CPU time 598.28 seconds
Started Oct 09 06:17:51 PM UTC 24
Finished Oct 09 06:27:58 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339892800 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.339892800
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2279317171
Short name T282
Test name
Test status
Simulation time 3004482000 ps
CPU time 63.64 seconds
Started Oct 09 06:12:38 PM UTC 24
Finished Oct 09 06:13:43 PM UTC 24
Peak memory 274232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279317171 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.2279317171
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2002567710
Short name T230
Test name
Test status
Simulation time 34455500 ps
CPU time 36.52 seconds
Started Oct 09 06:12:29 PM UTC 24
Finished Oct 09 06:13:07 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002567710 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.2002567710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.678673626
Short name T127
Test name
Test status
Simulation time 54776700 ps
CPU time 18.4 seconds
Started Oct 09 06:12:43 PM UTC 24
Finished Oct 09 06:13:03 PM UTC 24
Peak memory 286568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=678673626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.678673626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1493859641
Short name T228
Test name
Test status
Simulation time 41561400 ps
CPU time 26.41 seconds
Started Oct 09 06:12:34 PM UTC 24
Finished Oct 09 06:13:02 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493859641 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1493859641
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2349802355
Short name T316
Test name
Test status
Simulation time 52105400 ps
CPU time 25.68 seconds
Started Oct 09 06:12:18 PM UTC 24
Finished Oct 09 06:12:45 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349802355 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2349802355
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4083512645
Short name T258
Test name
Test status
Simulation time 32013900 ps
CPU time 20.05 seconds
Started Oct 09 06:12:28 PM UTC 24
Finished Oct 09 06:12:49 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083512645 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.4083512645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4055272104
Short name T1150
Test name
Test status
Simulation time 57651000 ps
CPU time 24.48 seconds
Started Oct 09 06:12:24 PM UTC 24
Finished Oct 09 06:12:50 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055272104 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.4055272104
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3691700571
Short name T260
Test name
Test status
Simulation time 87810900 ps
CPU time 30.08 seconds
Started Oct 09 06:12:40 PM UTC 24
Finished Oct 09 06:13:11 PM UTC 24
Peak memory 276472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3691700571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
same_csr_outstanding.3691700571
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.869286020
Short name T1148
Test name
Test status
Simulation time 24222900 ps
CPU time 22.03 seconds
Started Oct 09 06:12:12 PM UTC 24
Finished Oct 09 06:12:35 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869
286020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shad
ow_reg_errors.869286020
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.801329107
Short name T1149
Test name
Test status
Simulation time 18031600 ps
CPU time 26.29 seconds
Started Oct 09 06:12:15 PM UTC 24
Finished Oct 09 06:12:42 PM UTC 24
Peak memory 274160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=801329107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.801329107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.430579259
Short name T1247
Test name
Test status
Simulation time 16986100 ps
CPU time 25.42 seconds
Started Oct 09 06:18:13 PM UTC 24
Finished Oct 09 06:18:40 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430579259 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.430579259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1075292118
Short name T1244
Test name
Test status
Simulation time 54252500 ps
CPU time 21.16 seconds
Started Oct 09 06:18:14 PM UTC 24
Finished Oct 09 06:18:36 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075292118 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.1075292118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2353637158
Short name T1243
Test name
Test status
Simulation time 14906100 ps
CPU time 20.05 seconds
Started Oct 09 06:18:14 PM UTC 24
Finished Oct 09 06:18:35 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353637158 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.2353637158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3047425539
Short name T1246
Test name
Test status
Simulation time 17063400 ps
CPU time 19.75 seconds
Started Oct 09 06:18:18 PM UTC 24
Finished Oct 09 06:18:39 PM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047425539 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.3047425539
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1485610573
Short name T1249
Test name
Test status
Simulation time 18381000 ps
CPU time 24.09 seconds
Started Oct 09 06:18:19 PM UTC 24
Finished Oct 09 06:18:45 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485610573 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.1485610573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2282489077
Short name T1250
Test name
Test status
Simulation time 52682500 ps
CPU time 24.17 seconds
Started Oct 09 06:18:19 PM UTC 24
Finished Oct 09 06:18:45 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282489077 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.2282489077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1053093966
Short name T1248
Test name
Test status
Simulation time 32184700 ps
CPU time 20.98 seconds
Started Oct 09 06:18:21 PM UTC 24
Finished Oct 09 06:18:44 PM UTC 24
Peak memory 274108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053093966 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.1053093966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1703845720
Short name T1252
Test name
Test status
Simulation time 31576100 ps
CPU time 24.21 seconds
Started Oct 09 06:18:23 PM UTC 24
Finished Oct 09 06:18:49 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703845720 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.1703845720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.2035721249
Short name T1251
Test name
Test status
Simulation time 69582200 ps
CPU time 18.06 seconds
Started Oct 09 06:18:28 PM UTC 24
Finished Oct 09 06:18:47 PM UTC 24
Peak memory 274108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035721249 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.2035721249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.3710278607
Short name T1254
Test name
Test status
Simulation time 214499800 ps
CPU time 24.65 seconds
Started Oct 09 06:18:30 PM UTC 24
Finished Oct 09 06:18:56 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710278607 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.3710278607
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1881616889
Short name T278
Test name
Test status
Simulation time 842714100 ps
CPU time 52.43 seconds
Started Oct 09 06:13:14 PM UTC 24
Finished Oct 09 06:14:08 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881616889 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1881616889
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.359417751
Short name T279
Test name
Test status
Simulation time 1466239100 ps
CPU time 58.95 seconds
Started Oct 09 06:13:12 PM UTC 24
Finished Oct 09 06:14:13 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359417751 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.359417751
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2529016188
Short name T1160
Test name
Test status
Simulation time 118005200 ps
CPU time 84.48 seconds
Started Oct 09 06:13:05 PM UTC 24
Finished Oct 09 06:14:31 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529016188 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.2529016188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1397819241
Short name T254
Test name
Test status
Simulation time 64714100 ps
CPU time 21.88 seconds
Started Oct 09 06:13:20 PM UTC 24
Finished Oct 09 06:13:44 PM UTC 24
Peak memory 286712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1397819241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1397819241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2993308989
Short name T352
Test name
Test status
Simulation time 174776300 ps
CPU time 20.78 seconds
Started Oct 09 06:13:08 PM UTC 24
Finished Oct 09 06:13:30 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993308989 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.2993308989
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3170439631
Short name T259
Test name
Test status
Simulation time 30255700 ps
CPU time 25.74 seconds
Started Oct 09 06:13:04 PM UTC 24
Finished Oct 09 06:13:31 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170439631 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.3170439631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.973697166
Short name T1152
Test name
Test status
Simulation time 17777500 ps
CPU time 19.25 seconds
Started Oct 09 06:13:03 PM UTC 24
Finished Oct 09 06:13:23 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973697166 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.973697166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3086832474
Short name T277
Test name
Test status
Simulation time 846787800 ps
CPU time 28.85 seconds
Started Oct 09 06:13:14 PM UTC 24
Finished Oct 09 06:13:44 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3086832474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
same_csr_outstanding.3086832474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2076755704
Short name T1151
Test name
Test status
Simulation time 12346000 ps
CPU time 22.02 seconds
Started Oct 09 06:12:50 PM UTC 24
Finished Oct 09 06:13:13 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207
6755704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha
dow_reg_errors.2076755704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.559512635
Short name T1153
Test name
Test status
Simulation time 11760800 ps
CPU time 26.49 seconds
Started Oct 09 06:13:01 PM UTC 24
Finished Oct 09 06:13:29 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=559512635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.559512635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.873453842
Short name T206
Test name
Test status
Simulation time 138555700 ps
CPU time 32.11 seconds
Started Oct 09 06:12:46 PM UTC 24
Finished Oct 09 06:13:20 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873453842 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.873453842
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.843200529
Short name T349
Test name
Test status
Simulation time 1378696200 ps
CPU time 1290.88 seconds
Started Oct 09 06:12:50 PM UTC 24
Finished Oct 09 06:34:38 PM UTC 24
Peak memory 276472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843200529 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.843200529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1385588494
Short name T1258
Test name
Test status
Simulation time 17928100 ps
CPU time 26.91 seconds
Started Oct 09 06:18:36 PM UTC 24
Finished Oct 09 06:19:05 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385588494 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1385588494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.601934501
Short name T1257
Test name
Test status
Simulation time 55196300 ps
CPU time 26.92 seconds
Started Oct 09 06:18:36 PM UTC 24
Finished Oct 09 06:19:05 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601934501 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.601934501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.2958961092
Short name T1253
Test name
Test status
Simulation time 18306600 ps
CPU time 15.95 seconds
Started Oct 09 06:18:37 PM UTC 24
Finished Oct 09 06:18:54 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958961092 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.2958961092
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.857695660
Short name T1259
Test name
Test status
Simulation time 15764000 ps
CPU time 26.24 seconds
Started Oct 09 06:18:38 PM UTC 24
Finished Oct 09 06:19:06 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857695660 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.857695660
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2609869801
Short name T1260
Test name
Test status
Simulation time 42479100 ps
CPU time 25.94 seconds
Started Oct 09 06:18:40 PM UTC 24
Finished Oct 09 06:19:08 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609869801 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.2609869801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2917909072
Short name T1255
Test name
Test status
Simulation time 58236100 ps
CPU time 19.65 seconds
Started Oct 09 06:18:40 PM UTC 24
Finished Oct 09 06:19:02 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917909072 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2917909072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.3433586202
Short name T1263
Test name
Test status
Simulation time 252952800 ps
CPU time 26.5 seconds
Started Oct 09 06:18:44 PM UTC 24
Finished Oct 09 06:19:12 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433586202 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.3433586202
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.119469974
Short name T1261
Test name
Test status
Simulation time 25912400 ps
CPU time 22.02 seconds
Started Oct 09 06:18:45 PM UTC 24
Finished Oct 09 06:19:09 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119469974 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.119469974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3422312795
Short name T1256
Test name
Test status
Simulation time 14461600 ps
CPU time 15.71 seconds
Started Oct 09 06:18:45 PM UTC 24
Finished Oct 09 06:19:03 PM UTC 24
Peak memory 274368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422312795 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.3422312795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.738406293
Short name T1264
Test name
Test status
Simulation time 19057900 ps
CPU time 23.57 seconds
Started Oct 09 06:18:48 PM UTC 24
Finished Oct 09 06:19:13 PM UTC 24
Peak memory 274300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738406293 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.738406293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3889455785
Short name T355
Test name
Test status
Simulation time 440193800 ps
CPU time 66.13 seconds
Started Oct 09 06:13:45 PM UTC 24
Finished Oct 09 06:14:53 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889455785 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3889455785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.793886230
Short name T354
Test name
Test status
Simulation time 662475200 ps
CPU time 81.29 seconds
Started Oct 09 06:13:44 PM UTC 24
Finished Oct 09 06:15:07 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793886230 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.793886230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3634584399
Short name T1163
Test name
Test status
Simulation time 20370800 ps
CPU time 62.55 seconds
Started Oct 09 06:13:42 PM UTC 24
Finished Oct 09 06:14:46 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634584399 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.3634584399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.925824312
Short name T240
Test name
Test status
Simulation time 209524900 ps
CPU time 33.69 seconds
Started Oct 09 06:13:49 PM UTC 24
Finished Oct 09 06:14:25 PM UTC 24
Peak memory 290664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=925824312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.925824312
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1409860262
Short name T292
Test name
Test status
Simulation time 94523600 ps
CPU time 22.61 seconds
Started Oct 09 06:13:44 PM UTC 24
Finished Oct 09 06:14:08 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409860262 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.1409860262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.3883354854
Short name T318
Test name
Test status
Simulation time 25714200 ps
CPU time 20.62 seconds
Started Oct 09 06:13:32 PM UTC 24
Finished Oct 09 06:13:54 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883354854 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3883354854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2350638315
Short name T1154
Test name
Test status
Simulation time 80090900 ps
CPU time 22.1 seconds
Started Oct 09 06:13:33 PM UTC 24
Finished Oct 09 06:13:57 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350638315 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.2350638315
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3729947830
Short name T1157
Test name
Test status
Simulation time 269586400 ps
CPU time 21.08 seconds
Started Oct 09 06:13:45 PM UTC 24
Finished Oct 09 06:14:08 PM UTC 24
Peak memory 274424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3729947830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
same_csr_outstanding.3729947830
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.529313317
Short name T1156
Test name
Test status
Simulation time 11857600 ps
CPU time 30.14 seconds
Started Oct 09 06:13:31 PM UTC 24
Finished Oct 09 06:14:02 PM UTC 24
Peak memory 274232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529
313317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shad
ow_reg_errors.529313317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2125970582
Short name T1155
Test name
Test status
Simulation time 126030500 ps
CPU time 26.56 seconds
Started Oct 09 06:13:32 PM UTC 24
Finished Oct 09 06:14:00 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2125970582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2125970582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1897572022
Short name T237
Test name
Test status
Simulation time 394934700 ps
CPU time 26.89 seconds
Started Oct 09 06:13:24 PM UTC 24
Finished Oct 09 06:13:53 PM UTC 24
Peak memory 276284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897572022 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1897572022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1323793419
Short name T222
Test name
Test status
Simulation time 351267400 ps
CPU time 616.38 seconds
Started Oct 09 06:13:31 PM UTC 24
Finished Oct 09 06:23:55 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323793419 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.1323793419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2504695825
Short name T1262
Test name
Test status
Simulation time 16911000 ps
CPU time 19.4 seconds
Started Oct 09 06:18:50 PM UTC 24
Finished Oct 09 06:19:10 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504695825 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.2504695825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2716708537
Short name T1266
Test name
Test status
Simulation time 25427300 ps
CPU time 25.05 seconds
Started Oct 09 06:18:54 PM UTC 24
Finished Oct 09 06:19:21 PM UTC 24
Peak memory 274372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716708537 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.2716708537
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.386409569
Short name T1265
Test name
Test status
Simulation time 56325300 ps
CPU time 19.58 seconds
Started Oct 09 06:18:55 PM UTC 24
Finished Oct 09 06:19:16 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386409569 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.386409569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.4169281364
Short name T1267
Test name
Test status
Simulation time 56523100 ps
CPU time 24.74 seconds
Started Oct 09 06:18:56 PM UTC 24
Finished Oct 09 06:19:23 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169281364 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.4169281364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.741492437
Short name T1270
Test name
Test status
Simulation time 51797100 ps
CPU time 23.86 seconds
Started Oct 09 06:19:02 PM UTC 24
Finished Oct 09 06:19:28 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741492437 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.741492437
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1559389413
Short name T1272
Test name
Test status
Simulation time 27934300 ps
CPU time 23.85 seconds
Started Oct 09 06:19:04 PM UTC 24
Finished Oct 09 06:19:29 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559389413 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.1559389413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.4111700634
Short name T1269
Test name
Test status
Simulation time 79448400 ps
CPU time 19.14 seconds
Started Oct 09 06:19:06 PM UTC 24
Finished Oct 09 06:19:26 PM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111700634 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.4111700634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3804012416
Short name T1271
Test name
Test status
Simulation time 46532600 ps
CPU time 21.06 seconds
Started Oct 09 06:19:06 PM UTC 24
Finished Oct 09 06:19:28 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804012416 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.3804012416
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.3428869335
Short name T1268
Test name
Test status
Simulation time 58605000 ps
CPU time 16.43 seconds
Started Oct 09 06:19:07 PM UTC 24
Finished Oct 09 06:19:24 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428869335 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.3428869335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.1288402651
Short name T1273
Test name
Test status
Simulation time 57147900 ps
CPU time 20.5 seconds
Started Oct 09 06:19:09 PM UTC 24
Finished Oct 09 06:19:31 PM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288402651 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.1288402651
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2510398797
Short name T353
Test name
Test status
Simulation time 48049500 ps
CPU time 28.52 seconds
Started Oct 09 06:14:09 PM UTC 24
Finished Oct 09 06:14:39 PM UTC 24
Peak memory 290680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2510398797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2510398797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4041254882
Short name T1161
Test name
Test status
Simulation time 29804700 ps
CPU time 28.11 seconds
Started Oct 09 06:14:04 PM UTC 24
Finished Oct 09 06:14:34 PM UTC 24
Peak memory 276276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041254882 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.4041254882
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.3305970915
Short name T319
Test name
Test status
Simulation time 51715200 ps
CPU time 26.89 seconds
Started Oct 09 06:14:03 PM UTC 24
Finished Oct 09 06:14:31 PM UTC 24
Peak memory 274308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305970915 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3305970915
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1857417979
Short name T1162
Test name
Test status
Simulation time 587469700 ps
CPU time 35.56 seconds
Started Oct 09 06:14:08 PM UTC 24
Finished Oct 09 06:14:45 PM UTC 24
Peak memory 276472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1857417979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
same_csr_outstanding.1857417979
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1950783523
Short name T1158
Test name
Test status
Simulation time 12764800 ps
CPU time 27.51 seconds
Started Oct 09 06:13:58 PM UTC 24
Finished Oct 09 06:14:27 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195
0783523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha
dow_reg_errors.1950783523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4259583150
Short name T1159
Test name
Test status
Simulation time 18512800 ps
CPU time 29.06 seconds
Started Oct 09 06:14:01 PM UTC 24
Finished Oct 09 06:14:31 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4259583150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.4259583150
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4270136559
Short name T233
Test name
Test status
Simulation time 61630100 ps
CPU time 37.32 seconds
Started Oct 09 06:13:55 PM UTC 24
Finished Oct 09 06:14:34 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270136559 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.4270136559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3101015994
Short name T348
Test name
Test status
Simulation time 1030620900 ps
CPU time 1403.29 seconds
Started Oct 09 06:13:55 PM UTC 24
Finished Oct 09 06:37:37 PM UTC 24
Peak memory 278460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101015994 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.3101015994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3649964107
Short name T242
Test name
Test status
Simulation time 29366200 ps
CPU time 23.4 seconds
Started Oct 09 06:14:34 PM UTC 24
Finished Oct 09 06:14:59 PM UTC 24
Peak memory 286776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3649964107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3649964107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2339735580
Short name T280
Test name
Test status
Simulation time 251959100 ps
CPU time 21.69 seconds
Started Oct 09 06:14:32 PM UTC 24
Finished Oct 09 06:14:55 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339735580 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.2339735580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1821057704
Short name T335
Test name
Test status
Simulation time 101888700 ps
CPU time 24.52 seconds
Started Oct 09 06:14:32 PM UTC 24
Finished Oct 09 06:14:58 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821057704 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1821057704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3131093019
Short name T281
Test name
Test status
Simulation time 739672100 ps
CPU time 32.37 seconds
Started Oct 09 06:14:32 PM UTC 24
Finished Oct 09 06:15:06 PM UTC 24
Peak memory 276536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3131093019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
same_csr_outstanding.3131093019
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.500686222
Short name T1164
Test name
Test status
Simulation time 21692300 ps
CPU time 26.69 seconds
Started Oct 09 06:14:26 PM UTC 24
Finished Oct 09 06:14:54 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500
686222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shad
ow_reg_errors.500686222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1912140488
Short name T1165
Test name
Test status
Simulation time 13892800 ps
CPU time 30.72 seconds
Started Oct 09 06:14:28 PM UTC 24
Finished Oct 09 06:15:00 PM UTC 24
Peak memory 274156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1912140488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1912140488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1840762525
Short name T208
Test name
Test status
Simulation time 469343700 ps
CPU time 29.72 seconds
Started Oct 09 06:14:09 PM UTC 24
Finished Oct 09 06:14:40 PM UTC 24
Peak memory 276288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840762525 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1840762525
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3243665048
Short name T244
Test name
Test status
Simulation time 4817186700 ps
CPU time 1418.27 seconds
Started Oct 09 06:14:14 PM UTC 24
Finished Oct 09 06:38:11 PM UTC 24
Peak memory 278452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243665048 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.3243665048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1105218529
Short name T284
Test name
Test status
Simulation time 203496400 ps
CPU time 32.42 seconds
Started Oct 09 06:14:54 PM UTC 24
Finished Oct 09 06:15:28 PM UTC 24
Peak memory 286584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1105218529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1105218529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.34266709
Short name T1168
Test name
Test status
Simulation time 149547700 ps
CPU time 28.48 seconds
Started Oct 09 06:14:46 PM UTC 24
Finished Oct 09 06:15:16 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34266709 -assert n
opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.34266709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2101526747
Short name T320
Test name
Test status
Simulation time 14515100 ps
CPU time 25.99 seconds
Started Oct 09 06:14:41 PM UTC 24
Finished Oct 09 06:15:08 PM UTC 24
Peak memory 274108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101526747 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2101526747
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1634693549
Short name T283
Test name
Test status
Simulation time 216386300 ps
CPU time 21.21 seconds
Started Oct 09 06:14:47 PM UTC 24
Finished Oct 09 06:15:10 PM UTC 24
Peak memory 276344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1634693549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
same_csr_outstanding.1634693549
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.552300123
Short name T1166
Test name
Test status
Simulation time 11996800 ps
CPU time 25.84 seconds
Started Oct 09 06:14:40 PM UTC 24
Finished Oct 09 06:15:07 PM UTC 24
Peak memory 274168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552
300123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shad
ow_reg_errors.552300123
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4023004903
Short name T1167
Test name
Test status
Simulation time 16663100 ps
CPU time 26.78 seconds
Started Oct 09 06:14:40 PM UTC 24
Finished Oct 09 06:15:08 PM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4023004903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.4023004903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3367921172
Short name T234
Test name
Test status
Simulation time 150416700 ps
CPU time 29.22 seconds
Started Oct 09 06:14:34 PM UTC 24
Finished Oct 09 06:15:05 PM UTC 24
Peak memory 276292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367921172 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3367921172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1371820280
Short name T224
Test name
Test status
Simulation time 462740400 ps
CPU time 696.61 seconds
Started Oct 09 06:14:38 PM UTC 24
Finished Oct 09 06:26:24 PM UTC 24
Peak memory 276348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371820280 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.1371820280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1946912091
Short name T1174
Test name
Test status
Simulation time 44367600 ps
CPU time 33.98 seconds
Started Oct 09 06:15:08 PM UTC 24
Finished Oct 09 06:15:44 PM UTC 24
Peak memory 292856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1946912091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1946912091
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1414981188
Short name T1171
Test name
Test status
Simulation time 56607900 ps
CPU time 26.54 seconds
Started Oct 09 06:15:06 PM UTC 24
Finished Oct 09 06:15:34 PM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414981188 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.1414981188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.688889669
Short name T321
Test name
Test status
Simulation time 14241400 ps
CPU time 23.77 seconds
Started Oct 09 06:15:01 PM UTC 24
Finished Oct 09 06:15:26 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688889669 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.688889669
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1637842293
Short name T285
Test name
Test status
Simulation time 1673835000 ps
CPU time 29.34 seconds
Started Oct 09 06:15:07 PM UTC 24
Finished Oct 09 06:15:38 PM UTC 24
Peak memory 276472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1637842293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
same_csr_outstanding.1637842293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.889859013
Short name T1170
Test name
Test status
Simulation time 11633900 ps
CPU time 31.39 seconds
Started Oct 09 06:14:58 PM UTC 24
Finished Oct 09 06:15:31 PM UTC 24
Peak memory 274164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889
859013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shad
ow_reg_errors.889859013
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.536534173
Short name T1169
Test name
Test status
Simulation time 12067800 ps
CPU time 19.72 seconds
Started Oct 09 06:15:00 PM UTC 24
Finished Oct 09 06:15:21 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=536534173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.536534173
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3554810832
Short name T239
Test name
Test status
Simulation time 36214600 ps
CPU time 28.99 seconds
Started Oct 09 06:14:54 PM UTC 24
Finished Oct 09 06:15:25 PM UTC 24
Peak memory 276292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554810832 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3554810832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2410528150
Short name T338
Test name
Test status
Simulation time 322169400 ps
CPU time 725.86 seconds
Started Oct 09 06:14:55 PM UTC 24
Finished Oct 09 06:27:11 PM UTC 24
Peak memory 276340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410528150 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.2410528150
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3450009315
Short name T286
Test name
Test status
Simulation time 227493000 ps
CPU time 24.31 seconds
Started Oct 09 06:15:25 PM UTC 24
Finished Oct 09 06:15:51 PM UTC 24
Peak memory 286584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3450009315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3450009315
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3459981754
Short name T1175
Test name
Test status
Simulation time 127513900 ps
CPU time 29.29 seconds
Started Oct 09 06:15:17 PM UTC 24
Finished Oct 09 06:15:48 PM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459981754 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.3459981754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1006418668
Short name T322
Test name
Test status
Simulation time 15592500 ps
CPU time 26.72 seconds
Started Oct 09 06:15:12 PM UTC 24
Finished Oct 09 06:15:41 PM UTC 24
Peak memory 274180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006418668 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1006418668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.650175879
Short name T1177
Test name
Test status
Simulation time 751352400 ps
CPU time 34.99 seconds
Started Oct 09 06:15:21 PM UTC 24
Finished Oct 09 06:15:58 PM UTC 24
Peak memory 274428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
650175879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_s
ame_csr_outstanding.650175879
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3422563594
Short name T1173
Test name
Test status
Simulation time 22693600 ps
CPU time 30.34 seconds
Started Oct 09 06:15:09 PM UTC 24
Finished Oct 09 06:15:41 PM UTC 24
Peak memory 274160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342
2563594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha
dow_reg_errors.3422563594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.656015702
Short name T1172
Test name
Test status
Simulation time 32017800 ps
CPU time 22.25 seconds
Started Oct 09 06:15:10 PM UTC 24
Finished Oct 09 06:15:34 PM UTC 24
Peak memory 263924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=656015702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.656015702
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3902977826
Short name T236
Test name
Test status
Simulation time 80536600 ps
CPU time 24.33 seconds
Started Oct 09 06:15:08 PM UTC 24
Finished Oct 09 06:15:34 PM UTC 24
Peak memory 276416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902977826 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3902977826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2746549888
Short name T124
Test name
Test status
Simulation time 27997100 ps
CPU time 20.73 seconds
Started Oct 09 07:15:55 PM UTC 24
Finished Oct 09 07:16:17 PM UTC 24
Peak memory 273116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746549888 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.2746549888
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1950955128
Short name T25
Test name
Test status
Simulation time 50945300 ps
CPU time 25.22 seconds
Started Oct 09 07:15:02 PM UTC 24
Finished Oct 09 07:15:28 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950955128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1950955128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2685540405
Short name T57
Test name
Test status
Simulation time 738895800 ps
CPU time 252.67 seconds
Started Oct 09 07:12:08 PM UTC 24
Finished Oct 09 07:16:25 PM UTC 24
Peak memory 289972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2685540405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.flash_ctrl_derr_detect.2685540405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3630346629
Short name T271
Test name
Test status
Simulation time 2471734800 ps
CPU time 3266.66 seconds
Started Oct 09 07:08:01 PM UTC 24
Finished Oct 09 08:03:09 PM UTC 24
Peak memory 275872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630346629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3630346629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1750075789
Short name T104
Test name
Test status
Simulation time 635475000 ps
CPU time 45.07 seconds
Started Oct 09 07:15:20 PM UTC 24
Finished Oct 09 07:16:07 PM UTC 24
Peak memory 273248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750075
789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f
s_sup.1750075789
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.357373688
Short name T379
Test name
Test status
Simulation time 41001800 ps
CPU time 44.97 seconds
Started Oct 09 07:16:18 PM UTC 24
Finished Oct 09 07:17:04 PM UTC 24
Peak memory 285368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357373688
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hos
t_addr_infection.357373688
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.2606157977
Short name T3
Test name
Test status
Simulation time 64731600 ps
CPU time 42.12 seconds
Started Oct 09 07:04:35 PM UTC 24
Finished Oct 09 07:05:18 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606157977 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2606157977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2274726405
Short name T130
Test name
Test status
Simulation time 10035667700 ps
CPU time 76.28 seconds
Started Oct 09 07:16:08 PM UTC 24
Finished Oct 09 07:17:26 PM UTC 24
Peak memory 293712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2274726405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2274726405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1474374480
Short name T129
Test name
Test status
Simulation time 80147504400 ps
CPU time 999.49 seconds
Started Oct 09 07:05:12 PM UTC 24
Finished Oct 09 07:22:07 PM UTC 24
Peak memory 278020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474374480
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.1474374480
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.169868734
Short name T45
Test name
Test status
Simulation time 4301211200 ps
CPU time 231.82 seconds
Started Oct 09 07:12:52 PM UTC 24
Finished Oct 09 07:16:48 PM UTC 24
Peak memory 302184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169868734 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.169868734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1636926892
Short name T38
Test name
Test status
Simulation time 35230085900 ps
CPU time 236.53 seconds
Started Oct 09 07:13:21 PM UTC 24
Finished Oct 09 07:17:23 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636926892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1636926892
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.692795830
Short name T134
Test name
Test status
Simulation time 82244200 ps
CPU time 20.48 seconds
Started Oct 09 07:15:57 PM UTC 24
Finished Oct 09 07:16:19 PM UTC 24
Peak memory 273484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=692795830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_lcmgr_intg.692795830
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1709049444
Short name T24
Test name
Test status
Simulation time 2127233500 ps
CPU time 235.9 seconds
Started Oct 09 07:12:11 PM UTC 24
Finished Oct 09 07:16:11 PM UTC 24
Peak memory 302064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1709049444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_oversize_error.1709049444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.555683805
Short name T54
Test name
Test status
Simulation time 315363800 ps
CPU time 579.12 seconds
Started Oct 09 07:04:37 PM UTC 24
Finished Oct 09 07:14:25 PM UTC 24
Peak memory 277948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555683805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.555683805
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.4179385541
Short name T23
Test name
Test status
Simulation time 57838300 ps
CPU time 21.26 seconds
Started Oct 09 07:15:34 PM UTC 24
Finished Oct 09 07:15:57 PM UTC 24
Peak memory 273488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4179385541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4179385541
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1651846176
Short name T72
Test name
Test status
Simulation time 42419800 ps
CPU time 21.65 seconds
Started Oct 09 07:13:34 PM UTC 24
Finished Oct 09 07:13:57 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651846176 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.1651846176
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2513381743
Short name T144
Test name
Test status
Simulation time 588504900 ps
CPU time 1383.33 seconds
Started Oct 09 07:04:32 PM UTC 24
Finished Oct 09 07:27:55 PM UTC 24
Peak memory 294312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513381743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2513381743
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2697346295
Short name T18
Test name
Test status
Simulation time 201804200 ps
CPU time 165 seconds
Started Oct 09 07:04:36 PM UTC 24
Finished Oct 09 07:07:24 PM UTC 24
Peak memory 273408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697346295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2697346295
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.1791810665
Short name T377
Test name
Test status
Simulation time 77567700 ps
CPU time 65.22 seconds
Started Oct 09 07:16:12 PM UTC 24
Finished Oct 09 07:17:19 PM UTC 24
Peak memory 287684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791810665 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.1791810665
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.3101898237
Short name T37
Test name
Test status
Simulation time 100646300 ps
CPU time 51.77 seconds
Started Oct 09 07:14:26 PM UTC 24
Finished Oct 09 07:15:19 PM UTC 24
Peak memory 283584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101898237 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.3101898237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1656734565
Short name T19
Test name
Test status
Simulation time 24776000 ps
CPU time 21.87 seconds
Started Oct 09 07:09:23 PM UTC 24
Finished Oct 09 07:09:46 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656734565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1656734565
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2138208255
Short name T53
Test name
Test status
Simulation time 17717000 ps
CPU time 33.65 seconds
Started Oct 09 07:11:32 PM UTC 24
Finished Oct 09 07:12:07 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2138208255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_read_word_sweep_derr.2138208255
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2755691130
Short name T66
Test name
Test status
Simulation time 45237300 ps
CPU time 34.76 seconds
Started Oct 09 07:09:54 PM UTC 24
Finished Oct 09 07:10:30 PM UTC 24
Peak memory 275392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755691130 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.2755691130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.1432572709
Short name T13
Test name
Test status
Simulation time 505207100 ps
CPU time 120.86 seconds
Started Oct 09 07:09:30 PM UTC 24
Finished Oct 09 07:11:33 PM UTC 24
Peak memory 302080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1432572709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.1432572709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.767847560
Short name T61
Test name
Test status
Simulation time 1426757500 ps
CPU time 171.23 seconds
Started Oct 09 07:11:35 PM UTC 24
Finished Oct 09 07:14:29 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767847560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.767847560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2806344911
Short name T49
Test name
Test status
Simulation time 2601995200 ps
CPU time 156.47 seconds
Started Oct 09 07:10:11 PM UTC 24
Finished Oct 09 07:12:51 PM UTC 24
Peak memory 306360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2806344911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_ro_serr.2806344911
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.2339168009
Short name T142
Test name
Test status
Simulation time 18825135200 ps
CPU time 679.09 seconds
Started Oct 09 07:09:47 PM UTC 24
Finished Oct 09 07:21:16 PM UTC 24
Peak memory 320528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339168009 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.2339168009
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.2203153523
Short name T34
Test name
Test status
Simulation time 196604900 ps
CPU time 45.59 seconds
Started Oct 09 07:13:58 PM UTC 24
Finished Oct 09 07:14:45 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203153523 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.2203153523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.539557286
Short name T35
Test name
Test status
Simulation time 118445100 ps
CPU time 47.15 seconds
Started Oct 09 07:14:12 PM UTC 24
Finished Oct 09 07:15:01 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=539557286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctr
l_rw_evict_all_en.539557286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1102801878
Short name T14
Test name
Test status
Simulation time 25038612800 ps
CPU time 6758.2 seconds
Started Oct 09 07:14:44 PM UTC 24
Finished Oct 09 09:08:41 PM UTC 24
Peak memory 318288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102801878 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1102801878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3889637086
Short name T70
Test name
Test status
Simulation time 2545476400 ps
CPU time 92.95 seconds
Started Oct 09 07:11:25 PM UTC 24
Finished Oct 09 07:13:01 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388
9637086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_address.3889637086
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.779773160
Short name T48
Test name
Test status
Simulation time 292021900 ps
CPU time 58.66 seconds
Started Oct 09 07:10:37 PM UTC 24
Finished Oct 09 07:11:38 PM UTC 24
Peak memory 285700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77
9773160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_counter.779773160
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.3120199217
Short name T17
Test name
Test status
Simulation time 146777200 ps
CPU time 120.27 seconds
Started Oct 09 07:04:26 PM UTC 24
Finished Oct 09 07:06:30 PM UTC 24
Peak memory 287616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120199217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3120199217
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.990372862
Short name T1
Test name
Test status
Simulation time 23845800 ps
CPU time 42.25 seconds
Started Oct 09 07:04:27 PM UTC 24
Finished Oct 09 07:05:11 PM UTC 24
Peak memory 271236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990372862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.990372862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.310558950
Short name T210
Test name
Test status
Simulation time 53935700 ps
CPU time 343.55 seconds
Started Oct 09 07:14:46 PM UTC 24
Finished Oct 09 07:20:35 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310558950 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.310558950
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.1452243940
Short name T2
Test name
Test status
Simulation time 34990900 ps
CPU time 42.17 seconds
Started Oct 09 07:04:35 PM UTC 24
Finished Oct 09 07:05:18 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452243940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1452243940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2112383905
Short name T71
Test name
Test status
Simulation time 16859246100 ps
CPU time 152.62 seconds
Started Oct 09 07:08:54 PM UTC 24
Finished Oct 09 07:11:30 PM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2112383905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.2112383905
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.933587196
Short name T10
Test name
Test status
Simulation time 50093300 ps
CPU time 22.98 seconds
Started Oct 09 07:08:57 PM UTC 24
Finished Oct 09 07:09:22 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933587196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.933587196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2496302609
Short name T21
Test name
Test status
Simulation time 14558000 ps
CPU time 21.67 seconds
Started Oct 09 07:30:19 PM UTC 24
Finished Oct 09 07:30:42 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2496302609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2496302609
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.1127180063
Short name T111
Test name
Test status
Simulation time 68407200 ps
CPU time 21.62 seconds
Started Oct 09 07:31:32 PM UTC 24
Finished Oct 09 07:31:55 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127180063 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1127180063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.3482577027
Short name T26
Test name
Test status
Simulation time 27124900 ps
CPU time 25.03 seconds
Started Oct 09 07:29:28 PM UTC 24
Finished Oct 09 07:29:54 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482577027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3482577027
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.1105777853
Short name T261
Test name
Test status
Simulation time 1493960100 ps
CPU time 270.64 seconds
Started Oct 09 07:24:16 PM UTC 24
Finished Oct 09 07:28:51 PM UTC 24
Peak memory 289780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1105777853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_derr_detect.1105777853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.71027558
Short name T424
Test name
Test status
Simulation time 11172900 ps
CPU time 33.38 seconds
Started Oct 09 07:28:52 PM UTC 24
Finished Oct 09 07:29:27 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=71027558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctr
l_disable.71027558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.521323846
Short name T31
Test name
Test status
Simulation time 7715131200 ps
CPU time 662.21 seconds
Started Oct 09 07:17:06 PM UTC 24
Finished Oct 09 07:28:18 PM UTC 24
Peak memory 276116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521323846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.521323846
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.3805098234
Short name T272
Test name
Test status
Simulation time 23441297100 ps
CPU time 3554.54 seconds
Started Oct 09 07:19:54 PM UTC 24
Finished Oct 09 08:19:52 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805098234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.3805098234
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2082235987
Short name T274
Test name
Test status
Simulation time 2072510900 ps
CPU time 1320.9 seconds
Started Oct 09 07:19:38 PM UTC 24
Finished Oct 09 07:41:57 PM UTC 24
Peak memory 288104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082235987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2082235987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2101412142
Short name T426
Test name
Test status
Simulation time 310330100 ps
CPU time 49.29 seconds
Started Oct 09 07:30:22 PM UTC 24
Finished Oct 09 07:31:13 PM UTC 24
Peak memory 275324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101412
142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f
s_sup.2101412142
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.215252040
Short name T151
Test name
Test status
Simulation time 116407723700 ps
CPU time 3794.18 seconds
Started Oct 09 07:18:41 PM UTC 24
Finished Oct 09 08:22:43 PM UTC 24
Peak memory 277888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215252040 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.215252040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2684810304
Short name T288
Test name
Test status
Simulation time 65826400 ps
CPU time 47.01 seconds
Started Oct 09 07:31:28 PM UTC 24
Finished Oct 09 07:32:17 PM UTC 24
Peak memory 281596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268481030
4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho
st_addr_infection.2684810304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.2886186595
Short name T212
Test name
Test status
Simulation time 74742100 ps
CPU time 41.29 seconds
Started Oct 09 07:16:44 PM UTC 24
Finished Oct 09 07:17:27 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886186595 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2886186595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1883227881
Short name T165
Test name
Test status
Simulation time 16629500 ps
CPU time 21.12 seconds
Started Oct 09 07:31:14 PM UTC 24
Finished Oct 09 07:31:36 PM UTC 24
Peak memory 271144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1883227881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_hw_read_seed_err.1883227881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.316576413
Short name T132
Test name
Test status
Simulation time 104097729600 ps
CPU time 2022.95 seconds
Started Oct 09 07:17:17 PM UTC 24
Finished Oct 09 07:51:27 PM UTC 24
Peak memory 275772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316576413 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.316576413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3008498406
Short name T378
Test name
Test status
Simulation time 5125673600 ps
CPU time 700.65 seconds
Started Oct 09 07:24:47 PM UTC 24
Finished Oct 09 07:36:38 PM UTC 24
Peak memory 343264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3008498406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr
ity.3008498406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.831498401
Short name T47
Test name
Test status
Simulation time 1593944600 ps
CPU time 257.92 seconds
Started Oct 09 07:25:33 PM UTC 24
Finished Oct 09 07:29:56 PM UTC 24
Peak memory 293792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831498401 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.831498401
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1373626145
Short name T80
Test name
Test status
Simulation time 35208940200 ps
CPU time 357.6 seconds
Started Oct 09 07:26:45 PM UTC 24
Finished Oct 09 07:32:49 PM UTC 24
Peak memory 301880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1373626145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_intr_rd_slow_flash.1373626145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.2462083317
Short name T39
Test name
Test status
Simulation time 48444392300 ps
CPU time 119.21 seconds
Started Oct 09 07:25:53 PM UTC 24
Finished Oct 09 07:27:55 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462083317 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.2462083317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4283169116
Short name T427
Test name
Test status
Simulation time 45751571800 ps
CPU time 313.25 seconds
Started Oct 09 07:27:56 PM UTC 24
Finished Oct 09 07:33:14 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283169116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.4283169116
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.3357516133
Short name T89
Test name
Test status
Simulation time 3531198000 ps
CPU time 91.88 seconds
Started Oct 09 07:20:25 PM UTC 24
Finished Oct 09 07:22:00 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357516133 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3357516133
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2618191379
Short name T167
Test name
Test status
Simulation time 25006700 ps
CPU time 21.38 seconds
Started Oct 09 07:31:09 PM UTC 24
Finished Oct 09 07:31:31 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2618191379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_lcmgr_intg.2618191379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3164205905
Short name T41
Test name
Test status
Simulation time 6436852500 ps
CPU time 141.81 seconds
Started Oct 09 07:17:28 PM UTC 24
Finished Oct 09 07:19:53 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3164205905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_mp_regions.3164205905
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1854260877
Short name T84
Test name
Test status
Simulation time 40161600 ps
CPU time 214.15 seconds
Started Oct 09 07:17:24 PM UTC 24
Finished Oct 09 07:21:02 PM UTC 24
Peak memory 275356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854260877 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1854260877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3440966314
Short name T55
Test name
Test status
Simulation time 1409375100 ps
CPU time 231.51 seconds
Started Oct 09 07:24:17 PM UTC 24
Finished Oct 09 07:28:13 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3440966314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_oversize_error.3440966314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1079560870
Short name T69
Test name
Test status
Simulation time 25283900 ps
CPU time 22.74 seconds
Started Oct 09 07:30:49 PM UTC 24
Finished Oct 09 07:31:13 PM UTC 24
Peak memory 293124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079560870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1079560870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1281379224
Short name T143
Test name
Test status
Simulation time 745685500 ps
CPU time 512.98 seconds
Started Oct 09 07:16:51 PM UTC 24
Finished Oct 09 07:25:33 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281379224 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1281379224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3329830621
Short name T215
Test name
Test status
Simulation time 14462400 ps
CPU time 23.32 seconds
Started Oct 09 07:30:43 PM UTC 24
Finished Oct 09 07:31:08 PM UTC 24
Peak memory 273516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3329830621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3329830621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1705049085
Short name T425
Test name
Test status
Simulation time 5429301800 ps
CPU time 157.02 seconds
Started Oct 09 07:27:56 PM UTC 24
Finished Oct 09 07:30:36 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705049085 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.1705049085
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2926321256
Short name T153
Test name
Test status
Simulation time 125133400 ps
CPU time 1488.92 seconds
Started Oct 09 07:16:26 PM UTC 24
Finished Oct 09 07:41:37 PM UTC 24
Peak memory 298408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926321256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2926321256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.108280839
Short name T30
Test name
Test status
Simulation time 15340339800 ps
CPU time 211.54 seconds
Started Oct 09 07:16:49 PM UTC 24
Finished Oct 09 07:20:25 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108280839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.108280839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.3028907907
Short name T193
Test name
Test status
Simulation time 86911900 ps
CPU time 51.94 seconds
Started Oct 09 07:29:55 PM UTC 24
Finished Oct 09 07:30:49 PM UTC 24
Peak memory 287548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302890790
7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.3028907907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1784988723
Short name T250
Test name
Test status
Simulation time 72696700 ps
CPU time 48.79 seconds
Started Oct 09 07:28:19 PM UTC 24
Finished Oct 09 07:29:10 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784988723 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.1784988723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1982553331
Short name T185
Test name
Test status
Simulation time 18263800 ps
CPU time 34.62 seconds
Started Oct 09 07:23:18 PM UTC 24
Finished Oct 09 07:23:54 PM UTC 24
Peak memory 275372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1982553331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_read_word_sweep_derr.1982553331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.1551436725
Short name T182
Test name
Test status
Simulation time 40248600 ps
CPU time 34.91 seconds
Started Oct 09 07:22:01 PM UTC 24
Finished Oct 09 07:22:37 PM UTC 24
Peak memory 275376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551436725 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.1551436725
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2182405373
Short name T161
Test name
Test status
Simulation time 84816935700 ps
CPU time 1279.52 seconds
Started Oct 09 07:31:09 PM UTC 24
Finished Oct 09 07:52:45 PM UTC 24
Peak memory 473692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2182405373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_rma_err.2182405373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.4274175895
Short name T184
Test name
Test status
Simulation time 839594500 ps
CPU time 131.64 seconds
Started Oct 09 07:21:03 PM UTC 24
Finished Oct 09 07:23:17 PM UTC 24
Peak memory 291740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4274175895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.4274175895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.230289757
Short name T199
Test name
Test status
Simulation time 3117718800 ps
CPU time 166.42 seconds
Started Oct 09 07:23:55 PM UTC 24
Finished Oct 09 07:26:45 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230289757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.230289757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3157893645
Short name T113
Test name
Test status
Simulation time 996917800 ps
CPU time 125.91 seconds
Started Oct 09 07:22:07 PM UTC 24
Finished Oct 09 07:24:16 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3157893645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_ro_serr.3157893645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.3159943924
Short name T198
Test name
Test status
Simulation time 50121259900 ps
CPU time 580.8 seconds
Started Oct 09 07:21:18 PM UTC 24
Finished Oct 09 07:31:07 PM UTC 24
Peak memory 320744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159943924 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.3159943924
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.2032301680
Short name T156
Test name
Test status
Simulation time 1697606800 ps
CPU time 230.56 seconds
Started Oct 09 07:24:15 PM UTC 24
Finished Oct 09 07:28:10 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2032301680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rw_derr.2032301680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.170697273
Short name T36
Test name
Test status
Simulation time 29653500 ps
CPU time 45.52 seconds
Started Oct 09 07:28:11 PM UTC 24
Finished Oct 09 07:28:58 PM UTC 24
Peak memory 281456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170697273 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.170697273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2519598640
Short name T386
Test name
Test status
Simulation time 1391212300 ps
CPU time 211.67 seconds
Started Oct 09 07:22:17 PM UTC 24
Finished Oct 09 07:25:53 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2519598640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.2519598640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.2767674936
Short name T186
Test name
Test status
Simulation time 2515782700 ps
CPU time 89.22 seconds
Started Oct 09 07:22:42 PM UTC 24
Finished Oct 09 07:24:14 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276
7674936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_address.2767674936
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1615090179
Short name T187
Test name
Test status
Simulation time 1394159200 ps
CPU time 94.07 seconds
Started Oct 09 07:22:38 PM UTC 24
Finished Oct 09 07:24:15 PM UTC 24
Peak memory 275440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
15090179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se
rr_counter.1615090179
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.254651067
Short name T56
Test name
Test status
Simulation time 103541800 ps
CPU time 191.55 seconds
Started Oct 09 07:16:22 PM UTC 24
Finished Oct 09 07:19:37 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254651067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.254651067
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3752543909
Short name T58
Test name
Test status
Simulation time 25988700 ps
CPU time 38.3 seconds
Started Oct 09 07:16:24 PM UTC 24
Finished Oct 09 07:17:04 PM UTC 24
Peak memory 270984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752543909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3752543909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2240053321
Short name T380
Test name
Test status
Simulation time 307898000 ps
CPU time 959.68 seconds
Started Oct 09 07:29:10 PM UTC 24
Finished Oct 09 07:45:24 PM UTC 24
Peak memory 291596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240053321 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.2240053321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2636221515
Short name T298
Test name
Test status
Simulation time 26574700 ps
CPU time 38.05 seconds
Started Oct 09 07:16:35 PM UTC 24
Finished Oct 09 07:17:16 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636221515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2636221515
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.856496088
Short name T595
Test name
Test status
Simulation time 36800900 ps
CPU time 24.84 seconds
Started Oct 09 08:11:07 PM UTC 24
Finished Oct 09 08:11:34 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856496088 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.856496088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1764821284
Short name T586
Test name
Test status
Simulation time 22435200 ps
CPU time 23.97 seconds
Started Oct 09 08:10:40 PM UTC 24
Finished Oct 09 08:11:05 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764821284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1764821284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2817618528
Short name T601
Test name
Test status
Simulation time 10018569900 ps
CPU time 77.22 seconds
Started Oct 09 08:11:06 PM UTC 24
Finished Oct 09 08:12:25 PM UTC 24
Peak memory 275428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2817618528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2817618528
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2815302385
Short name T263
Test name
Test status
Simulation time 15544000 ps
CPU time 20.13 seconds
Started Oct 09 08:10:54 PM UTC 24
Finished Oct 09 08:11:16 PM UTC 24
Peak memory 269252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2815302385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_hw_read_seed_err.2815302385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.643133393
Short name T587
Test name
Test status
Simulation time 8985654300 ps
CPU time 142.98 seconds
Started Oct 09 08:08:41 PM UTC 24
Finished Oct 09 08:11:06 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643133393 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.643133393
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.1571448734
Short name T332
Test name
Test status
Simulation time 4882003600 ps
CPU time 198.89 seconds
Started Oct 09 08:09:34 PM UTC 24
Finished Oct 09 08:12:56 PM UTC 24
Peak memory 306256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571448734 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.1571448734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.679819275
Short name T621
Test name
Test status
Simulation time 25244861800 ps
CPU time 284.46 seconds
Started Oct 09 08:09:48 PM UTC 24
Finished Oct 09 08:14:37 PM UTC 24
Peak memory 306184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=679819275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_intr_rd_slow_flash.679819275
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.4198892393
Short name T584
Test name
Test status
Simulation time 2889548800 ps
CPU time 94.26 seconds
Started Oct 09 08:09:02 PM UTC 24
Finished Oct 09 08:10:39 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198892393 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.4198892393
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.2414605451
Short name T591
Test name
Test status
Simulation time 38745900 ps
CPU time 26.38 seconds
Started Oct 09 08:10:51 PM UTC 24
Finished Oct 09 08:11:19 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2414605451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_lcmgr_intg.2414605451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.3442756197
Short name T310
Test name
Test status
Simulation time 4553864100 ps
CPU time 185.26 seconds
Started Oct 09 08:08:50 PM UTC 24
Finished Oct 09 08:11:59 PM UTC 24
Peak memory 275128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3442756197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_mp_regions.3442756197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.3205998891
Short name T600
Test name
Test status
Simulation time 42202600 ps
CPU time 214.56 seconds
Started Oct 09 08:08:47 PM UTC 24
Finished Oct 09 08:12:25 PM UTC 24
Peak memory 271200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205998891 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.3205998891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.2991602665
Short name T639
Test name
Test status
Simulation time 2897782600 ps
CPU time 492.54 seconds
Started Oct 09 08:08:40 PM UTC 24
Finished Oct 09 08:16:59 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991602665 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2991602665
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.98964901
Short name T583
Test name
Test status
Simulation time 23815500 ps
CPU time 25.41 seconds
Started Oct 09 08:10:04 PM UTC 24
Finished Oct 09 08:10:31 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98964901 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.98964901
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.170301016
Short name T703
Test name
Test status
Simulation time 11758655900 ps
CPU time 949.32 seconds
Started Oct 09 08:08:38 PM UTC 24
Finished Oct 09 08:24:39 PM UTC 24
Peak memory 293576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170301016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.170301016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.1529123063
Short name T590
Test name
Test status
Simulation time 99016000 ps
CPU time 44.99 seconds
Started Oct 09 08:10:30 PM UTC 24
Finished Oct 09 08:11:17 PM UTC 24
Peak memory 283644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529123063 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.1529123063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.1200499928
Short name T594
Test name
Test status
Simulation time 2197429800 ps
CPU time 126.37 seconds
Started Oct 09 08:09:23 PM UTC 24
Finished Oct 09 08:11:32 PM UTC 24
Peak memory 308216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1200499928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.1200499928
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.4243441152
Short name T588
Test name
Test status
Simulation time 66081100 ps
CPU time 54.51 seconds
Started Oct 09 08:10:16 PM UTC 24
Finished Oct 09 08:11:12 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243441152 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.4243441152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.1709385085
Short name T589
Test name
Test status
Simulation time 43005600 ps
CPU time 49.05 seconds
Started Oct 09 08:10:23 PM UTC 24
Finished Oct 09 08:11:14 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1709385085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw_evict_all_en.1709385085
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.3182406063
Short name T599
Test name
Test status
Simulation time 178508800 ps
CPU time 217.06 seconds
Started Oct 09 08:08:32 PM UTC 24
Finished Oct 09 08:12:13 PM UTC 24
Peak memory 277188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182406063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3182406063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.368489878
Short name T598
Test name
Test status
Simulation time 13192478800 ps
CPU time 183.44 seconds
Started Oct 09 08:09:04 PM UTC 24
Finished Oct 09 08:12:11 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=368489878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.368489878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1214718864
Short name T615
Test name
Test status
Simulation time 98200000 ps
CPU time 26.41 seconds
Started Oct 09 08:13:12 PM UTC 24
Finished Oct 09 08:13:40 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214718864 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1214718864
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3073580552
Short name T608
Test name
Test status
Simulation time 26296900 ps
CPU time 23.32 seconds
Started Oct 09 08:12:56 PM UTC 24
Finished Oct 09 08:13:20 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073580552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3073580552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.1759953475
Short name T607
Test name
Test status
Simulation time 10700400 ps
CPU time 45.78 seconds
Started Oct 09 08:12:26 PM UTC 24
Finished Oct 09 08:13:14 PM UTC 24
Peak memory 285880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1759953475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_
ctrl_disable.1759953475
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.4220139954
Short name T707
Test name
Test status
Simulation time 380259711000 ps
CPU time 813.44 seconds
Started Oct 09 08:11:18 PM UTC 24
Finished Oct 09 08:25:01 PM UTC 24
Peak memory 275164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220139954
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res
et.4220139954
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3404758186
Short name T597
Test name
Test status
Simulation time 3544091100 ps
CPU time 49.72 seconds
Started Oct 09 08:11:17 PM UTC 24
Finished Oct 09 08:12:08 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404758186 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.3404758186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1595737568
Short name T625
Test name
Test status
Simulation time 12829301800 ps
CPU time 186.01 seconds
Started Oct 09 08:12:09 PM UTC 24
Finished Oct 09 08:15:18 PM UTC 24
Peak memory 303940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1595737568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_intr_rd_slow_flash.1595737568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2391512639
Short name T602
Test name
Test status
Simulation time 1576711300 ps
CPU time 82.35 seconds
Started Oct 09 08:11:31 PM UTC 24
Finished Oct 09 08:12:55 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391512639 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2391512639
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1337702563
Short name T609
Test name
Test status
Simulation time 79906600 ps
CPU time 24.39 seconds
Started Oct 09 08:12:57 PM UTC 24
Finished Oct 09 08:13:23 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337702563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_lcmgr_intg.1337702563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.2078046290
Short name T138
Test name
Test status
Simulation time 13770987000 ps
CPU time 414.32 seconds
Started Oct 09 08:11:21 PM UTC 24
Finished Oct 09 08:18:21 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2078046290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_mp_regions.2078046290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3763579450
Short name T160
Test name
Test status
Simulation time 143419900 ps
CPU time 209.18 seconds
Started Oct 09 08:11:19 PM UTC 24
Finished Oct 09 08:14:52 PM UTC 24
Peak memory 273312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763579450 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.3763579450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.1909976795
Short name T618
Test name
Test status
Simulation time 3074209800 ps
CPU time 180.18 seconds
Started Oct 09 08:11:15 PM UTC 24
Finished Oct 09 08:14:18 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909976795 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1909976795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.668910917
Short name T619
Test name
Test status
Simulation time 16023283100 ps
CPU time 131.51 seconds
Started Oct 09 08:12:12 PM UTC 24
Finished Oct 09 08:14:27 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668910917 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.668910917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.2762864441
Short name T1022
Test name
Test status
Simulation time 2903825900 ps
CPU time 1780.28 seconds
Started Oct 09 08:11:14 PM UTC 24
Finished Oct 09 08:41:14 PM UTC 24
Peak memory 297672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762864441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2762864441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.172372959
Short name T612
Test name
Test status
Simulation time 103315100 ps
CPU time 69.88 seconds
Started Oct 09 08:12:22 PM UTC 24
Finished Oct 09 08:13:34 PM UTC 24
Peak memory 283580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172372959 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.172372959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2920208028
Short name T614
Test name
Test status
Simulation time 657275700 ps
CPU time 118.14 seconds
Started Oct 09 08:11:35 PM UTC 24
Finished Oct 09 08:13:35 PM UTC 24
Peak memory 304204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2920208028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.2920208028
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.1260256186
Short name T663
Test name
Test status
Simulation time 9543602700 ps
CPU time 493.96 seconds
Started Oct 09 08:11:50 PM UTC 24
Finished Oct 09 08:20:11 PM UTC 24
Peak memory 324808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260256186 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.1260256186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1870979275
Short name T603
Test name
Test status
Simulation time 33380100 ps
CPU time 50.96 seconds
Started Oct 09 08:12:14 PM UTC 24
Finished Oct 09 08:13:07 PM UTC 24
Peak memory 287636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870979275 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1870979275
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1116056570
Short name T605
Test name
Test status
Simulation time 75705300 ps
CPU time 51.47 seconds
Started Oct 09 08:12:18 PM UTC 24
Finished Oct 09 08:13:11 PM UTC 24
Peak memory 285592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1116056570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw_evict_all_en.1116056570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.845427211
Short name T616
Test name
Test status
Simulation time 16285410500 ps
CPU time 99.11 seconds
Started Oct 09 08:12:26 PM UTC 24
Finished Oct 09 08:14:08 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845427211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.845427211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.301601235
Short name T634
Test name
Test status
Simulation time 93040000 ps
CPU time 304.35 seconds
Started Oct 09 08:11:13 PM UTC 24
Finished Oct 09 08:16:22 PM UTC 24
Peak memory 291532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301601235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.301601235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.3573517236
Short name T620
Test name
Test status
Simulation time 1813354200 ps
CPU time 177.99 seconds
Started Oct 09 08:11:34 PM UTC 24
Finished Oct 09 08:14:35 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3573517236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.3573517236
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1577578436
Short name T632
Test name
Test status
Simulation time 37694400 ps
CPU time 24.59 seconds
Started Oct 09 08:15:30 PM UTC 24
Finished Oct 09 08:15:56 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577578436 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.1577578436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1171533180
Short name T628
Test name
Test status
Simulation time 17197900 ps
CPU time 23.43 seconds
Started Oct 09 08:15:12 PM UTC 24
Finished Oct 09 08:15:36 PM UTC 24
Peak memory 284960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171533180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1171533180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2825423110
Short name T650
Test name
Test status
Simulation time 10012182200 ps
CPU time 158.28 seconds
Started Oct 09 08:15:28 PM UTC 24
Finished Oct 09 08:18:10 PM UTC 24
Peak memory 275412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2825423110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2825423110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.3162853846
Short name T631
Test name
Test status
Simulation time 181079200 ps
CPU time 25.7 seconds
Started Oct 09 08:15:19 PM UTC 24
Finished Oct 09 08:15:46 PM UTC 24
Peak memory 275524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3162853846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
12.flash_ctrl_hw_read_seed_err.3162853846
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.469762771
Short name T723
Test name
Test status
Simulation time 120165822600 ps
CPU time 763.98 seconds
Started Oct 09 08:13:26 PM UTC 24
Finished Oct 09 08:26:19 PM UTC 24
Peak memory 275304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469762771 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_reset.469762771
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2318224720
Short name T617
Test name
Test status
Simulation time 1970160900 ps
CPU time 43.49 seconds
Started Oct 09 08:13:24 PM UTC 24
Finished Oct 09 08:14:09 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318224720 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.2318224720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.2644550364
Short name T336
Test name
Test status
Simulation time 1528302500 ps
CPU time 140.25 seconds
Started Oct 09 08:14:10 PM UTC 24
Finished Oct 09 08:16:33 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644550364 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.2644550364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.202189280
Short name T333
Test name
Test status
Simulation time 66806864300 ps
CPU time 335.66 seconds
Started Oct 09 08:14:19 PM UTC 24
Finished Oct 09 08:20:00 PM UTC 24
Peak memory 301864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=202189280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_intr_rd_slow_flash.202189280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2977226243
Short name T624
Test name
Test status
Simulation time 15216985200 ps
CPU time 96.33 seconds
Started Oct 09 08:13:35 PM UTC 24
Finished Oct 09 08:15:14 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977226243 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2977226243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.2058303248
Short name T629
Test name
Test status
Simulation time 55695700 ps
CPU time 25.33 seconds
Started Oct 09 08:15:15 PM UTC 24
Finished Oct 09 08:15:42 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2058303248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_lcmgr_intg.2058303248
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.4023166878
Short name T150
Test name
Test status
Simulation time 20039653900 ps
CPU time 369.2 seconds
Started Oct 09 08:13:35 PM UTC 24
Finished Oct 09 08:19:49 PM UTC 24
Peak memory 283324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4023166878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_mp_regions.4023166878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.592421334
Short name T176
Test name
Test status
Simulation time 180351900 ps
CPU time 194.03 seconds
Started Oct 09 08:13:31 PM UTC 24
Finished Oct 09 08:16:48 PM UTC 24
Peak memory 271132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592421334 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.592421334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.481848008
Short name T622
Test name
Test status
Simulation time 46896900 ps
CPU time 103.32 seconds
Started Oct 09 08:13:22 PM UTC 24
Finished Oct 09 08:15:07 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481848008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.481848008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.3323613529
Short name T643
Test name
Test status
Simulation time 2021934900 ps
CPU time 187.12 seconds
Started Oct 09 08:14:21 PM UTC 24
Finished Oct 09 08:17:32 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323613529 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.3323613529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.2836459249
Short name T777
Test name
Test status
Simulation time 128116800 ps
CPU time 984.56 seconds
Started Oct 09 08:13:15 PM UTC 24
Finished Oct 09 08:29:51 PM UTC 24
Peak memory 293576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836459249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2836459249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.3903418357
Short name T627
Test name
Test status
Simulation time 205467800 ps
CPU time 56.41 seconds
Started Oct 09 08:14:37 PM UTC 24
Finished Oct 09 08:15:35 PM UTC 24
Peak memory 289724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903418357 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.3903418357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.980934896
Short name T626
Test name
Test status
Simulation time 462740200 ps
CPU time 110.7 seconds
Started Oct 09 08:13:41 PM UTC 24
Finished Oct 09 08:15:34 PM UTC 24
Peak memory 308212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=980934896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.980934896
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.2717809927
Short name T684
Test name
Test status
Simulation time 8638948300 ps
CPU time 490.18 seconds
Started Oct 09 08:14:09 PM UTC 24
Finished Oct 09 08:22:25 PM UTC 24
Peak memory 322576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717809927 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.2717809927
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.3998922544
Short name T623
Test name
Test status
Simulation time 28073200 ps
CPU time 41.4 seconds
Started Oct 09 08:14:28 PM UTC 24
Finished Oct 09 08:15:11 PM UTC 24
Peak memory 287700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998922544 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.3998922544
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.1071007876
Short name T638
Test name
Test status
Simulation time 6416878400 ps
CPU time 107.23 seconds
Started Oct 09 08:15:08 PM UTC 24
Finished Oct 09 08:16:57 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071007876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1071007876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1941687191
Short name T630
Test name
Test status
Simulation time 66779800 ps
CPU time 148.25 seconds
Started Oct 09 08:13:12 PM UTC 24
Finished Oct 09 08:15:43 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941687191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1941687191
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.2942176769
Short name T306
Test name
Test status
Simulation time 3293324000 ps
CPU time 150.65 seconds
Started Oct 09 08:13:36 PM UTC 24
Finished Oct 09 08:16:10 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2942176769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.2942176769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.726533037
Short name T647
Test name
Test status
Simulation time 35018600 ps
CPU time 29.66 seconds
Started Oct 09 08:17:25 PM UTC 24
Finished Oct 09 08:17:57 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726533037 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.726533037
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.493503862
Short name T641
Test name
Test status
Simulation time 63859400 ps
CPU time 21.81 seconds
Started Oct 09 08:17:00 PM UTC 24
Finished Oct 09 08:17:23 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493503862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.493503862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1509426891
Short name T358
Test name
Test status
Simulation time 10865800 ps
CPU time 34.44 seconds
Started Oct 09 08:16:52 PM UTC 24
Finished Oct 09 08:17:27 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1509426891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_
ctrl_disable.1509426891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.61161263
Short name T106
Test name
Test status
Simulation time 10013480100 ps
CPU time 346.56 seconds
Started Oct 09 08:17:24 PM UTC 24
Finished Oct 09 08:23:16 PM UTC 24
Peak memory 332552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=61161263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.61161263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.2304384920
Short name T646
Test name
Test status
Simulation time 15467200 ps
CPU time 25.56 seconds
Started Oct 09 08:17:21 PM UTC 24
Finished Oct 09 08:17:48 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2304384920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_hw_read_seed_err.2304384920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.3281874995
Short name T782
Test name
Test status
Simulation time 200179795000 ps
CPU time 852.66 seconds
Started Oct 09 08:15:43 PM UTC 24
Finished Oct 09 08:30:06 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281874995
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res
et.3281874995
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.1248008357
Short name T640
Test name
Test status
Simulation time 1987293600 ps
CPU time 84.4 seconds
Started Oct 09 08:15:42 PM UTC 24
Finished Oct 09 08:17:08 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248008357 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.1248008357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2940937857
Short name T651
Test name
Test status
Simulation time 6580410300 ps
CPU time 170.27 seconds
Started Oct 09 08:16:22 PM UTC 24
Finished Oct 09 08:19:15 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2940937857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_intr_rd_slow_flash.2940937857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3800015806
Short name T642
Test name
Test status
Simulation time 1528697100 ps
CPU time 94.86 seconds
Started Oct 09 08:15:47 PM UTC 24
Finished Oct 09 08:17:25 PM UTC 24
Peak memory 271104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800015806 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3800015806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.3083636528
Short name T644
Test name
Test status
Simulation time 47454000 ps
CPU time 27.03 seconds
Started Oct 09 08:17:09 PM UTC 24
Finished Oct 09 08:17:37 PM UTC 24
Peak memory 275228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3083636528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_lcmgr_intg.3083636528
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3960626493
Short name T700
Test name
Test status
Simulation time 68247321300 ps
CPU time 504.59 seconds
Started Oct 09 08:15:44 PM UTC 24
Finished Oct 09 08:24:16 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3960626493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_mp_regions.3960626493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.650335385
Short name T158
Test name
Test status
Simulation time 35593500 ps
CPU time 184.07 seconds
Started Oct 09 08:15:43 PM UTC 24
Finished Oct 09 08:18:50 PM UTC 24
Peak memory 270940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650335385 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.650335385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.309552894
Short name T726
Test name
Test status
Simulation time 735866000 ps
CPU time 646.93 seconds
Started Oct 09 08:15:38 PM UTC 24
Finished Oct 09 08:26:33 PM UTC 24
Peak memory 275268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309552894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.309552894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1285441383
Short name T637
Test name
Test status
Simulation time 115568000 ps
CPU time 15.22 seconds
Started Oct 09 08:16:34 PM UTC 24
Finished Oct 09 08:16:51 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285441383 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.1285441383
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.847168514
Short name T735
Test name
Test status
Simulation time 207601400 ps
CPU time 679.13 seconds
Started Oct 09 08:15:37 PM UTC 24
Finished Oct 09 08:27:05 PM UTC 24
Peak memory 291720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847168514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.847168514
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3125443196
Short name T645
Test name
Test status
Simulation time 139638400 ps
CPU time 53.4 seconds
Started Oct 09 08:16:50 PM UTC 24
Finished Oct 09 08:17:44 PM UTC 24
Peak memory 287900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125443196 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.3125443196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1647076163
Short name T648
Test name
Test status
Simulation time 3199707600 ps
CPU time 108.81 seconds
Started Oct 09 08:16:08 PM UTC 24
Finished Oct 09 08:17:59 PM UTC 24
Peak memory 292044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1647076163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1647076163
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.3584842424
Short name T730
Test name
Test status
Simulation time 4010020200 ps
CPU time 627.28 seconds
Started Oct 09 08:16:11 PM UTC 24
Finished Oct 09 08:26:46 PM UTC 24
Peak memory 320608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584842424 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.3584842424
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2610065305
Short name T423
Test name
Test status
Simulation time 66541500 ps
CPU time 34.52 seconds
Started Oct 09 08:16:44 PM UTC 24
Finished Oct 09 08:17:20 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2610065305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw_evict_all_en.2610065305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2848381775
Short name T649
Test name
Test status
Simulation time 1641769500 ps
CPU time 63.46 seconds
Started Oct 09 08:16:58 PM UTC 24
Finished Oct 09 08:18:03 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848381775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2848381775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3182759413
Short name T635
Test name
Test status
Simulation time 30124500 ps
CPU time 64.47 seconds
Started Oct 09 08:15:36 PM UTC 24
Finished Oct 09 08:16:42 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182759413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3182759413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.651366391
Short name T658
Test name
Test status
Simulation time 2312435700 ps
CPU time 235.06 seconds
Started Oct 09 08:15:57 PM UTC 24
Finished Oct 09 08:19:57 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=651366391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.651366391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.4136011259
Short name T665
Test name
Test status
Simulation time 327335300 ps
CPU time 27.46 seconds
Started Oct 09 08:19:54 PM UTC 24
Finished Oct 09 08:20:23 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136011259 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.4136011259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.1062917137
Short name T660
Test name
Test status
Simulation time 91543400 ps
CPU time 19.15 seconds
Started Oct 09 08:19:42 PM UTC 24
Finished Oct 09 08:20:03 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062917137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1062917137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.4022999752
Short name T661
Test name
Test status
Simulation time 10492100 ps
CPU time 30.26 seconds
Started Oct 09 08:19:34 PM UTC 24
Finished Oct 09 08:20:06 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4022999752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_
ctrl_disable.4022999752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2152509732
Short name T107
Test name
Test status
Simulation time 10014879600 ps
CPU time 223.8 seconds
Started Oct 09 08:19:52 PM UTC 24
Finished Oct 09 08:23:40 PM UTC 24
Peak memory 279300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2152509732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2152509732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.4016254698
Short name T664
Test name
Test status
Simulation time 46309200 ps
CPU time 23.27 seconds
Started Oct 09 08:19:51 PM UTC 24
Finished Oct 09 08:20:16 PM UTC 24
Peak memory 269276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4016254698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
14.flash_ctrl_hw_read_seed_err.4016254698
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3079758006
Short name T828
Test name
Test status
Simulation time 40123454600 ps
CPU time 898.9 seconds
Started Oct 09 08:17:47 PM UTC 24
Finished Oct 09 08:32:57 PM UTC 24
Peak memory 275220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079758006
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res
et.3079758006
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.1729544730
Short name T653
Test name
Test status
Simulation time 3604482800 ps
CPU time 120.45 seconds
Started Oct 09 08:17:38 PM UTC 24
Finished Oct 09 08:19:41 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729544730 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.1729544730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2586254981
Short name T670
Test name
Test status
Simulation time 11727826100 ps
CPU time 180.05 seconds
Started Oct 09 08:18:23 PM UTC 24
Finished Oct 09 08:21:26 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2586254981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_intr_rd_slow_flash.2586254981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.2815988971
Short name T655
Test name
Test status
Simulation time 3578748500 ps
CPU time 116.22 seconds
Started Oct 09 08:17:49 PM UTC 24
Finished Oct 09 08:19:48 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815988971 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2815988971
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1355959992
Short name T662
Test name
Test status
Simulation time 16332300 ps
CPU time 15.99 seconds
Started Oct 09 08:19:50 PM UTC 24
Finished Oct 09 08:20:07 PM UTC 24
Peak memory 273224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1355959992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_lcmgr_intg.1355959992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.4101271231
Short name T141
Test name
Test status
Simulation time 33236573100 ps
CPU time 438.22 seconds
Started Oct 09 08:17:48 PM UTC 24
Finished Oct 09 08:25:13 PM UTC 24
Peak memory 283324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4101271231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_mp_regions.4101271231
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3871431837
Short name T171
Test name
Test status
Simulation time 149182600 ps
CPU time 232.75 seconds
Started Oct 09 08:17:48 PM UTC 24
Finished Oct 09 08:21:45 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871431837 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.3871431837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.3331923193
Short name T696
Test name
Test status
Simulation time 59248800 ps
CPU time 390.33 seconds
Started Oct 09 08:17:33 PM UTC 24
Finished Oct 09 08:24:09 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331923193 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3331923193
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2584535688
Short name T688
Test name
Test status
Simulation time 2994119400 ps
CPU time 237.67 seconds
Started Oct 09 08:18:50 PM UTC 24
Finished Oct 09 08:22:51 PM UTC 24
Peak memory 271364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584535688 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.2584535688
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.226174959
Short name T717
Test name
Test status
Simulation time 154537700 ps
CPU time 505.72 seconds
Started Oct 09 08:17:29 PM UTC 24
Finished Oct 09 08:26:01 PM UTC 24
Peak memory 291528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226174959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.226174959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.1516675659
Short name T666
Test name
Test status
Simulation time 155637400 ps
CPU time 49.2 seconds
Started Oct 09 08:19:33 PM UTC 24
Finished Oct 09 08:20:24 PM UTC 24
Peak memory 287700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516675659 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.1516675659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.510663035
Short name T659
Test name
Test status
Simulation time 5826416000 ps
CPU time 120.56 seconds
Started Oct 09 08:18:00 PM UTC 24
Finished Oct 09 08:20:03 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=510663035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.510663035
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.4063097112
Short name T748
Test name
Test status
Simulation time 7158263600 ps
CPU time 586.83 seconds
Started Oct 09 08:18:04 PM UTC 24
Finished Oct 09 08:27:58 PM UTC 24
Peak memory 324600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063097112 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.4063097112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.690971809
Short name T654
Test name
Test status
Simulation time 39711900 ps
CPU time 48.29 seconds
Started Oct 09 08:18:51 PM UTC 24
Finished Oct 09 08:19:41 PM UTC 24
Peak memory 281792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690971809 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.690971809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1479169357
Short name T656
Test name
Test status
Simulation time 29543100 ps
CPU time 34.58 seconds
Started Oct 09 08:19:16 PM UTC 24
Finished Oct 09 08:19:53 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1479169357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw_evict_all_en.1479169357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.1831867557
Short name T667
Test name
Test status
Simulation time 23784100 ps
CPU time 192.28 seconds
Started Oct 09 08:17:28 PM UTC 24
Finished Oct 09 08:20:43 PM UTC 24
Peak memory 289476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831867557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1831867557
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3300231104
Short name T674
Test name
Test status
Simulation time 2632247100 ps
CPU time 224.36 seconds
Started Oct 09 08:17:58 PM UTC 24
Finished Oct 09 08:21:46 PM UTC 24
Peak memory 271352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3300231104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.3300231104
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3113241108
Short name T680
Test name
Test status
Simulation time 38107400 ps
CPU time 17.91 seconds
Started Oct 09 08:21:57 PM UTC 24
Finished Oct 09 08:22:16 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113241108 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.3113241108
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.4275562968
Short name T676
Test name
Test status
Simulation time 16716000 ps
CPU time 23.92 seconds
Started Oct 09 08:21:35 PM UTC 24
Finished Oct 09 08:22:01 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275562968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.4275562968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.1052332435
Short name T389
Test name
Test status
Simulation time 12737800 ps
CPU time 33.22 seconds
Started Oct 09 08:21:27 PM UTC 24
Finished Oct 09 08:22:02 PM UTC 24
Peak memory 285648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1052332435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_
ctrl_disable.1052332435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2523065237
Short name T698
Test name
Test status
Simulation time 10012147900 ps
CPU time 142.15 seconds
Started Oct 09 08:21:47 PM UTC 24
Finished Oct 09 08:24:11 PM UTC 24
Peak memory 314540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2523065237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2523065237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.2730225485
Short name T679
Test name
Test status
Simulation time 106220200 ps
CPU time 18.81 seconds
Started Oct 09 08:21:46 PM UTC 24
Finished Oct 09 08:22:06 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2730225485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_hw_read_seed_err.2730225485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1956460837
Short name T848
Test name
Test status
Simulation time 40124323600 ps
CPU time 818.58 seconds
Started Oct 09 08:20:04 PM UTC 24
Finished Oct 09 08:33:53 PM UTC 24
Peak memory 275032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956460837
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res
et.1956460837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3260040315
Short name T669
Test name
Test status
Simulation time 682525200 ps
CPU time 65.29 seconds
Started Oct 09 08:20:04 PM UTC 24
Finished Oct 09 08:21:11 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260040315 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.3260040315
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.1807118317
Short name T706
Test name
Test status
Simulation time 1826348200 ps
CPU time 264.79 seconds
Started Oct 09 08:20:26 PM UTC 24
Finished Oct 09 08:24:55 PM UTC 24
Peak memory 302032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807118317 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.1807118317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3313006029
Short name T702
Test name
Test status
Simulation time 20945710400 ps
CPU time 228.76 seconds
Started Oct 09 08:20:36 PM UTC 24
Finished Oct 09 08:24:28 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3313006029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_intr_rd_slow_flash.3313006029
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.545246929
Short name T671
Test name
Test status
Simulation time 1481470000 ps
CPU time 76.07 seconds
Started Oct 09 08:20:12 PM UTC 24
Finished Oct 09 08:21:29 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545246929 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.545246929
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1082671197
Short name T686
Test name
Test status
Simulation time 5225611800 ps
CPU time 147.04 seconds
Started Oct 09 08:20:08 PM UTC 24
Finished Oct 09 08:22:38 PM UTC 24
Peak memory 275064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1082671197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_mp_regions.1082671197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.3528335510
Short name T169
Test name
Test status
Simulation time 240802200 ps
CPU time 228.67 seconds
Started Oct 09 08:20:07 PM UTC 24
Finished Oct 09 08:24:00 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528335510 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.3528335510
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.1712040747
Short name T769
Test name
Test status
Simulation time 1421783400 ps
CPU time 557.04 seconds
Started Oct 09 08:20:01 PM UTC 24
Finished Oct 09 08:29:25 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712040747 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1712040747
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1200189409
Short name T668
Test name
Test status
Simulation time 56262900 ps
CPU time 24.93 seconds
Started Oct 09 08:20:44 PM UTC 24
Finished Oct 09 08:21:10 PM UTC 24
Peak memory 271364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200189409 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.1200189409
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.3236139775
Short name T791
Test name
Test status
Simulation time 20227118300 ps
CPU time 633.69 seconds
Started Oct 09 08:19:58 PM UTC 24
Finished Oct 09 08:30:39 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236139775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3236139775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1309049898
Short name T675
Test name
Test status
Simulation time 70248000 ps
CPU time 46.12 seconds
Started Oct 09 08:21:12 PM UTC 24
Finished Oct 09 08:22:00 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309049898 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.1309049898
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.3838002873
Short name T685
Test name
Test status
Simulation time 6410332500 ps
CPU time 133.47 seconds
Started Oct 09 08:20:20 PM UTC 24
Finished Oct 09 08:22:36 PM UTC 24
Peak memory 302072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3838002873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.3838002873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.2777266719
Short name T789
Test name
Test status
Simulation time 11702894200 ps
CPU time 603.28 seconds
Started Oct 09 08:20:23 PM UTC 24
Finished Oct 09 08:30:35 PM UTC 24
Peak memory 322572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777266719 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.2777266719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.1327963917
Short name T673
Test name
Test status
Simulation time 126655000 ps
CPU time 36.77 seconds
Started Oct 09 08:20:57 PM UTC 24
Finished Oct 09 08:21:35 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327963917 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.1327963917
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.2923467289
Short name T678
Test name
Test status
Simulation time 191137700 ps
CPU time 48.49 seconds
Started Oct 09 08:21:11 PM UTC 24
Finished Oct 09 08:22:01 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2923467289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw_evict_all_en.2923467289
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.3190123288
Short name T687
Test name
Test status
Simulation time 5206616300 ps
CPU time 74.66 seconds
Started Oct 09 08:21:30 PM UTC 24
Finished Oct 09 08:22:47 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190123288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3190123288
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.4220843658
Short name T692
Test name
Test status
Simulation time 24852800 ps
CPU time 222.26 seconds
Started Oct 09 08:19:55 PM UTC 24
Finished Oct 09 08:23:41 PM UTC 24
Peak memory 291532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220843658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.4220843658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.345076009
Short name T681
Test name
Test status
Simulation time 2731560100 ps
CPU time 120.21 seconds
Started Oct 09 08:20:17 PM UTC 24
Finished Oct 09 08:22:19 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=345076009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.345076009
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.123087666
Short name T699
Test name
Test status
Simulation time 178699800 ps
CPU time 24.33 seconds
Started Oct 09 08:23:49 PM UTC 24
Finished Oct 09 08:24:15 PM UTC 24
Peak memory 269048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123087666 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.123087666
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.2300953109
Short name T694
Test name
Test status
Simulation time 13467700 ps
CPU time 18.49 seconds
Started Oct 09 08:23:39 PM UTC 24
Finished Oct 09 08:23:58 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300953109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2300953109
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.3511475713
Short name T116
Test name
Test status
Simulation time 20891100 ps
CPU time 29.52 seconds
Started Oct 09 08:23:17 PM UTC 24
Finished Oct 09 08:23:48 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3511475713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_
ctrl_disable.3511475713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1698906726
Short name T725
Test name
Test status
Simulation time 10012184700 ps
CPU time 152.36 seconds
Started Oct 09 08:23:49 PM UTC 24
Finished Oct 09 08:26:24 PM UTC 24
Peak memory 277476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1698906726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1698906726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3976652049
Short name T695
Test name
Test status
Simulation time 15509400 ps
CPU time 23.62 seconds
Started Oct 09 08:23:42 PM UTC 24
Finished Oct 09 08:24:07 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3976652049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.flash_ctrl_hw_read_seed_err.3976652049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2541655732
Short name T1010
Test name
Test status
Simulation time 160168798800 ps
CPU time 1111.07 seconds
Started Oct 09 08:22:03 PM UTC 24
Finished Oct 09 08:40:49 PM UTC 24
Peak memory 275020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541655732
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res
et.2541655732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.248346172
Short name T701
Test name
Test status
Simulation time 6314696300 ps
CPU time 139.53 seconds
Started Oct 09 08:22:03 PM UTC 24
Finished Oct 09 08:24:25 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248346172 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.248346172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.2301829987
Short name T704
Test name
Test status
Simulation time 579570300 ps
CPU time 123.93 seconds
Started Oct 09 08:22:37 PM UTC 24
Finished Oct 09 08:24:43 PM UTC 24
Peak memory 293804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301829987 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.2301829987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3640937673
Short name T753
Test name
Test status
Simulation time 63379484200 ps
CPU time 324.81 seconds
Started Oct 09 08:22:40 PM UTC 24
Finished Oct 09 08:28:09 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3640937673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_intr_rd_slow_flash.3640937673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.176213663
Short name T691
Test name
Test status
Simulation time 854392400 ps
CPU time 75.69 seconds
Started Oct 09 08:22:20 PM UTC 24
Finished Oct 09 08:23:38 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176213663 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.176213663
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.883820281
Short name T697
Test name
Test status
Simulation time 15696300 ps
CPU time 28.41 seconds
Started Oct 09 08:23:41 PM UTC 24
Finished Oct 09 08:24:11 PM UTC 24
Peak memory 271120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=883820281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_lcmgr_intg.883820281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.4120035933
Short name T729
Test name
Test status
Simulation time 22802906400 ps
CPU time 264.2 seconds
Started Oct 09 08:22:17 PM UTC 24
Finished Oct 09 08:26:45 PM UTC 24
Peak memory 283324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4120035933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_mp_regions.4120035933
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.3372648399
Short name T709
Test name
Test status
Simulation time 41313600 ps
CPU time 178.44 seconds
Started Oct 09 08:22:07 PM UTC 24
Finished Oct 09 08:25:09 PM UTC 24
Peak memory 275232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372648399 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.3372648399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.1956923431
Short name T778
Test name
Test status
Simulation time 95110500 ps
CPU time 464.32 seconds
Started Oct 09 08:22:02 PM UTC 24
Finished Oct 09 08:29:52 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956923431 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1956923431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.1334159232
Short name T732
Test name
Test status
Simulation time 2477212800 ps
CPU time 237.9 seconds
Started Oct 09 08:22:48 PM UTC 24
Finished Oct 09 08:26:50 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334159232 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.1334159232
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.2388069750
Short name T888
Test name
Test status
Simulation time 500372400 ps
CPU time 804.8 seconds
Started Oct 09 08:22:02 PM UTC 24
Finished Oct 09 08:35:36 PM UTC 24
Peak memory 291720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388069750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2388069750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.1699209825
Short name T201
Test name
Test status
Simulation time 428873600 ps
CPU time 52.25 seconds
Started Oct 09 08:23:07 PM UTC 24
Finished Oct 09 08:24:01 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699209825 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.1699209825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.2879011464
Short name T705
Test name
Test status
Simulation time 1067061200 ps
CPU time 135.7 seconds
Started Oct 09 08:22:25 PM UTC 24
Finished Oct 09 08:24:43 PM UTC 24
Peak memory 301964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2879011464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.2879011464
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.3429449512
Short name T786
Test name
Test status
Simulation time 12759861600 ps
CPU time 475.07 seconds
Started Oct 09 08:22:26 PM UTC 24
Finished Oct 09 08:30:27 PM UTC 24
Peak memory 324624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429449512 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.3429449512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.2542962444
Short name T690
Test name
Test status
Simulation time 70049000 ps
CPU time 39.16 seconds
Started Oct 09 08:22:50 PM UTC 24
Finished Oct 09 08:23:30 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542962444 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.2542962444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.1598605999
Short name T693
Test name
Test status
Simulation time 93813600 ps
CPU time 53.85 seconds
Started Oct 09 08:22:53 PM UTC 24
Finished Oct 09 08:23:48 PM UTC 24
Peak memory 287964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1598605999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw_evict_all_en.1598605999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3387076661
Short name T361
Test name
Test status
Simulation time 8849970500 ps
CPU time 98.67 seconds
Started Oct 09 08:23:31 PM UTC 24
Finished Oct 09 08:25:12 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387076661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3387076661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.2607805696
Short name T689
Test name
Test status
Simulation time 23765100 ps
CPU time 62.25 seconds
Started Oct 09 08:22:02 PM UTC 24
Finished Oct 09 08:23:05 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607805696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2607805696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1171302872
Short name T714
Test name
Test status
Simulation time 3905310400 ps
CPU time 195.54 seconds
Started Oct 09 08:22:22 PM UTC 24
Finished Oct 09 08:25:40 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1171302872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.1171302872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2330827451
Short name T718
Test name
Test status
Simulation time 52329200 ps
CPU time 25.26 seconds
Started Oct 09 08:25:36 PM UTC 24
Finished Oct 09 08:26:02 PM UTC 24
Peak memory 269056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330827451 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.2330827451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.206751486
Short name T715
Test name
Test status
Simulation time 62255500 ps
CPU time 32 seconds
Started Oct 09 08:25:13 PM UTC 24
Finished Oct 09 08:25:46 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206751486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.206751486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.3002035125
Short name T712
Test name
Test status
Simulation time 12474000 ps
CPU time 24.62 seconds
Started Oct 09 08:25:08 PM UTC 24
Finished Oct 09 08:25:34 PM UTC 24
Peak memory 285752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3002035125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_
ctrl_disable.3002035125
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2562413773
Short name T727
Test name
Test status
Simulation time 10026939200 ps
CPU time 62.49 seconds
Started Oct 09 08:25:34 PM UTC 24
Finished Oct 09 08:26:39 PM UTC 24
Peak memory 281748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2562413773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2562413773
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2858721303
Short name T719
Test name
Test status
Simulation time 23023600 ps
CPU time 29.75 seconds
Started Oct 09 08:25:32 PM UTC 24
Finished Oct 09 08:26:04 PM UTC 24
Peak memory 275240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2858721303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_hw_read_seed_err.2858721303
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.1873313183
Short name T986
Test name
Test status
Simulation time 160172351000 ps
CPU time 944.61 seconds
Started Oct 09 08:24:08 PM UTC 24
Finished Oct 09 08:40:04 PM UTC 24
Peak memory 275032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873313183
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res
et.1873313183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1741688516
Short name T724
Test name
Test status
Simulation time 4360452100 ps
CPU time 135.85 seconds
Started Oct 09 08:24:04 PM UTC 24
Finished Oct 09 08:26:22 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741688516 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.1741688516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.749330787
Short name T749
Test name
Test status
Simulation time 1830087100 ps
CPU time 207.32 seconds
Started Oct 09 08:24:29 PM UTC 24
Finished Oct 09 08:28:01 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749330787 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.749330787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2036963253
Short name T737
Test name
Test status
Simulation time 12025700000 ps
CPU time 151.54 seconds
Started Oct 09 08:24:40 PM UTC 24
Finished Oct 09 08:27:14 PM UTC 24
Peak memory 304104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2036963253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_intr_rd_slow_flash.2036963253
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.1602182343
Short name T716
Test name
Test status
Simulation time 2549721100 ps
CPU time 93.29 seconds
Started Oct 09 08:24:12 PM UTC 24
Finished Oct 09 08:25:48 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602182343 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1602182343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.1438225101
Short name T713
Test name
Test status
Simulation time 45919800 ps
CPU time 24.42 seconds
Started Oct 09 08:25:14 PM UTC 24
Finished Oct 09 08:25:40 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1438225101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_lcmgr_intg.1438225101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3191800685
Short name T1091
Test name
Test status
Simulation time 58694781700 ps
CPU time 1148.05 seconds
Started Oct 09 08:24:11 PM UTC 24
Finished Oct 09 08:43:33 PM UTC 24
Peak memory 283516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3191800685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_mp_regions.3191800685
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1569115997
Short name T736
Test name
Test status
Simulation time 72662100 ps
CPU time 180.31 seconds
Started Oct 09 08:24:10 PM UTC 24
Finished Oct 09 08:27:13 PM UTC 24
Peak memory 271456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569115997 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.1569115997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.489770671
Short name T750
Test name
Test status
Simulation time 44909500 ps
CPU time 236.48 seconds
Started Oct 09 08:24:02 PM UTC 24
Finished Oct 09 08:28:02 PM UTC 24
Peak memory 275460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489770671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.489770671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.754962497
Short name T708
Test name
Test status
Simulation time 20551800 ps
CPU time 22.47 seconds
Started Oct 09 08:24:44 PM UTC 24
Finished Oct 09 08:25:08 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754962497 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.754962497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2080749663
Short name T1136
Test name
Test status
Simulation time 267331500 ps
CPU time 1407.79 seconds
Started Oct 09 08:24:01 PM UTC 24
Finished Oct 09 08:47:44 PM UTC 24
Peak memory 298668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080749663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2080749663
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.256965739
Short name T720
Test name
Test status
Simulation time 65067800 ps
CPU time 61.41 seconds
Started Oct 09 08:25:02 PM UTC 24
Finished Oct 09 08:26:05 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256965739 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.256965739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3899543980
Short name T731
Test name
Test status
Simulation time 1115557500 ps
CPU time 149.71 seconds
Started Oct 09 08:24:17 PM UTC 24
Finished Oct 09 08:26:50 PM UTC 24
Peak memory 291908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3899543980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.3899543980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.1451486787
Short name T843
Test name
Test status
Simulation time 19557594400 ps
CPU time 544.09 seconds
Started Oct 09 08:24:26 PM UTC 24
Finished Oct 09 08:33:38 PM UTC 24
Peak memory 337100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451486787 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.1451486787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.506556353
Short name T710
Test name
Test status
Simulation time 76634700 ps
CPU time 45.4 seconds
Started Oct 09 08:24:44 PM UTC 24
Finished Oct 09 08:25:31 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506556353 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.506556353
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.2699635278
Short name T711
Test name
Test status
Simulation time 205051500 ps
CPU time 37.28 seconds
Started Oct 09 08:24:55 PM UTC 24
Finished Oct 09 08:25:34 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2699635278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw_evict_all_en.2699635278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.146968183
Short name T728
Test name
Test status
Simulation time 3810004100 ps
CPU time 89.78 seconds
Started Oct 09 08:25:09 PM UTC 24
Finished Oct 09 08:26:41 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146968183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.146968183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.765244490
Short name T721
Test name
Test status
Simulation time 76484800 ps
CPU time 128.03 seconds
Started Oct 09 08:23:59 PM UTC 24
Finished Oct 09 08:26:10 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765244490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.765244490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.3714409153
Short name T733
Test name
Test status
Simulation time 3818544200 ps
CPU time 152.9 seconds
Started Oct 09 08:24:16 PM UTC 24
Finished Oct 09 08:26:51 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3714409153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.3714409153
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.323443844
Short name T746
Test name
Test status
Simulation time 38156400 ps
CPU time 17.61 seconds
Started Oct 09 08:27:15 PM UTC 24
Finished Oct 09 08:27:34 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323443844 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.323443844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.2367246113
Short name T738
Test name
Test status
Simulation time 39998200 ps
CPU time 22.25 seconds
Started Oct 09 08:26:51 PM UTC 24
Finished Oct 09 08:27:15 PM UTC 24
Peak memory 284736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367246113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2367246113
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.839971963
Short name T740
Test name
Test status
Simulation time 66054300 ps
CPU time 26.59 seconds
Started Oct 09 08:26:48 PM UTC 24
Finished Oct 09 08:27:16 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=839971963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_disable.839971963
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.55125559
Short name T742
Test name
Test status
Simulation time 24461000 ps
CPU time 20.89 seconds
Started Oct 09 08:27:00 PM UTC 24
Finished Oct 09 08:27:22 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=55125559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18
.flash_ctrl_hw_read_seed_err.55125559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.3146154723
Short name T1016
Test name
Test status
Simulation time 420295205900 ps
CPU time 892.78 seconds
Started Oct 09 08:26:01 PM UTC 24
Finished Oct 09 08:41:05 PM UTC 24
Peak memory 275356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146154723
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res
et.3146154723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3256372787
Short name T747
Test name
Test status
Simulation time 24824959100 ps
CPU time 125.25 seconds
Started Oct 09 08:25:49 PM UTC 24
Finished Oct 09 08:27:57 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256372787 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.3256372787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.3398576343
Short name T784
Test name
Test status
Simulation time 5637681800 ps
CPU time 236.84 seconds
Started Oct 09 08:26:23 PM UTC 24
Finished Oct 09 08:30:24 PM UTC 24
Peak memory 302188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398576343 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.3398576343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.487735682
Short name T744
Test name
Test status
Simulation time 2591961400 ps
CPU time 77.55 seconds
Started Oct 09 08:26:06 PM UTC 24
Finished Oct 09 08:27:26 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487735682 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.487735682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2892240669
Short name T739
Test name
Test status
Simulation time 26305600 ps
CPU time 21.21 seconds
Started Oct 09 08:26:52 PM UTC 24
Finished Oct 09 08:27:15 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2892240669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_lcmgr_intg.2892240669
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.333973560
Short name T767
Test name
Test status
Simulation time 24796586300 ps
CPU time 188.91 seconds
Started Oct 09 08:26:05 PM UTC 24
Finished Oct 09 08:29:17 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=333973560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_mp_regions.333973560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.4058894677
Short name T170
Test name
Test status
Simulation time 487415600 ps
CPU time 223.17 seconds
Started Oct 09 08:26:02 PM UTC 24
Finished Oct 09 08:29:49 PM UTC 24
Peak memory 275444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058894677 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.4058894677
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1990339415
Short name T890
Test name
Test status
Simulation time 1001115800 ps
CPU time 587.38 seconds
Started Oct 09 08:25:47 PM UTC 24
Finished Oct 09 08:35:42 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990339415 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1990339415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.1205102067
Short name T734
Test name
Test status
Simulation time 59800000 ps
CPU time 23.99 seconds
Started Oct 09 08:26:34 PM UTC 24
Finished Oct 09 08:26:59 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205102067 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.1205102067
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.2425619295
Short name T1140
Test name
Test status
Simulation time 1089359400 ps
CPU time 1671.62 seconds
Started Oct 09 08:25:41 PM UTC 24
Finished Oct 09 08:53:51 PM UTC 24
Peak memory 298412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425619295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.2425619295
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.2404650576
Short name T745
Test name
Test status
Simulation time 267380600 ps
CPU time 39.48 seconds
Started Oct 09 08:26:47 PM UTC 24
Finished Oct 09 08:27:28 PM UTC 24
Peak memory 283572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404650576 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.2404650576
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.1966358413
Short name T751
Test name
Test status
Simulation time 819763500 ps
CPU time 101.46 seconds
Started Oct 09 08:26:18 PM UTC 24
Finished Oct 09 08:28:02 PM UTC 24
Peak memory 291724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1966358413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.1966358413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3567484908
Short name T846
Test name
Test status
Simulation time 29906511000 ps
CPU time 441.23 seconds
Started Oct 09 08:26:20 PM UTC 24
Finished Oct 09 08:33:47 PM UTC 24
Peak memory 332800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567484908 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3567484908
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.281290518
Short name T743
Test name
Test status
Simulation time 69127300 ps
CPU time 41.42 seconds
Started Oct 09 08:26:40 PM UTC 24
Finished Oct 09 08:27:23 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281290518 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.281290518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.1351795025
Short name T741
Test name
Test status
Simulation time 69410600 ps
CPU time 34.7 seconds
Started Oct 09 08:26:42 PM UTC 24
Finished Oct 09 08:27:18 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1351795025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw_evict_all_en.1351795025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.1933428036
Short name T752
Test name
Test status
Simulation time 587380700 ps
CPU time 72.14 seconds
Started Oct 09 08:26:51 PM UTC 24
Finished Oct 09 08:28:05 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933428036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1933428036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.1288793233
Short name T756
Test name
Test status
Simulation time 73420400 ps
CPU time 164.48 seconds
Started Oct 09 08:25:41 PM UTC 24
Finished Oct 09 08:28:28 PM UTC 24
Peak memory 287556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288793233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1288793233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.581020006
Short name T772
Test name
Test status
Simulation time 2694894500 ps
CPU time 197.63 seconds
Started Oct 09 08:26:11 PM UTC 24
Finished Oct 09 08:29:32 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=581020006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.581020006
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.3510632729
Short name T768
Test name
Test status
Simulation time 259721300 ps
CPU time 25.95 seconds
Started Oct 09 08:28:50 PM UTC 24
Finished Oct 09 08:29:18 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510632729 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.3510632729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.4053094716
Short name T758
Test name
Test status
Simulation time 41918100 ps
CPU time 25.95 seconds
Started Oct 09 08:28:22 PM UTC 24
Finished Oct 09 08:28:49 PM UTC 24
Peak memory 284868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053094716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.4053094716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3783036149
Short name T821
Test name
Test status
Simulation time 10012152400 ps
CPU time 225.06 seconds
Started Oct 09 08:28:48 PM UTC 24
Finished Oct 09 08:32:37 PM UTC 24
Peak memory 412700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3783036149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3783036149
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.456663310
Short name T764
Test name
Test status
Simulation time 93686200 ps
CPU time 20.18 seconds
Started Oct 09 08:28:44 PM UTC 24
Finished Oct 09 08:29:05 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=456663310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.flash_ctrl_hw_read_seed_err.456663310
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3835944306
Short name T996
Test name
Test status
Simulation time 40125771100 ps
CPU time 778.55 seconds
Started Oct 09 08:27:19 PM UTC 24
Finished Oct 09 08:40:27 PM UTC 24
Peak memory 275032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835944306
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res
et.3835944306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1315242487
Short name T754
Test name
Test status
Simulation time 3629830300 ps
CPU time 60.94 seconds
Started Oct 09 08:27:17 PM UTC 24
Finished Oct 09 08:28:20 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315242487 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.1315242487
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1412444151
Short name T794
Test name
Test status
Simulation time 1273858900 ps
CPU time 170.53 seconds
Started Oct 09 08:27:58 PM UTC 24
Finished Oct 09 08:30:52 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412444151 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.1412444151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1508826851
Short name T851
Test name
Test status
Simulation time 25811836400 ps
CPU time 356.89 seconds
Started Oct 09 08:28:00 PM UTC 24
Finished Oct 09 08:34:02 PM UTC 24
Peak memory 301864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1508826851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_intr_rd_slow_flash.1508826851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.1234759243
Short name T760
Test name
Test status
Simulation time 14625850000 ps
CPU time 88.8 seconds
Started Oct 09 08:27:27 PM UTC 24
Finished Oct 09 08:28:58 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234759243 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1234759243
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.2839595896
Short name T759
Test name
Test status
Simulation time 44407500 ps
CPU time 25.83 seconds
Started Oct 09 08:28:29 PM UTC 24
Finished Oct 09 08:28:56 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2839595896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_lcmgr_intg.2839595896
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.3625576781
Short name T803
Test name
Test status
Simulation time 10691425800 ps
CPU time 231.76 seconds
Started Oct 09 08:27:23 PM UTC 24
Finished Oct 09 08:31:19 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3625576781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_mp_regions.3625576781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.258080598
Short name T931
Test name
Test status
Simulation time 1042323900 ps
CPU time 623.09 seconds
Started Oct 09 08:27:16 PM UTC 24
Finished Oct 09 08:37:47 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258080598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.258080598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.811143384
Short name T755
Test name
Test status
Simulation time 56641100 ps
CPU time 17.74 seconds
Started Oct 09 08:28:02 PM UTC 24
Finished Oct 09 08:28:21 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811143384 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.811143384
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1096308674
Short name T1141
Test name
Test status
Simulation time 929679900 ps
CPU time 1839.84 seconds
Started Oct 09 08:27:16 PM UTC 24
Finished Oct 09 08:58:16 PM UTC 24
Peak memory 300456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096308674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1096308674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2318699745
Short name T761
Test name
Test status
Simulation time 135631700 ps
CPU time 49.77 seconds
Started Oct 09 08:28:06 PM UTC 24
Finished Oct 09 08:28:58 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318699745 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.2318699745
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1110463156
Short name T774
Test name
Test status
Simulation time 1078523800 ps
CPU time 122.08 seconds
Started Oct 09 08:27:35 PM UTC 24
Finished Oct 09 08:29:40 PM UTC 24
Peak memory 292056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1110463156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1110463156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.755624762
Short name T909
Test name
Test status
Simulation time 4105024200 ps
CPU time 539.86 seconds
Started Oct 09 08:27:35 PM UTC 24
Finished Oct 09 08:36:42 PM UTC 24
Peak memory 330764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755624762 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.755624762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.612235736
Short name T757
Test name
Test status
Simulation time 99396200 ps
CPU time 42 seconds
Started Oct 09 08:28:03 PM UTC 24
Finished Oct 09 08:28:47 PM UTC 24
Peak memory 283776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612235736 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.612235736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1517825479
Short name T765
Test name
Test status
Simulation time 39423500 ps
CPU time 60.82 seconds
Started Oct 09 08:28:03 PM UTC 24
Finished Oct 09 08:29:06 PM UTC 24
Peak memory 285884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1517825479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw_evict_all_en.1517825479
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.1079595392
Short name T375
Test name
Test status
Simulation time 27286294100 ps
CPU time 90.97 seconds
Started Oct 09 08:28:20 PM UTC 24
Finished Oct 09 08:29:54 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079595392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1079595392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.3699340579
Short name T763
Test name
Test status
Simulation time 30932400 ps
CPU time 107.13 seconds
Started Oct 09 08:27:15 PM UTC 24
Finished Oct 09 08:29:04 PM UTC 24
Peak memory 287620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699340579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3699340579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.458353843
Short name T793
Test name
Test status
Simulation time 4794065500 ps
CPU time 199.91 seconds
Started Oct 09 08:27:29 PM UTC 24
Finished Oct 09 08:30:52 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=458353843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.458353843
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.2574311227
Short name T22
Test name
Test status
Simulation time 13163500 ps
CPU time 21.31 seconds
Started Oct 09 07:38:50 PM UTC 24
Finished Oct 09 07:39:13 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2574311227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2574311227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2238671608
Short name T112
Test name
Test status
Simulation time 160458800 ps
CPU time 21.33 seconds
Started Oct 09 07:39:36 PM UTC 24
Finished Oct 09 07:39:58 PM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238671608 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2238671608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3554459003
Short name T351
Test name
Test status
Simulation time 37240800 ps
CPU time 21.49 seconds
Started Oct 09 07:39:12 PM UTC 24
Finished Oct 09 07:39:35 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554459003 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.3554459003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.1883023276
Short name T287
Test name
Test status
Simulation time 2114080500 ps
CPU time 242.66 seconds
Started Oct 09 07:36:47 PM UTC 24
Finished Oct 09 07:40:54 PM UTC 24
Peak memory 287736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1883023276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_derr_detect.1883023276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1849258432
Short name T429
Test name
Test status
Simulation time 14735700 ps
CPU time 35.57 seconds
Started Oct 09 07:38:12 PM UTC 24
Finished Oct 09 07:38:49 PM UTC 24
Peak memory 285944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1849258432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_disable.1849258432
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.1681321365
Short name T218
Test name
Test status
Simulation time 2130607100 ps
CPU time 572.81 seconds
Started Oct 09 07:33:15 PM UTC 24
Finished Oct 09 07:42:56 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681321365 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1681321365
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1083883423
Short name T273
Test name
Test status
Simulation time 17162016400 ps
CPU time 3185.41 seconds
Started Oct 09 07:36:26 PM UTC 24
Finished Oct 09 08:30:06 PM UTC 24
Peak memory 275812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083883423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1083883423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.3107638104
Short name T275
Test name
Test status
Simulation time 2537463100 ps
CPU time 1211.21 seconds
Started Oct 09 07:36:26 PM UTC 24
Finished Oct 09 07:56:52 PM UTC 24
Peak memory 285396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107638104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3107638104
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.3284114503
Short name T59
Test name
Test status
Simulation time 403246900 ps
CPU time 39.53 seconds
Started Oct 09 07:36:14 PM UTC 24
Finished Oct 09 07:36:55 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32
84114503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc
h_code.3284114503
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1860209463
Short name T1129
Test name
Test status
Simulation time 52828500000 ps
CPU time 4138.25 seconds
Started Oct 09 07:36:23 PM UTC 24
Finished Oct 09 08:46:11 PM UTC 24
Peak memory 277876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860209463 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.1860209463
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.709207056
Short name T431
Test name
Test status
Simulation time 27237100 ps
CPU time 46.6 seconds
Started Oct 09 07:39:31 PM UTC 24
Finished Oct 09 07:40:20 PM UTC 24
Peak memory 287476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709207056
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hos
t_addr_infection.709207056
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.1344459719
Short name T214
Test name
Test status
Simulation time 145282000 ps
CPU time 113.39 seconds
Started Oct 09 07:32:31 PM UTC 24
Finished Oct 09 07:34:28 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344459719 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1344459719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3115565256
Short name T192
Test name
Test status
Simulation time 10036018200 ps
CPU time 92.87 seconds
Started Oct 09 07:39:28 PM UTC 24
Finished Oct 09 07:41:03 PM UTC 24
Peak memory 295772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3115565256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3115565256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.315455009
Short name T166
Test name
Test status
Simulation time 49050700 ps
CPU time 21.16 seconds
Started Oct 09 07:39:28 PM UTC 24
Finished Oct 09 07:39:51 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=315455009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_hw_read_seed_err.315455009
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2376592962
Short name T181
Test name
Test status
Simulation time 340531425600 ps
CPU time 2159.95 seconds
Started Oct 09 07:33:36 PM UTC 24
Finished Oct 09 08:10:03 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376592962
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.2376592962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2597410211
Short name T163
Test name
Test status
Simulation time 160176571200 ps
CPU time 1337.64 seconds
Started Oct 09 07:33:37 PM UTC 24
Finished Oct 09 07:56:13 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597410211
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.2597410211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.393330862
Short name T122
Test name
Test status
Simulation time 1444184300 ps
CPU time 63.86 seconds
Started Oct 09 07:33:00 PM UTC 24
Finished Oct 09 07:34:05 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393330862 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.393330862
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.1289092651
Short name T472
Test name
Test status
Simulation time 7332037700 ps
CPU time 641.92 seconds
Started Oct 09 07:36:56 PM UTC 24
Finished Oct 09 07:47:47 PM UTC 24
Peak memory 341208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1289092651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr
ity.1289092651
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3872679415
Short name T42
Test name
Test status
Simulation time 553361600 ps
CPU time 146.06 seconds
Started Oct 09 07:37:02 PM UTC 24
Finished Oct 09 07:39:31 PM UTC 24
Peak memory 302224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872679415 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.3872679415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3811466673
Short name T436
Test name
Test status
Simulation time 22796093800 ps
CPU time 210.67 seconds
Started Oct 09 07:37:14 PM UTC 24
Finished Oct 09 07:40:49 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3811466673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_intr_rd_slow_flash.3811466673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.3178111251
Short name T382
Test name
Test status
Simulation time 7751492500 ps
CPU time 77.75 seconds
Started Oct 09 07:37:12 PM UTC 24
Finished Oct 09 07:38:32 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178111251 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.3178111251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.676822517
Short name T462
Test name
Test status
Simulation time 263715277800 ps
CPU time 497.81 seconds
Started Oct 09 07:37:18 PM UTC 24
Finished Oct 09 07:45:43 PM UTC 24
Peak memory 275376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676822517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.676822517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2076181361
Short name T145
Test name
Test status
Simulation time 883911500 ps
CPU time 96.54 seconds
Started Oct 09 07:36:27 PM UTC 24
Finished Oct 09 07:38:06 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076181361 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2076181361
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2706929247
Short name T86
Test name
Test status
Simulation time 36009800 ps
CPU time 203.24 seconds
Started Oct 09 07:33:44 PM UTC 24
Finished Oct 09 07:37:11 PM UTC 24
Peak memory 275228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706929247 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.2706929247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.553183534
Short name T437
Test name
Test status
Simulation time 7496489500 ps
CPU time 263.18 seconds
Started Oct 09 07:36:48 PM UTC 24
Finished Oct 09 07:41:16 PM UTC 24
Peak memory 302064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=553183534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_oversize_error.553183534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2074032348
Short name T216
Test name
Test status
Simulation time 24132000 ps
CPU time 29.41 seconds
Started Oct 09 07:39:06 PM UTC 24
Finished Oct 09 07:39:37 PM UTC 24
Peak memory 275540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074032348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2074032348
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1645986180
Short name T433
Test name
Test status
Simulation time 76059800 ps
CPU time 443.88 seconds
Started Oct 09 07:32:50 PM UTC 24
Finished Oct 09 07:40:20 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645986180 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1645986180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.66213646
Short name T95
Test name
Test status
Simulation time 876793500 ps
CPU time 38.69 seconds
Started Oct 09 07:38:54 PM UTC 24
Finished Oct 09 07:39:35 PM UTC 24
Peak memory 275680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=66213646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.66213646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.4024691405
Short name T444
Test name
Test status
Simulation time 2437133700 ps
CPU time 257.93 seconds
Started Oct 09 07:37:52 PM UTC 24
Finished Oct 09 07:42:15 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024691405 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.4024691405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1892707115
Short name T154
Test name
Test status
Simulation time 149678600 ps
CPU time 734.98 seconds
Started Oct 09 07:32:16 PM UTC 24
Finished Oct 09 07:44:41 PM UTC 24
Peak memory 293756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892707115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1892707115
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1022973617
Short name T219
Test name
Test status
Simulation time 1465471300 ps
CPU time 208.98 seconds
Started Oct 09 07:32:40 PM UTC 24
Finished Oct 09 07:36:12 PM UTC 24
Peak memory 273152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022973617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1022973617
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2950184655
Short name T252
Test name
Test status
Simulation time 115730800 ps
CPU time 48.3 seconds
Started Oct 09 07:38:46 PM UTC 24
Finished Oct 09 07:39:35 PM UTC 24
Peak memory 287536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295018465
5 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.2950184655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2435480620
Short name T146
Test name
Test status
Simulation time 236850100 ps
CPU time 54.86 seconds
Started Oct 09 07:38:07 PM UTC 24
Finished Oct 09 07:39:03 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435480620 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.2435480620
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3782272861
Short name T384
Test name
Test status
Simulation time 154910400 ps
CPU time 36.14 seconds
Started Oct 09 07:36:39 PM UTC 24
Finished Oct 09 07:37:17 PM UTC 24
Peak memory 275388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3782272861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_derr.3782272861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.1305559149
Short name T428
Test name
Test status
Simulation time 39172400 ps
CPU time 34.39 seconds
Started Oct 09 07:36:38 PM UTC 24
Finished Oct 09 07:37:14 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305559149 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.1305559149
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.1476870872
Short name T162
Test name
Test status
Simulation time 43436625600 ps
CPU time 1120.32 seconds
Started Oct 09 07:39:13 PM UTC 24
Finished Oct 09 07:58:08 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1476870872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_rma_err.1476870872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2769407408
Short name T202
Test name
Test status
Simulation time 523975000 ps
CPU time 133.56 seconds
Started Oct 09 07:36:28 PM UTC 24
Finished Oct 09 07:38:45 PM UTC 24
Peak memory 304012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2769407408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2769407408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1964489024
Short name T194
Test name
Test status
Simulation time 975345400 ps
CPU time 178.89 seconds
Started Oct 09 07:36:41 PM UTC 24
Finished Oct 09 07:39:44 PM UTC 24
Peak memory 291836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964489024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1964489024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4041126322
Short name T465
Test name
Test status
Simulation time 20082139800 ps
CPU time 590.63 seconds
Started Oct 09 07:36:35 PM UTC 24
Finished Oct 09 07:46:33 PM UTC 24
Peak memory 331040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041126322 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.4041126322
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1009495419
Short name T438
Test name
Test status
Simulation time 1494218600 ps
CPU time 267.06 seconds
Started Oct 09 07:36:45 PM UTC 24
Finished Oct 09 07:41:17 PM UTC 24
Peak memory 295940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1009495419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rw_derr.1009495419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1359019518
Short name T289
Test name
Test status
Simulation time 28014500 ps
CPU time 52.21 seconds
Started Oct 09 07:37:59 PM UTC 24
Finished Oct 09 07:38:53 PM UTC 24
Peak memory 283776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359019518 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.1359019518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1534611706
Short name T422
Test name
Test status
Simulation time 49875300 ps
CPU time 44.7 seconds
Started Oct 09 07:38:02 PM UTC 24
Finished Oct 09 07:38:48 PM UTC 24
Peak memory 281520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1534611706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw_evict_all_en.1534611706
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.384484849
Short name T296
Test name
Test status
Simulation time 6525564200 ps
CPU time 253.16 seconds
Started Oct 09 07:36:39 PM UTC 24
Finished Oct 09 07:40:57 PM UTC 24
Peak memory 291312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=384484849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.384484849
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2957952588
Short name T191
Test name
Test status
Simulation time 1572151000 ps
CPU time 91.77 seconds
Started Oct 09 07:38:20 PM UTC 24
Finished Oct 09 07:39:54 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957952588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2957952588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2112957137
Short name T383
Test name
Test status
Simulation time 645088800 ps
CPU time 89.73 seconds
Started Oct 09 07:36:39 PM UTC 24
Finished Oct 09 07:38:11 PM UTC 24
Peak memory 275104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211
2957137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser
r_address.2112957137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.2707893185
Short name T385
Test name
Test status
Simulation time 1841183700 ps
CPU time 70.78 seconds
Started Oct 09 07:36:39 PM UTC 24
Finished Oct 09 07:37:52 PM UTC 24
Peak memory 285700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
07893185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se
rr_counter.2707893185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1342121863
Short name T211
Test name
Test status
Simulation time 55679900 ps
CPU time 115.03 seconds
Started Oct 09 07:31:37 PM UTC 24
Finished Oct 09 07:33:35 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342121863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1342121863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.420354363
Short name T209
Test name
Test status
Simulation time 31571300 ps
CPU time 40.81 seconds
Started Oct 09 07:31:56 PM UTC 24
Finished Oct 09 07:32:39 PM UTC 24
Peak memory 270976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420354363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.420354363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.1945396201
Short name T582
Test name
Test status
Simulation time 500770800 ps
CPU time 1894.26 seconds
Started Oct 09 07:38:33 PM UTC 24
Finished Oct 09 08:10:30 PM UTC 24
Peak memory 297740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945396201 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.1945396201
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.2778711166
Short name T294
Test name
Test status
Simulation time 24382500 ps
CPU time 40.13 seconds
Started Oct 09 07:32:17 PM UTC 24
Finished Oct 09 07:32:59 PM UTC 24
Peak memory 272960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778711166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2778711166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1461505497
Short name T430
Test name
Test status
Simulation time 2092498700 ps
CPU time 187.89 seconds
Started Oct 09 07:36:27 PM UTC 24
Finished Oct 09 07:39:39 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1461505497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.1461505497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.1908883095
Short name T20
Test name
Test status
Simulation time 77700500 ps
CPU time 32.8 seconds
Started Oct 09 07:38:49 PM UTC 24
Finished Oct 09 07:39:23 PM UTC 24
Peak memory 275356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1908883095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_wr_intg.1908883095
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.522605049
Short name T779
Test name
Test status
Simulation time 119304800 ps
CPU time 29.13 seconds
Started Oct 09 08:29:25 PM UTC 24
Finished Oct 09 08:29:56 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522605049 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.522605049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.1015799408
Short name T776
Test name
Test status
Simulation time 25803900 ps
CPU time 24.92 seconds
Started Oct 09 08:29:18 PM UTC 24
Finished Oct 09 08:29:44 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015799408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1015799408
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.3407504660
Short name T393
Test name
Test status
Simulation time 13208500 ps
CPU time 28.25 seconds
Started Oct 09 08:29:16 PM UTC 24
Finished Oct 09 08:29:45 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3407504660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_
ctrl_disable.3407504660
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.3058083247
Short name T773
Test name
Test status
Simulation time 3074783700 ps
CPU time 38.11 seconds
Started Oct 09 08:28:57 PM UTC 24
Finished Oct 09 08:29:37 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058083247 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.3058083247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.468742261
Short name T813
Test name
Test status
Simulation time 1491183800 ps
CPU time 188.01 seconds
Started Oct 09 08:28:59 PM UTC 24
Finished Oct 09 08:32:10 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468742261 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.468742261
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3048459075
Short name T810
Test name
Test status
Simulation time 5989749100 ps
CPU time 162.36 seconds
Started Oct 09 08:29:02 PM UTC 24
Finished Oct 09 08:31:47 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3048459075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.flash_ctrl_intr_rd_slow_flash.3048459075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3120566425
Short name T822
Test name
Test status
Simulation time 278822000 ps
CPU time 214.8 seconds
Started Oct 09 08:28:59 PM UTC 24
Finished Oct 09 08:32:37 PM UTC 24
Peak memory 273312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120566425 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.3120566425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.3059141431
Short name T771
Test name
Test status
Simulation time 69338700 ps
CPU time 22.8 seconds
Started Oct 09 08:29:05 PM UTC 24
Finished Oct 09 08:29:29 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059141431 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.3059141431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.425611487
Short name T775
Test name
Test status
Simulation time 28013200 ps
CPU time 34.04 seconds
Started Oct 09 08:29:06 PM UTC 24
Finished Oct 09 08:29:42 PM UTC 24
Peak memory 283584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425611487 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.425611487
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.4285310380
Short name T780
Test name
Test status
Simulation time 69250500 ps
CPU time 50.29 seconds
Started Oct 09 08:29:07 PM UTC 24
Finished Oct 09 08:29:59 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4285310380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c
trl_rw_evict_all_en.4285310380
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2132493882
Short name T374
Test name
Test status
Simulation time 7622107200 ps
CPU time 77.85 seconds
Started Oct 09 08:29:18 PM UTC 24
Finished Oct 09 08:30:38 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132493882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2132493882
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.178501063
Short name T833
Test name
Test status
Simulation time 34816300 ps
CPU time 254.93 seconds
Started Oct 09 08:28:51 PM UTC 24
Finished Oct 09 08:33:10 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178501063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.178501063
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.71643742
Short name T785
Test name
Test status
Simulation time 43178700 ps
CPU time 28.42 seconds
Started Oct 09 08:29:55 PM UTC 24
Finished Oct 09 08:30:25 PM UTC 24
Peak memory 269316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71643742 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.71643742
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.3950578500
Short name T783
Test name
Test status
Simulation time 50258800 ps
CPU time 26.57 seconds
Started Oct 09 08:29:53 PM UTC 24
Finished Oct 09 08:30:21 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950578500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3950578500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.3646903519
Short name T117
Test name
Test status
Simulation time 11294400 ps
CPU time 43.65 seconds
Started Oct 09 08:29:50 PM UTC 24
Finished Oct 09 08:30:36 PM UTC 24
Peak memory 285880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3646903519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_
ctrl_disable.3646903519
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.1866494997
Short name T795
Test name
Test status
Simulation time 1658586800 ps
CPU time 83.92 seconds
Started Oct 09 08:29:30 PM UTC 24
Finished Oct 09 08:30:57 PM UTC 24
Peak memory 273108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866494997 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.1866494997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.704997136
Short name T826
Test name
Test status
Simulation time 1412687700 ps
CPU time 189.39 seconds
Started Oct 09 08:29:38 PM UTC 24
Finished Oct 09 08:32:50 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704997136 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.704997136
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2179076946
Short name T823
Test name
Test status
Simulation time 11294420600 ps
CPU time 173.45 seconds
Started Oct 09 08:29:41 PM UTC 24
Finished Oct 09 08:32:37 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2179076946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.flash_ctrl_intr_rd_slow_flash.2179076946
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.1699513859
Short name T825
Test name
Test status
Simulation time 39734900 ps
CPU time 188.04 seconds
Started Oct 09 08:29:33 PM UTC 24
Finished Oct 09 08:32:44 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699513859 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.1699513859
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.62504441
Short name T781
Test name
Test status
Simulation time 18382500 ps
CPU time 17.08 seconds
Started Oct 09 08:29:43 PM UTC 24
Finished Oct 09 08:30:01 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62504441 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.62504441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.987310233
Short name T790
Test name
Test status
Simulation time 48015800 ps
CPU time 49.32 seconds
Started Oct 09 08:29:45 PM UTC 24
Finished Oct 09 08:30:36 PM UTC 24
Peak memory 281792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987310233 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.987310233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.3867841886
Short name T787
Test name
Test status
Simulation time 28312800 ps
CPU time 39.92 seconds
Started Oct 09 08:29:46 PM UTC 24
Finished Oct 09 08:30:28 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3867841886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c
trl_rw_evict_all_en.3867841886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.2924173350
Short name T799
Test name
Test status
Simulation time 1767031900 ps
CPU time 72.42 seconds
Started Oct 09 08:29:52 PM UTC 24
Finished Oct 09 08:31:06 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924173350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2924173350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2055313161
Short name T811
Test name
Test status
Simulation time 94167200 ps
CPU time 141.51 seconds
Started Oct 09 08:29:27 PM UTC 24
Finished Oct 09 08:31:52 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055313161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2055313161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.1952788993
Short name T800
Test name
Test status
Simulation time 326881700 ps
CPU time 29.84 seconds
Started Oct 09 08:30:36 PM UTC 24
Finished Oct 09 08:31:07 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952788993 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.1952788993
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.3851878029
Short name T796
Test name
Test status
Simulation time 64954400 ps
CPU time 25.29 seconds
Started Oct 09 08:30:30 PM UTC 24
Finished Oct 09 08:30:57 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851878029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3851878029
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.1025201068
Short name T797
Test name
Test status
Simulation time 171758500 ps
CPU time 32.39 seconds
Started Oct 09 08:30:28 PM UTC 24
Finished Oct 09 08:31:02 PM UTC 24
Peak memory 285448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1025201068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_
ctrl_disable.1025201068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2504307722
Short name T301
Test name
Test status
Simulation time 3064954200 ps
CPU time 107.56 seconds
Started Oct 09 08:30:00 PM UTC 24
Finished Oct 09 08:31:50 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504307722 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.2504307722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1808800260
Short name T875
Test name
Test status
Simulation time 18236281200 ps
CPU time 284.8 seconds
Started Oct 09 08:30:08 PM UTC 24
Finished Oct 09 08:34:57 PM UTC 24
Peak memory 302120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1808800260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.flash_ctrl_intr_rd_slow_flash.1808800260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3422690972
Short name T792
Test name
Test status
Simulation time 35081700 ps
CPU time 18.27 seconds
Started Oct 09 08:30:22 PM UTC 24
Finished Oct 09 08:30:41 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422690972 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3422690972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.1759481401
Short name T798
Test name
Test status
Simulation time 44729800 ps
CPU time 35.96 seconds
Started Oct 09 08:30:25 PM UTC 24
Finished Oct 09 08:31:02 PM UTC 24
Peak memory 287964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759481401 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.1759481401
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.2749094655
Short name T802
Test name
Test status
Simulation time 35778400 ps
CPU time 49.09 seconds
Started Oct 09 08:30:26 PM UTC 24
Finished Oct 09 08:31:17 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2749094655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c
trl_rw_evict_all_en.2749094655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.996158622
Short name T809
Test name
Test status
Simulation time 2279973100 ps
CPU time 74.83 seconds
Started Oct 09 08:30:28 PM UTC 24
Finished Oct 09 08:31:45 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996158622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.996158622
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.1995473666
Short name T818
Test name
Test status
Simulation time 32998700 ps
CPU time 147.62 seconds
Started Oct 09 08:29:57 PM UTC 24
Finished Oct 09 08:32:27 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995473666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1995473666
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1146536292
Short name T807
Test name
Test status
Simulation time 87394400 ps
CPU time 30.39 seconds
Started Oct 09 08:31:07 PM UTC 24
Finished Oct 09 08:31:39 PM UTC 24
Peak memory 275380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146536292 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1146536292
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.2976494199
Short name T805
Test name
Test status
Simulation time 17204900 ps
CPU time 27.23 seconds
Started Oct 09 08:31:03 PM UTC 24
Finished Oct 09 08:31:32 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976494199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2976494199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.1707175299
Short name T804
Test name
Test status
Simulation time 10965000 ps
CPU time 28.73 seconds
Started Oct 09 08:30:58 PM UTC 24
Finished Oct 09 08:31:28 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1707175299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_
ctrl_disable.1707175299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3931440878
Short name T801
Test name
Test status
Simulation time 565739100 ps
CPU time 31.83 seconds
Started Oct 09 08:30:37 PM UTC 24
Finished Oct 09 08:31:10 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931440878 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3931440878
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.1094251153
Short name T863
Test name
Test status
Simulation time 1723713900 ps
CPU time 223.53 seconds
Started Oct 09 08:30:40 PM UTC 24
Finished Oct 09 08:34:28 PM UTC 24
Peak memory 294032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094251153 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.1094251153
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.871897458
Short name T834
Test name
Test status
Simulation time 6008273300 ps
CPU time 149.67 seconds
Started Oct 09 08:30:42 PM UTC 24
Finished Oct 09 08:33:15 PM UTC 24
Peak memory 304172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=871897458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 23.flash_ctrl_intr_rd_slow_flash.871897458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3152979082
Short name T853
Test name
Test status
Simulation time 43415000 ps
CPU time 199.45 seconds
Started Oct 09 08:30:39 PM UTC 24
Finished Oct 09 08:34:02 PM UTC 24
Peak memory 275444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152979082 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.3152979082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.4013614978
Short name T857
Test name
Test status
Simulation time 8669832400 ps
CPU time 195.87 seconds
Started Oct 09 08:30:53 PM UTC 24
Finished Oct 09 08:34:12 PM UTC 24
Peak memory 275336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013614978 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.4013614978
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.2391486118
Short name T808
Test name
Test status
Simulation time 30972800 ps
CPU time 47.09 seconds
Started Oct 09 08:30:54 PM UTC 24
Finished Oct 09 08:31:42 PM UTC 24
Peak memory 283572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391486118 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.2391486118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3848505666
Short name T806
Test name
Test status
Simulation time 66758200 ps
CPU time 37.69 seconds
Started Oct 09 08:30:58 PM UTC 24
Finished Oct 09 08:31:37 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3848505666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c
trl_rw_evict_all_en.3848505666
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.3867596112
Short name T820
Test name
Test status
Simulation time 1428655800 ps
CPU time 91.2 seconds
Started Oct 09 08:31:03 PM UTC 24
Finished Oct 09 08:32:36 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867596112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3867596112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.2792074961
Short name T827
Test name
Test status
Simulation time 24935900 ps
CPU time 135.65 seconds
Started Oct 09 08:30:37 PM UTC 24
Finished Oct 09 08:32:55 PM UTC 24
Peak memory 287620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792074961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2792074961
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.3809741693
Short name T815
Test name
Test status
Simulation time 41733100 ps
CPU time 23.2 seconds
Started Oct 09 08:31:51 PM UTC 24
Finished Oct 09 08:32:16 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809741693 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.3809741693
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.1680717481
Short name T816
Test name
Test status
Simulation time 27544000 ps
CPU time 27.92 seconds
Started Oct 09 08:31:48 PM UTC 24
Finished Oct 09 08:32:18 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680717481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1680717481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.186417397
Short name T814
Test name
Test status
Simulation time 10837600 ps
CPU time 31.33 seconds
Started Oct 09 08:31:43 PM UTC 24
Finished Oct 09 08:32:16 PM UTC 24
Peak memory 285572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=186417397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_disable.186417397
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.3966487783
Short name T817
Test name
Test status
Simulation time 1816957700 ps
CPU time 72.21 seconds
Started Oct 09 08:31:10 PM UTC 24
Finished Oct 09 08:32:25 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966487783 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.3966487783
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.1920869242
Short name T840
Test name
Test status
Simulation time 568462300 ps
CPU time 131.65 seconds
Started Oct 09 08:31:20 PM UTC 24
Finished Oct 09 08:33:35 PM UTC 24
Peak memory 302032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920869242 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.1920869242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3419445779
Short name T862
Test name
Test status
Simulation time 11809495900 ps
CPU time 173.1 seconds
Started Oct 09 08:31:28 PM UTC 24
Finished Oct 09 08:34:25 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3419445779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.flash_ctrl_intr_rd_slow_flash.3419445779
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.4152278628
Short name T868
Test name
Test status
Simulation time 129354600 ps
CPU time 194.76 seconds
Started Oct 09 08:31:18 PM UTC 24
Finished Oct 09 08:34:36 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152278628 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.4152278628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.2671519076
Short name T812
Test name
Test status
Simulation time 19301600 ps
CPU time 21.89 seconds
Started Oct 09 08:31:33 PM UTC 24
Finished Oct 09 08:31:56 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671519076 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.2671519076
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.4189250105
Short name T824
Test name
Test status
Simulation time 43012500 ps
CPU time 62.33 seconds
Started Oct 09 08:31:38 PM UTC 24
Finished Oct 09 08:32:42 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189250105 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.4189250105
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3802156129
Short name T819
Test name
Test status
Simulation time 76040500 ps
CPU time 48.09 seconds
Started Oct 09 08:31:40 PM UTC 24
Finished Oct 09 08:32:30 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3802156129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_rw_evict_all_en.3802156129
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.855545935
Short name T830
Test name
Test status
Simulation time 4394977200 ps
CPU time 71.06 seconds
Started Oct 09 08:31:46 PM UTC 24
Finished Oct 09 08:32:59 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855545935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.855545935
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.997438109
Short name T882
Test name
Test status
Simulation time 34989400 ps
CPU time 251.89 seconds
Started Oct 09 08:31:08 PM UTC 24
Finished Oct 09 08:35:24 PM UTC 24
Peak memory 289664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997438109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.997438109
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1686283558
Short name T832
Test name
Test status
Simulation time 111389100 ps
CPU time 24.19 seconds
Started Oct 09 08:32:38 PM UTC 24
Finished Oct 09 08:33:03 PM UTC 24
Peak memory 275460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686283558 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.1686283558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1370552609
Short name T829
Test name
Test status
Simulation time 21021300 ps
CPU time 19.11 seconds
Started Oct 09 08:32:38 PM UTC 24
Finished Oct 09 08:32:58 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370552609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1370552609
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3237973166
Short name T831
Test name
Test status
Simulation time 17035600 ps
CPU time 28.53 seconds
Started Oct 09 08:32:31 PM UTC 24
Finished Oct 09 08:33:01 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3237973166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_
ctrl_disable.3237973166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3847792074
Short name T845
Test name
Test status
Simulation time 789742400 ps
CPU time 102.12 seconds
Started Oct 09 08:31:57 PM UTC 24
Finished Oct 09 08:33:41 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847792074 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3847792074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.1197317717
Short name T308
Test name
Test status
Simulation time 7318534800 ps
CPU time 275.47 seconds
Started Oct 09 08:32:17 PM UTC 24
Finished Oct 09 08:36:57 PM UTC 24
Peak memory 302288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197317717 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.1197317717
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3124542532
Short name T905
Test name
Test status
Simulation time 12310131900 ps
CPU time 258.16 seconds
Started Oct 09 08:32:17 PM UTC 24
Finished Oct 09 08:36:39 PM UTC 24
Peak memory 302148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3124542532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.flash_ctrl_intr_rd_slow_flash.3124542532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.2564474388
Short name T872
Test name
Test status
Simulation time 157601700 ps
CPU time 157.98 seconds
Started Oct 09 08:32:11 PM UTC 24
Finished Oct 09 08:34:51 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564474388 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.2564474388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.3405325471
Short name T887
Test name
Test status
Simulation time 2416027000 ps
CPU time 192.23 seconds
Started Oct 09 08:32:18 PM UTC 24
Finished Oct 09 08:35:34 PM UTC 24
Peak memory 271364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405325471 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.3405325471
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.3250546654
Short name T835
Test name
Test status
Simulation time 29116800 ps
CPU time 49.63 seconds
Started Oct 09 08:32:25 PM UTC 24
Finished Oct 09 08:33:17 PM UTC 24
Peak memory 283572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250546654 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.3250546654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.648079964
Short name T836
Test name
Test status
Simulation time 30122100 ps
CPU time 53.8 seconds
Started Oct 09 08:32:29 PM UTC 24
Finished Oct 09 08:33:24 PM UTC 24
Peak memory 279480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=648079964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ct
rl_rw_evict_all_en.648079964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.548915093
Short name T860
Test name
Test status
Simulation time 1300996300 ps
CPU time 100.23 seconds
Started Oct 09 08:32:37 PM UTC 24
Finished Oct 09 08:34:19 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548915093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.548915093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.2481193218
Short name T844
Test name
Test status
Simulation time 20080300 ps
CPU time 105.43 seconds
Started Oct 09 08:31:53 PM UTC 24
Finished Oct 09 08:33:40 PM UTC 24
Peak memory 279244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481193218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2481193218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2128430396
Short name T839
Test name
Test status
Simulation time 121579500 ps
CPU time 16.96 seconds
Started Oct 09 08:33:12 PM UTC 24
Finished Oct 09 08:33:30 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128430396 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.2128430396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.2493070255
Short name T842
Test name
Test status
Simulation time 44099300 ps
CPU time 23.71 seconds
Started Oct 09 08:33:11 PM UTC 24
Finished Oct 09 08:33:36 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493070255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2493070255
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.3674947879
Short name T838
Test name
Test status
Simulation time 12093900 ps
CPU time 27.09 seconds
Started Oct 09 08:33:01 PM UTC 24
Finished Oct 09 08:33:30 PM UTC 24
Peak memory 285880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3674947879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_
ctrl_disable.3674947879
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1677101510
Short name T841
Test name
Test status
Simulation time 2177452200 ps
CPU time 50.63 seconds
Started Oct 09 08:32:43 PM UTC 24
Finished Oct 09 08:33:36 PM UTC 24
Peak memory 273108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677101510 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.1677101510
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.4193516228
Short name T904
Test name
Test status
Simulation time 1979914200 ps
CPU time 222.25 seconds
Started Oct 09 08:32:52 PM UTC 24
Finished Oct 09 08:36:37 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193516228 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.4193516228
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2804015655
Short name T913
Test name
Test status
Simulation time 10759935300 ps
CPU time 232.5 seconds
Started Oct 09 08:32:56 PM UTC 24
Finished Oct 09 08:36:52 PM UTC 24
Peak memory 304168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2804015655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.flash_ctrl_intr_rd_slow_flash.2804015655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.3308380634
Short name T159
Test name
Test status
Simulation time 154122400 ps
CPU time 164.8 seconds
Started Oct 09 08:32:44 PM UTC 24
Finished Oct 09 08:35:32 PM UTC 24
Peak memory 271008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308380634 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.3308380634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.17352566
Short name T837
Test name
Test status
Simulation time 32251200 ps
CPU time 27.39 seconds
Started Oct 09 08:32:58 PM UTC 24
Finished Oct 09 08:33:27 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17352566 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.17352566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.2042643903
Short name T852
Test name
Test status
Simulation time 30958200 ps
CPU time 60.73 seconds
Started Oct 09 08:32:59 PM UTC 24
Finished Oct 09 08:34:02 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042643903 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.2042643903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.3575805500
Short name T847
Test name
Test status
Simulation time 42004800 ps
CPU time 50.18 seconds
Started Oct 09 08:33:00 PM UTC 24
Finished Oct 09 08:33:52 PM UTC 24
Peak memory 285884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3575805500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c
trl_rw_evict_all_en.3575805500
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.3705715973
Short name T864
Test name
Test status
Simulation time 35968600 ps
CPU time 108.49 seconds
Started Oct 09 08:32:38 PM UTC 24
Finished Oct 09 08:34:29 PM UTC 24
Peak memory 279240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705715973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3705715973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.1403874196
Short name T856
Test name
Test status
Simulation time 59065000 ps
CPU time 26.24 seconds
Started Oct 09 08:33:42 PM UTC 24
Finished Oct 09 08:34:10 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403874196 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.1403874196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3974220546
Short name T849
Test name
Test status
Simulation time 40857200 ps
CPU time 17.48 seconds
Started Oct 09 08:33:41 PM UTC 24
Finished Oct 09 08:34:00 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974220546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3974220546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.1866958050
Short name T858
Test name
Test status
Simulation time 13315100 ps
CPU time 33.82 seconds
Started Oct 09 08:33:37 PM UTC 24
Finished Oct 09 08:34:12 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1866958050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_
ctrl_disable.1866958050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.2137654684
Short name T855
Test name
Test status
Simulation time 6943258600 ps
CPU time 46.04 seconds
Started Oct 09 08:33:18 PM UTC 24
Finished Oct 09 08:34:06 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137654684 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.2137654684
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.3228925146
Short name T914
Test name
Test status
Simulation time 4199994800 ps
CPU time 203.11 seconds
Started Oct 09 08:33:27 PM UTC 24
Finished Oct 09 08:36:54 PM UTC 24
Peak memory 302032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228925146 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.3228925146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.981609042
Short name T948
Test name
Test status
Simulation time 12311650300 ps
CPU time 294.15 seconds
Started Oct 09 08:33:30 PM UTC 24
Finished Oct 09 08:38:30 PM UTC 24
Peak memory 301892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=981609042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 27.flash_ctrl_intr_rd_slow_flash.981609042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.537178221
Short name T912
Test name
Test status
Simulation time 35385900 ps
CPU time 201.57 seconds
Started Oct 09 08:33:25 PM UTC 24
Finished Oct 09 08:36:50 PM UTC 24
Peak memory 275228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537178221 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.537178221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2421546344
Short name T850
Test name
Test status
Simulation time 196528500 ps
CPU time 27.79 seconds
Started Oct 09 08:33:32 PM UTC 24
Finished Oct 09 08:34:01 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421546344 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2421546344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2848528926
Short name T859
Test name
Test status
Simulation time 60042800 ps
CPU time 38.25 seconds
Started Oct 09 08:33:36 PM UTC 24
Finished Oct 09 08:34:15 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848528926 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.2848528926
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.4079327441
Short name T861
Test name
Test status
Simulation time 70060300 ps
CPU time 42.51 seconds
Started Oct 09 08:33:37 PM UTC 24
Finished Oct 09 08:34:21 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4079327441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c
trl_rw_evict_all_en.4079327441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.3279412044
Short name T871
Test name
Test status
Simulation time 2220573500 ps
CPU time 64.19 seconds
Started Oct 09 08:33:39 PM UTC 24
Finished Oct 09 08:34:45 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279412044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3279412044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.196440594
Short name T881
Test name
Test status
Simulation time 40065300 ps
CPU time 124.35 seconds
Started Oct 09 08:33:16 PM UTC 24
Finished Oct 09 08:35:23 PM UTC 24
Peak memory 277192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196440594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.196440594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.1103124192
Short name T869
Test name
Test status
Simulation time 104851300 ps
CPU time 24.95 seconds
Started Oct 09 08:34:13 PM UTC 24
Finished Oct 09 08:34:40 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103124192 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.1103124192
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.1509713925
Short name T867
Test name
Test status
Simulation time 53313900 ps
CPU time 19.54 seconds
Started Oct 09 08:34:13 PM UTC 24
Finished Oct 09 08:34:34 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509713925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1509713925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.1392292838
Short name T874
Test name
Test status
Simulation time 16054200 ps
CPU time 40.78 seconds
Started Oct 09 08:34:13 PM UTC 24
Finished Oct 09 08:34:56 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1392292838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_
ctrl_disable.1392292838
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.4076468262
Short name T885
Test name
Test status
Simulation time 9824672000 ps
CPU time 94.96 seconds
Started Oct 09 08:33:53 PM UTC 24
Finished Oct 09 08:35:30 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076468262 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.4076468262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.3120237111
Short name T916
Test name
Test status
Simulation time 2208414700 ps
CPU time 180.22 seconds
Started Oct 09 08:34:01 PM UTC 24
Finished Oct 09 08:37:04 PM UTC 24
Peak memory 306088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120237111 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.3120237111
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2422167942
Short name T908
Test name
Test status
Simulation time 6134935200 ps
CPU time 155.13 seconds
Started Oct 09 08:34:02 PM UTC 24
Finished Oct 09 08:36:40 PM UTC 24
Peak memory 303908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2422167942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.flash_ctrl_intr_rd_slow_flash.2422167942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.743689223
Short name T900
Test name
Test status
Simulation time 50358600 ps
CPU time 147.42 seconds
Started Oct 09 08:33:54 PM UTC 24
Finished Oct 09 08:36:24 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743689223 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.743689223
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.3030435524
Short name T865
Test name
Test status
Simulation time 19431100 ps
CPU time 28.26 seconds
Started Oct 09 08:34:02 PM UTC 24
Finished Oct 09 08:34:32 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030435524 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.3030435524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.2662401579
Short name T870
Test name
Test status
Simulation time 46100300 ps
CPU time 36.44 seconds
Started Oct 09 08:34:02 PM UTC 24
Finished Oct 09 08:34:40 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662401579 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.2662401579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.4220780286
Short name T873
Test name
Test status
Simulation time 72948900 ps
CPU time 48.05 seconds
Started Oct 09 08:34:03 PM UTC 24
Finished Oct 09 08:34:53 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4220780286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c
trl_rw_evict_all_en.4220780286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.795935357
Short name T889
Test name
Test status
Simulation time 1566958500 ps
CPU time 83.91 seconds
Started Oct 09 08:34:13 PM UTC 24
Finished Oct 09 08:35:39 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795935357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.795935357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.649771521
Short name T886
Test name
Test status
Simulation time 52132000 ps
CPU time 102.03 seconds
Started Oct 09 08:33:49 PM UTC 24
Finished Oct 09 08:35:33 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649771521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.649771521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.3234717754
Short name T877
Test name
Test status
Simulation time 62170000 ps
CPU time 25.82 seconds
Started Oct 09 08:34:37 PM UTC 24
Finished Oct 09 08:35:04 PM UTC 24
Peak memory 269056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234717754 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.3234717754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1994849074
Short name T876
Test name
Test status
Simulation time 66422400 ps
CPU time 25.9 seconds
Started Oct 09 08:34:37 PM UTC 24
Finished Oct 09 08:35:04 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994849074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1994849074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2886152423
Short name T879
Test name
Test status
Simulation time 36258700 ps
CPU time 34.92 seconds
Started Oct 09 08:34:35 PM UTC 24
Finished Oct 09 08:35:11 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2886152423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_
ctrl_disable.2886152423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.4063436033
Short name T906
Test name
Test status
Simulation time 23953922900 ps
CPU time 146.08 seconds
Started Oct 09 08:34:17 PM UTC 24
Finished Oct 09 08:36:45 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063436033 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.4063436033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.2259901021
Short name T911
Test name
Test status
Simulation time 1046011700 ps
CPU time 139.76 seconds
Started Oct 09 08:34:22 PM UTC 24
Finished Oct 09 08:36:45 PM UTC 24
Peak memory 306120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259901021 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.2259901021
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.851043728
Short name T975
Test name
Test status
Simulation time 70980017900 ps
CPU time 317.25 seconds
Started Oct 09 08:34:26 PM UTC 24
Finished Oct 09 08:39:48 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=851043728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 29.flash_ctrl_intr_rd_slow_flash.851043728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.638097889
Short name T929
Test name
Test status
Simulation time 37920900 ps
CPU time 190.07 seconds
Started Oct 09 08:34:21 PM UTC 24
Finished Oct 09 08:37:34 PM UTC 24
Peak memory 273308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638097889 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.638097889
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.1281239850
Short name T907
Test name
Test status
Simulation time 3176232100 ps
CPU time 140.23 seconds
Started Oct 09 08:34:28 PM UTC 24
Finished Oct 09 08:36:51 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281239850 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.1281239850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.4187925336
Short name T878
Test name
Test status
Simulation time 75089900 ps
CPU time 36.42 seconds
Started Oct 09 08:34:30 PM UTC 24
Finished Oct 09 08:35:08 PM UTC 24
Peak memory 285916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187925336 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.4187925336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.4289828892
Short name T880
Test name
Test status
Simulation time 26722900 ps
CPU time 42.65 seconds
Started Oct 09 08:34:32 PM UTC 24
Finished Oct 09 08:35:17 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4289828892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_rw_evict_all_en.4289828892
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.4273131985
Short name T893
Test name
Test status
Simulation time 1866568800 ps
CPU time 84.06 seconds
Started Oct 09 08:34:35 PM UTC 24
Finished Oct 09 08:36:01 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273131985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.4273131985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.2754840403
Short name T941
Test name
Test status
Simulation time 68503700 ps
CPU time 239.35 seconds
Started Oct 09 08:34:13 PM UTC 24
Finished Oct 09 08:38:16 PM UTC 24
Peak memory 289476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754840403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2754840403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1498295491
Short name T295
Test name
Test status
Simulation time 52177800 ps
CPU time 28.6 seconds
Started Oct 09 07:43:03 PM UTC 24
Finished Oct 09 07:43:33 PM UTC 24
Peak memory 269032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498295491 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1498295491
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1320517552
Short name T454
Test name
Test status
Simulation time 74760100 ps
CPU time 28.64 seconds
Started Oct 09 07:42:58 PM UTC 24
Finished Oct 09 07:43:28 PM UTC 24
Peak memory 273324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320517552 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.1320517552
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.886596686
Short name T449
Test name
Test status
Simulation time 24319100 ps
CPU time 19.53 seconds
Started Oct 09 07:42:42 PM UTC 24
Finished Oct 09 07:43:03 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886596686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.886596686
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.842782899
Short name T253
Test name
Test status
Simulation time 1229658500 ps
CPU time 267.99 seconds
Started Oct 09 07:41:34 PM UTC 24
Finished Oct 09 07:46:07 PM UTC 24
Peak memory 287928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=842782899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_derr_detect.842782899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.936997732
Short name T221
Test name
Test status
Simulation time 2843869600 ps
CPU time 464.36 seconds
Started Oct 09 07:39:45 PM UTC 24
Finished Oct 09 07:47:35 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936997732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.936997732
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.2268708558
Short name T866
Test name
Test status
Simulation time 4349679300 ps
CPU time 3216.55 seconds
Started Oct 09 07:40:22 PM UTC 24
Finished Oct 09 08:34:33 PM UTC 24
Peak memory 275880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268708558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2268708558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.1238317399
Short name T108
Test name
Test status
Simulation time 326303400 ps
CPU time 2802.02 seconds
Started Oct 09 07:40:20 PM UTC 24
Finished Oct 09 08:27:34 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12
38317399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_error_prog_type.1238317399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1752886249
Short name T541
Test name
Test status
Simulation time 2524679900 ps
CPU time 1294.01 seconds
Started Oct 09 07:40:22 PM UTC 24
Finished Oct 09 08:02:11 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752886249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1752886249
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4182255758
Short name T60
Test name
Test status
Simulation time 638603900 ps
CPU time 32.51 seconds
Started Oct 09 07:39:55 PM UTC 24
Finished Oct 09 07:40:29 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41
82255758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc
h_code.4182255758
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.874652369
Short name T140
Test name
Test status
Simulation time 159045360100 ps
CPU time 2480.98 seconds
Started Oct 09 07:39:59 PM UTC 24
Finished Oct 09 08:21:48 PM UTC 24
Peak memory 275100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874652369 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.874652369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.4070857943
Short name T766
Test name
Test status
Simulation time 246082271600 ps
CPU time 2932.89 seconds
Started Oct 09 07:39:49 PM UTC 24
Finished Oct 09 08:29:15 PM UTC 24
Peak memory 276504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070857943 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.4070857943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2128309422
Short name T442
Test name
Test status
Simulation time 53377100 ps
CPU time 128.45 seconds
Started Oct 09 07:39:38 PM UTC 24
Finished Oct 09 07:41:49 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128309422 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2128309422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.315307710
Short name T267
Test name
Test status
Simulation time 10058285600 ps
CPU time 76.7 seconds
Started Oct 09 07:43:02 PM UTC 24
Finished Oct 09 07:44:20 PM UTC 24
Peak memory 275668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=315307710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.315307710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.2498175238
Short name T451
Test name
Test status
Simulation time 67951600 ps
CPU time 23.69 seconds
Started Oct 09 07:43:01 PM UTC 24
Finished Oct 09 07:43:26 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2498175238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_hw_read_seed_err.2498175238
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1325271600
Short name T180
Test name
Test status
Simulation time 160158766300 ps
CPU time 1095.06 seconds
Started Oct 09 07:39:46 PM UTC 24
Finished Oct 09 07:58:15 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325271600
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.1325271600
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3280570760
Short name T435
Test name
Test status
Simulation time 649847900 ps
CPU time 59.43 seconds
Started Oct 09 07:39:41 PM UTC 24
Finished Oct 09 07:40:43 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280570760 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.3280570760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2463159229
Short name T489
Test name
Test status
Simulation time 17250385500 ps
CPU time 592.68 seconds
Started Oct 09 07:41:38 PM UTC 24
Finished Oct 09 07:51:38 PM UTC 24
Peak memory 345120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2463159229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr
ity.2463159229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1217349723
Short name T203
Test name
Test status
Simulation time 470499200 ps
CPU time 125.47 seconds
Started Oct 09 07:41:41 PM UTC 24
Finished Oct 09 07:43:49 PM UTC 24
Peak memory 294032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217349723 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.1217349723
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4220352719
Short name T327
Test name
Test status
Simulation time 44945208600 ps
CPU time 225.14 seconds
Started Oct 09 07:41:49 PM UTC 24
Finished Oct 09 07:45:38 PM UTC 24
Peak memory 301856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4220352719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_intr_rd_slow_flash.4220352719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1931168497
Short name T452
Test name
Test status
Simulation time 7515829500 ps
CPU time 98.42 seconds
Started Oct 09 07:41:46 PM UTC 24
Finished Oct 09 07:43:27 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931168497 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.1931168497
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1532802004
Short name T473
Test name
Test status
Simulation time 93549796100 ps
CPU time 352.7 seconds
Started Oct 09 07:41:50 PM UTC 24
Finished Oct 09 07:47:48 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532802004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1532802004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1980242534
Short name T152
Test name
Test status
Simulation time 4650793300 ps
CPU time 66.71 seconds
Started Oct 09 07:40:27 PM UTC 24
Finished Oct 09 07:41:36 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980242534 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1980242534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2990157635
Short name T269
Test name
Test status
Simulation time 25889100 ps
CPU time 27.22 seconds
Started Oct 09 07:42:58 PM UTC 24
Finished Oct 09 07:43:27 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2990157635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_lcmgr_intg.2990157635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.1121033863
Short name T83
Test name
Test status
Simulation time 47045194300 ps
CPU time 416.58 seconds
Started Oct 09 07:39:51 PM UTC 24
Finished Oct 09 07:46:54 PM UTC 24
Peak memory 283344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1121033863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_mp_regions.1121033863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.3680017465
Short name T173
Test name
Test status
Simulation time 69715400 ps
CPU time 187.67 seconds
Started Oct 09 07:39:48 PM UTC 24
Finished Oct 09 07:42:59 PM UTC 24
Peak memory 273456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680017465 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.3680017465
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.135887788
Short name T461
Test name
Test status
Simulation time 3799050600 ps
CPU time 201.1 seconds
Started Oct 09 07:41:37 PM UTC 24
Finished Oct 09 07:45:01 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=135887788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_oversize_error.135887788
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1416347121
Short name T217
Test name
Test status
Simulation time 99897700 ps
CPU time 22.9 seconds
Started Oct 09 07:42:57 PM UTC 24
Finished Oct 09 07:43:21 PM UTC 24
Peak memory 273784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416347121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1416347121
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1510195469
Short name T483
Test name
Test status
Simulation time 2113225500 ps
CPU time 623.53 seconds
Started Oct 09 07:39:41 PM UTC 24
Finished Oct 09 07:50:13 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510195469 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1510195469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.2428150493
Short name T450
Test name
Test status
Simulation time 43889900 ps
CPU time 28.51 seconds
Started Oct 09 07:42:52 PM UTC 24
Finished Oct 09 07:43:22 PM UTC 24
Peak memory 275824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2428150493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.2428150493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.27775872
Short name T445
Test name
Test status
Simulation time 30941600 ps
CPU time 17.67 seconds
Started Oct 09 07:41:58 PM UTC 24
Finished Oct 09 07:42:17 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27775872 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.27775872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.3226056729
Short name T440
Test name
Test status
Simulation time 25469100 ps
CPU time 121.56 seconds
Started Oct 09 07:39:36 PM UTC 24
Finished Oct 09 07:41:40 PM UTC 24
Peak memory 279236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226056729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3226056729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.3979374273
Short name T443
Test name
Test status
Simulation time 76914100 ps
CPU time 146.49 seconds
Started Oct 09 07:39:40 PM UTC 24
Finished Oct 09 07:42:10 PM UTC 24
Peak memory 273144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979374273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3979374273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1724234918
Short name T403
Test name
Test status
Simulation time 78725800 ps
CPU time 43.61 seconds
Started Oct 09 07:42:16 PM UTC 24
Finished Oct 09 07:43:01 PM UTC 24
Peak memory 287700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724234918 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.1724234918
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3437766940
Short name T441
Test name
Test status
Simulation time 58658800 ps
CPU time 28.57 seconds
Started Oct 09 07:41:18 PM UTC 24
Finished Oct 09 07:41:48 PM UTC 24
Peak memory 275376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3437766940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_read_word_sweep_derr.3437766940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.586682072
Short name T439
Test name
Test status
Simulation time 168244100 ps
CPU time 30.25 seconds
Started Oct 09 07:40:50 PM UTC 24
Finished Oct 09 07:41:22 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586682072 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.586682072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3066972069
Short name T248
Test name
Test status
Simulation time 545302600 ps
CPU time 107.76 seconds
Started Oct 09 07:40:44 PM UTC 24
Finished Oct 09 07:42:35 PM UTC 24
Peak memory 302240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3066972069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.3066972069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3432407752
Short name T460
Test name
Test status
Simulation time 620318200 ps
CPU time 189.89 seconds
Started Oct 09 07:41:23 PM UTC 24
Finished Oct 09 07:44:36 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432407752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3432407752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.529701540
Short name T453
Test name
Test status
Simulation time 1602952600 ps
CPU time 148.51 seconds
Started Oct 09 07:40:56 PM UTC 24
Finished Oct 09 07:43:27 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=529701540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_
ctrl_ro_serr.529701540
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.38478469
Short name T416
Test name
Test status
Simulation time 3952252100 ps
CPU time 516.89 seconds
Started Oct 09 07:40:49 PM UTC 24
Finished Oct 09 07:49:33 PM UTC 24
Peak memory 320532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38478469 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.38478469
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3536448619
Short name T249
Test name
Test status
Simulation time 6083460800 ps
CPU time 215.14 seconds
Started Oct 09 07:41:32 PM UTC 24
Finished Oct 09 07:45:11 PM UTC 24
Peak memory 295944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3536448619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_rw_derr.3536448619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.2726655220
Short name T400
Test name
Test status
Simulation time 112366200 ps
CPU time 38.55 seconds
Started Oct 09 07:42:06 PM UTC 24
Finished Oct 09 07:42:46 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726655220 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.2726655220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.1892894826
Short name T407
Test name
Test status
Simulation time 69318800 ps
CPU time 38.28 seconds
Started Oct 09 07:42:11 PM UTC 24
Finished Oct 09 07:42:51 PM UTC 24
Peak memory 287696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1892894826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw_evict_all_en.1892894826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1550776826
Short name T458
Test name
Test status
Simulation time 1613802300 ps
CPU time 191.96 seconds
Started Oct 09 07:40:58 PM UTC 24
Finished Oct 09 07:44:13 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1550776826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.1550776826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.2607194195
Short name T73
Test name
Test status
Simulation time 1549477900 ps
CPU time 6738.01 seconds
Started Oct 09 07:42:30 PM UTC 24
Finished Oct 09 09:36:02 PM UTC 24
Peak memory 310028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607194195 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2607194195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1132285538
Short name T356
Test name
Test status
Simulation time 2095407900 ps
CPU time 89.97 seconds
Started Oct 09 07:42:35 PM UTC 24
Finished Oct 09 07:44:07 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132285538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1132285538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1979578951
Short name T448
Test name
Test status
Simulation time 3704010300 ps
CPU time 103.82 seconds
Started Oct 09 07:41:17 PM UTC 24
Finished Oct 09 07:43:03 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197
9578951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser
r_address.1979578951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.2398069918
Short name T447
Test name
Test status
Simulation time 987279300 ps
CPU time 94.13 seconds
Started Oct 09 07:41:05 PM UTC 24
Finished Oct 09 07:42:41 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23
98069918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se
rr_counter.2398069918
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.728499722
Short name T446
Test name
Test status
Simulation time 134354300 ps
CPU time 170.26 seconds
Started Oct 09 07:39:36 PM UTC 24
Finished Oct 09 07:42:29 PM UTC 24
Peak memory 279424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728499722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.728499722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.3941190749
Short name T432
Test name
Test status
Simulation time 25144900 ps
CPU time 42.76 seconds
Started Oct 09 07:39:36 PM UTC 24
Finished Oct 09 07:40:20 PM UTC 24
Peak memory 270984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941190749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3941190749
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.486957075
Short name T491
Test name
Test status
Simulation time 198805300 ps
CPU time 543.68 seconds
Started Oct 09 07:42:35 PM UTC 24
Finished Oct 09 07:51:46 PM UTC 24
Peak memory 301832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486957075 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.486957075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1220352675
Short name T434
Test name
Test status
Simulation time 95432100 ps
CPU time 47.29 seconds
Started Oct 09 07:39:37 PM UTC 24
Finished Oct 09 07:40:26 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220352675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1220352675
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3099387521
Short name T455
Test name
Test status
Simulation time 4356202000 ps
CPU time 179.05 seconds
Started Oct 09 07:40:30 PM UTC 24
Finished Oct 09 07:43:33 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3099387521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.3099387521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.3773639625
Short name T884
Test name
Test status
Simulation time 88697800 ps
CPU time 20.89 seconds
Started Oct 09 08:35:05 PM UTC 24
Finished Oct 09 08:35:27 PM UTC 24
Peak memory 269236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773639625 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.3773639625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.1199781584
Short name T883
Test name
Test status
Simulation time 29273900 ps
CPU time 19.83 seconds
Started Oct 09 08:35:05 PM UTC 24
Finished Oct 09 08:35:26 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199781584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1199781584
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.1324116270
Short name T302
Test name
Test status
Simulation time 1786334800 ps
CPU time 113.56 seconds
Started Oct 09 08:34:41 PM UTC 24
Finished Oct 09 08:36:37 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324116270 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.1324116270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.3329611230
Short name T928
Test name
Test status
Simulation time 3891487400 ps
CPU time 166.4 seconds
Started Oct 09 08:34:41 PM UTC 24
Finished Oct 09 08:37:31 PM UTC 24
Peak memory 293760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329611230 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.3329611230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.850114443
Short name T944
Test name
Test status
Simulation time 17883628000 ps
CPU time 214.75 seconds
Started Oct 09 08:34:45 PM UTC 24
Finished Oct 09 08:38:24 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=850114443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 30.flash_ctrl_intr_rd_slow_flash.850114443
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.3977051637
Short name T891
Test name
Test status
Simulation time 44582500 ps
CPU time 49.48 seconds
Started Oct 09 08:34:53 PM UTC 24
Finished Oct 09 08:35:44 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977051637 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.3977051637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.969528538
Short name T933
Test name
Test status
Simulation time 45847500 ps
CPU time 191.87 seconds
Started Oct 09 08:34:40 PM UTC 24
Finished Oct 09 08:37:55 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969528538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.969528538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.4017014368
Short name T892
Test name
Test status
Simulation time 37083900 ps
CPU time 24.59 seconds
Started Oct 09 08:35:34 PM UTC 24
Finished Oct 09 08:36:00 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017014368 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.4017014368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.475391251
Short name T894
Test name
Test status
Simulation time 32028000 ps
CPU time 28.4 seconds
Started Oct 09 08:35:33 PM UTC 24
Finished Oct 09 08:36:03 PM UTC 24
Peak memory 294980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475391251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.475391251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1154804368
Short name T895
Test name
Test status
Simulation time 19313800 ps
CPU time 32.9 seconds
Started Oct 09 08:35:28 PM UTC 24
Finished Oct 09 08:36:03 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1154804368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_
ctrl_disable.1154804368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.2963068382
Short name T897
Test name
Test status
Simulation time 554639400 ps
CPU time 65.39 seconds
Started Oct 09 08:35:12 PM UTC 24
Finished Oct 09 08:36:19 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963068382 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.2963068382
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.539218861
Short name T930
Test name
Test status
Simulation time 553896700 ps
CPU time 131.01 seconds
Started Oct 09 08:35:24 PM UTC 24
Finished Oct 09 08:37:37 PM UTC 24
Peak memory 306280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539218861 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.539218861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3808846214
Short name T961
Test name
Test status
Simulation time 10310351200 ps
CPU time 224.68 seconds
Started Oct 09 08:35:25 PM UTC 24
Finished Oct 09 08:39:13 PM UTC 24
Peak memory 301892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3808846214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.flash_ctrl_intr_rd_slow_flash.3808846214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2989942239
Short name T940
Test name
Test status
Simulation time 449526100 ps
CPU time 172.12 seconds
Started Oct 09 08:35:18 PM UTC 24
Finished Oct 09 08:38:13 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989942239 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2989942239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.3943124035
Short name T898
Test name
Test status
Simulation time 28768700 ps
CPU time 53.3 seconds
Started Oct 09 08:35:26 PM UTC 24
Finished Oct 09 08:36:22 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943124035 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.3943124035
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.1351967214
Short name T896
Test name
Test status
Simulation time 72385700 ps
CPU time 35.41 seconds
Started Oct 09 08:35:27 PM UTC 24
Finished Oct 09 08:36:05 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1351967214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_rw_evict_all_en.1351967214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.3088162922
Short name T919
Test name
Test status
Simulation time 583939500 ps
CPU time 105.71 seconds
Started Oct 09 08:35:31 PM UTC 24
Finished Oct 09 08:37:19 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088162922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3088162922
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.3867586206
Short name T937
Test name
Test status
Simulation time 26194600 ps
CPU time 176.4 seconds
Started Oct 09 08:35:09 PM UTC 24
Finished Oct 09 08:38:09 PM UTC 24
Peak memory 289476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867586206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3867586206
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.15530792
Short name T901
Test name
Test status
Simulation time 179093100 ps
CPU time 23.1 seconds
Started Oct 09 08:36:04 PM UTC 24
Finished Oct 09 08:36:29 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15530792 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.15530792
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1259475069
Short name T899
Test name
Test status
Simulation time 14541200 ps
CPU time 18.76 seconds
Started Oct 09 08:36:03 PM UTC 24
Finished Oct 09 08:36:23 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259475069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1259475069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.2912546449
Short name T910
Test name
Test status
Simulation time 12738100 ps
CPU time 40.96 seconds
Started Oct 09 08:36:01 PM UTC 24
Finished Oct 09 08:36:43 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2912546449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_
ctrl_disable.2912546449
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.3757455916
Short name T1007
Test name
Test status
Simulation time 12682705000 ps
CPU time 302.82 seconds
Started Oct 09 08:35:36 PM UTC 24
Finished Oct 09 08:40:44 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757455916 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.3757455916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.1001070244
Short name T973
Test name
Test status
Simulation time 5366128500 ps
CPU time 244.33 seconds
Started Oct 09 08:35:38 PM UTC 24
Finished Oct 09 08:39:46 PM UTC 24
Peak memory 302284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001070244 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.1001070244
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3109027423
Short name T958
Test name
Test status
Simulation time 11540334800 ps
CPU time 194.3 seconds
Started Oct 09 08:35:40 PM UTC 24
Finished Oct 09 08:38:59 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3109027423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.flash_ctrl_intr_rd_slow_flash.3109027423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.3117506242
Short name T945
Test name
Test status
Simulation time 589838100 ps
CPU time 166.06 seconds
Started Oct 09 08:35:37 PM UTC 24
Finished Oct 09 08:38:26 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117506242 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.3117506242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.647345004
Short name T903
Test name
Test status
Simulation time 32379100 ps
CPU time 51.97 seconds
Started Oct 09 08:35:43 PM UTC 24
Finished Oct 09 08:36:36 PM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647345004 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.647345004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2337029573
Short name T902
Test name
Test status
Simulation time 34602800 ps
CPU time 49.26 seconds
Started Oct 09 08:35:45 PM UTC 24
Finished Oct 09 08:36:36 PM UTC 24
Peak memory 285852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2337029573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c
trl_rw_evict_all_en.2337029573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3517807850
Short name T920
Test name
Test status
Simulation time 1674708300 ps
CPU time 76.27 seconds
Started Oct 09 08:36:02 PM UTC 24
Finished Oct 09 08:37:20 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517807850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3517807850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.525876542
Short name T950
Test name
Test status
Simulation time 36633000 ps
CPU time 176.99 seconds
Started Oct 09 08:35:35 PM UTC 24
Finished Oct 09 08:38:35 PM UTC 24
Peak memory 289664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525876542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.525876542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.1079922440
Short name T915
Test name
Test status
Simulation time 135338200 ps
CPU time 15.84 seconds
Started Oct 09 08:36:38 PM UTC 24
Finished Oct 09 08:36:55 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079922440 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.1079922440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.1401088711
Short name T917
Test name
Test status
Simulation time 25024200 ps
CPU time 28.47 seconds
Started Oct 09 08:36:38 PM UTC 24
Finished Oct 09 08:37:08 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401088711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1401088711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.3955726961
Short name T359
Test name
Test status
Simulation time 15839500 ps
CPU time 37.93 seconds
Started Oct 09 08:36:37 PM UTC 24
Finished Oct 09 08:37:16 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3955726961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_
ctrl_disable.3955726961
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.2324678996
Short name T959
Test name
Test status
Simulation time 19679661700 ps
CPU time 157.92 seconds
Started Oct 09 08:36:20 PM UTC 24
Finished Oct 09 08:39:01 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324678996 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.2324678996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.4269061740
Short name T981
Test name
Test status
Simulation time 5904163300 ps
CPU time 208.62 seconds
Started Oct 09 08:36:24 PM UTC 24
Finished Oct 09 08:39:56 PM UTC 24
Peak memory 302252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269061740 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.4269061740
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.123611962
Short name T955
Test name
Test status
Simulation time 5626117700 ps
CPU time 144.54 seconds
Started Oct 09 08:36:25 PM UTC 24
Finished Oct 09 08:38:52 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=123611962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 33.flash_ctrl_intr_rd_slow_flash.123611962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.1321819196
Short name T980
Test name
Test status
Simulation time 71271800 ps
CPU time 209.35 seconds
Started Oct 09 08:36:23 PM UTC 24
Finished Oct 09 08:39:56 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321819196 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.1321819196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2896977778
Short name T918
Test name
Test status
Simulation time 28236800 ps
CPU time 40.46 seconds
Started Oct 09 08:36:29 PM UTC 24
Finished Oct 09 08:37:12 PM UTC 24
Peak memory 287708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896977778 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.2896977778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.1556789737
Short name T925
Test name
Test status
Simulation time 27371700 ps
CPU time 49.85 seconds
Started Oct 09 08:36:37 PM UTC 24
Finished Oct 09 08:37:28 PM UTC 24
Peak memory 285852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1556789737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_rw_evict_all_en.1556789737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3608446446
Short name T995
Test name
Test status
Simulation time 130962800 ps
CPU time 255.62 seconds
Started Oct 09 08:36:06 PM UTC 24
Finished Oct 09 08:40:25 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608446446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3608446446
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.300095721
Short name T924
Test name
Test status
Simulation time 60054200 ps
CPU time 29.52 seconds
Started Oct 09 08:36:56 PM UTC 24
Finished Oct 09 08:37:27 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300095721 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.300095721
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.1829302788
Short name T921
Test name
Test status
Simulation time 15542700 ps
CPU time 25.91 seconds
Started Oct 09 08:36:56 PM UTC 24
Finished Oct 09 08:37:23 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829302788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1829302788
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.3064083449
Short name T922
Test name
Test status
Simulation time 26556600 ps
CPU time 31.07 seconds
Started Oct 09 08:36:52 PM UTC 24
Finished Oct 09 08:37:25 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3064083449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_
ctrl_disable.3064083449
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.916023208
Short name T926
Test name
Test status
Simulation time 2107083200 ps
CPU time 45.53 seconds
Started Oct 09 08:36:41 PM UTC 24
Finished Oct 09 08:37:28 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916023208 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.916023208
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2760630050
Short name T998
Test name
Test status
Simulation time 6620717900 ps
CPU time 220.08 seconds
Started Oct 09 08:36:45 PM UTC 24
Finished Oct 09 08:40:28 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760630050 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2760630050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3639014433
Short name T976
Test name
Test status
Simulation time 6018112700 ps
CPU time 184.96 seconds
Started Oct 09 08:36:46 PM UTC 24
Finished Oct 09 08:39:54 PM UTC 24
Peak memory 303932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3639014433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.flash_ctrl_intr_rd_slow_flash.3639014433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.2110114881
Short name T923
Test name
Test status
Simulation time 27897500 ps
CPU time 37.52 seconds
Started Oct 09 08:36:46 PM UTC 24
Finished Oct 09 08:37:25 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110114881 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.2110114881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.457733273
Short name T410
Test name
Test status
Simulation time 64302700 ps
CPU time 49.13 seconds
Started Oct 09 08:36:51 PM UTC 24
Finished Oct 09 08:37:42 PM UTC 24
Peak memory 279408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=457733273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ct
rl_rw_evict_all_en.457733273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1204393479
Short name T938
Test name
Test status
Simulation time 6135429100 ps
CPU time 74.04 seconds
Started Oct 09 08:36:53 PM UTC 24
Finished Oct 09 08:38:09 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204393479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1204393479
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.2605916927
Short name T939
Test name
Test status
Simulation time 25149500 ps
CPU time 87.67 seconds
Started Oct 09 08:36:40 PM UTC 24
Finished Oct 09 08:38:10 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605916927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2605916927
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.55861064
Short name T934
Test name
Test status
Simulation time 103618300 ps
CPU time 30.32 seconds
Started Oct 09 08:37:27 PM UTC 24
Finished Oct 09 08:37:59 PM UTC 24
Peak memory 269300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55861064 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.55861064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.4096977680
Short name T932
Test name
Test status
Simulation time 61911600 ps
CPU time 23.67 seconds
Started Oct 09 08:37:26 PM UTC 24
Finished Oct 09 08:37:51 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096977680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.4096977680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.929983235
Short name T936
Test name
Test status
Simulation time 20280400 ps
CPU time 39.04 seconds
Started Oct 09 08:37:24 PM UTC 24
Finished Oct 09 08:38:05 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=929983235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_disable.929983235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.3313316874
Short name T965
Test name
Test status
Simulation time 15793707800 ps
CPU time 135.86 seconds
Started Oct 09 08:37:06 PM UTC 24
Finished Oct 09 08:39:24 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313316874 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.3313316874
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.1379346504
Short name T978
Test name
Test status
Simulation time 1180970800 ps
CPU time 159.92 seconds
Started Oct 09 08:37:12 PM UTC 24
Finished Oct 09 08:39:55 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379346504 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.1379346504
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2635234222
Short name T997
Test name
Test status
Simulation time 23112662000 ps
CPU time 187.89 seconds
Started Oct 09 08:37:17 PM UTC 24
Finished Oct 09 08:40:28 PM UTC 24
Peak memory 303944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2635234222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.flash_ctrl_intr_rd_slow_flash.2635234222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.1442206511
Short name T983
Test name
Test status
Simulation time 42287900 ps
CPU time 167.56 seconds
Started Oct 09 08:37:09 PM UTC 24
Finished Oct 09 08:39:59 PM UTC 24
Peak memory 275616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442206511 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.1442206511
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3235179161
Short name T404
Test name
Test status
Simulation time 68899000 ps
CPU time 45.8 seconds
Started Oct 09 08:37:19 PM UTC 24
Finished Oct 09 08:38:07 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235179161 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.3235179161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.2145416444
Short name T935
Test name
Test status
Simulation time 50524600 ps
CPU time 39.01 seconds
Started Oct 09 08:37:22 PM UTC 24
Finished Oct 09 08:38:02 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2145416444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_rw_evict_all_en.2145416444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.4234699831
Short name T957
Test name
Test status
Simulation time 475183900 ps
CPU time 87.98 seconds
Started Oct 09 08:37:26 PM UTC 24
Finished Oct 09 08:38:56 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234699831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.4234699831
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.2891263647
Short name T968
Test name
Test status
Simulation time 62657800 ps
CPU time 153.4 seconds
Started Oct 09 08:36:58 PM UTC 24
Finished Oct 09 08:39:34 PM UTC 24
Peak memory 287628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891263647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2891263647
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.505849381
Short name T949
Test name
Test status
Simulation time 25496200 ps
CPU time 28.42 seconds
Started Oct 09 08:38:00 PM UTC 24
Finished Oct 09 08:38:30 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505849381 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.505849381
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.331281391
Short name T947
Test name
Test status
Simulation time 25271400 ps
CPU time 31.6 seconds
Started Oct 09 08:37:55 PM UTC 24
Finished Oct 09 08:38:28 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331281391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.331281391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.3826402658
Short name T943
Test name
Test status
Simulation time 126922300 ps
CPU time 32.88 seconds
Started Oct 09 08:37:48 PM UTC 24
Finished Oct 09 08:38:22 PM UTC 24
Peak memory 285752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3826402658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_
ctrl_disable.3826402658
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.534259060
Short name T951
Test name
Test status
Simulation time 909130300 ps
CPU time 67.09 seconds
Started Oct 09 08:37:29 PM UTC 24
Finished Oct 09 08:38:39 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534259060 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.534259060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.720010713
Short name T1084
Test name
Test status
Simulation time 13915868100 ps
CPU time 344.66 seconds
Started Oct 09 08:37:35 PM UTC 24
Finished Oct 09 08:43:25 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=720010713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.flash_ctrl_intr_rd_slow_flash.720010713
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.2560179709
Short name T994
Test name
Test status
Simulation time 72037600 ps
CPU time 169 seconds
Started Oct 09 08:37:29 PM UTC 24
Finished Oct 09 08:40:21 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560179709 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.2560179709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.723176900
Short name T942
Test name
Test status
Simulation time 44135400 ps
CPU time 36.6 seconds
Started Oct 09 08:37:39 PM UTC 24
Finished Oct 09 08:38:17 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723176900 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.723176900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.3269778479
Short name T946
Test name
Test status
Simulation time 80183400 ps
CPU time 43.01 seconds
Started Oct 09 08:37:43 PM UTC 24
Finished Oct 09 08:38:27 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3269778479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c
trl_rw_evict_all_en.3269778479
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.4001779648
Short name T960
Test name
Test status
Simulation time 1760167900 ps
CPU time 75.51 seconds
Started Oct 09 08:37:52 PM UTC 24
Finished Oct 09 08:39:10 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001779648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.4001779648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.2146518012
Short name T969
Test name
Test status
Simulation time 73283100 ps
CPU time 126 seconds
Started Oct 09 08:37:29 PM UTC 24
Finished Oct 09 08:39:38 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146518012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2146518012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1133788578
Short name T953
Test name
Test status
Simulation time 28841500 ps
CPU time 26.13 seconds
Started Oct 09 08:38:23 PM UTC 24
Finished Oct 09 08:38:50 PM UTC 24
Peak memory 269300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133788578 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.1133788578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.3094211142
Short name T954
Test name
Test status
Simulation time 26988800 ps
CPU time 32.47 seconds
Started Oct 09 08:38:18 PM UTC 24
Finished Oct 09 08:38:52 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094211142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3094211142
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.2629722715
Short name T360
Test name
Test status
Simulation time 15326500 ps
CPU time 36.26 seconds
Started Oct 09 08:38:14 PM UTC 24
Finished Oct 09 08:38:51 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2629722715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_
ctrl_disable.2629722715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1854073215
Short name T305
Test name
Test status
Simulation time 22664436800 ps
CPU time 142.86 seconds
Started Oct 09 08:38:06 PM UTC 24
Finished Oct 09 08:40:31 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854073215 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.1854073215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.2450567438
Short name T324
Test name
Test status
Simulation time 4795782900 ps
CPU time 197.76 seconds
Started Oct 09 08:38:10 PM UTC 24
Finished Oct 09 08:41:31 PM UTC 24
Peak memory 306088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450567438 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.2450567438
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2520375442
Short name T1037
Test name
Test status
Simulation time 8916805300 ps
CPU time 213.67 seconds
Started Oct 09 08:38:10 PM UTC 24
Finished Oct 09 08:41:47 PM UTC 24
Peak memory 301864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2520375442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.flash_ctrl_intr_rd_slow_flash.2520375442
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.3652667752
Short name T1024
Test name
Test status
Simulation time 163004900 ps
CPU time 188.02 seconds
Started Oct 09 08:38:08 PM UTC 24
Finished Oct 09 08:41:19 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652667752 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.3652667752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.2685129770
Short name T956
Test name
Test status
Simulation time 70461800 ps
CPU time 42.7 seconds
Started Oct 09 08:38:11 PM UTC 24
Finished Oct 09 08:38:56 PM UTC 24
Peak memory 287700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685129770 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.2685129770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.3141867458
Short name T952
Test name
Test status
Simulation time 28512900 ps
CPU time 37.52 seconds
Started Oct 09 08:38:11 PM UTC 24
Finished Oct 09 08:38:50 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3141867458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c
trl_rw_evict_all_en.3141867458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.475249468
Short name T984
Test name
Test status
Simulation time 13482020800 ps
CPU time 101.11 seconds
Started Oct 09 08:38:18 PM UTC 24
Finished Oct 09 08:40:01 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475249468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.475249468
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.1367332460
Short name T989
Test name
Test status
Simulation time 53442100 ps
CPU time 124.38 seconds
Started Oct 09 08:38:03 PM UTC 24
Finished Oct 09 08:40:09 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367332460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1367332460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3062711364
Short name T963
Test name
Test status
Simulation time 61452800 ps
CPU time 22.18 seconds
Started Oct 09 08:38:52 PM UTC 24
Finished Oct 09 08:39:16 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062711364 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.3062711364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2933244988
Short name T966
Test name
Test status
Simulation time 15249700 ps
CPU time 32.24 seconds
Started Oct 09 08:38:51 PM UTC 24
Finished Oct 09 08:39:25 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933244988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2933244988
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.3125492864
Short name T964
Test name
Test status
Simulation time 15856000 ps
CPU time 40.89 seconds
Started Oct 09 08:38:40 PM UTC 24
Finished Oct 09 08:39:23 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3125492864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_
ctrl_disable.3125492864
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.2828774641
Short name T967
Test name
Test status
Simulation time 1599000100 ps
CPU time 58.77 seconds
Started Oct 09 08:38:27 PM UTC 24
Finished Oct 09 08:39:28 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828774641 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.2828774641
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.303350239
Short name T1019
Test name
Test status
Simulation time 1156788200 ps
CPU time 157.83 seconds
Started Oct 09 08:38:29 PM UTC 24
Finished Oct 09 08:41:10 PM UTC 24
Peak memory 306088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303350239 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.303350239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.824142048
Short name T1100
Test name
Test status
Simulation time 31972312000 ps
CPU time 324.5 seconds
Started Oct 09 08:38:31 PM UTC 24
Finished Oct 09 08:44:00 PM UTC 24
Peak memory 301860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=824142048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 38.flash_ctrl_intr_rd_slow_flash.824142048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.1789800434
Short name T1026
Test name
Test status
Simulation time 164417000 ps
CPU time 168.33 seconds
Started Oct 09 08:38:28 PM UTC 24
Finished Oct 09 08:41:20 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789800434 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.1789800434
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.1543989923
Short name T962
Test name
Test status
Simulation time 67419900 ps
CPU time 41.31 seconds
Started Oct 09 08:38:32 PM UTC 24
Finished Oct 09 08:39:14 PM UTC 24
Peak memory 283772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543989923 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.1543989923
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.891616456
Short name T412
Test name
Test status
Simulation time 31699500 ps
CPU time 62.21 seconds
Started Oct 09 08:38:36 PM UTC 24
Finished Oct 09 08:39:40 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=891616456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ct
rl_rw_evict_all_en.891616456
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.3079768131
Short name T1008
Test name
Test status
Simulation time 6781167800 ps
CPU time 111.64 seconds
Started Oct 09 08:38:51 PM UTC 24
Finished Oct 09 08:40:46 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079768131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3079768131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.3177699530
Short name T1023
Test name
Test status
Simulation time 27783700 ps
CPU time 166.72 seconds
Started Oct 09 08:38:25 PM UTC 24
Finished Oct 09 08:41:15 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177699530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3177699530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.3677775036
Short name T972
Test name
Test status
Simulation time 149776400 ps
CPU time 24.52 seconds
Started Oct 09 08:39:17 PM UTC 24
Finished Oct 09 08:39:43 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677775036 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.3677775036
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.3267942992
Short name T971
Test name
Test status
Simulation time 51520800 ps
CPU time 25.67 seconds
Started Oct 09 08:39:16 PM UTC 24
Finished Oct 09 08:39:43 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267942992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3267942992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.4268252127
Short name T979
Test name
Test status
Simulation time 59612200 ps
CPU time 43.32 seconds
Started Oct 09 08:39:10 PM UTC 24
Finished Oct 09 08:39:56 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4268252127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_
ctrl_disable.4268252127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.2422427802
Short name T974
Test name
Test status
Simulation time 1236502600 ps
CPU time 51.12 seconds
Started Oct 09 08:38:54 PM UTC 24
Finished Oct 09 08:39:46 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422427802 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.2422427802
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.1831928516
Short name T1092
Test name
Test status
Simulation time 6227552000 ps
CPU time 272.33 seconds
Started Oct 09 08:38:57 PM UTC 24
Finished Oct 09 08:43:34 PM UTC 24
Peak memory 302252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831928516 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.1831928516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3628329976
Short name T1128
Test name
Test status
Simulation time 171418782500 ps
CPU time 424.07 seconds
Started Oct 09 08:38:59 PM UTC 24
Finished Oct 09 08:46:09 PM UTC 24
Peak memory 302020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3628329976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.flash_ctrl_intr_rd_slow_flash.3628329976
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.1893345168
Short name T1047
Test name
Test status
Simulation time 83302300 ps
CPU time 182.67 seconds
Started Oct 09 08:38:57 PM UTC 24
Finished Oct 09 08:42:03 PM UTC 24
Peak memory 271604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893345168 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.1893345168
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.1307778484
Short name T970
Test name
Test status
Simulation time 43539200 ps
CPU time 39.33 seconds
Started Oct 09 08:39:01 PM UTC 24
Finished Oct 09 08:39:42 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307778484 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.1307778484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.4224451554
Short name T977
Test name
Test status
Simulation time 72453900 ps
CPU time 46.82 seconds
Started Oct 09 08:39:06 PM UTC 24
Finished Oct 09 08:39:55 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4224451554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c
trl_rw_evict_all_en.4224451554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.1021618866
Short name T1003
Test name
Test status
Simulation time 2458723100 ps
CPU time 79.18 seconds
Started Oct 09 08:39:14 PM UTC 24
Finished Oct 09 08:40:35 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021618866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1021618866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.3740145026
Short name T1001
Test name
Test status
Simulation time 31310500 ps
CPU time 94.44 seconds
Started Oct 09 08:38:53 PM UTC 24
Finished Oct 09 08:40:29 PM UTC 24
Peak memory 287492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740145026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3740145026
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2688037956
Short name T479
Test name
Test status
Simulation time 51084200 ps
CPU time 24.55 seconds
Started Oct 09 07:48:21 PM UTC 24
Finished Oct 09 07:48:47 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688037956 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2688037956
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.2348950655
Short name T477
Test name
Test status
Simulation time 35903900 ps
CPU time 24.41 seconds
Started Oct 09 07:48:08 PM UTC 24
Finished Oct 09 07:48:33 PM UTC 24
Peak memory 275100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348950655 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.2348950655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2609836934
Short name T102
Test name
Test status
Simulation time 28342000 ps
CPU time 26.46 seconds
Started Oct 09 07:47:42 PM UTC 24
Finished Oct 09 07:48:10 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609836934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2609836934
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.2930166626
Short name T481
Test name
Test status
Simulation time 3052283300 ps
CPU time 215.85 seconds
Started Oct 09 07:45:45 PM UTC 24
Finished Oct 09 07:49:24 PM UTC 24
Peak memory 289796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2930166626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.flash_ctrl_derr_detect.2930166626
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2490817832
Short name T100
Test name
Test status
Simulation time 10707700 ps
CPU time 44.5 seconds
Started Oct 09 07:47:35 PM UTC 24
Finished Oct 09 07:48:21 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2490817832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_disable.2490817832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1197263202
Short name T522
Test name
Test status
Simulation time 4165977500 ps
CPU time 900.28 seconds
Started Oct 09 07:43:29 PM UTC 24
Finished Oct 09 07:58:40 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197263202 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1197263202
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.392958890
Short name T527
Test name
Test status
Simulation time 1364922900 ps
CPU time 943.1 seconds
Started Oct 09 07:44:08 PM UTC 24
Finished Oct 09 08:00:02 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392958890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.392958890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1965970052
Short name T74
Test name
Test status
Simulation time 382499500 ps
CPU time 49.78 seconds
Started Oct 09 07:43:46 PM UTC 24
Finished Oct 09 07:44:38 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19
65970052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc
h_code.1965970052
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.197079716
Short name T415
Test name
Test status
Simulation time 326332900 ps
CPU time 60.18 seconds
Started Oct 09 07:47:48 PM UTC 24
Finished Oct 09 07:48:50 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970797
16 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fs
_sup.197079716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.4227202607
Short name T854
Test name
Test status
Simulation time 181603300700 ps
CPU time 2980.67 seconds
Started Oct 09 07:43:49 PM UTC 24
Finished Oct 09 08:34:05 PM UTC 24
Peak memory 276064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227202607 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.4227202607
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3386506143
Short name T200
Test name
Test status
Simulation time 587007082100 ps
CPU time 3076.21 seconds
Started Oct 09 07:43:34 PM UTC 24
Finished Oct 09 08:35:25 PM UTC 24
Peak memory 278048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386506143 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3386506143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.4104443153
Short name T457
Test name
Test status
Simulation time 40009800 ps
CPU time 35.63 seconds
Started Oct 09 07:43:26 PM UTC 24
Finished Oct 09 07:44:04 PM UTC 24
Peak memory 273148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104443153 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.4104443153
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1041880081
Short name T268
Test name
Test status
Simulation time 10019636600 ps
CPU time 89.14 seconds
Started Oct 09 07:48:20 PM UTC 24
Finished Oct 09 07:49:51 PM UTC 24
Peak memory 289772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1041880081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1041880081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3240789297
Short name T179
Test name
Test status
Simulation time 40125556500 ps
CPU time 817.5 seconds
Started Oct 09 07:43:30 PM UTC 24
Finished Oct 09 07:57:17 PM UTC 24
Peak memory 275052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240789297
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.3240789297
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1060426866
Short name T470
Test name
Test status
Simulation time 25188972700 ps
CPU time 249.11 seconds
Started Oct 09 07:43:28 PM UTC 24
Finished Oct 09 07:47:41 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060426866 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.1060426866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.4195090745
Short name T504
Test name
Test status
Simulation time 56972849100 ps
CPU time 533.52 seconds
Started Oct 09 07:45:57 PM UTC 24
Finished Oct 09 07:54:58 PM UTC 24
Peak memory 341008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4195090745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr
ity.4195090745
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.258916458
Short name T43
Test name
Test status
Simulation time 1551024400 ps
CPU time 135.9 seconds
Started Oct 09 07:46:07 PM UTC 24
Finished Oct 09 07:48:26 PM UTC 24
Peak memory 306108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258916458 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.258916458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1200652850
Short name T307
Test name
Test status
Simulation time 36165713900 ps
CPU time 288.11 seconds
Started Oct 09 07:46:29 PM UTC 24
Finished Oct 09 07:51:22 PM UTC 24
Peak memory 305984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1200652850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_intr_rd_slow_flash.1200652850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3497921423
Short name T469
Test name
Test status
Simulation time 6824286200 ps
CPU time 74.24 seconds
Started Oct 09 07:46:24 PM UTC 24
Finished Oct 09 07:47:40 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497921423 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.3497921423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3033698285
Short name T484
Test name
Test status
Simulation time 74905866000 ps
CPU time 218.42 seconds
Started Oct 09 07:46:33 PM UTC 24
Finished Oct 09 07:50:15 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033698285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3033698285
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1698263433
Short name T155
Test name
Test status
Simulation time 6213740600 ps
CPU time 77.27 seconds
Started Oct 09 07:44:17 PM UTC 24
Finished Oct 09 07:45:36 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698263433 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1698263433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.612016155
Short name T270
Test name
Test status
Simulation time 29550100 ps
CPU time 21.61 seconds
Started Oct 09 07:48:11 PM UTC 24
Finished Oct 09 07:48:34 PM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=612016155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_lcmgr_intg.612016155
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3191096683
Short name T79
Test name
Test status
Simulation time 5039948100 ps
CPU time 129.22 seconds
Started Oct 09 07:44:21 PM UTC 24
Finished Oct 09 07:46:33 PM UTC 24
Peak memory 271128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191096683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3191096683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4091097359
Short name T88
Test name
Test status
Simulation time 49295307100 ps
CPU time 971.06 seconds
Started Oct 09 07:43:34 PM UTC 24
Finished Oct 09 07:59:57 PM UTC 24
Peak memory 283328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4091097359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.4091097359
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1521883169
Short name T91
Test name
Test status
Simulation time 68973600 ps
CPU time 174 seconds
Started Oct 09 07:43:32 PM UTC 24
Finished Oct 09 07:46:29 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521883169 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1521883169
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2816576369
Short name T478
Test name
Test status
Simulation time 15921008300 ps
CPU time 159.73 seconds
Started Oct 09 07:45:53 PM UTC 24
Finished Oct 09 07:48:35 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2816576369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_oversize_error.2816576369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3115003328
Short name T488
Test name
Test status
Simulation time 751832800 ps
CPU time 474.99 seconds
Started Oct 09 07:43:27 PM UTC 24
Finished Oct 09 07:51:29 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115003328 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3115003328
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.481768419
Short name T475
Test name
Test status
Simulation time 26213400 ps
CPU time 16.36 seconds
Started Oct 09 07:47:49 PM UTC 24
Finished Oct 09 07:48:07 PM UTC 24
Peak memory 273492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=481768419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.481768419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3987670750
Short name T466
Test name
Test status
Simulation time 159414600 ps
CPU time 23.5 seconds
Started Oct 09 07:46:35 PM UTC 24
Finished Oct 09 07:46:59 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987670750 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.3987670750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.941102080
Short name T482
Test name
Test status
Simulation time 143213500 ps
CPU time 372.85 seconds
Started Oct 09 07:43:22 PM UTC 24
Finished Oct 09 07:49:40 PM UTC 24
Peak memory 291784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941102080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.941102080
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3520790849
Short name T220
Test name
Test status
Simulation time 1459491600 ps
CPU time 146.21 seconds
Started Oct 09 07:43:27 PM UTC 24
Finished Oct 09 07:45:56 PM UTC 24
Peak memory 273280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520790849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3520790849
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.1634644600
Short name T464
Test name
Test status
Simulation time 18744900 ps
CPU time 44.11 seconds
Started Oct 09 07:45:37 PM UTC 24
Finished Oct 09 07:46:23 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1634644600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_derr.1634644600
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1623287992
Short name T463
Test name
Test status
Simulation time 85249100 ps
CPU time 40.01 seconds
Started Oct 09 07:45:02 PM UTC 24
Finished Oct 09 07:45:43 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623287992 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.1623287992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1444172922
Short name T476
Test name
Test status
Simulation time 4841124900 ps
CPU time 150.94 seconds
Started Oct 09 07:45:38 PM UTC 24
Finished Oct 09 07:48:12 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444172922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1444172922
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1512321557
Short name T471
Test name
Test status
Simulation time 1617722700 ps
CPU time 146.09 seconds
Started Oct 09 07:45:12 PM UTC 24
Finished Oct 09 07:47:41 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1512321557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_ro_serr.1512321557
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2865216850
Short name T197
Test name
Test status
Simulation time 6368559200 ps
CPU time 228.74 seconds
Started Oct 09 07:45:45 PM UTC 24
Finished Oct 09 07:49:37 PM UTC 24
Peak memory 297992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2865216850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_rw_derr.2865216850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.4046669422
Short name T399
Test name
Test status
Simulation time 112127000 ps
CPU time 51.47 seconds
Started Oct 09 07:46:55 PM UTC 24
Finished Oct 09 07:47:49 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046669422 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.4046669422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.797158430
Short name T474
Test name
Test status
Simulation time 92524100 ps
CPU time 49.93 seconds
Started Oct 09 07:47:00 PM UTC 24
Finished Oct 09 07:47:53 PM UTC 24
Peak memory 279480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=797158430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr
l_rw_evict_all_en.797158430
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.1034922622
Short name T394
Test name
Test status
Simulation time 1802125800 ps
CPU time 277.27 seconds
Started Oct 09 07:45:12 PM UTC 24
Finished Oct 09 07:49:54 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1034922622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.1034922622
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2457377875
Short name T135
Test name
Test status
Simulation time 5525817400 ps
CPU time 6046.47 seconds
Started Oct 09 07:47:36 PM UTC 24
Finished Oct 09 09:29:25 PM UTC 24
Peak memory 312156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457377875 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2457377875
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.452378731
Short name T372
Test name
Test status
Simulation time 8213393500 ps
CPU time 74.61 seconds
Started Oct 09 07:47:41 PM UTC 24
Finished Oct 09 07:48:57 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452378731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.452378731
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.443822101
Short name T467
Test name
Test status
Simulation time 1604920800 ps
CPU time 112.23 seconds
Started Oct 09 07:45:24 PM UTC 24
Finished Oct 09 07:47:19 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443
822101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_serr
_address.443822101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.915076920
Short name T468
Test name
Test status
Simulation time 1602895100 ps
CPU time 129.91 seconds
Started Oct 09 07:45:21 PM UTC 24
Finished Oct 09 07:47:34 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91
5076920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser
r_counter.915076920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2808989378
Short name T381
Test name
Test status
Simulation time 29330200 ps
CPU time 133.49 seconds
Started Oct 09 07:43:04 PM UTC 24
Finished Oct 09 07:45:20 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808989378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2808989378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3809442728
Short name T456
Test name
Test status
Simulation time 32007900 ps
CPU time 39.59 seconds
Started Oct 09 07:43:04 PM UTC 24
Finished Oct 09 07:43:45 PM UTC 24
Peak memory 270980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809442728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3809442728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.878260839
Short name T613
Test name
Test status
Simulation time 436005400 ps
CPU time 1535.44 seconds
Started Oct 09 07:47:42 PM UTC 24
Finished Oct 09 08:13:35 PM UTC 24
Peak memory 295688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878260839 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.878260839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.708430134
Short name T459
Test name
Test status
Simulation time 22549300 ps
CPU time 50.72 seconds
Started Oct 09 07:43:23 PM UTC 24
Finished Oct 09 07:44:16 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708430134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.708430134
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1944717645
Short name T480
Test name
Test status
Simulation time 11047783800 ps
CPU time 263.75 seconds
Started Oct 09 07:44:37 PM UTC 24
Finished Oct 09 07:49:05 PM UTC 24
Peak memory 271364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1944717645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.1944717645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.3208148872
Short name T985
Test name
Test status
Simulation time 88436100 ps
CPU time 21.78 seconds
Started Oct 09 08:39:41 PM UTC 24
Finished Oct 09 08:40:04 PM UTC 24
Peak memory 275444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208148872 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.3208148872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.3200373203
Short name T982
Test name
Test status
Simulation time 15574200 ps
CPU time 18.03 seconds
Started Oct 09 08:39:39 PM UTC 24
Finished Oct 09 08:39:58 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200373203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3200373203
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.2812197270
Short name T987
Test name
Test status
Simulation time 94145600 ps
CPU time 37.06 seconds
Started Oct 09 08:39:28 PM UTC 24
Finished Oct 09 08:40:07 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2812197270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_
ctrl_disable.2812197270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.916474378
Short name T1002
Test name
Test status
Simulation time 1031934800 ps
CPU time 62.88 seconds
Started Oct 09 08:39:25 PM UTC 24
Finished Oct 09 08:40:30 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916474378 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.916474378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.961625453
Short name T1061
Test name
Test status
Simulation time 99789700 ps
CPU time 193 seconds
Started Oct 09 08:39:26 PM UTC 24
Finished Oct 09 08:42:43 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961625453 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.961625453
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2078922083
Short name T1020
Test name
Test status
Simulation time 2252201000 ps
CPU time 94.66 seconds
Started Oct 09 08:39:35 PM UTC 24
Finished Oct 09 08:41:12 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078922083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2078922083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.371446529
Short name T1018
Test name
Test status
Simulation time 43690400 ps
CPU time 103.3 seconds
Started Oct 09 08:39:23 PM UTC 24
Finished Oct 09 08:41:08 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371446529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.371446529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3515961444
Short name T990
Test name
Test status
Simulation time 88342900 ps
CPU time 16.7 seconds
Started Oct 09 08:39:55 PM UTC 24
Finished Oct 09 08:40:13 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515961444 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3515961444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.1502822391
Short name T988
Test name
Test status
Simulation time 56358900 ps
CPU time 19.2 seconds
Started Oct 09 08:39:49 PM UTC 24
Finished Oct 09 08:40:09 PM UTC 24
Peak memory 284768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502822391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1502822391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.379359816
Short name T991
Test name
Test status
Simulation time 106752700 ps
CPU time 26.82 seconds
Started Oct 09 08:39:47 PM UTC 24
Finished Oct 09 08:40:16 PM UTC 24
Peak memory 285940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=379359816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_c
trl_disable.379359816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.995015581
Short name T1006
Test name
Test status
Simulation time 5391774900 ps
CPU time 50.9 seconds
Started Oct 09 08:39:44 PM UTC 24
Finished Oct 09 08:40:37 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995015581 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.995015581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.4177624368
Short name T1055
Test name
Test status
Simulation time 85408800 ps
CPU time 162.14 seconds
Started Oct 09 08:39:44 PM UTC 24
Finished Oct 09 08:42:29 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177624368 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.4177624368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.580326640
Short name T1028
Test name
Test status
Simulation time 3362488700 ps
CPU time 96.08 seconds
Started Oct 09 08:39:47 PM UTC 24
Finished Oct 09 08:41:26 PM UTC 24
Peak memory 271056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580326640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.580326640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2418057162
Short name T1054
Test name
Test status
Simulation time 28516400 ps
CPU time 162.43 seconds
Started Oct 09 08:39:43 PM UTC 24
Finished Oct 09 08:42:28 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418057162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2418057162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.451826411
Short name T992
Test name
Test status
Simulation time 147397400 ps
CPU time 17.23 seconds
Started Oct 09 08:40:01 PM UTC 24
Finished Oct 09 08:40:19 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451826411 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.451826411
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.592933966
Short name T993
Test name
Test status
Simulation time 51056200 ps
CPU time 19.78 seconds
Started Oct 09 08:39:59 PM UTC 24
Finished Oct 09 08:40:21 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592933966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.592933966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.1353199371
Short name T1005
Test name
Test status
Simulation time 19775800 ps
CPU time 37.61 seconds
Started Oct 09 08:39:57 PM UTC 24
Finished Oct 09 08:40:36 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1353199371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_
ctrl_disable.1353199371
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2034184369
Short name T1025
Test name
Test status
Simulation time 34043131500 ps
CPU time 80.33 seconds
Started Oct 09 08:39:57 PM UTC 24
Finished Oct 09 08:41:19 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034184369 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.2034184369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.3920228110
Short name T1072
Test name
Test status
Simulation time 40829200 ps
CPU time 181.1 seconds
Started Oct 09 08:39:57 PM UTC 24
Finished Oct 09 08:43:01 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920228110 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.3920228110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.2741604877
Short name T371
Test name
Test status
Simulation time 4384013100 ps
CPU time 98.08 seconds
Started Oct 09 08:39:57 PM UTC 24
Finished Oct 09 08:41:38 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741604877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2741604877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.2733611645
Short name T1065
Test name
Test status
Simulation time 20119400 ps
CPU time 168.61 seconds
Started Oct 09 08:39:56 PM UTC 24
Finished Oct 09 08:42:47 PM UTC 24
Peak memory 279232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733611645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2733611645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2767250566
Short name T1000
Test name
Test status
Simulation time 65498300 ps
CPU time 16.74 seconds
Started Oct 09 08:40:10 PM UTC 24
Finished Oct 09 08:40:28 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767250566 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.2767250566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3922914008
Short name T1004
Test name
Test status
Simulation time 23942400 ps
CPU time 24.15 seconds
Started Oct 09 08:40:10 PM UTC 24
Finished Oct 09 08:40:36 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922914008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3922914008
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.2422652218
Short name T303
Test name
Test status
Simulation time 3045158100 ps
CPU time 196.05 seconds
Started Oct 09 08:40:05 PM UTC 24
Finished Oct 09 08:43:24 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422652218 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.2422652218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.3693895179
Short name T1078
Test name
Test status
Simulation time 137091600 ps
CPU time 181.95 seconds
Started Oct 09 08:40:05 PM UTC 24
Finished Oct 09 08:43:10 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693895179 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.3693895179
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.890558041
Short name T1033
Test name
Test status
Simulation time 2249801900 ps
CPU time 80.95 seconds
Started Oct 09 08:40:08 PM UTC 24
Finished Oct 09 08:41:31 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890558041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.890558041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2802938378
Short name T1114
Test name
Test status
Simulation time 26357600 ps
CPU time 312.42 seconds
Started Oct 09 08:40:02 PM UTC 24
Finished Oct 09 08:45:19 PM UTC 24
Peak memory 279500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802938378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2802938378
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1618657287
Short name T1009
Test name
Test status
Simulation time 33657400 ps
CPU time 18.6 seconds
Started Oct 09 08:40:27 PM UTC 24
Finished Oct 09 08:40:47 PM UTC 24
Peak memory 269316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618657287 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1618657287
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.2624067333
Short name T1012
Test name
Test status
Simulation time 22757600 ps
CPU time 31.11 seconds
Started Oct 09 08:40:26 PM UTC 24
Finished Oct 09 08:40:59 PM UTC 24
Peak memory 294916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624067333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2624067333
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2704888614
Short name T1011
Test name
Test status
Simulation time 21902400 ps
CPU time 29.96 seconds
Started Oct 09 08:40:21 PM UTC 24
Finished Oct 09 08:40:52 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2704888614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_
ctrl_disable.2704888614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.2210211480
Short name T1057
Test name
Test status
Simulation time 2315176900 ps
CPU time 131.17 seconds
Started Oct 09 08:40:17 PM UTC 24
Finished Oct 09 08:42:30 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210211480 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.2210211480
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.1140101396
Short name T1077
Test name
Test status
Simulation time 176763900 ps
CPU time 165.19 seconds
Started Oct 09 08:40:20 PM UTC 24
Finished Oct 09 08:43:08 PM UTC 24
Peak memory 271456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140101396 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.1140101396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.4055667478
Short name T1034
Test name
Test status
Simulation time 1619463300 ps
CPU time 68.47 seconds
Started Oct 09 08:40:22 PM UTC 24
Finished Oct 09 08:41:32 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055667478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.4055667478
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.2540379135
Short name T1050
Test name
Test status
Simulation time 31109900 ps
CPU time 124.12 seconds
Started Oct 09 08:40:14 PM UTC 24
Finished Oct 09 08:42:20 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540379135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2540379135
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.54910050
Short name T1014
Test name
Test status
Simulation time 28934000 ps
CPU time 24.64 seconds
Started Oct 09 08:40:36 PM UTC 24
Finished Oct 09 08:41:02 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54910050 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.54910050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.1252136766
Short name T1015
Test name
Test status
Simulation time 47731500 ps
CPU time 30.31 seconds
Started Oct 09 08:40:32 PM UTC 24
Finished Oct 09 08:41:04 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252136766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1252136766
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2566443916
Short name T1013
Test name
Test status
Simulation time 27025600 ps
CPU time 28.59 seconds
Started Oct 09 08:40:30 PM UTC 24
Finished Oct 09 08:41:00 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2566443916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_
ctrl_disable.2566443916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.4292565873
Short name T1082
Test name
Test status
Simulation time 8552241300 ps
CPU time 160.97 seconds
Started Oct 09 08:40:30 PM UTC 24
Finished Oct 09 08:43:14 PM UTC 24
Peak memory 273108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292565873 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.4292565873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2028444487
Short name T1086
Test name
Test status
Simulation time 62013500 ps
CPU time 173.32 seconds
Started Oct 09 08:40:30 PM UTC 24
Finished Oct 09 08:43:26 PM UTC 24
Peak memory 275444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028444487 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.2028444487
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.629818786
Short name T1056
Test name
Test status
Simulation time 4122796800 ps
CPU time 116.19 seconds
Started Oct 09 08:40:31 PM UTC 24
Finished Oct 09 08:42:30 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629818786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.629818786
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1342653218
Short name T1080
Test name
Test status
Simulation time 96912900 ps
CPU time 158.1 seconds
Started Oct 09 08:40:30 PM UTC 24
Finished Oct 09 08:43:11 PM UTC 24
Peak memory 287420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342653218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1342653218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.1124064119
Short name T1017
Test name
Test status
Simulation time 106896700 ps
CPU time 17.43 seconds
Started Oct 09 08:40:48 PM UTC 24
Finished Oct 09 08:41:07 PM UTC 24
Peak memory 275460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124064119 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.1124064119
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.783158726
Short name T1021
Test name
Test status
Simulation time 44067100 ps
CPU time 23.81 seconds
Started Oct 09 08:40:47 PM UTC 24
Finished Oct 09 08:41:12 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783158726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.783158726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.1618863692
Short name T1027
Test name
Test status
Simulation time 56154400 ps
CPU time 39.2 seconds
Started Oct 09 08:40:43 PM UTC 24
Finished Oct 09 08:41:23 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1618863692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_
ctrl_disable.1618863692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.483793775
Short name T1069
Test name
Test status
Simulation time 9936385900 ps
CPU time 134.95 seconds
Started Oct 09 08:40:37 PM UTC 24
Finished Oct 09 08:42:55 PM UTC 24
Peak memory 273092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483793775 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.483793775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1953620251
Short name T1087
Test name
Test status
Simulation time 145185300 ps
CPU time 166.48 seconds
Started Oct 09 08:40:38 PM UTC 24
Finished Oct 09 08:43:27 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953620251 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.1953620251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3661110476
Short name T1046
Test name
Test status
Simulation time 1751229500 ps
CPU time 75.01 seconds
Started Oct 09 08:40:45 PM UTC 24
Finished Oct 09 08:42:03 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661110476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3661110476
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.122548704
Short name T1101
Test name
Test status
Simulation time 1807382500 ps
CPU time 214.08 seconds
Started Oct 09 08:40:36 PM UTC 24
Finished Oct 09 08:44:14 PM UTC 24
Peak memory 291712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122548704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.122548704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.2476941273
Short name T1029
Test name
Test status
Simulation time 56648100 ps
CPU time 18.23 seconds
Started Oct 09 08:41:06 PM UTC 24
Finished Oct 09 08:41:26 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476941273 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.2476941273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.4092473533
Short name T1030
Test name
Test status
Simulation time 25740900 ps
CPU time 21.01 seconds
Started Oct 09 08:41:05 PM UTC 24
Finished Oct 09 08:41:28 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092473533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4092473533
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.2885732278
Short name T1032
Test name
Test status
Simulation time 10897900 ps
CPU time 28.9 seconds
Started Oct 09 08:41:01 PM UTC 24
Finished Oct 09 08:41:31 PM UTC 24
Peak memory 285640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2885732278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_
ctrl_disable.2885732278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.2338570634
Short name T1040
Test name
Test status
Simulation time 2285093400 ps
CPU time 60.1 seconds
Started Oct 09 08:40:53 PM UTC 24
Finished Oct 09 08:41:55 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338570634 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.2338570634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3877427352
Short name T1097
Test name
Test status
Simulation time 269035400 ps
CPU time 160.57 seconds
Started Oct 09 08:41:00 PM UTC 24
Finished Oct 09 08:43:43 PM UTC 24
Peak memory 271264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877427352 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.3877427352
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.610189440
Short name T362
Test name
Test status
Simulation time 584550600 ps
CPU time 61.86 seconds
Started Oct 09 08:41:03 PM UTC 24
Finished Oct 09 08:42:07 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610189440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.610189440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3221793930
Short name T1059
Test name
Test status
Simulation time 109510100 ps
CPU time 102.32 seconds
Started Oct 09 08:40:49 PM UTC 24
Finished Oct 09 08:42:34 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221793930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3221793930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1831953803
Short name T1035
Test name
Test status
Simulation time 225770000 ps
CPU time 20.69 seconds
Started Oct 09 08:41:16 PM UTC 24
Finished Oct 09 08:41:38 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831953803 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1831953803
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.103578324
Short name T1036
Test name
Test status
Simulation time 58541800 ps
CPU time 22.54 seconds
Started Oct 09 08:41:15 PM UTC 24
Finished Oct 09 08:41:39 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103578324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.103578324
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.2919331212
Short name T1038
Test name
Test status
Simulation time 36345200 ps
CPU time 40.04 seconds
Started Oct 09 08:41:13 PM UTC 24
Finished Oct 09 08:41:54 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2919331212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_
ctrl_disable.2919331212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.3146286602
Short name T1090
Test name
Test status
Simulation time 6678105300 ps
CPU time 137.31 seconds
Started Oct 09 08:41:09 PM UTC 24
Finished Oct 09 08:43:30 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146286602 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.3146286602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.2781544299
Short name T1106
Test name
Test status
Simulation time 50931300 ps
CPU time 207.4 seconds
Started Oct 09 08:41:11 PM UTC 24
Finished Oct 09 08:44:42 PM UTC 24
Peak memory 271604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781544299 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.2781544299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.3141000460
Short name T1066
Test name
Test status
Simulation time 1840568700 ps
CPU time 91.66 seconds
Started Oct 09 08:41:14 PM UTC 24
Finished Oct 09 08:42:48 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141000460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3141000460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3790676139
Short name T1073
Test name
Test status
Simulation time 15723400 ps
CPU time 110.64 seconds
Started Oct 09 08:41:08 PM UTC 24
Finished Oct 09 08:43:02 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790676139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3790676139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.2029926076
Short name T1043
Test name
Test status
Simulation time 36338300 ps
CPU time 25.82 seconds
Started Oct 09 08:41:29 PM UTC 24
Finished Oct 09 08:41:56 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029926076 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.2029926076
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1548646621
Short name T1039
Test name
Test status
Simulation time 23484200 ps
CPU time 26.46 seconds
Started Oct 09 08:41:27 PM UTC 24
Finished Oct 09 08:41:55 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548646621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1548646621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1780807413
Short name T1041
Test name
Test status
Simulation time 11432100 ps
CPU time 29.64 seconds
Started Oct 09 08:41:25 PM UTC 24
Finished Oct 09 08:41:56 PM UTC 24
Peak memory 285944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1780807413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_
ctrl_disable.1780807413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.808648890
Short name T1031
Test name
Test status
Simulation time 8496129300 ps
CPU time 77.14 seconds
Started Oct 09 08:41:20 PM UTC 24
Finished Oct 09 08:42:39 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808648890 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.808648890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2950502268
Short name T1102
Test name
Test status
Simulation time 148163100 ps
CPU time 178.13 seconds
Started Oct 09 08:41:20 PM UTC 24
Finished Oct 09 08:44:22 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950502268 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.2950502268
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.3567253154
Short name T1060
Test name
Test status
Simulation time 342662500 ps
CPU time 66.58 seconds
Started Oct 09 08:41:27 PM UTC 24
Finished Oct 09 08:42:35 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567253154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3567253154
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2109785640
Short name T1063
Test name
Test status
Simulation time 223693700 ps
CPU time 82.63 seconds
Started Oct 09 08:41:20 PM UTC 24
Finished Oct 09 08:42:45 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109785640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2109785640
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2261397806
Short name T299
Test name
Test status
Simulation time 133198900 ps
CPU time 25.49 seconds
Started Oct 09 07:52:12 PM UTC 24
Finished Oct 09 07:52:39 PM UTC 24
Peak memory 269056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261397806 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2261397806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1909072127
Short name T103
Test name
Test status
Simulation time 47386000 ps
CPU time 27.89 seconds
Started Oct 09 07:51:47 PM UTC 24
Finished Oct 09 07:52:16 PM UTC 24
Peak memory 284868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909072127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1909072127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.2136538368
Short name T177
Test name
Test status
Simulation time 10568600 ps
CPU time 36.2 seconds
Started Oct 09 07:51:39 PM UTC 24
Finished Oct 09 07:52:16 PM UTC 24
Peak memory 285608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2136538368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c
trl_disable.2136538368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.56383385
Short name T1067
Test name
Test status
Simulation time 6106093600 ps
CPU time 3194.43 seconds
Started Oct 09 07:48:58 PM UTC 24
Finished Oct 09 08:42:48 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56383385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.56383385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2944497159
Short name T606
Test name
Test status
Simulation time 1345492100 ps
CPU time 1443.84 seconds
Started Oct 09 07:48:51 PM UTC 24
Finished Oct 09 08:13:12 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944497159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2944497159
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.298645546
Short name T64
Test name
Test status
Simulation time 824569600 ps
CPU time 44.38 seconds
Started Oct 09 07:48:48 PM UTC 24
Finished Oct 09 07:49:34 PM UTC 24
Peak memory 273348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
8645546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch
_code.298645546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1480281286
Short name T266
Test name
Test status
Simulation time 10040092800 ps
CPU time 54.02 seconds
Started Oct 09 07:52:08 PM UTC 24
Finished Oct 09 07:53:04 PM UTC 24
Peak memory 281436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1480281286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1480281286
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3949231268
Short name T497
Test name
Test status
Simulation time 15328300 ps
CPU time 24.41 seconds
Started Oct 09 07:52:08 PM UTC 24
Finished Oct 09 07:52:34 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3949231268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_hw_read_seed_err.3949231268
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3729238281
Short name T164
Test name
Test status
Simulation time 60125602800 ps
CPU time 893.7 seconds
Started Oct 09 07:48:35 PM UTC 24
Finished Oct 09 08:03:40 PM UTC 24
Peak memory 275052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729238281
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.3729238281
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1270510432
Short name T485
Test name
Test status
Simulation time 3621022700 ps
CPU time 117.17 seconds
Started Oct 09 07:48:31 PM UTC 24
Finished Oct 09 07:50:30 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270510432 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.1270510432
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.1162733696
Short name T329
Test name
Test status
Simulation time 927649600 ps
CPU time 186.96 seconds
Started Oct 09 07:50:13 PM UTC 24
Finished Oct 09 07:53:24 PM UTC 24
Peak memory 304048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162733696 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.1162733696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.22605293
Short name T499
Test name
Test status
Simulation time 5479566800 ps
CPU time 202.78 seconds
Started Oct 09 07:50:31 PM UTC 24
Finished Oct 09 07:53:57 PM UTC 24
Peak memory 304108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=22605293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.flash_ctrl_intr_rd_slow_flash.22605293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.3778800448
Short name T492
Test name
Test status
Simulation time 15388022900 ps
CPU time 103.85 seconds
Started Oct 09 07:50:17 PM UTC 24
Finished Oct 09 07:52:03 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778800448 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.3778800448
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.572957771
Short name T534
Test name
Test status
Simulation time 423266468600 ps
CPU time 576.26 seconds
Started Oct 09 07:50:48 PM UTC 24
Finished Oct 09 08:00:31 PM UTC 24
Peak memory 271296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572957771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.572957771
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.782052137
Short name T486
Test name
Test status
Simulation time 3129648100 ps
CPU time 97.83 seconds
Started Oct 09 07:49:06 PM UTC 24
Finished Oct 09 07:50:47 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782052137 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.782052137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1818676499
Short name T496
Test name
Test status
Simulation time 45295900 ps
CPU time 22.53 seconds
Started Oct 09 07:52:03 PM UTC 24
Finished Oct 09 07:52:27 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1818676499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_lcmgr_intg.1818676499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.195760451
Short name T87
Test name
Test status
Simulation time 89301411500 ps
CPU time 329.85 seconds
Started Oct 09 07:48:36 PM UTC 24
Finished Oct 09 07:54:10 PM UTC 24
Peak memory 283328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=195760451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_mp_regions.195760451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.63093161
Short name T174
Test name
Test status
Simulation time 76313800 ps
CPU time 277.28 seconds
Started Oct 09 07:48:35 PM UTC 24
Finished Oct 09 07:53:16 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63093161 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.63093161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.3367780912
Short name T519
Test name
Test status
Simulation time 75222300 ps
CPU time 591.64 seconds
Started Oct 09 07:48:27 PM UTC 24
Finished Oct 09 07:58:26 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367780912 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3367780912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.1615322534
Short name T503
Test name
Test status
Simulation time 2636236100 ps
CPU time 214 seconds
Started Oct 09 07:51:12 PM UTC 24
Finished Oct 09 07:54:50 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615322534 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.1615322534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1768248752
Short name T523
Test name
Test status
Simulation time 8269782400 ps
CPU time 625.03 seconds
Started Oct 09 07:48:22 PM UTC 24
Finished Oct 09 07:58:55 PM UTC 24
Peak memory 293572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768248752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1768248752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.3513370040
Short name T247
Test name
Test status
Simulation time 83045400 ps
CPU time 52.35 seconds
Started Oct 09 07:51:30 PM UTC 24
Finished Oct 09 07:52:24 PM UTC 24
Peak memory 287708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513370040 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.3513370040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3386728938
Short name T487
Test name
Test status
Simulation time 1906408000 ps
CPU time 95.83 seconds
Started Oct 09 07:49:34 PM UTC 24
Finished Oct 09 07:51:12 PM UTC 24
Peak memory 291960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3386728938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.3386728938
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.318582564
Short name T494
Test name
Test status
Simulation time 484793300 ps
CPU time 136.45 seconds
Started Oct 09 07:49:52 PM UTC 24
Finished Oct 09 07:52:11 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318582564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.318582564
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.2271459623
Short name T495
Test name
Test status
Simulation time 9859724800 ps
CPU time 162.75 seconds
Started Oct 09 07:49:38 PM UTC 24
Finished Oct 09 07:52:24 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2271459623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_ro_serr.2271459623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2445861321
Short name T501
Test name
Test status
Simulation time 1838845300 ps
CPU time 257.7 seconds
Started Oct 09 07:49:54 PM UTC 24
Finished Oct 09 07:54:16 PM UTC 24
Peak memory 297964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2445861321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_rw_derr.2445861321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1911680678
Short name T418
Test name
Test status
Simulation time 52065100 ps
CPU time 43.22 seconds
Started Oct 09 07:51:22 PM UTC 24
Finished Oct 09 07:52:07 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911680678 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.1911680678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.1178204484
Short name T493
Test name
Test status
Simulation time 41579400 ps
CPU time 36.47 seconds
Started Oct 09 07:51:29 PM UTC 24
Finished Oct 09 07:52:07 PM UTC 24
Peak memory 279480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1178204484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw_evict_all_en.1178204484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.3078081344
Short name T395
Test name
Test status
Simulation time 7972747900 ps
CPU time 271.72 seconds
Started Oct 09 07:49:41 PM UTC 24
Finished Oct 09 07:54:17 PM UTC 24
Peak memory 291892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3078081344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.3078081344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.2812312002
Short name T376
Test name
Test status
Simulation time 4534009900 ps
CPU time 81.19 seconds
Started Oct 09 07:51:46 PM UTC 24
Finished Oct 09 07:53:09 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812312002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2812312002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.975366025
Short name T490
Test name
Test status
Simulation time 231986100 ps
CPU time 200.66 seconds
Started Oct 09 07:48:21 PM UTC 24
Finished Oct 09 07:51:45 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975366025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.975366025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.1914455909
Short name T498
Test name
Test status
Simulation time 2052047900 ps
CPU time 204.19 seconds
Started Oct 09 07:49:25 PM UTC 24
Finished Oct 09 07:52:52 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1914455909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.1914455909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.1108809159
Short name T1045
Test name
Test status
Simulation time 28703500 ps
CPU time 28.13 seconds
Started Oct 09 08:41:32 PM UTC 24
Finished Oct 09 08:42:02 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108809159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1108809159
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.913839940
Short name T1108
Test name
Test status
Simulation time 39475200 ps
CPU time 191.91 seconds
Started Oct 09 08:41:32 PM UTC 24
Finished Oct 09 08:44:47 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913839940 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.913839940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.2714121994
Short name T1042
Test name
Test status
Simulation time 16747800 ps
CPU time 21.23 seconds
Started Oct 09 08:41:33 PM UTC 24
Finished Oct 09 08:41:56 PM UTC 24
Peak memory 284932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714121994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2714121994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.1242677548
Short name T1109
Test name
Test status
Simulation time 89374700 ps
CPU time 194.23 seconds
Started Oct 09 08:41:32 PM UTC 24
Finished Oct 09 08:44:50 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242677548 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.1242677548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.2957086555
Short name T1044
Test name
Test status
Simulation time 14041400 ps
CPU time 20.51 seconds
Started Oct 09 08:41:39 PM UTC 24
Finished Oct 09 08:42:00 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957086555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2957086555
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2850623635
Short name T1105
Test name
Test status
Simulation time 574412200 ps
CPU time 180.1 seconds
Started Oct 09 08:41:38 PM UTC 24
Finished Oct 09 08:44:42 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850623635 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.2850623635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.1030465581
Short name T1048
Test name
Test status
Simulation time 28775000 ps
CPU time 21.25 seconds
Started Oct 09 08:41:48 PM UTC 24
Finished Oct 09 08:42:10 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030465581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1030465581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.32474880
Short name T1107
Test name
Test status
Simulation time 37572500 ps
CPU time 183.89 seconds
Started Oct 09 08:41:40 PM UTC 24
Finished Oct 09 08:44:47 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32474880 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.32474880
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.1355878423
Short name T1053
Test name
Test status
Simulation time 43199700 ps
CPU time 27.42 seconds
Started Oct 09 08:41:55 PM UTC 24
Finished Oct 09 08:42:24 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355878423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1355878423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.4281212117
Short name T1103
Test name
Test status
Simulation time 302794400 ps
CPU time 160.28 seconds
Started Oct 09 08:41:55 PM UTC 24
Finished Oct 09 08:44:38 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281212117 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.4281212117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.1435378511
Short name T1051
Test name
Test status
Simulation time 41957800 ps
CPU time 25.86 seconds
Started Oct 09 08:41:56 PM UTC 24
Finished Oct 09 08:42:23 PM UTC 24
Peak memory 284868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435378511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1435378511
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.485730332
Short name T1113
Test name
Test status
Simulation time 284502200 ps
CPU time 196.84 seconds
Started Oct 09 08:41:56 PM UTC 24
Finished Oct 09 08:45:16 PM UTC 24
Peak memory 273456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485730332 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.485730332
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.3415701183
Short name T1049
Test name
Test status
Simulation time 152564100 ps
CPU time 18.2 seconds
Started Oct 09 08:41:57 PM UTC 24
Finished Oct 09 08:42:17 PM UTC 24
Peak memory 294916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415701183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3415701183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.2483453042
Short name T1104
Test name
Test status
Simulation time 69077100 ps
CPU time 159.14 seconds
Started Oct 09 08:41:57 PM UTC 24
Finished Oct 09 08:44:39 PM UTC 24
Peak memory 270940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483453042 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.2483453042
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.331156908
Short name T1052
Test name
Test status
Simulation time 14217100 ps
CPU time 19.63 seconds
Started Oct 09 08:42:03 PM UTC 24
Finished Oct 09 08:42:24 PM UTC 24
Peak memory 294984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331156908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.331156908
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.504655096
Short name T1110
Test name
Test status
Simulation time 139754500 ps
CPU time 174.28 seconds
Started Oct 09 08:42:02 PM UTC 24
Finished Oct 09 08:44:59 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504655096 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.504655096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.2703185435
Short name T1058
Test name
Test status
Simulation time 13449800 ps
CPU time 27.49 seconds
Started Oct 09 08:42:04 PM UTC 24
Finished Oct 09 08:42:33 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703185435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2703185435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.1592657661
Short name T1112
Test name
Test status
Simulation time 138507000 ps
CPU time 185.98 seconds
Started Oct 09 08:42:04 PM UTC 24
Finished Oct 09 08:45:13 PM UTC 24
Peak memory 271264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592657661 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.1592657661
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.2435105815
Short name T999
Test name
Test status
Simulation time 18708700 ps
CPU time 26.97 seconds
Started Oct 09 08:42:11 PM UTC 24
Finished Oct 09 08:42:40 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435105815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2435105815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2380870573
Short name T1116
Test name
Test status
Simulation time 148970800 ps
CPU time 193.29 seconds
Started Oct 09 08:42:08 PM UTC 24
Finished Oct 09 08:45:25 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380870573 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.2380870573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3328670595
Short name T514
Test name
Test status
Simulation time 48500500 ps
CPU time 25.64 seconds
Started Oct 09 07:56:33 PM UTC 24
Finished Oct 09 07:57:00 PM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328670595 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3328670595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.3508828889
Short name T511
Test name
Test status
Simulation time 16464000 ps
CPU time 22.54 seconds
Started Oct 09 07:56:15 PM UTC 24
Finished Oct 09 07:56:39 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508828889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3508828889
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.4097080617
Short name T178
Test name
Test status
Simulation time 10957300 ps
CPU time 37.05 seconds
Started Oct 09 07:56:09 PM UTC 24
Finished Oct 09 07:56:48 PM UTC 24
Peak memory 285680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4097080617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c
trl_disable.4097080617
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.2568090509
Short name T1125
Test name
Test status
Simulation time 5809744800 ps
CPU time 3140.92 seconds
Started Oct 09 07:53:04 PM UTC 24
Finished Oct 09 08:46:00 PM UTC 24
Peak memory 277924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568090509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2568090509
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.4021809088
Short name T593
Test name
Test status
Simulation time 1705418400 ps
CPU time 1103.26 seconds
Started Oct 09 07:52:53 PM UTC 24
Finished Oct 09 08:11:30 PM UTC 24
Peak memory 283536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021809088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.4021809088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.1959864729
Short name T65
Test name
Test status
Simulation time 844599400 ps
CPU time 38.16 seconds
Started Oct 09 07:52:45 PM UTC 24
Finished Oct 09 07:53:25 PM UTC 24
Peak memory 273152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19
59864729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc
h_code.1959864729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2588321948
Short name T517
Test name
Test status
Simulation time 10018094800 ps
CPU time 84.3 seconds
Started Oct 09 07:56:30 PM UTC 24
Finished Oct 09 07:57:56 PM UTC 24
Peak memory 295920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2588321948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2588321948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1058840257
Short name T265
Test name
Test status
Simulation time 15902900 ps
CPU time 25.1 seconds
Started Oct 09 07:56:25 PM UTC 24
Finished Oct 09 07:56:51 PM UTC 24
Peak memory 275240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1058840257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_hw_read_seed_err.1058840257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.794298482
Short name T387
Test name
Test status
Simulation time 110157152400 ps
CPU time 1054.66 seconds
Started Oct 09 07:52:28 PM UTC 24
Finished Oct 09 08:10:15 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794298482 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.794298482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1110894756
Short name T290
Test name
Test status
Simulation time 984457600 ps
CPU time 51.89 seconds
Started Oct 09 07:52:25 PM UTC 24
Finished Oct 09 07:53:18 PM UTC 24
Peak memory 273228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110894756 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.1110894756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.3979296257
Short name T44
Test name
Test status
Simulation time 1955518800 ps
CPU time 249.32 seconds
Started Oct 09 07:54:17 PM UTC 24
Finished Oct 09 07:58:30 PM UTC 24
Peak memory 302000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979296257 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.3979296257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1616172760
Short name T524
Test name
Test status
Simulation time 12352766500 ps
CPU time 284.71 seconds
Started Oct 09 07:54:45 PM UTC 24
Finished Oct 09 07:59:34 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1616172760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_intr_rd_slow_flash.1616172760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.3380086465
Short name T509
Test name
Test status
Simulation time 13134434600 ps
CPU time 127.92 seconds
Started Oct 09 07:54:18 PM UTC 24
Finished Oct 09 07:56:29 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380086465 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.3380086465
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.302442505
Short name T520
Test name
Test status
Simulation time 44171815700 ps
CPU time 217.11 seconds
Started Oct 09 07:54:51 PM UTC 24
Finished Oct 09 07:58:31 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302442505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.302442505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.2680355980
Short name T500
Test name
Test status
Simulation time 3603994700 ps
CPU time 61.66 seconds
Started Oct 09 07:53:10 PM UTC 24
Finished Oct 09 07:54:13 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680355980 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2680355980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3026054801
Short name T512
Test name
Test status
Simulation time 20420500 ps
CPU time 24.43 seconds
Started Oct 09 07:56:22 PM UTC 24
Finished Oct 09 07:56:47 PM UTC 24
Peak memory 271108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3026054801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_lcmgr_intg.3026054801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3407610083
Short name T136
Test name
Test status
Simulation time 54807077600 ps
CPU time 509.19 seconds
Started Oct 09 07:52:40 PM UTC 24
Finished Oct 09 08:01:16 PM UTC 24
Peak memory 283344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3407610083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_mp_regions.3407610083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.941135569
Short name T175
Test name
Test status
Simulation time 601089300 ps
CPU time 186.09 seconds
Started Oct 09 07:52:35 PM UTC 24
Finished Oct 09 07:55:44 PM UTC 24
Peak memory 275364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941135569 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.941135569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3550078923
Short name T552
Test name
Test status
Simulation time 97374600 ps
CPU time 714.69 seconds
Started Oct 09 07:52:25 PM UTC 24
Finished Oct 09 08:04:29 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550078923 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3550078923
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1543416806
Short name T313
Test name
Test status
Simulation time 34305000 ps
CPU time 27.42 seconds
Started Oct 09 07:54:59 PM UTC 24
Finished Oct 09 07:55:27 PM UTC 24
Peak memory 269132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543416806 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.1543416806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.1477407951
Short name T147
Test name
Test status
Simulation time 3213102700 ps
CPU time 972.35 seconds
Started Oct 09 07:52:18 PM UTC 24
Finished Oct 09 08:08:41 PM UTC 24
Peak memory 293636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477407951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1477407951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.2666708957
Short name T505
Test name
Test status
Simulation time 3340814000 ps
CPU time 114.94 seconds
Started Oct 09 07:53:19 PM UTC 24
Finished Oct 09 07:55:16 PM UTC 24
Peak memory 304160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2666708957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.2666708957
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3938657093
Short name T506
Test name
Test status
Simulation time 2457766800 ps
CPU time 113.87 seconds
Started Oct 09 07:54:12 PM UTC 24
Finished Oct 09 07:56:08 PM UTC 24
Peak memory 292088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938657093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3938657093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1154948856
Short name T508
Test name
Test status
Simulation time 1384479200 ps
CPU time 171.34 seconds
Started Oct 09 07:53:26 PM UTC 24
Finished Oct 09 07:56:20 PM UTC 24
Peak memory 306184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1154948856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_ro_serr.1154948856
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.1992754229
Short name T528
Test name
Test status
Simulation time 2970517900 ps
CPU time 392.09 seconds
Started Oct 09 07:53:25 PM UTC 24
Finished Oct 09 08:00:02 PM UTC 24
Peak memory 332796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992754229 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.1992754229
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.811713435
Short name T513
Test name
Test status
Simulation time 1137034000 ps
CPU time 161.2 seconds
Started Oct 09 07:54:14 PM UTC 24
Finished Oct 09 07:56:58 PM UTC 24
Peak memory 292088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=811713435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_rw_derr.811713435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.4116877581
Short name T507
Test name
Test status
Simulation time 44599100 ps
CPU time 55.49 seconds
Started Oct 09 07:55:17 PM UTC 24
Finished Oct 09 07:56:14 PM UTC 24
Peak memory 285852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116877581 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.4116877581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.3663185776
Short name T419
Test name
Test status
Simulation time 106813700 ps
CPU time 53.76 seconds
Started Oct 09 07:55:28 PM UTC 24
Finished Oct 09 07:56:23 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3663185776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw_evict_all_en.3663185776
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.445817991
Short name T516
Test name
Test status
Simulation time 4855608200 ps
CPU time 196.9 seconds
Started Oct 09 07:53:58 PM UTC 24
Finished Oct 09 07:57:19 PM UTC 24
Peak memory 306172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=445817991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.445817991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.836436902
Short name T367
Test name
Test status
Simulation time 3629792300 ps
CPU time 83.32 seconds
Started Oct 09 07:56:14 PM UTC 24
Finished Oct 09 07:57:40 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836436902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.836436902
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2292251894
Short name T502
Test name
Test status
Simulation time 25296100 ps
CPU time 144.68 seconds
Started Oct 09 07:52:18 PM UTC 24
Finished Oct 09 07:54:45 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292251894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2292251894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.4051738185
Short name T510
Test name
Test status
Simulation time 8246364500 ps
CPU time 193.12 seconds
Started Oct 09 07:53:18 PM UTC 24
Finished Oct 09 07:56:34 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4051738185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.4051738185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3009252367
Short name T1062
Test name
Test status
Simulation time 15509200 ps
CPU time 20.94 seconds
Started Oct 09 08:42:20 PM UTC 24
Finished Oct 09 08:42:43 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009252367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3009252367
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2561958826
Short name T1119
Test name
Test status
Simulation time 142445700 ps
CPU time 193.02 seconds
Started Oct 09 08:42:17 PM UTC 24
Finished Oct 09 08:45:34 PM UTC 24
Peak memory 271456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561958826 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.2561958826
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1659347991
Short name T1064
Test name
Test status
Simulation time 43715000 ps
CPU time 19.57 seconds
Started Oct 09 08:42:25 PM UTC 24
Finished Oct 09 08:42:46 PM UTC 24
Peak memory 295112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659347991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1659347991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3852979114
Short name T1117
Test name
Test status
Simulation time 46129300 ps
CPU time 182.61 seconds
Started Oct 09 08:42:25 PM UTC 24
Finished Oct 09 08:45:30 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852979114 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.3852979114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.4043945811
Short name T1070
Test name
Test status
Simulation time 16526500 ps
CPU time 25.27 seconds
Started Oct 09 08:42:29 PM UTC 24
Finished Oct 09 08:42:56 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043945811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.4043945811
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.778365749
Short name T1118
Test name
Test status
Simulation time 85910600 ps
CPU time 185.22 seconds
Started Oct 09 08:42:25 PM UTC 24
Finished Oct 09 08:45:33 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778365749 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.778365749
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.1063408312
Short name T1068
Test name
Test status
Simulation time 23022200 ps
CPU time 20.82 seconds
Started Oct 09 08:42:30 PM UTC 24
Finished Oct 09 08:42:53 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063408312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1063408312
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3963991837
Short name T1115
Test name
Test status
Simulation time 40201800 ps
CPU time 168.64 seconds
Started Oct 09 08:42:30 PM UTC 24
Finished Oct 09 08:45:22 PM UTC 24
Peak memory 271604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963991837 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.3963991837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.3739449653
Short name T1071
Test name
Test status
Simulation time 39406600 ps
CPU time 22.22 seconds
Started Oct 09 08:42:33 PM UTC 24
Finished Oct 09 08:42:57 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739449653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3739449653
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3637648075
Short name T1120
Test name
Test status
Simulation time 142819600 ps
CPU time 182.35 seconds
Started Oct 09 08:42:31 PM UTC 24
Finished Oct 09 08:45:37 PM UTC 24
Peak memory 273308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637648075 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.3637648075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.2430781548
Short name T1074
Test name
Test status
Simulation time 22814400 ps
CPU time 27.79 seconds
Started Oct 09 08:42:36 PM UTC 24
Finished Oct 09 08:43:05 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430781548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2430781548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.165307756
Short name T1122
Test name
Test status
Simulation time 151419700 ps
CPU time 192.85 seconds
Started Oct 09 08:42:35 PM UTC 24
Finished Oct 09 08:45:51 PM UTC 24
Peak memory 271516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165307756 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.165307756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.3682598860
Short name T1076
Test name
Test status
Simulation time 15068000 ps
CPU time 24.82 seconds
Started Oct 09 08:42:41 PM UTC 24
Finished Oct 09 08:43:07 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682598860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3682598860
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.138852741
Short name T311
Test name
Test status
Simulation time 75747900 ps
CPU time 175.87 seconds
Started Oct 09 08:42:41 PM UTC 24
Finished Oct 09 08:45:40 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138852741 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.138852741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.2785443772
Short name T1075
Test name
Test status
Simulation time 16079800 ps
CPU time 21.99 seconds
Started Oct 09 08:42:43 PM UTC 24
Finished Oct 09 08:43:07 PM UTC 24
Peak memory 284736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785443772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2785443772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.1952057711
Short name T1123
Test name
Test status
Simulation time 73142100 ps
CPU time 184.91 seconds
Started Oct 09 08:42:43 PM UTC 24
Finished Oct 09 08:45:51 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952057711 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.1952057711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.1491056945
Short name T1081
Test name
Test status
Simulation time 13886500 ps
CPU time 23.38 seconds
Started Oct 09 08:42:47 PM UTC 24
Finished Oct 09 08:43:11 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491056945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1491056945
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2561425468
Short name T1111
Test name
Test status
Simulation time 78247000 ps
CPU time 133.65 seconds
Started Oct 09 08:42:45 PM UTC 24
Finished Oct 09 08:45:02 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561425468 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.2561425468
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.76679768
Short name T1079
Test name
Test status
Simulation time 13406600 ps
CPU time 19.81 seconds
Started Oct 09 08:42:49 PM UTC 24
Finished Oct 09 08:43:10 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76679768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.76679768
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1335064043
Short name T1124
Test name
Test status
Simulation time 82382600 ps
CPU time 182.6 seconds
Started Oct 09 08:42:49 PM UTC 24
Finished Oct 09 08:45:54 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335064043 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.1335064043
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.745712114
Short name T533
Test name
Test status
Simulation time 30857600 ps
CPU time 15.76 seconds
Started Oct 09 08:00:11 PM UTC 24
Finished Oct 09 08:00:28 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745712114 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.745712114
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1884883743
Short name T530
Test name
Test status
Simulation time 16124600 ps
CPU time 26.35 seconds
Started Oct 09 07:59:56 PM UTC 24
Finished Oct 09 08:00:23 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884883743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1884883743
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.575979880
Short name T391
Test name
Test status
Simulation time 15292100 ps
CPU time 31.3 seconds
Started Oct 09 07:59:41 PM UTC 24
Finished Oct 09 08:00:14 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=575979880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_disable.575979880
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.512667526
Short name T1138
Test name
Test status
Simulation time 14748559200 ps
CPU time 3093.41 seconds
Started Oct 09 07:57:18 PM UTC 24
Finished Oct 09 08:49:25 PM UTC 24
Peak memory 275868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512667526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.512667526
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1466486655
Short name T636
Test name
Test status
Simulation time 893969900 ps
CPU time 1160.81 seconds
Started Oct 09 07:57:09 PM UTC 24
Finished Oct 09 08:16:43 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466486655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1466486655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.2924581390
Short name T312
Test name
Test status
Simulation time 142470200 ps
CPU time 40.26 seconds
Started Oct 09 07:57:01 PM UTC 24
Finished Oct 09 07:57:43 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
24581390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc
h_code.2924581390
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2629093727
Short name T537
Test name
Test status
Simulation time 10041818000 ps
CPU time 62.47 seconds
Started Oct 09 08:00:09 PM UTC 24
Finished Oct 09 08:01:14 PM UTC 24
Peak memory 293720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2629093727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2629093727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.3331278156
Short name T262
Test name
Test status
Simulation time 15670600 ps
CPU time 23.5 seconds
Started Oct 09 08:00:09 PM UTC 24
Finished Oct 09 08:00:34 PM UTC 24
Peak memory 269268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3331278156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_hw_read_seed_err.3331278156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.204150996
Short name T585
Test name
Test status
Simulation time 160202125500 ps
CPU time 828.56 seconds
Started Oct 09 07:56:51 PM UTC 24
Finished Oct 09 08:10:50 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204150996 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.204150996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1655039055
Short name T297
Test name
Test status
Simulation time 7948560800 ps
CPU time 149.64 seconds
Started Oct 09 07:56:49 PM UTC 24
Finished Oct 09 07:59:22 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655039055 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.1655039055
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2308642739
Short name T538
Test name
Test status
Simulation time 3060418800 ps
CPU time 200.47 seconds
Started Oct 09 07:58:31 PM UTC 24
Finished Oct 09 08:01:55 PM UTC 24
Peak memory 302256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308642739 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2308642739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.428230228
Short name T328
Test name
Test status
Simulation time 50109777300 ps
CPU time 249.7 seconds
Started Oct 09 07:58:41 PM UTC 24
Finished Oct 09 08:02:55 PM UTC 24
Peak memory 302092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=428230228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_rd_slow_flash.428230228
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2551784919
Short name T526
Test name
Test status
Simulation time 10064770600 ps
CPU time 80.27 seconds
Started Oct 09 07:58:32 PM UTC 24
Finished Oct 09 07:59:54 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551784919 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.2551784919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1341152120
Short name T315
Test name
Test status
Simulation time 20723705000 ps
CPU time 303.18 seconds
Started Oct 09 07:58:41 PM UTC 24
Finished Oct 09 08:03:49 PM UTC 24
Peak memory 271300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341152120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1341152120
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2414569744
Short name T521
Test name
Test status
Simulation time 905508400 ps
CPU time 79.19 seconds
Started Oct 09 07:57:19 PM UTC 24
Finished Oct 09 07:58:40 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414569744 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2414569744
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3483507498
Short name T531
Test name
Test status
Simulation time 58581300 ps
CPU time 26.74 seconds
Started Oct 09 07:59:58 PM UTC 24
Finished Oct 09 08:00:26 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3483507498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_lcmgr_intg.3483507498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4129622727
Short name T139
Test name
Test status
Simulation time 167430748000 ps
CPU time 1383.3 seconds
Started Oct 09 07:56:59 PM UTC 24
Finished Oct 09 08:20:19 PM UTC 24
Peak memory 283320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4129622727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_mp_regions.4129622727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.105470467
Short name T92
Test name
Test status
Simulation time 52746400 ps
CPU time 220.16 seconds
Started Oct 09 07:56:53 PM UTC 24
Finished Oct 09 08:00:36 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105470467 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.105470467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1349984305
Short name T568
Test name
Test status
Simulation time 726230900 ps
CPU time 673.16 seconds
Started Oct 09 07:56:48 PM UTC 24
Finished Oct 09 08:08:09 PM UTC 24
Peak memory 275396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349984305 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1349984305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.4250981194
Short name T542
Test name
Test status
Simulation time 27077926300 ps
CPU time 210.7 seconds
Started Oct 09 07:58:56 PM UTC 24
Finished Oct 09 08:02:30 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250981194 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.4250981194
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1557404835
Short name T148
Test name
Test status
Simulation time 1454394000 ps
CPU time 1128.07 seconds
Started Oct 09 07:56:40 PM UTC 24
Finished Oct 09 08:15:42 PM UTC 24
Peak memory 293572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557404835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1557404835
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.2338928117
Short name T402
Test name
Test status
Simulation time 231501100 ps
CPU time 52.57 seconds
Started Oct 09 07:59:35 PM UTC 24
Finished Oct 09 08:00:29 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338928117 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.2338928117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1450418470
Short name T525
Test name
Test status
Simulation time 544370700 ps
CPU time 119.37 seconds
Started Oct 09 07:57:43 PM UTC 24
Finished Oct 09 07:59:45 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1450418470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.1450418470
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2812884093
Short name T535
Test name
Test status
Simulation time 2715052300 ps
CPU time 162.98 seconds
Started Oct 09 07:58:16 PM UTC 24
Finished Oct 09 08:01:02 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812884093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2812884093
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1159122225
Short name T532
Test name
Test status
Simulation time 702730000 ps
CPU time 140.76 seconds
Started Oct 09 07:58:04 PM UTC 24
Finished Oct 09 08:00:27 PM UTC 24
Peak memory 306168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1159122225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_ro_serr.1159122225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.261275736
Short name T251
Test name
Test status
Simulation time 3327948200 ps
CPU time 444.66 seconds
Started Oct 09 07:57:57 PM UTC 24
Finished Oct 09 08:05:28 PM UTC 24
Peak memory 324820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261275736 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.261275736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3705742609
Short name T539
Test name
Test status
Simulation time 4200098000 ps
CPU time 215.45 seconds
Started Oct 09 07:58:27 PM UTC 24
Finished Oct 09 08:02:06 PM UTC 24
Peak memory 294068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3705742609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_rw_derr.3705742609
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.1860179178
Short name T409
Test name
Test status
Simulation time 93919800 ps
CPU time 34.54 seconds
Started Oct 09 07:59:05 PM UTC 24
Finished Oct 09 07:59:41 PM UTC 24
Peak memory 285648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860179178 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.1860179178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.999269436
Short name T413
Test name
Test status
Simulation time 71104900 ps
CPU time 45.32 seconds
Started Oct 09 07:59:23 PM UTC 24
Finished Oct 09 08:00:10 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=999269436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctr
l_rw_evict_all_en.999269436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.4202161593
Short name T544
Test name
Test status
Simulation time 2192315600 ps
CPU time 260.16 seconds
Started Oct 09 07:58:10 PM UTC 24
Finished Oct 09 08:02:34 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4202161593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.4202161593
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3599475581
Short name T363
Test name
Test status
Simulation time 4272278700 ps
CPU time 83.74 seconds
Started Oct 09 07:59:45 PM UTC 24
Finished Oct 09 08:01:11 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599475581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3599475581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4088420867
Short name T518
Test name
Test status
Simulation time 24570000 ps
CPU time 85.59 seconds
Started Oct 09 07:56:35 PM UTC 24
Finished Oct 09 07:58:02 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088420867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.4088420867
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2232767379
Short name T529
Test name
Test status
Simulation time 2233245100 ps
CPU time 148.65 seconds
Started Oct 09 07:57:40 PM UTC 24
Finished Oct 09 08:00:12 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2232767379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.2232767379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.3941313305
Short name T1083
Test name
Test status
Simulation time 29355200 ps
CPU time 25.68 seconds
Started Oct 09 08:42:53 PM UTC 24
Finished Oct 09 08:43:20 PM UTC 24
Peak memory 284896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941313305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3941313305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2285423491
Short name T1127
Test name
Test status
Simulation time 39923700 ps
CPU time 192.56 seconds
Started Oct 09 08:42:50 PM UTC 24
Finished Oct 09 08:46:06 PM UTC 24
Peak memory 271348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285423491 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.2285423491
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.713943433
Short name T1085
Test name
Test status
Simulation time 18117000 ps
CPU time 26.49 seconds
Started Oct 09 08:42:57 PM UTC 24
Finished Oct 09 08:43:25 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713943433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.713943433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2808721340
Short name T1130
Test name
Test status
Simulation time 56303800 ps
CPU time 197.31 seconds
Started Oct 09 08:42:56 PM UTC 24
Finished Oct 09 08:46:17 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808721340 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.2808721340
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.1563964278
Short name T1089
Test name
Test status
Simulation time 23454400 ps
CPU time 24.7 seconds
Started Oct 09 08:43:03 PM UTC 24
Finished Oct 09 08:43:29 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563964278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1563964278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1909927149
Short name T1131
Test name
Test status
Simulation time 75133900 ps
CPU time 197.34 seconds
Started Oct 09 08:42:58 PM UTC 24
Finished Oct 09 08:46:19 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909927149 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.1909927149
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.2632573933
Short name T1088
Test name
Test status
Simulation time 17085400 ps
CPU time 19.52 seconds
Started Oct 09 08:43:07 PM UTC 24
Finished Oct 09 08:43:28 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632573933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2632573933
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.9710619
Short name T1134
Test name
Test status
Simulation time 78415900 ps
CPU time 203.18 seconds
Started Oct 09 08:43:03 PM UTC 24
Finished Oct 09 08:46:29 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9710619 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.9710619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3152434781
Short name T1095
Test name
Test status
Simulation time 21162800 ps
CPU time 26.53 seconds
Started Oct 09 08:43:08 PM UTC 24
Finished Oct 09 08:43:36 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152434781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3152434781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.470224696
Short name T1096
Test name
Test status
Simulation time 16702900 ps
CPU time 25.38 seconds
Started Oct 09 08:43:11 PM UTC 24
Finished Oct 09 08:43:38 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470224696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.470224696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.459243404
Short name T1132
Test name
Test status
Simulation time 64077400 ps
CPU time 187.95 seconds
Started Oct 09 08:43:09 PM UTC 24
Finished Oct 09 08:46:20 PM UTC 24
Peak memory 271388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459243404 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.459243404
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.946209834
Short name T1093
Test name
Test status
Simulation time 39938900 ps
CPU time 22.62 seconds
Started Oct 09 08:43:11 PM UTC 24
Finished Oct 09 08:43:35 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946209834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.946209834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1881614329
Short name T1133
Test name
Test status
Simulation time 41139200 ps
CPU time 191.32 seconds
Started Oct 09 08:43:11 PM UTC 24
Finished Oct 09 08:46:26 PM UTC 24
Peak memory 271456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881614329 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.1881614329
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3368101299
Short name T1094
Test name
Test status
Simulation time 15739700 ps
CPU time 19.78 seconds
Started Oct 09 08:43:15 PM UTC 24
Finished Oct 09 08:43:36 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368101299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3368101299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1322109126
Short name T1126
Test name
Test status
Simulation time 243143600 ps
CPU time 167.06 seconds
Started Oct 09 08:43:13 PM UTC 24
Finished Oct 09 08:46:02 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322109126 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.1322109126
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.2073534829
Short name T1098
Test name
Test status
Simulation time 92000900 ps
CPU time 25.8 seconds
Started Oct 09 08:43:25 PM UTC 24
Finished Oct 09 08:43:52 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073534829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2073534829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.968087817
Short name T1135
Test name
Test status
Simulation time 75952500 ps
CPU time 190.62 seconds
Started Oct 09 08:43:21 PM UTC 24
Finished Oct 09 08:46:35 PM UTC 24
Peak memory 270940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968087817 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.968087817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.3130563412
Short name T1099
Test name
Test status
Simulation time 20758400 ps
CPU time 26.85 seconds
Started Oct 09 08:43:26 PM UTC 24
Finished Oct 09 08:43:55 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130563412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3130563412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1644010403
Short name T1121
Test name
Test status
Simulation time 112524700 ps
CPU time 142.08 seconds
Started Oct 09 08:43:25 PM UTC 24
Finished Oct 09 08:45:50 PM UTC 24
Peak memory 275360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644010403 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.1644010403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3628916054
Short name T551
Test name
Test status
Simulation time 412052000 ps
CPU time 18.02 seconds
Started Oct 09 08:04:05 PM UTC 24
Finished Oct 09 08:04:25 PM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628916054 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3628916054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.2939780335
Short name T549
Test name
Test status
Simulation time 16060000 ps
CPU time 23.5 seconds
Started Oct 09 08:03:50 PM UTC 24
Finished Oct 09 08:04:15 PM UTC 24
Peak memory 284676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939780335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2939780335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2210751719
Short name T118
Test name
Test status
Simulation time 10345300 ps
CPU time 45.28 seconds
Started Oct 09 08:03:41 PM UTC 24
Finished Oct 09 08:04:28 PM UTC 24
Peak memory 285608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2210751719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c
trl_disable.2210751719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3595638032
Short name T1137
Test name
Test status
Simulation time 11721783100 ps
CPU time 2867.86 seconds
Started Oct 09 08:00:38 PM UTC 24
Finished Oct 09 08:48:56 PM UTC 24
Peak memory 277920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595638032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3595638032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1936938581
Short name T683
Test name
Test status
Simulation time 2450467900 ps
CPU time 1292.68 seconds
Started Oct 09 08:00:36 PM UTC 24
Finished Oct 09 08:22:24 PM UTC 24
Peak memory 285524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936938581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1936938581
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.2838492739
Short name T536
Test name
Test status
Simulation time 1488319800 ps
CPU time 37.96 seconds
Started Oct 09 08:00:32 PM UTC 24
Finished Oct 09 08:01:12 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
38492739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc
h_code.2838492739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1241592492
Short name T559
Test name
Test status
Simulation time 10018732600 ps
CPU time 144.71 seconds
Started Oct 09 08:03:58 PM UTC 24
Finished Oct 09 08:06:26 PM UTC 24
Peak memory 283600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1241592492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1241592492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.875803868
Short name T314
Test name
Test status
Simulation time 19019900 ps
CPU time 29.45 seconds
Started Oct 09 08:03:55 PM UTC 24
Finished Oct 09 08:04:26 PM UTC 24
Peak memory 271276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=875803868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8
.flash_ctrl_hw_read_seed_err.875803868
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.3585446317
Short name T388
Test name
Test status
Simulation time 120148285200 ps
CPU time 890.44 seconds
Started Oct 09 08:00:28 PM UTC 24
Finished Oct 09 08:15:30 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585446317
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.3585446317
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.348403257
Short name T545
Test name
Test status
Simulation time 2874371600 ps
CPU time 139.55 seconds
Started Oct 09 08:00:27 PM UTC 24
Finished Oct 09 08:02:49 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348403257 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.348403257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1072674952
Short name T334
Test name
Test status
Simulation time 14711512000 ps
CPU time 202.66 seconds
Started Oct 09 08:02:11 PM UTC 24
Finished Oct 09 08:05:38 PM UTC 24
Peak memory 306128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072674952 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1072674952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1969907351
Short name T566
Test name
Test status
Simulation time 24322148200 ps
CPU time 320.14 seconds
Started Oct 09 08:02:34 PM UTC 24
Finished Oct 09 08:07:59 PM UTC 24
Peak memory 301892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1969907351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_intr_rd_slow_flash.1969907351
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2766706690
Short name T548
Test name
Test status
Simulation time 4115413700 ps
CPU time 84.65 seconds
Started Oct 09 08:02:31 PM UTC 24
Finished Oct 09 08:03:57 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766706690 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.2766706690
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.4026178498
Short name T554
Test name
Test status
Simulation time 35756993400 ps
CPU time 158.6 seconds
Started Oct 09 08:02:35 PM UTC 24
Finished Oct 09 08:05:16 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026178498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.4026178498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3742377719
Short name T543
Test name
Test status
Simulation time 7026222600 ps
CPU time 88.39 seconds
Started Oct 09 08:01:03 PM UTC 24
Finished Oct 09 08:02:33 PM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742377719 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3742377719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.107594305
Short name T309
Test name
Test status
Simulation time 44470600 ps
CPU time 17.25 seconds
Started Oct 09 08:03:50 PM UTC 24
Finished Oct 09 08:04:09 PM UTC 24
Peak memory 275300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107594305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_lcmgr_intg.107594305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.452030574
Short name T137
Test name
Test status
Simulation time 10431639400 ps
CPU time 348.52 seconds
Started Oct 09 08:00:30 PM UTC 24
Finished Oct 09 08:06:24 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=452030574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_mp_regions.452030574
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1936608728
Short name T93
Test name
Test status
Simulation time 39924300 ps
CPU time 191.38 seconds
Started Oct 09 08:00:28 PM UTC 24
Finished Oct 09 08:03:43 PM UTC 24
Peak memory 271260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936608728 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.1936608728
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.2798235166
Short name T596
Test name
Test status
Simulation time 775431500 ps
CPU time 677.41 seconds
Started Oct 09 08:00:24 PM UTC 24
Finished Oct 09 08:11:50 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798235166 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2798235166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.2242418002
Short name T558
Test name
Test status
Simulation time 2139993700 ps
CPU time 198.33 seconds
Started Oct 09 08:02:50 PM UTC 24
Finished Oct 09 08:06:12 PM UTC 24
Peak memory 271372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242418002 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.2242418002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2837632147
Short name T722
Test name
Test status
Simulation time 3034503600 ps
CPU time 1543.99 seconds
Started Oct 09 08:00:15 PM UTC 24
Finished Oct 09 08:26:17 PM UTC 24
Peak memory 295624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837632147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2837632147
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.2023256510
Short name T547
Test name
Test status
Simulation time 230352400 ps
CPU time 41.98 seconds
Started Oct 09 08:03:11 PM UTC 24
Finished Oct 09 08:03:54 PM UTC 24
Peak memory 283580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023256510 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.2023256510
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1062665062
Short name T546
Test name
Test status
Simulation time 1838081300 ps
CPU time 107.32 seconds
Started Oct 09 08:01:13 PM UTC 24
Finished Oct 09 08:03:03 PM UTC 24
Peak memory 302084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1062665062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.1062665062
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.3738826080
Short name T553
Test name
Test status
Simulation time 770234300 ps
CPU time 156.13 seconds
Started Oct 09 08:02:07 PM UTC 24
Finished Oct 09 08:04:46 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738826080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.3738826080
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3001217126
Short name T550
Test name
Test status
Simulation time 1260449900 ps
CPU time 177.85 seconds
Started Oct 09 08:01:18 PM UTC 24
Finished Oct 09 08:04:19 PM UTC 24
Peak memory 292088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3001217126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_ro_serr.3001217126
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.529792672
Short name T408
Test name
Test status
Simulation time 14456429400 ps
CPU time 556.26 seconds
Started Oct 09 08:01:14 PM UTC 24
Finished Oct 09 08:10:38 PM UTC 24
Peak memory 324628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529792672 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.529792672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.2911752073
Short name T560
Test name
Test status
Simulation time 9721945800 ps
CPU time 271.26 seconds
Started Oct 09 08:02:08 PM UTC 24
Finished Oct 09 08:06:44 PM UTC 24
Peak memory 302324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2911752073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_rw_derr.2911752073
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.2583204014
Short name T405
Test name
Test status
Simulation time 151140100 ps
CPU time 52.61 seconds
Started Oct 09 08:02:55 PM UTC 24
Finished Oct 09 08:03:50 PM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583204014 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.2583204014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.2409107139
Short name T421
Test name
Test status
Simulation time 50474600 ps
CPU time 59.47 seconds
Started Oct 09 08:03:03 PM UTC 24
Finished Oct 09 08:04:05 PM UTC 24
Peak memory 287864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2409107139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw_evict_all_en.2409107139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3318436791
Short name T557
Test name
Test status
Simulation time 1295237100 ps
CPU time 246.93 seconds
Started Oct 09 08:01:56 PM UTC 24
Finished Oct 09 08:06:07 PM UTC 24
Peak memory 291840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3318436791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.3318436791
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3052980630
Short name T364
Test name
Test status
Simulation time 1230486400 ps
CPU time 86.27 seconds
Started Oct 09 08:03:44 PM UTC 24
Finished Oct 09 08:05:13 PM UTC 24
Peak memory 275280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052980630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3052980630
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3429093692
Short name T540
Test name
Test status
Simulation time 39810300 ps
CPU time 112.93 seconds
Started Oct 09 08:00:13 PM UTC 24
Finished Oct 09 08:02:08 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429093692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3429093692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3654217684
Short name T555
Test name
Test status
Simulation time 2540791700 ps
CPU time 249.26 seconds
Started Oct 09 08:01:12 PM UTC 24
Finished Oct 09 08:05:25 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3654217684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.3654217684
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1389959724
Short name T577
Test name
Test status
Simulation time 108082700 ps
CPU time 28.48 seconds
Started Oct 09 08:08:31 PM UTC 24
Finished Oct 09 08:09:02 PM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389959724 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1389959724
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1872407074
Short name T571
Test name
Test status
Simulation time 14302700 ps
CPU time 19.19 seconds
Started Oct 09 08:08:10 PM UTC 24
Finished Oct 09 08:08:30 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872407074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1872407074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3718273554
Short name T119
Test name
Test status
Simulation time 10293000 ps
CPU time 45.23 seconds
Started Oct 09 08:07:59 PM UTC 24
Finished Oct 09 08:08:46 PM UTC 24
Peak memory 285880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3718273554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c
trl_disable.3718273554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1784409282
Short name T1139
Test name
Test status
Simulation time 8561326400 ps
CPU time 2877.41 seconds
Started Oct 09 08:05:17 PM UTC 24
Finished Oct 09 08:53:47 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784409282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1784409282
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2732507296
Short name T672
Test name
Test status
Simulation time 1080826400 ps
CPU time 969.68 seconds
Started Oct 09 08:05:14 PM UTC 24
Finished Oct 09 08:21:34 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732507296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2732507296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.4267690134
Short name T556
Test name
Test status
Simulation time 159426500 ps
CPU time 40.01 seconds
Started Oct 09 08:04:47 PM UTC 24
Finished Oct 09 08:05:29 PM UTC 24
Peak memory 275336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
67690134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc
h_code.4267690134
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2776866816
Short name T580
Test name
Test status
Simulation time 10045026600 ps
CPU time 69.99 seconds
Started Oct 09 08:08:21 PM UTC 24
Finished Oct 09 08:09:33 PM UTC 24
Peak memory 275416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2776866816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2776866816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3392979829
Short name T574
Test name
Test status
Simulation time 26504500 ps
CPU time 23.41 seconds
Started Oct 09 08:08:14 PM UTC 24
Finished Oct 09 08:08:39 PM UTC 24
Peak memory 275240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3392979829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_hw_read_seed_err.3392979829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.40782563
Short name T657
Test name
Test status
Simulation time 110158852600 ps
CPU time 914.28 seconds
Started Oct 09 08:04:27 PM UTC 24
Finished Oct 09 08:19:53 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40782563 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.40782563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.230353016
Short name T300
Test name
Test status
Simulation time 17179880900 ps
CPU time 155.91 seconds
Started Oct 09 08:04:26 PM UTC 24
Finished Oct 09 08:07:05 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230353016 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.230353016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1021655207
Short name T330
Test name
Test status
Simulation time 631363300 ps
CPU time 179.24 seconds
Started Oct 09 08:06:44 PM UTC 24
Finished Oct 09 08:09:47 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021655207 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.1021655207
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3368209701
Short name T326
Test name
Test status
Simulation time 49104374300 ps
CPU time 313.2 seconds
Started Oct 09 08:07:00 PM UTC 24
Finished Oct 09 08:12:17 PM UTC 24
Peak memory 302120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3368209701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_intr_rd_slow_flash.3368209701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2353306074
Short name T575
Test name
Test status
Simulation time 9194852100 ps
CPU time 98.65 seconds
Started Oct 09 08:06:59 PM UTC 24
Finished Oct 09 08:08:40 PM UTC 24
Peak memory 271360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353306074 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2353306074
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3754162945
Short name T592
Test name
Test status
Simulation time 73515876100 ps
CPU time 251.26 seconds
Started Oct 09 08:07:06 PM UTC 24
Finished Oct 09 08:11:21 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754162945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3754162945
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2567955910
Short name T563
Test name
Test status
Simulation time 6342490700 ps
CPU time 101.1 seconds
Started Oct 09 08:05:26 PM UTC 24
Finished Oct 09 08:07:09 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567955910 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2567955910
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.382235279
Short name T572
Test name
Test status
Simulation time 16168200 ps
CPU time 16.22 seconds
Started Oct 09 08:08:14 PM UTC 24
Finished Oct 09 08:08:31 PM UTC 24
Peak memory 271168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=382235279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_lcmgr_intg.382235279
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1223656046
Short name T564
Test name
Test status
Simulation time 1924675100 ps
CPU time 166.86 seconds
Started Oct 09 08:04:29 PM UTC 24
Finished Oct 09 08:07:19 PM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1223656046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_mp_regions.1223656046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2209889689
Short name T562
Test name
Test status
Simulation time 78019200 ps
CPU time 147.91 seconds
Started Oct 09 08:04:28 PM UTC 24
Finished Oct 09 08:06:59 PM UTC 24
Peak memory 271256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209889689 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.2209889689
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.3018812252
Short name T633
Test name
Test status
Simulation time 5771380700 ps
CPU time 698.3 seconds
Started Oct 09 08:04:20 PM UTC 24
Finished Oct 09 08:16:07 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018812252 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3018812252
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1345726612
Short name T565
Test name
Test status
Simulation time 181986300 ps
CPU time 29.27 seconds
Started Oct 09 08:07:09 PM UTC 24
Finished Oct 09 08:07:40 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345726612 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.1345726612
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.745825049
Short name T604
Test name
Test status
Simulation time 253079300 ps
CPU time 526.43 seconds
Started Oct 09 08:04:16 PM UTC 24
Finished Oct 09 08:13:09 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745825049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.745825049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.2387144757
Short name T573
Test name
Test status
Simulation time 618694700 ps
CPU time 55.13 seconds
Started Oct 09 08:07:41 PM UTC 24
Finished Oct 09 08:08:38 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387144757 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.2387144757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3474006219
Short name T567
Test name
Test status
Simulation time 753575100 ps
CPU time 149.74 seconds
Started Oct 09 08:05:30 PM UTC 24
Finished Oct 09 08:08:03 PM UTC 24
Peak memory 291712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3474006219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.3474006219
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2942641825
Short name T578
Test name
Test status
Simulation time 4918212000 ps
CPU time 155.23 seconds
Started Oct 09 08:06:25 PM UTC 24
Finished Oct 09 08:09:03 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942641825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2942641825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.567978844
Short name T576
Test name
Test status
Simulation time 505561700 ps
CPU time 157.7 seconds
Started Oct 09 08:06:08 PM UTC 24
Finished Oct 09 08:08:49 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=567978844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_
ctrl_ro_serr.567978844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.4000470521
Short name T610
Test name
Test status
Simulation time 2967731800 ps
CPU time 460.22 seconds
Started Oct 09 08:05:38 PM UTC 24
Finished Oct 09 08:13:25 PM UTC 24
Peak memory 320528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000470521 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.4000470521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3303714356
Short name T581
Test name
Test status
Simulation time 6089494800 ps
CPU time 231.5 seconds
Started Oct 09 08:06:26 PM UTC 24
Finished Oct 09 08:10:22 PM UTC 24
Peak memory 298012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3303714356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_rw_derr.3303714356
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.3277551485
Short name T414
Test name
Test status
Simulation time 44063600 ps
CPU time 60.31 seconds
Started Oct 09 08:07:11 PM UTC 24
Finished Oct 09 08:08:13 PM UTC 24
Peak memory 283584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277551485 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.3277551485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.169948172
Short name T570
Test name
Test status
Simulation time 30946300 ps
CPU time 58.22 seconds
Started Oct 09 08:07:20 PM UTC 24
Finished Oct 09 08:08:20 PM UTC 24
Peak memory 281528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=169948172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctr
l_rw_evict_all_en.169948172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3125870857
Short name T579
Test name
Test status
Simulation time 8133193000 ps
CPU time 191.52 seconds
Started Oct 09 08:06:13 PM UTC 24
Finished Oct 09 08:09:27 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3125870857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.3125870857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.1285351161
Short name T368
Test name
Test status
Simulation time 564380900 ps
CPU time 76.93 seconds
Started Oct 09 08:08:04 PM UTC 24
Finished Oct 09 08:09:22 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285351161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1285351161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.528535276
Short name T561
Test name
Test status
Simulation time 50268100 ps
CPU time 165.51 seconds
Started Oct 09 08:04:10 PM UTC 24
Finished Oct 09 08:06:58 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528535276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.528535276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2933986256
Short name T569
Test name
Test status
Simulation time 8661625300 ps
CPU time 160.97 seconds
Started Oct 09 08:05:29 PM UTC 24
Finished Oct 09 08:08:13 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2933986256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.2933986256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest
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