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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.25 93.98 98.31 91.84 97.18 96.99 98.18


Total test records in report: 1268
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T474 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.970103653 Sep 11 05:49:17 PM UTC 24 Sep 11 05:52:36 PM UTC 24 5907694200 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.4102322078 Sep 11 05:46:26 PM UTC 24 Sep 11 05:52:37 PM UTC 24 319372800 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1921078477 Sep 11 05:49:22 PM UTC 24 Sep 11 05:52:41 PM UTC 24 2134470000 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.3561714082 Sep 11 05:51:58 PM UTC 24 Sep 11 05:52:41 PM UTC 24 1917193600 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.3480360325 Sep 11 05:51:29 PM UTC 24 Sep 11 05:52:41 PM UTC 24 35331600 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1895982976 Sep 11 05:51:40 PM UTC 24 Sep 11 05:53:02 PM UTC 24 799645300 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.4221380284 Sep 11 05:49:07 PM UTC 24 Sep 11 05:53:02 PM UTC 24 1346529000 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2197863464 Sep 11 05:49:26 PM UTC 24 Sep 11 05:53:46 PM UTC 24 30105618100 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.3395906544 Sep 11 05:51:55 PM UTC 24 Sep 11 05:54:11 PM UTC 24 5114565200 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.615963629 Sep 11 05:52:23 PM UTC 24 Sep 11 05:54:12 PM UTC 24 3625322400 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3512459476 Sep 11 05:52:28 PM UTC 24 Sep 11 05:54:13 PM UTC 24 511655800 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.2012684851 Sep 11 05:52:37 PM UTC 24 Sep 11 05:54:25 PM UTC 24 1052585700 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1332998046 Sep 11 05:53:03 PM UTC 24 Sep 11 05:54:31 PM UTC 24 1744729700 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3109908433 Sep 11 05:54:12 PM UTC 24 Sep 11 05:54:37 PM UTC 24 32615400 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2040405526 Sep 11 05:40:27 PM UTC 24 Sep 11 05:54:38 PM UTC 24 160774071500 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1159657659 Sep 11 05:54:32 PM UTC 24 Sep 11 05:54:59 PM UTC 24 27864400 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.4259622381 Sep 11 05:54:39 PM UTC 24 Sep 11 05:55:08 PM UTC 24 62849100 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1111182091 Sep 11 05:54:13 PM UTC 24 Sep 11 05:55:08 PM UTC 24 41058600 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4245802625 Sep 11 05:52:37 PM UTC 24 Sep 11 05:55:09 PM UTC 24 1968708700 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2357517778 Sep 11 05:41:30 PM UTC 24 Sep 11 05:55:13 PM UTC 24 170187642000 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2560715891 Sep 11 05:54:14 PM UTC 24 Sep 11 05:55:13 PM UTC 24 28282900 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.3791570746 Sep 11 05:52:41 PM UTC 24 Sep 11 05:55:15 PM UTC 24 614677500 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1789595504 Sep 11 05:54:26 PM UTC 24 Sep 11 05:55:18 PM UTC 24 120569100 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.4149176992 Sep 11 05:55:00 PM UTC 24 Sep 11 05:55:20 PM UTC 24 15693800 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.4208237846 Sep 11 05:55:09 PM UTC 24 Sep 11 05:55:27 PM UTC 24 16301600 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.53696112 Sep 11 05:51:51 PM UTC 24 Sep 11 05:55:32 PM UTC 24 94677400 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.2186902348 Sep 11 05:35:15 PM UTC 24 Sep 11 05:55:37 PM UTC 24 548716200 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1093118882 Sep 11 05:55:10 PM UTC 24 Sep 11 05:55:40 PM UTC 24 52137500 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3017518496 Sep 11 05:54:37 PM UTC 24 Sep 11 05:55:55 PM UTC 24 967366700 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.254104842 Sep 11 05:47:47 PM UTC 24 Sep 11 05:55:55 PM UTC 24 3617182200 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.4186625713 Sep 11 05:52:43 PM UTC 24 Sep 11 05:55:59 PM UTC 24 709372300 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.3977570811 Sep 11 05:52:25 PM UTC 24 Sep 11 05:56:09 PM UTC 24 3916310600 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.71168439 Sep 11 05:55:38 PM UTC 24 Sep 11 05:56:18 PM UTC 24 377325600 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2675832681 Sep 11 05:52:43 PM UTC 24 Sep 11 05:57:00 PM UTC 24 1815621800 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.3519491391 Sep 11 05:39:41 PM UTC 24 Sep 11 05:57:07 PM UTC 24 175402400 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.4001921538 Sep 11 05:55:14 PM UTC 24 Sep 11 05:57:21 PM UTC 24 68966100 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3593530492 Sep 11 05:55:56 PM UTC 24 Sep 11 05:57:28 PM UTC 24 1166913600 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.808261140 Sep 11 05:53:47 PM UTC 24 Sep 11 05:57:28 PM UTC 24 44437297100 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.51725078 Sep 11 05:49:19 PM UTC 24 Sep 11 05:57:33 PM UTC 24 17886990000 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.4161726116 Sep 11 05:51:39 PM UTC 24 Sep 11 05:57:55 PM UTC 24 703294100 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.2646452651 Sep 11 05:56:09 PM UTC 24 Sep 11 05:58:00 PM UTC 24 2991004600 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3627677214 Sep 11 05:55:27 PM UTC 24 Sep 11 05:58:20 PM UTC 24 39270100 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.1849904617 Sep 11 05:55:18 PM UTC 24 Sep 11 05:58:35 PM UTC 24 25894077000 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2811355383 Sep 11 05:53:03 PM UTC 24 Sep 11 05:58:41 PM UTC 24 86121814900 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2095611717 Sep 11 05:55:09 PM UTC 24 Sep 11 05:58:42 PM UTC 24 10012723800 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2098963965 Sep 11 05:52:36 PM UTC 24 Sep 11 05:58:52 PM UTC 24 22966483000 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1642524247 Sep 11 05:57:34 PM UTC 24 Sep 11 05:59:12 PM UTC 24 4397936800 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1437760607 Sep 11 05:56:00 PM UTC 24 Sep 11 05:59:21 PM UTC 24 2566546600 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.509299930 Sep 11 05:55:15 PM UTC 24 Sep 11 05:59:25 PM UTC 24 69272100 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2332589596 Sep 11 05:58:53 PM UTC 24 Sep 11 05:59:32 PM UTC 24 17198400 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3522281654 Sep 11 05:58:43 PM UTC 24 Sep 11 05:59:33 PM UTC 24 167688200 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.3961507127 Sep 11 05:58:42 PM UTC 24 Sep 11 05:59:34 PM UTC 24 76075200 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.517949201 Sep 11 05:57:02 PM UTC 24 Sep 11 05:59:43 PM UTC 24 1286282500 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.3185046159 Sep 11 05:59:22 PM UTC 24 Sep 11 05:59:44 PM UTC 24 98246600 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3210369232 Sep 11 05:59:32 PM UTC 24 Sep 11 05:59:55 PM UTC 24 15343100 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2425883250 Sep 11 05:59:26 PM UTC 24 Sep 11 05:59:55 PM UTC 24 75488600 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.1115835000 Sep 11 05:59:33 PM UTC 24 Sep 11 05:59:58 PM UTC 24 281149000 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.42066634 Sep 11 05:57:08 PM UTC 24 Sep 11 06:00:00 PM UTC 24 2679816400 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.1472135048 Sep 11 05:57:29 PM UTC 24 Sep 11 06:00:12 PM UTC 24 521927800 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3469197052 Sep 11 05:57:22 PM UTC 24 Sep 11 06:00:18 PM UTC 24 685059000 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.556590260 Sep 11 05:57:56 PM UTC 24 Sep 11 06:00:21 PM UTC 24 5847074300 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2093361996 Sep 11 05:51:30 PM UTC 24 Sep 11 06:00:26 PM UTC 24 2198651300 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3473276998 Sep 11 05:55:33 PM UTC 24 Sep 11 06:00:32 PM UTC 24 6721822900 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.4072013476 Sep 11 05:59:13 PM UTC 24 Sep 11 06:00:41 PM UTC 24 2814529500 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1118355191 Sep 11 06:00:13 PM UTC 24 Sep 11 06:00:52 PM UTC 24 420236300 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.1901227037 Sep 11 05:29:41 PM UTC 24 Sep 11 06:01:01 PM UTC 24 127483535400 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1310000162 Sep 11 05:57:29 PM UTC 24 Sep 11 06:01:13 PM UTC 24 2268688300 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3458149147 Sep 11 05:46:34 PM UTC 24 Sep 11 06:01:15 PM UTC 24 160175625500 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.3074188974 Sep 11 05:58:20 PM UTC 24 Sep 11 06:01:25 PM UTC 24 3549974000 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1193987385 Sep 11 05:59:56 PM UTC 24 Sep 11 06:01:34 PM UTC 24 9409885400 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1297803261 Sep 11 06:00:26 PM UTC 24 Sep 11 06:01:42 PM UTC 24 9056648300 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2274151266 Sep 11 05:58:00 PM UTC 24 Sep 11 06:01:43 PM UTC 24 19594730300 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.2064713558 Sep 11 05:46:20 PM UTC 24 Sep 11 06:01:47 PM UTC 24 1410299500 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.3790079335 Sep 11 05:59:45 PM UTC 24 Sep 11 06:01:55 PM UTC 24 44564700 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.273865190 Sep 11 06:01:56 PM UTC 24 Sep 11 06:02:20 PM UTC 24 35440400 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1710047174 Sep 11 05:59:33 PM UTC 24 Sep 11 06:02:33 PM UTC 24 10021275000 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.2544493951 Sep 11 05:59:59 PM UTC 24 Sep 11 06:02:47 PM UTC 24 38716700 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.274058836 Sep 11 05:59:34 PM UTC 24 Sep 11 06:02:55 PM UTC 24 37516500 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1639711009 Sep 11 06:01:02 PM UTC 24 Sep 11 06:02:59 PM UTC 24 531469900 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3437450475 Sep 11 06:02:21 PM UTC 24 Sep 11 06:02:59 PM UTC 24 75911800 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.865319318 Sep 11 06:00:42 PM UTC 24 Sep 11 06:03:00 PM UTC 24 2163682700 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3814041737 Sep 11 06:01:43 PM UTC 24 Sep 11 06:03:11 PM UTC 24 8612528100 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.1389373510 Sep 11 06:02:34 PM UTC 24 Sep 11 06:03:26 PM UTC 24 43556200 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.4262269520 Sep 11 06:03:01 PM UTC 24 Sep 11 06:03:26 PM UTC 24 15663900 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2287114799 Sep 11 06:03:00 PM UTC 24 Sep 11 06:03:27 PM UTC 24 27769200 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.4197543813 Sep 11 06:03:12 PM UTC 24 Sep 11 06:03:29 PM UTC 24 15667100 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3835278879 Sep 11 06:02:56 PM UTC 24 Sep 11 06:03:34 PM UTC 24 12706000 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2801875977 Sep 11 06:01:16 PM UTC 24 Sep 11 06:03:46 PM UTC 24 747052100 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.57835618 Sep 11 06:02:48 PM UTC 24 Sep 11 06:03:50 PM UTC 24 63614800 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.3471935457 Sep 11 06:03:27 PM UTC 24 Sep 11 06:03:51 PM UTC 24 24424200 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.613027031 Sep 11 05:33:27 PM UTC 24 Sep 11 06:03:57 PM UTC 24 313242500 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.2130727763 Sep 11 06:01:26 PM UTC 24 Sep 11 06:04:02 PM UTC 24 1402581100 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.4285131926 Sep 11 06:00:33 PM UTC 24 Sep 11 06:04:28 PM UTC 24 28932365800 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.935282415 Sep 11 05:56:19 PM UTC 24 Sep 11 06:04:31 PM UTC 24 4158670300 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.1149056348 Sep 11 06:02:59 PM UTC 24 Sep 11 06:04:31 PM UTC 24 7736916200 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.421779148 Sep 11 06:01:14 PM UTC 24 Sep 11 06:04:34 PM UTC 24 2478868100 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.2917912264 Sep 11 06:00:01 PM UTC 24 Sep 11 06:04:36 PM UTC 24 18949165700 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.260149 Sep 11 06:03:27 PM UTC 24 Sep 11 06:04:37 PM UTC 24 10032388400 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.449386603 Sep 11 06:03:58 PM UTC 24 Sep 11 06:04:44 PM UTC 24 6579222900 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.680271518 Sep 11 06:03:43 PM UTC 24 Sep 11 06:04:44 PM UTC 24 2282337200 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3325796320 Sep 11 06:01:35 PM UTC 24 Sep 11 06:04:52 PM UTC 24 3157021700 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3145316789 Sep 11 06:01:44 PM UTC 24 Sep 11 06:04:56 PM UTC 24 6097532600 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2545554106 Sep 11 05:34:36 PM UTC 24 Sep 11 06:05:05 PM UTC 24 187785061500 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.663787219 Sep 11 05:51:49 PM UTC 24 Sep 11 06:05:05 PM UTC 24 40125144800 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.178146999 Sep 11 06:03:29 PM UTC 24 Sep 11 06:05:41 PM UTC 24 24814500 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.107489307 Sep 11 06:04:32 PM UTC 24 Sep 11 06:05:50 PM UTC 24 16129132700 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1174138476 Sep 11 06:05:05 PM UTC 24 Sep 11 06:06:04 PM UTC 24 7352275800 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3600794470 Sep 11 06:04:38 PM UTC 24 Sep 11 06:06:31 PM UTC 24 1252646600 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.148737862 Sep 11 06:04:45 PM UTC 24 Sep 11 06:06:35 PM UTC 24 1262021800 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1977642089 Sep 11 05:42:05 PM UTC 24 Sep 11 06:06:35 PM UTC 24 1491222300 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3600463064 Sep 11 06:03:52 PM UTC 24 Sep 11 06:06:43 PM UTC 24 70419600 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.3812927417 Sep 11 06:04:35 PM UTC 24 Sep 11 06:06:47 PM UTC 24 912635500 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.1766954358 Sep 11 06:06:05 PM UTC 24 Sep 11 06:06:57 PM UTC 24 30259200 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1236343128 Sep 11 05:28:16 PM UTC 24 Sep 11 06:06:59 PM UTC 24 4710315300 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1687045916 Sep 11 06:06:36 PM UTC 24 Sep 11 06:07:02 PM UTC 24 56411600 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1396057928 Sep 11 06:06:47 PM UTC 24 Sep 11 06:07:08 PM UTC 24 27642000 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.398664493 Sep 11 06:03:35 PM UTC 24 Sep 11 06:07:20 PM UTC 24 3957104700 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3588703854 Sep 11 05:25:51 PM UTC 24 Sep 11 06:07:22 PM UTC 24 82670703100 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1352572845 Sep 11 06:06:58 PM UTC 24 Sep 11 06:07:23 PM UTC 24 16001100 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2388842789 Sep 11 05:47:19 PM UTC 24 Sep 11 06:07:25 PM UTC 24 608193700 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.4082755599 Sep 11 06:07:01 PM UTC 24 Sep 11 06:07:25 PM UTC 24 25149700 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3865869393 Sep 11 06:06:32 PM UTC 24 Sep 11 06:07:29 PM UTC 24 66663100 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.2200599758 Sep 11 06:07:10 PM UTC 24 Sep 11 06:07:31 PM UTC 24 50659900 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.4039974627 Sep 11 06:04:32 PM UTC 24 Sep 11 06:07:35 PM UTC 24 3647376800 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.781617044 Sep 11 06:01:48 PM UTC 24 Sep 11 06:07:37 PM UTC 24 23857437200 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.236310046 Sep 11 06:06:35 PM UTC 24 Sep 11 06:07:42 PM UTC 24 101813700 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.537352581 Sep 11 06:06:43 PM UTC 24 Sep 11 06:07:48 PM UTC 24 2488981000 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.656919881 Sep 11 06:04:45 PM UTC 24 Sep 11 06:08:01 PM UTC 24 4778125300 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2843154783 Sep 11 06:07:03 PM UTC 24 Sep 11 06:08:01 PM UTC 24 10042811300 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.4077128712 Sep 11 06:04:57 PM UTC 24 Sep 11 06:08:05 PM UTC 24 1748150900 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.3242958375 Sep 11 06:07:35 PM UTC 24 Sep 11 06:08:14 PM UTC 24 103028100 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.3695597755 Sep 11 06:07:31 PM UTC 24 Sep 11 06:08:57 PM UTC 24 51958500 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3430232883 Sep 11 06:05:51 PM UTC 24 Sep 11 06:08:58 PM UTC 24 2614340100 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1946412992 Sep 11 05:55:21 PM UTC 24 Sep 11 06:09:16 PM UTC 24 40121791100 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.610542897 Sep 11 06:04:53 PM UTC 24 Sep 11 06:09:17 PM UTC 24 2967281200 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.1760142840 Sep 11 06:07:49 PM UTC 24 Sep 11 06:09:30 PM UTC 24 2718362900 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.1810136106 Sep 11 06:07:21 PM UTC 24 Sep 11 06:09:31 PM UTC 24 39500400 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.694899820 Sep 11 05:50:26 PM UTC 24 Sep 11 06:10:02 PM UTC 24 392497300 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1839711135 Sep 11 06:08:02 PM UTC 24 Sep 11 06:10:10 PM UTC 24 1976148300 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3907778322 Sep 11 06:08:02 PM UTC 24 Sep 11 06:10:11 PM UTC 24 523925600 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2484653733 Sep 11 06:07:32 PM UTC 24 Sep 11 06:10:11 PM UTC 24 39399900 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2825400977 Sep 11 06:10:11 PM UTC 24 Sep 11 06:10:37 PM UTC 24 20735900 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.491576821 Sep 11 06:09:31 PM UTC 24 Sep 11 06:10:49 PM UTC 24 4227015800 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2425273314 Sep 11 06:08:15 PM UTC 24 Sep 11 06:10:50 PM UTC 24 537897300 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3328070502 Sep 11 06:05:06 PM UTC 24 Sep 11 06:10:53 PM UTC 24 18745631300 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.3955467320 Sep 11 06:00:52 PM UTC 24 Sep 11 06:10:56 PM UTC 24 4274101400 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1389493201 Sep 11 06:05:42 PM UTC 24 Sep 11 06:11:04 PM UTC 24 28949993800 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.481858775 Sep 11 06:10:12 PM UTC 24 Sep 11 06:11:06 PM UTC 24 317425300 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.3705655031 Sep 11 06:10:11 PM UTC 24 Sep 11 06:11:07 PM UTC 24 146414400 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.167437459 Sep 11 06:10:54 PM UTC 24 Sep 11 06:11:17 PM UTC 24 22271200 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1870122881 Sep 11 05:59:45 PM UTC 24 Sep 11 06:11:19 PM UTC 24 254775500 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3370561468 Sep 11 06:10:38 PM UTC 24 Sep 11 06:11:21 PM UTC 24 70064800 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1487575619 Sep 11 06:10:57 PM UTC 24 Sep 11 06:11:25 PM UTC 24 20198000 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.4149973963 Sep 11 06:10:50 PM UTC 24 Sep 11 06:11:28 PM UTC 24 16222700 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.434778594 Sep 11 06:11:05 PM UTC 24 Sep 11 06:11:30 PM UTC 24 19473400 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.943274525 Sep 11 06:11:08 PM UTC 24 Sep 11 06:11:31 PM UTC 24 45407900 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3069390672 Sep 11 06:08:59 PM UTC 24 Sep 11 06:11:35 PM UTC 24 2459192800 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.4214625987 Sep 11 06:09:32 PM UTC 24 Sep 11 06:12:00 PM UTC 24 5817747100 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.1087200131 Sep 11 06:04:38 PM UTC 24 Sep 11 06:12:13 PM UTC 24 7907200600 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.956773200 Sep 11 06:07:32 PM UTC 24 Sep 11 06:12:14 PM UTC 24 10724966300 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3323796775 Sep 11 06:09:18 PM UTC 24 Sep 11 06:12:15 PM UTC 24 1922336600 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3476077376 Sep 11 06:09:17 PM UTC 24 Sep 11 06:12:23 PM UTC 24 5929183400 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3555234252 Sep 11 06:08:58 PM UTC 24 Sep 11 06:12:27 PM UTC 24 1364380200 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3477893932 Sep 11 06:10:51 PM UTC 24 Sep 11 06:12:30 PM UTC 24 3678869000 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.1875479504 Sep 11 06:03:52 PM UTC 24 Sep 11 06:12:36 PM UTC 24 20576212100 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.323337893 Sep 11 06:12:28 PM UTC 24 Sep 11 06:12:45 PM UTC 24 19766900 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.620982975 Sep 11 06:07:32 PM UTC 24 Sep 11 06:13:03 PM UTC 24 22208027100 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3594167559 Sep 11 06:12:31 PM UTC 24 Sep 11 06:13:18 PM UTC 24 75660800 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.2080598392 Sep 11 06:11:37 PM UTC 24 Sep 11 06:13:20 PM UTC 24 10442649800 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3931081469 Sep 11 06:12:37 PM UTC 24 Sep 11 06:13:27 PM UTC 24 66037700 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2479660173 Sep 11 06:11:07 PM UTC 24 Sep 11 06:13:30 PM UTC 24 10017153900 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.3136060004 Sep 11 06:13:05 PM UTC 24 Sep 11 06:13:33 PM UTC 24 10849000 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.735014827 Sep 11 06:12:45 PM UTC 24 Sep 11 06:13:35 PM UTC 24 71669200 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1098451933 Sep 11 06:11:18 PM UTC 24 Sep 11 06:13:41 PM UTC 24 58416900 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1601072312 Sep 11 06:13:21 PM UTC 24 Sep 11 06:13:44 PM UTC 24 17020700 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.3524136946 Sep 11 05:52:11 PM UTC 24 Sep 11 06:13:50 PM UTC 24 5171324700 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1448172287 Sep 11 05:25:48 PM UTC 24 Sep 11 06:13:52 PM UTC 24 580918976900 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.455584381 Sep 11 06:13:30 PM UTC 24 Sep 11 06:13:55 PM UTC 24 46238400 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.1548246380 Sep 11 06:11:27 PM UTC 24 Sep 11 06:13:58 PM UTC 24 18145463700 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.2145478137 Sep 11 06:13:28 PM UTC 24 Sep 11 06:13:59 PM UTC 24 15467300 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.1993706785 Sep 11 06:13:35 PM UTC 24 Sep 11 06:14:00 PM UTC 24 21958300 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2035273779 Sep 11 06:11:32 PM UTC 24 Sep 11 06:14:08 PM UTC 24 27179849900 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.4277805966 Sep 11 06:12:14 PM UTC 24 Sep 11 06:14:22 PM UTC 24 570111600 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2363525093 Sep 11 06:12:15 PM UTC 24 Sep 11 06:14:40 PM UTC 24 5560550600 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3182808402 Sep 11 06:13:53 PM UTC 24 Sep 11 06:14:44 PM UTC 24 3827401900 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2658778811 Sep 11 06:13:19 PM UTC 24 Sep 11 06:14:44 PM UTC 24 16742473600 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.518493829 Sep 11 06:11:22 PM UTC 24 Sep 11 06:15:00 PM UTC 24 39422600 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.1434205767 Sep 11 05:55:41 PM UTC 24 Sep 11 06:15:02 PM UTC 24 350333000 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.625862565 Sep 11 06:15:00 PM UTC 24 Sep 11 06:15:16 PM UTC 24 30840900 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.734560811 Sep 11 05:59:56 PM UTC 24 Sep 11 06:15:23 PM UTC 24 200235735100 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1000141594 Sep 11 06:12:01 PM UTC 24 Sep 11 06:15:28 PM UTC 24 2782688100 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1496333776 Sep 11 06:07:31 PM UTC 24 Sep 11 06:15:30 PM UTC 24 86998800 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1328139751 Sep 11 06:13:33 PM UTC 24 Sep 11 06:15:35 PM UTC 24 10036825100 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2086696440 Sep 11 06:11:31 PM UTC 24 Sep 11 06:15:41 PM UTC 24 38990900 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.3686659724 Sep 11 06:15:03 PM UTC 24 Sep 11 06:15:44 PM UTC 24 73482200 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1019677352 Sep 11 06:14:01 PM UTC 24 Sep 11 06:15:46 PM UTC 24 8491846300 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.910260684 Sep 11 06:15:17 PM UTC 24 Sep 11 06:15:59 PM UTC 24 69981900 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.4234196620 Sep 11 06:15:36 PM UTC 24 Sep 11 06:16:00 PM UTC 24 26653800 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1479079936 Sep 11 06:15:24 PM UTC 24 Sep 11 06:16:05 PM UTC 24 93658000 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.2264396883 Sep 11 05:30:09 PM UTC 24 Sep 11 06:16:06 PM UTC 24 330799248900 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.2876530322 Sep 11 06:15:41 PM UTC 24 Sep 11 06:16:07 PM UTC 24 20572400 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.2527012102 Sep 11 06:15:44 PM UTC 24 Sep 11 06:16:09 PM UTC 24 27187400 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2037065865 Sep 11 06:15:29 PM UTC 24 Sep 11 06:16:09 PM UTC 24 43517800 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1957990725 Sep 11 06:15:59 PM UTC 24 Sep 11 06:16:24 PM UTC 24 49422500 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1691937531 Sep 11 06:14:09 PM UTC 24 Sep 11 06:16:30 PM UTC 24 1536151700 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2821719925 Sep 11 06:14:23 PM UTC 24 Sep 11 06:16:38 PM UTC 24 2381263300 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2401142791 Sep 11 05:34:45 PM UTC 24 Sep 11 06:16:52 PM UTC 24 420686878400 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1795069777 Sep 11 06:08:06 PM UTC 24 Sep 11 06:17:00 PM UTC 24 7865050900 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.1300147070 Sep 11 06:13:59 PM UTC 24 Sep 11 06:17:01 PM UTC 24 72490000 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2232361399 Sep 11 06:12:24 PM UTC 24 Sep 11 06:17:05 PM UTC 24 189180999300 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.3968256068 Sep 11 06:15:31 PM UTC 24 Sep 11 06:17:14 PM UTC 24 1568320100 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.424002368 Sep 11 06:17:15 PM UTC 24 Sep 11 06:17:44 PM UTC 24 65582000 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1235768614 Sep 11 06:16:02 PM UTC 24 Sep 11 06:17:46 PM UTC 24 71751000 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.767145231 Sep 11 06:16:30 PM UTC 24 Sep 11 06:18:01 PM UTC 24 7115874700 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.45233285 Sep 11 05:25:52 PM UTC 24 Sep 11 06:18:08 PM UTC 24 45848151000 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2186733991 Sep 11 06:16:13 PM UTC 24 Sep 11 06:18:19 PM UTC 24 9905579100 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.975677128 Sep 11 06:15:47 PM UTC 24 Sep 11 06:18:30 PM UTC 24 10012236700 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.877285895 Sep 11 06:17:47 PM UTC 24 Sep 11 06:18:30 PM UTC 24 30681700 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.375576491 Sep 11 06:17:45 PM UTC 24 Sep 11 06:18:32 PM UTC 24 46490700 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4250238301 Sep 11 06:16:53 PM UTC 24 Sep 11 06:18:38 PM UTC 24 6206684300 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.438336536 Sep 11 06:18:10 PM UTC 24 Sep 11 06:18:45 PM UTC 24 43472500 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1353365127 Sep 11 06:18:32 PM UTC 24 Sep 11 06:18:48 PM UTC 24 49017100 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1592241232 Sep 11 06:18:31 PM UTC 24 Sep 11 06:18:54 PM UTC 24 26231200 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.46679443 Sep 11 06:18:31 PM UTC 24 Sep 11 06:18:56 PM UTC 24 15046800 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.2714785655 Sep 11 06:13:43 PM UTC 24 Sep 11 06:19:05 PM UTC 24 48927600 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3581435534 Sep 11 06:14:44 PM UTC 24 Sep 11 06:19:05 PM UTC 24 4726590900 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1381795055 Sep 11 06:18:46 PM UTC 24 Sep 11 06:19:08 PM UTC 24 82841500 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.3918513813 Sep 11 06:18:01 PM UTC 24 Sep 11 06:19:10 PM UTC 24 66891700 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.337118741 Sep 11 06:13:59 PM UTC 24 Sep 11 06:19:23 PM UTC 24 11109078500 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2216786647 Sep 11 06:10:03 PM UTC 24 Sep 11 06:19:30 PM UTC 24 252922663300 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2007455708 Sep 11 06:16:13 PM UTC 24 Sep 11 06:19:32 PM UTC 24 56315600 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.609354536 Sep 11 06:03:47 PM UTC 24 Sep 11 06:19:39 PM UTC 24 160185359500 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.332372410 Sep 11 06:12:15 PM UTC 24 Sep 11 06:19:47 PM UTC 24 5882214500 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3067257102 Sep 11 05:25:51 PM UTC 24 Sep 11 06:19:51 PM UTC 24 2770039400 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.1862843234 Sep 11 06:17:02 PM UTC 24 Sep 11 06:19:57 PM UTC 24 2298283200 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3977540833 Sep 11 06:18:20 PM UTC 24 Sep 11 06:20:00 PM UTC 24 12588563200 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.708782935 Sep 11 06:19:06 PM UTC 24 Sep 11 06:20:08 PM UTC 24 2750290600 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3445391340 Sep 11 05:25:44 PM UTC 24 Sep 11 06:20:16 PM UTC 24 1332817955000 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.792057995 Sep 11 06:11:20 PM UTC 24 Sep 11 06:20:25 PM UTC 24 2919269700 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.695495533 Sep 11 06:18:57 PM UTC 24 Sep 11 06:20:32 PM UTC 24 40833700 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.4256299380 Sep 11 06:19:24 PM UTC 24 Sep 11 06:20:47 PM UTC 24 1567967500 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.826701138 Sep 11 06:20:01 PM UTC 24 Sep 11 06:20:51 PM UTC 24 28662500 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1859884880 Sep 11 06:14:44 PM UTC 24 Sep 11 06:20:52 PM UTC 24 49439339900 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.4246009852 Sep 11 06:03:31 PM UTC 24 Sep 11 06:20:55 PM UTC 24 1449241800 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.2447806451 Sep 11 06:13:51 PM UTC 24 Sep 11 06:20:56 PM UTC 24 1378873100 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3783372878 Sep 11 06:20:08 PM UTC 24 Sep 11 06:20:57 PM UTC 24 147536200 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1353026632 Sep 11 06:00:19 PM UTC 24 Sep 11 06:21:03 PM UTC 24 507519200 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1479570928 Sep 11 06:20:25 PM UTC 24 Sep 11 06:21:03 PM UTC 24 21547100 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.999098757 Sep 11 05:29:56 PM UTC 24 Sep 11 06:21:04 PM UTC 24 397926718800 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.3495318539 Sep 11 06:20:48 PM UTC 24 Sep 11 06:21:12 PM UTC 24 29196600 ps
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