| T99 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2075968971 |
|
|
Feb 09 05:10:31 AM UTC 25 |
Feb 09 05:31:07 AM UTC 25 |
62553184200 ps |
| T517 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1655455714 |
|
|
Feb 09 05:30:50 AM UTC 25 |
Feb 09 05:31:16 AM UTC 25 |
43008100 ps |
| T90 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.4217724491 |
|
|
Feb 09 05:27:35 AM UTC 25 |
Feb 09 05:31:19 AM UTC 25 |
746861600 ps |
| T407 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.3270418540 |
|
|
Feb 09 05:29:58 AM UTC 25 |
Feb 09 05:31:28 AM UTC 25 |
1727287500 ps |
| T518 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1450444372 |
|
|
Feb 09 05:28:15 AM UTC 25 |
Feb 09 05:31:29 AM UTC 25 |
12078373300 ps |
| T519 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.4069868302 |
|
|
Feb 09 05:16:10 AM UTC 25 |
Feb 09 05:31:33 AM UTC 25 |
305007000 ps |
| T144 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4019750469 |
|
|
Feb 09 05:25:10 AM UTC 25 |
Feb 09 05:31:40 AM UTC 25 |
29075361300 ps |
| T315 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2383344990 |
|
|
Feb 09 05:31:05 AM UTC 25 |
Feb 09 05:31:49 AM UTC 25 |
383777500 ps |
| T520 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1540501262 |
|
|
Feb 09 05:24:41 AM UTC 25 |
Feb 09 05:31:58 AM UTC 25 |
279541700 ps |
| T521 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3723998245 |
|
|
Feb 09 05:31:21 AM UTC 25 |
Feb 09 05:32:20 AM UTC 25 |
3198674300 ps |
| T522 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2731155547 |
|
|
Feb 09 05:28:41 AM UTC 25 |
Feb 09 05:32:25 AM UTC 25 |
27474945400 ps |
| T182 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2076511194 |
|
|
Feb 09 05:17:01 AM UTC 25 |
Feb 09 05:32:40 AM UTC 25 |
171144710300 ps |
| T523 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.4167156874 |
|
|
Feb 09 05:31:30 AM UTC 25 |
Feb 09 05:33:01 AM UTC 25 |
2786576500 ps |
| T102 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1237130030 |
|
|
Feb 09 05:30:49 AM UTC 25 |
Feb 09 05:33:05 AM UTC 25 |
10031493700 ps |
| T324 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.642858075 |
|
|
Feb 09 05:24:36 AM UTC 25 |
Feb 09 05:33:16 AM UTC 25 |
2090746000 ps |
| T524 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1230445489 |
|
|
Feb 09 05:31:05 AM UTC 25 |
Feb 09 05:33:24 AM UTC 25 |
6145549400 ps |
| T136 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.833685555 |
|
|
Feb 09 05:17:43 AM UTC 25 |
Feb 09 05:33:33 AM UTC 25 |
260238299100 ps |
| T525 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3204418350 |
|
|
Feb 09 05:33:07 AM UTC 25 |
Feb 09 05:33:40 AM UTC 25 |
879658200 ps |
| T302 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.2102917609 |
|
|
Feb 09 05:31:01 AM UTC 25 |
Feb 09 05:33:44 AM UTC 25 |
329535500 ps |
| T308 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2034348046 |
|
|
Feb 09 05:30:51 AM UTC 25 |
Feb 09 05:33:45 AM UTC 25 |
76822400 ps |
| T526 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.3033367886 |
|
|
Feb 09 05:26:15 AM UTC 25 |
Feb 09 05:33:51 AM UTC 25 |
2792671200 ps |
| T445 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3550448245 |
|
|
Feb 09 05:33:17 AM UTC 25 |
Feb 09 05:34:00 AM UTC 25 |
93993800 ps |
| T455 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.675220376 |
|
|
Feb 09 05:33:25 AM UTC 25 |
Feb 09 05:34:06 AM UTC 25 |
71767800 ps |
| T527 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.303341625 |
|
|
Feb 09 05:31:29 AM UTC 25 |
Feb 09 05:34:07 AM UTC 25 |
4547890800 ps |
| T528 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1321033188 |
|
|
Feb 09 05:33:46 AM UTC 25 |
Feb 09 05:34:13 AM UTC 25 |
15332100 ps |
| T529 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.694397504 |
|
|
Feb 09 05:32:00 AM UTC 25 |
Feb 09 05:34:15 AM UTC 25 |
1304066600 ps |
| T530 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1975826241 |
|
|
Feb 09 05:31:41 AM UTC 25 |
Feb 09 05:34:16 AM UTC 25 |
602693500 ps |
| T311 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3026891607 |
|
|
Feb 09 05:33:52 AM UTC 25 |
Feb 09 05:34:18 AM UTC 25 |
15482800 ps |
| T531 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.2211834960 |
|
|
Feb 09 05:32:29 AM UTC 25 |
Feb 09 05:34:19 AM UTC 25 |
5018835200 ps |
| T404 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.2229891892 |
|
|
Feb 09 05:33:41 AM UTC 25 |
Feb 09 05:34:24 AM UTC 25 |
18313000 ps |
| T318 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.4191121428 |
|
|
Feb 09 05:34:08 AM UTC 25 |
Feb 09 05:34:27 AM UTC 25 |
164380800 ps |
| T325 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3750663345 |
|
|
Feb 09 05:34:01 AM UTC 25 |
Feb 09 05:34:31 AM UTC 25 |
16209600 ps |
| T326 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1035548908 |
|
|
Feb 09 05:33:33 AM UTC 25 |
Feb 09 05:34:31 AM UTC 25 |
66508900 ps |
| T532 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2509125859 |
|
|
Feb 09 05:30:56 AM UTC 25 |
Feb 09 05:34:35 AM UTC 25 |
2353545800 ps |
| T316 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4223665836 |
|
|
Feb 09 05:31:49 AM UTC 25 |
Feb 09 05:35:02 AM UTC 25 |
1431058400 ps |
| T275 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1625975394 |
|
|
Feb 09 05:34:07 AM UTC 25 |
Feb 09 05:35:04 AM UTC 25 |
10052991600 ps |
| T533 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.3314710591 |
|
|
Feb 09 05:34:32 AM UTC 25 |
Feb 09 05:35:08 AM UTC 25 |
266931200 ps |
| T534 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.452416448 |
|
|
Feb 09 05:34:14 AM UTC 25 |
Feb 09 05:35:14 AM UTC 25 |
36168900 ps |
| T327 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2399691045 |
|
|
Feb 09 05:32:22 AM UTC 25 |
Feb 09 05:35:21 AM UTC 25 |
4016453300 ps |
| T384 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3323320600 |
|
|
Feb 09 05:33:46 AM UTC 25 |
Feb 09 05:35:26 AM UTC 25 |
629934200 ps |
| T352 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.1656201111 |
|
|
Feb 09 05:32:26 AM UTC 25 |
Feb 09 05:35:30 AM UTC 25 |
3681404400 ps |
| T284 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.4106945402 |
|
|
Feb 09 05:11:39 AM UTC 25 |
Feb 09 05:36:04 AM UTC 25 |
1489860200 ps |
| T320 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2676098082 |
|
|
Feb 09 05:32:41 AM UTC 25 |
Feb 09 05:36:10 AM UTC 25 |
24635992900 ps |
| T309 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.890625994 |
|
|
Feb 09 05:34:19 AM UTC 25 |
Feb 09 05:36:22 AM UTC 25 |
3950336400 ps |
| T535 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2077263257 |
|
|
Feb 09 05:33:02 AM UTC 25 |
Feb 09 05:36:32 AM UTC 25 |
24206628700 ps |
| T536 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3710182852 |
|
|
Feb 09 05:35:03 AM UTC 25 |
Feb 09 05:36:33 AM UTC 25 |
1918138900 ps |
| T537 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2812290622 |
|
|
Feb 09 05:18:48 AM UTC 25 |
Feb 09 05:36:41 AM UTC 25 |
2098614600 ps |
| T538 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2138693545 |
|
|
Feb 09 05:27:52 AM UTC 25 |
Feb 09 05:36:50 AM UTC 25 |
3978263600 ps |
| T539 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3839113056 |
|
|
Feb 09 05:35:09 AM UTC 25 |
Feb 09 05:36:53 AM UTC 25 |
476178200 ps |
| T540 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.846134810 |
|
|
Feb 09 05:36:35 AM UTC 25 |
Feb 09 05:36:55 AM UTC 25 |
88899300 ps |
| T541 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.522173261 |
|
|
Feb 09 05:30:54 AM UTC 25 |
Feb 09 05:37:14 AM UTC 25 |
126737600 ps |
| T194 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3762820663 |
|
|
Feb 09 05:34:24 AM UTC 25 |
Feb 09 05:37:22 AM UTC 25 |
40374900 ps |
| T542 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.4248121644 |
|
|
Feb 09 05:36:11 AM UTC 25 |
Feb 09 05:37:24 AM UTC 25 |
1985780900 ps |
| T161 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.2253391759 |
|
|
Feb 09 05:34:27 AM UTC 25 |
Feb 09 05:39:39 AM UTC 25 |
44785900700 ps |
| T453 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3318627889 |
|
|
Feb 09 05:36:42 AM UTC 25 |
Feb 09 05:37:26 AM UTC 25 |
34745900 ps |
| T313 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.3148965185 |
|
|
Feb 09 05:36:51 AM UTC 25 |
Feb 09 05:37:35 AM UTC 25 |
29170900 ps |
| T116 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.749226519 |
|
|
Feb 09 05:36:56 AM UTC 25 |
Feb 09 05:37:35 AM UTC 25 |
24654800 ps |
| T543 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2276528271 |
|
|
Feb 09 05:37:23 AM UTC 25 |
Feb 09 05:37:44 AM UTC 25 |
88205500 ps |
| T433 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2616529529 |
|
|
Feb 09 05:36:54 AM UTC 25 |
Feb 09 05:37:45 AM UTC 25 |
71816900 ps |
| T544 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3203327039 |
|
|
Feb 09 05:37:24 AM UTC 25 |
Feb 09 05:37:49 AM UTC 25 |
45308600 ps |
| T271 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.237833142 |
|
|
Feb 09 05:37:27 AM UTC 25 |
Feb 09 05:37:49 AM UTC 25 |
30263900 ps |
| T545 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3195385748 |
|
|
Feb 09 05:37:36 AM UTC 25 |
Feb 09 05:38:03 AM UTC 25 |
115117400 ps |
| T137 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.3838490208 |
|
|
Feb 09 05:03:52 AM UTC 25 |
Feb 09 05:38:03 AM UTC 25 |
169178589300 ps |
| T546 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1660641910 |
|
|
Feb 09 05:35:22 AM UTC 25 |
Feb 09 05:38:06 AM UTC 25 |
1075909100 ps |
| T410 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3358628838 |
|
|
Feb 09 05:37:15 AM UTC 25 |
Feb 09 05:38:29 AM UTC 25 |
22967174900 ps |
| T547 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1780742202 |
|
|
Feb 09 05:30:51 AM UTC 25 |
Feb 09 05:38:33 AM UTC 25 |
206056700 ps |
| T548 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.134790219 |
|
|
Feb 09 05:35:30 AM UTC 25 |
Feb 09 05:38:45 AM UTC 25 |
3028062400 ps |
| T549 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3535685247 |
|
|
Feb 09 05:35:05 AM UTC 25 |
Feb 09 05:38:53 AM UTC 25 |
2227935600 ps |
| T59 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.476291703 |
|
|
Feb 09 05:38:30 AM UTC 25 |
Feb 09 05:38:58 AM UTC 25 |
755582100 ps |
| T353 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.765520 |
|
|
Feb 09 05:36:05 AM UTC 25 |
Feb 09 05:39:04 AM UTC 25 |
2676980500 ps |
| T435 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1898911441 |
|
|
Feb 09 05:31:34 AM UTC 25 |
Feb 09 05:39:17 AM UTC 25 |
6971242200 ps |
| T550 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.4072579532 |
|
|
Feb 09 05:35:26 AM UTC 25 |
Feb 09 05:39:24 AM UTC 25 |
22341459100 ps |
| T551 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2211058113 |
|
|
Feb 09 05:35:59 AM UTC 25 |
Feb 09 05:39:37 AM UTC 25 |
1309518400 ps |
| T203 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.757612719 |
|
|
Feb 09 05:24:55 AM UTC 25 |
Feb 09 05:39:47 AM UTC 25 |
120161338700 ps |
| T552 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4119097794 |
|
|
Feb 09 05:37:44 AM UTC 25 |
Feb 09 05:40:05 AM UTC 25 |
75000200 ps |
| T553 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.360727859 |
|
|
Feb 09 05:24:21 AM UTC 25 |
Feb 09 05:40:17 AM UTC 25 |
634349500 ps |
| T554 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2268199179 |
|
|
Feb 09 05:36:32 AM UTC 25 |
Feb 09 05:40:19 AM UTC 25 |
48803302900 ps |
| T220 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.903719048 |
|
|
Feb 09 05:38:53 AM UTC 25 |
Feb 09 05:40:43 AM UTC 25 |
28840581700 ps |
| T555 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1368473382 |
|
|
Feb 09 05:37:50 AM UTC 25 |
Feb 09 05:41:09 AM UTC 25 |
9388804900 ps |
| T556 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.897243952 |
|
|
Feb 09 05:39:25 AM UTC 25 |
Feb 09 05:41:38 AM UTC 25 |
1394111000 ps |
| T557 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.520261401 |
|
|
Feb 09 05:39:05 AM UTC 25 |
Feb 09 05:41:38 AM UTC 25 |
540370200 ps |
| T558 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.361654563 |
|
|
Feb 09 05:41:10 AM UTC 25 |
Feb 09 05:41:39 AM UTC 25 |
132250900 ps |
| T559 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3276481197 |
|
|
Feb 09 05:40:18 AM UTC 25 |
Feb 09 05:41:44 AM UTC 25 |
3539505300 ps |
| T103 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2052367257 |
|
|
Feb 09 05:37:36 AM UTC 25 |
Feb 09 05:41:49 AM UTC 25 |
10013326500 ps |
| T560 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.301598233 |
|
|
Feb 09 05:34:17 AM UTC 25 |
Feb 09 05:42:06 AM UTC 25 |
258225900 ps |
| T561 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3766985734 |
|
|
Feb 09 05:39:40 AM UTC 25 |
Feb 09 05:42:16 AM UTC 25 |
2540403000 ps |
| T195 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1031561100 |
|
|
Feb 09 05:38:04 AM UTC 25 |
Feb 09 05:42:30 AM UTC 25 |
245341700 ps |
| T117 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3545955439 |
|
|
Feb 09 05:41:45 AM UTC 25 |
Feb 09 05:42:30 AM UTC 25 |
64042900 ps |
| T461 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.1941461219 |
|
|
Feb 09 05:41:38 AM UTC 25 |
Feb 09 05:42:32 AM UTC 25 |
64086800 ps |
| T562 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3264706945 |
|
|
Feb 09 05:42:07 AM UTC 25 |
Feb 09 05:42:32 AM UTC 25 |
17498600 ps |
| T441 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.361209234 |
|
|
Feb 09 05:41:40 AM UTC 25 |
Feb 09 05:42:35 AM UTC 25 |
69905300 ps |
| T563 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3115244038 |
|
|
Feb 09 05:42:17 AM UTC 25 |
Feb 09 05:42:42 AM UTC 25 |
26234700 ps |
| T564 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.3720641123 |
|
|
Feb 09 05:39:38 AM UTC 25 |
Feb 09 05:42:44 AM UTC 25 |
3286827300 ps |
| T457 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.21480838 |
|
|
Feb 09 05:41:40 AM UTC 25 |
Feb 09 05:42:45 AM UTC 25 |
126252700 ps |
| T565 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1217918111 |
|
|
Feb 09 05:42:33 AM UTC 25 |
Feb 09 05:42:54 AM UTC 25 |
125870400 ps |
| T566 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.3178432804 |
|
|
Feb 09 05:34:16 AM UTC 25 |
Feb 09 05:42:56 AM UTC 25 |
6106904600 ps |
| T272 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1730228997 |
|
|
Feb 09 05:42:31 AM UTC 25 |
Feb 09 05:42:56 AM UTC 25 |
38842800 ps |
| T567 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3253992254 |
|
|
Feb 09 05:39:49 AM UTC 25 |
Feb 09 05:43:06 AM UTC 25 |
3987423700 ps |
| T417 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2876516076 |
|
|
Feb 09 05:41:50 AM UTC 25 |
Feb 09 05:43:18 AM UTC 25 |
1928289800 ps |
| T568 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.4190725623 |
|
|
Feb 09 05:30:08 AM UTC 25 |
Feb 09 05:43:27 AM UTC 25 |
762346000 ps |
| T60 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.1249393651 |
|
|
Feb 09 05:42:57 AM UTC 25 |
Feb 09 05:43:31 AM UTC 25 |
382683800 ps |
| T569 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1726550940 |
|
|
Feb 09 05:38:58 AM UTC 25 |
Feb 09 05:43:39 AM UTC 25 |
11706905400 ps |
| T570 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.4147782298 |
|
|
Feb 09 05:40:06 AM UTC 25 |
Feb 09 05:43:46 AM UTC 25 |
7868324900 ps |
| T571 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.50818696 |
|
|
Feb 09 05:42:42 AM UTC 25 |
Feb 09 05:44:09 AM UTC 25 |
59883400 ps |
| T336 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3723644206 |
|
|
Feb 09 05:42:31 AM UTC 25 |
Feb 09 05:44:10 AM UTC 25 |
10025909000 ps |
| T572 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2373915332 |
|
|
Feb 09 05:36:23 AM UTC 25 |
Feb 09 05:44:18 AM UTC 25 |
49224940900 ps |
| T573 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2999967893 |
|
|
Feb 09 05:40:43 AM UTC 25 |
Feb 09 05:44:25 AM UTC 25 |
20929341300 ps |
| T310 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3900904703 |
|
|
Feb 09 05:43:20 AM UTC 25 |
Feb 09 05:44:25 AM UTC 25 |
1082309000 ps |
| T574 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.2378112034 |
|
|
Feb 09 05:42:46 AM UTC 25 |
Feb 09 05:44:53 AM UTC 25 |
26266346100 ps |
| T575 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2033420017 |
|
|
Feb 09 05:25:22 AM UTC 25 |
Feb 09 05:44:54 AM UTC 25 |
3054957700 ps |
| T576 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.286800780 |
|
|
Feb 09 05:43:32 AM UTC 25 |
Feb 09 05:45:05 AM UTC 25 |
1859943700 ps |
| T577 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.1429331847 |
|
|
Feb 09 05:42:35 AM UTC 25 |
Feb 09 05:45:11 AM UTC 25 |
119247400 ps |
| T204 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.4276548358 |
|
|
Feb 09 05:30:58 AM UTC 25 |
Feb 09 05:45:11 AM UTC 25 |
40120850300 ps |
| T438 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2133680243 |
|
|
Feb 09 05:35:14 AM UTC 25 |
Feb 09 05:45:14 AM UTC 25 |
4575303500 ps |
| T578 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.41902400 |
|
|
Feb 09 05:45:06 AM UTC 25 |
Feb 09 05:45:29 AM UTC 25 |
33871600 ps |
| T579 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1737856226 |
|
|
Feb 09 05:40:20 AM UTC 25 |
Feb 09 05:45:44 AM UTC 25 |
12649660700 ps |
| T179 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3342952342 |
|
|
Feb 09 05:42:55 AM UTC 25 |
Feb 09 05:45:46 AM UTC 25 |
77528500 ps |
| T580 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1124403660 |
|
|
Feb 09 05:44:26 AM UTC 25 |
Feb 09 05:45:50 AM UTC 25 |
4381163500 ps |
| T581 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3647527743 |
|
|
Feb 09 05:45:12 AM UTC 25 |
Feb 09 05:45:52 AM UTC 25 |
34693000 ps |
| T582 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.2909538835 |
|
|
Feb 09 05:45:47 AM UTC 25 |
Feb 09 05:46:06 AM UTC 25 |
46879700 ps |
| T338 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.387289585 |
|
|
Feb 09 05:45:12 AM UTC 25 |
Feb 09 05:46:06 AM UTC 25 |
35301300 ps |
| T449 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.21545371 |
|
|
Feb 09 05:45:15 AM UTC 25 |
Feb 09 05:46:09 AM UTC 25 |
309472200 ps |
| T583 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.33853163 |
|
|
Feb 09 05:45:51 AM UTC 25 |
Feb 09 05:46:14 AM UTC 25 |
26669400 ps |
| T202 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2759459571 |
|
|
Feb 09 05:45:29 AM UTC 25 |
Feb 09 05:46:15 AM UTC 25 |
20697500 ps |
| T584 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1606671283 |
|
|
Feb 09 05:45:53 AM UTC 25 |
Feb 09 05:46:23 AM UTC 25 |
109146600 ps |
| T585 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.436533590 |
|
|
Feb 09 05:46:07 AM UTC 25 |
Feb 09 05:46:26 AM UTC 25 |
56051100 ps |
| T586 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3412996276 |
|
|
Feb 09 05:43:28 AM UTC 25 |
Feb 09 05:46:34 AM UTC 25 |
3748631100 ps |
| T587 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.2746892289 |
|
|
Feb 09 05:43:46 AM UTC 25 |
Feb 09 05:46:34 AM UTC 25 |
626393800 ps |
| T354 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1645446989 |
|
|
Feb 09 05:44:26 AM UTC 25 |
Feb 09 05:46:36 AM UTC 25 |
562860600 ps |
| T588 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.3384661395 |
|
|
Feb 09 05:44:10 AM UTC 25 |
Feb 09 05:46:50 AM UTC 25 |
661281800 ps |
| T139 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2469325845 |
|
|
Feb 09 05:11:06 AM UTC 25 |
Feb 09 05:46:55 AM UTC 25 |
337637611100 ps |
| T162 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3311223127 |
|
|
Feb 09 05:38:07 AM UTC 25 |
Feb 09 05:46:56 AM UTC 25 |
7269589900 ps |
| T589 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3330017794 |
|
|
Feb 09 05:42:33 AM UTC 25 |
Feb 09 05:47:03 AM UTC 25 |
58817300 ps |
| T163 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4058677391 |
|
|
Feb 09 04:58:32 AM UTC 25 |
Feb 09 05:47:05 AM UTC 25 |
720935779000 ps |
| T61 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.4224637045 |
|
|
Feb 09 05:46:37 AM UTC 25 |
Feb 09 05:47:17 AM UTC 25 |
604339400 ps |
| T590 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.3348449129 |
|
|
Feb 09 05:39:18 AM UTC 25 |
Feb 09 05:47:18 AM UTC 25 |
3769292300 ps |
| T591 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.356058189 |
|
|
Feb 09 05:46:07 AM UTC 25 |
Feb 09 05:47:24 AM UTC 25 |
10032083600 ps |
| T414 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.493685556 |
|
|
Feb 09 05:45:44 AM UTC 25 |
Feb 09 05:47:27 AM UTC 25 |
32726846300 ps |
| T592 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.2025890409 |
|
|
Feb 09 05:44:18 AM UTC 25 |
Feb 09 05:47:37 AM UTC 25 |
1538043700 ps |
| T217 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.3332025778 |
|
|
Feb 09 04:58:32 AM UTC 25 |
Feb 09 05:47:45 AM UTC 25 |
413999314400 ps |
| T593 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2657302297 |
|
|
Feb 09 05:46:24 AM UTC 25 |
Feb 09 05:47:49 AM UTC 25 |
1552500600 ps |
| T594 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.640802617 |
|
|
Feb 09 05:44:10 AM UTC 25 |
Feb 09 05:47:49 AM UTC 25 |
3271447000 ps |
| T595 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.3979473387 |
|
|
Feb 09 05:46:57 AM UTC 25 |
Feb 09 05:47:58 AM UTC 25 |
2727387200 ps |
| T596 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1149068756 |
|
|
Feb 09 05:48:21 AM UTC 25 |
Feb 09 05:48:50 AM UTC 25 |
33470900 ps |
| T597 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3578949657 |
|
|
Feb 09 05:46:10 AM UTC 25 |
Feb 09 05:48:54 AM UTC 25 |
77025200 ps |
| T267 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2421299324 |
|
|
Feb 09 05:47:13 AM UTC 25 |
Feb 09 05:49:02 AM UTC 25 |
2119862200 ps |
| T184 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1530938610 |
|
|
Feb 09 05:34:19 AM UTC 25 |
Feb 09 05:49:04 AM UTC 25 |
50123943500 ps |
| T598 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3157756645 |
|
|
Feb 09 05:46:34 AM UTC 25 |
Feb 09 05:49:12 AM UTC 25 |
70745400 ps |
| T599 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.836004219 |
|
|
Feb 09 05:37:50 AM UTC 25 |
Feb 09 05:49:14 AM UTC 25 |
343299400 ps |
| T600 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2943770757 |
|
|
Feb 09 05:47:03 AM UTC 25 |
Feb 09 05:49:25 AM UTC 25 |
4800875100 ps |
| T601 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2062866862 |
|
|
Feb 09 05:47:50 AM UTC 25 |
Feb 09 05:49:35 AM UTC 25 |
4895472400 ps |
| T439 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.3473243812 |
|
|
Feb 09 05:48:51 AM UTC 25 |
Feb 09 05:49:35 AM UTC 25 |
38351200 ps |
| T602 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3989389798 |
|
|
Feb 09 05:47:20 AM UTC 25 |
Feb 09 05:49:36 AM UTC 25 |
1073583000 ps |
| T335 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.864702890 |
|
|
Feb 09 05:48:55 AM UTC 25 |
Feb 09 05:49:38 AM UTC 25 |
105810000 ps |
| T603 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1251087461 |
|
|
Feb 09 05:49:14 AM UTC 25 |
Feb 09 05:49:41 AM UTC 25 |
186198100 ps |
| T604 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1511640270 |
|
|
Feb 09 05:49:25 AM UTC 25 |
Feb 09 05:49:47 AM UTC 25 |
44934400 ps |
| T118 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2976659198 |
|
|
Feb 09 05:49:05 AM UTC 25 |
Feb 09 05:49:49 AM UTC 25 |
13833700 ps |
| T605 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.185868130 |
|
|
Feb 09 05:47:28 AM UTC 25 |
Feb 09 05:49:53 AM UTC 25 |
1970401600 ps |
| T606 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2037359694 |
|
|
Feb 09 05:49:37 AM UTC 25 |
Feb 09 05:49:54 AM UTC 25 |
18800300 ps |
| T607 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3084487135 |
|
|
Feb 09 05:49:36 AM UTC 25 |
Feb 09 05:50:00 AM UTC 25 |
67184400 ps |
| T608 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.414316615 |
|
|
Feb 09 05:49:02 AM UTC 25 |
Feb 09 05:50:01 AM UTC 25 |
274125200 ps |
| T609 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2428642990 |
|
|
Feb 09 05:44:55 AM UTC 25 |
Feb 09 05:50:18 AM UTC 25 |
88595614200 ps |
| T610 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3369979969 |
|
|
Feb 09 05:49:12 AM UTC 25 |
Feb 09 05:50:20 AM UTC 25 |
1460433100 ps |
| T45 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1895317727 |
|
|
Feb 09 05:47:46 AM UTC 25 |
Feb 09 05:50:31 AM UTC 25 |
2058964300 ps |
| T215 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.974041673 |
|
|
Feb 09 05:47:26 AM UTC 25 |
Feb 09 05:50:38 AM UTC 25 |
2175569100 ps |
| T355 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3121575126 |
|
|
Feb 09 05:44:54 AM UTC 25 |
Feb 09 05:50:44 AM UTC 25 |
26754426500 ps |
| T611 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.1181387117 |
|
|
Feb 09 05:31:07 AM UTC 25 |
Feb 09 05:50:50 AM UTC 25 |
365369900 ps |
| T321 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3754549284 |
|
|
Feb 09 05:49:50 AM UTC 25 |
Feb 09 05:51:09 AM UTC 25 |
1375353300 ps |
| T612 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4083264908 |
|
|
Feb 09 05:49:36 AM UTC 25 |
Feb 09 05:51:26 AM UTC 25 |
10034532100 ps |
| T613 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.1929803704 |
|
|
Feb 09 05:43:40 AM UTC 25 |
Feb 09 05:51:29 AM UTC 25 |
6849436600 ps |
| T614 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2753688049 |
|
|
Feb 09 05:47:50 AM UTC 25 |
Feb 09 05:51:31 AM UTC 25 |
8768564800 ps |
| T615 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1079915156 |
|
|
Feb 09 05:50:02 AM UTC 25 |
Feb 09 05:51:32 AM UTC 25 |
1594285500 ps |
| T616 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2844858786 |
|
|
Feb 09 05:47:38 AM UTC 25 |
Feb 09 05:51:35 AM UTC 25 |
2387262200 ps |
| T280 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3796927530 |
|
|
Feb 09 04:58:40 AM UTC 25 |
Feb 09 05:51:42 AM UTC 25 |
2493057300 ps |
| T192 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1584367211 |
|
|
Feb 09 05:38:04 AM UTC 25 |
Feb 09 05:51:50 AM UTC 25 |
80136286500 ps |
| T617 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2211717690 |
|
|
Feb 09 05:50:20 AM UTC 25 |
Feb 09 05:51:57 AM UTC 25 |
488774500 ps |
| T448 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3693222420 |
|
|
Feb 09 05:51:10 AM UTC 25 |
Feb 09 05:51:58 AM UTC 25 |
46595100 ps |
| T442 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3855137582 |
|
|
Feb 09 05:51:26 AM UTC 25 |
Feb 09 05:52:03 AM UTC 25 |
55800600 ps |
| T618 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.4205791303 |
|
|
Feb 09 05:51:36 AM UTC 25 |
Feb 09 05:52:04 AM UTC 25 |
13817700 ps |
| T619 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.13114609 |
|
|
Feb 09 05:51:44 AM UTC 25 |
Feb 09 05:52:09 AM UTC 25 |
45244700 ps |
| T620 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.1696295379 |
|
|
Feb 09 05:51:31 AM UTC 25 |
Feb 09 05:52:12 AM UTC 25 |
16204300 ps |
| T621 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.203619237 |
|
|
Feb 09 05:51:51 AM UTC 25 |
Feb 09 05:52:17 AM UTC 25 |
15497200 ps |
| T622 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.1659292679 |
|
|
Feb 09 05:51:59 AM UTC 25 |
Feb 09 05:52:18 AM UTC 25 |
31439500 ps |
| T450 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2583150431 |
|
|
Feb 09 05:51:30 AM UTC 25 |
Feb 09 05:52:30 AM UTC 25 |
199093900 ps |
| T426 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.3401847720 |
|
|
Feb 09 05:51:33 AM UTC 25 |
Feb 09 05:52:38 AM UTC 25 |
4695851200 ps |
| T623 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2038954325 |
|
|
Feb 09 05:50:01 AM UTC 25 |
Feb 09 05:52:50 AM UTC 25 |
9241330600 ps |
| T624 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1008186482 |
|
|
Feb 09 05:49:55 AM UTC 25 |
Feb 09 05:52:51 AM UTC 25 |
162295100 ps |
| T337 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2035538426 |
|
|
Feb 09 05:34:32 AM UTC 25 |
Feb 09 05:53:10 AM UTC 25 |
5975743500 ps |
| T625 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.560810825 |
|
|
Feb 09 05:50:18 AM UTC 25 |
Feb 09 05:53:18 AM UTC 25 |
9344873000 ps |
| T626 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.860086885 |
|
|
Feb 09 05:46:16 AM UTC 25 |
Feb 09 05:53:28 AM UTC 25 |
837341300 ps |
| T348 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2475777974 |
|
|
Feb 09 05:50:39 AM UTC 25 |
Feb 09 05:53:31 AM UTC 25 |
1388265600 ps |
| T627 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.4056406965 |
|
|
Feb 09 05:49:39 AM UTC 25 |
Feb 09 05:53:41 AM UTC 25 |
58901200 ps |
| T628 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.3708412298 |
|
|
Feb 09 05:04:07 AM UTC 25 |
Feb 09 05:53:42 AM UTC 25 |
251941635900 ps |
| T629 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.866394117 |
|
|
Feb 09 05:47:59 AM UTC 25 |
Feb 09 05:53:51 AM UTC 25 |
24489445600 ps |
| T630 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.3760359899 |
|
|
Feb 09 05:52:39 AM UTC 25 |
Feb 09 05:54:00 AM UTC 25 |
3008250700 ps |
| T452 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1108521254 |
|
|
Feb 09 05:53:42 AM UTC 25 |
Feb 09 05:54:20 AM UTC 25 |
137521500 ps |
| T456 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.667785311 |
|
|
Feb 09 05:53:43 AM UTC 25 |
Feb 09 05:54:21 AM UTC 25 |
120272400 ps |
| T631 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3898967337 |
|
|
Feb 09 05:11:15 AM UTC 25 |
Feb 09 05:54:30 AM UTC 25 |
324258166400 ps |
| T401 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.3198868869 |
|
|
Feb 09 05:54:00 AM UTC 25 |
Feb 09 05:54:38 AM UTC 25 |
35798000 ps |
| T322 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3457156379 |
|
|
Feb 09 05:52:13 AM UTC 25 |
Feb 09 05:54:46 AM UTC 25 |
5437033200 ps |
| T632 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.135778917 |
|
|
Feb 09 05:54:22 AM UTC 25 |
Feb 09 05:54:48 AM UTC 25 |
21653200 ps |
| T633 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.528083027 |
|
|
Feb 09 05:50:51 AM UTC 25 |
Feb 09 05:54:48 AM UTC 25 |
10045235300 ps |
| T634 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1288618137 |
|
|
Feb 09 05:53:52 AM UTC 25 |
Feb 09 05:54:54 AM UTC 25 |
62003000 ps |
| T635 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.3984899396 |
|
|
Feb 09 05:54:31 AM UTC 25 |
Feb 09 05:54:55 AM UTC 25 |
24762000 ps |
| T636 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.963158411 |
|
|
Feb 09 05:51:58 AM UTC 25 |
Feb 09 05:55:03 AM UTC 25 |
10012191400 ps |
| T104 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.2877579874 |
|
|
Feb 09 04:58:33 AM UTC 25 |
Feb 09 05:55:04 AM UTC 25 |
919321700 ps |
| T637 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.2693471264 |
|
|
Feb 09 05:54:40 AM UTC 25 |
Feb 09 05:55:04 AM UTC 25 |
15620400 ps |
| T638 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.3179787877 |
|
|
Feb 09 05:52:03 AM UTC 25 |
Feb 09 05:55:07 AM UTC 25 |
44371400 ps |
| T639 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3419426928 |
|
|
Feb 09 05:52:18 AM UTC 25 |
Feb 09 05:55:15 AM UTC 25 |
77489000 ps |
| T640 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1133629155 |
|
|
Feb 09 05:54:49 AM UTC 25 |
Feb 09 05:55:15 AM UTC 25 |
83264900 ps |
| T185 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.3502534105 |
|
|
Feb 09 05:42:47 AM UTC 25 |
Feb 09 05:55:17 AM UTC 25 |
40120293400 ps |
| T641 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.1526022837 |
|
|
Feb 09 05:52:52 AM UTC 25 |
Feb 09 05:55:26 AM UTC 25 |
2234946500 ps |
| T642 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2384766340 |
|
|
Feb 09 05:54:20 AM UTC 25 |
Feb 09 05:55:48 AM UTC 25 |
2191792800 ps |
| T643 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2492726256 |
|
|
Feb 09 05:54:47 AM UTC 25 |
Feb 09 05:55:53 AM UTC 25 |
10036396100 ps |
| T644 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2477914056 |
|
|
Feb 09 05:53:29 AM UTC 25 |
Feb 09 05:56:03 AM UTC 25 |
5741939800 ps |
| T645 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2204799466 |
|
|
Feb 09 05:56:03 AM UTC 25 |
Feb 09 05:56:30 AM UTC 25 |
66504200 ps |
| T646 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.189953602 |
|
|
Feb 09 05:53:32 AM UTC 25 |
Feb 09 05:56:33 AM UTC 25 |
9808701300 ps |
| T647 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.3540837786 |
|
|
Feb 09 05:47:18 AM UTC 25 |
Feb 09 05:56:36 AM UTC 25 |
15911065600 ps |
| T648 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.553285231 |
|
|
Feb 09 05:55:16 AM UTC 25 |
Feb 09 05:56:42 AM UTC 25 |
923540400 ps |
| T649 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3520339977 |
|
|
Feb 09 05:38:34 AM UTC 25 |
Feb 09 05:57:04 AM UTC 25 |
2354777900 ps |
| T650 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2275697848 |
|
|
Feb 09 05:55:18 AM UTC 25 |
Feb 09 05:57:11 AM UTC 25 |
1232370600 ps |
| T402 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.1328282660 |
|
|
Feb 09 05:56:43 AM UTC 25 |
Feb 09 05:57:17 AM UTC 25 |
10293900 ps |
| T651 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.3280034923 |
|
|
Feb 09 05:56:32 AM UTC 25 |
Feb 09 05:57:24 AM UTC 25 |
29186700 ps |
| T652 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3072102217 |
|
|
Feb 09 05:55:16 AM UTC 25 |
Feb 09 05:57:30 AM UTC 25 |
1965691400 ps |
| T323 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3970837290 |
|
|
Feb 09 05:55:04 AM UTC 25 |
Feb 09 05:57:31 AM UTC 25 |
2017308000 ps |
| T459 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.474515121 |
|
|
Feb 09 05:56:34 AM UTC 25 |
Feb 09 05:57:36 AM UTC 25 |
77699300 ps |
| T653 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3769064473 |
|
|
Feb 09 05:57:18 AM UTC 25 |
Feb 09 05:57:36 AM UTC 25 |
48579100 ps |
| T654 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.2291272489 |
|
|
Feb 09 05:57:12 AM UTC 25 |
Feb 09 05:57:37 AM UTC 25 |
51426600 ps |
| T351 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1169209202 |
|
|
Feb 09 05:53:19 AM UTC 25 |
Feb 09 05:57:38 AM UTC 25 |
1681351400 ps |
| T443 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2785418336 |
|
|
Feb 09 05:56:37 AM UTC 25 |
Feb 09 05:57:39 AM UTC 25 |
75545900 ps |
| T655 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.3660384174 |
|
|
Feb 09 05:57:25 AM UTC 25 |
Feb 09 05:57:45 AM UTC 25 |
24948300 ps |
| T656 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.1228175857 |
|
|
Feb 09 05:49:48 AM UTC 25 |
Feb 09 05:57:45 AM UTC 25 |
144359400 ps |
| T105 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3146860809 |
|
|
Feb 09 05:04:55 AM UTC 25 |
Feb 09 05:57:47 AM UTC 25 |
852440500 ps |
| T657 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4153713364 |
|
|
Feb 09 05:50:45 AM UTC 25 |
Feb 09 05:57:47 AM UTC 25 |
163418704700 ps |
| T658 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2868211851 |
|
|
Feb 09 05:55:06 AM UTC 25 |
Feb 09 05:57:53 AM UTC 25 |
45673700 ps |
| T659 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1060768642 |
|
|
Feb 09 05:57:32 AM UTC 25 |
Feb 09 05:58:00 AM UTC 25 |
129405700 ps |
| T281 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2945776420 |
|
|
Feb 09 05:05:01 AM UTC 25 |
Feb 09 05:58:15 AM UTC 25 |
11056858300 ps |
| T660 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3146968208 |
|
|
Feb 09 05:55:53 AM UTC 25 |
Feb 09 05:58:19 AM UTC 25 |
12245691700 ps |
| T415 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3274742263 |
|
|
Feb 09 05:57:04 AM UTC 25 |
Feb 09 05:58:26 AM UTC 25 |
3409417700 ps |
| T661 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.3514152942 |
|
|
Feb 09 05:52:10 AM UTC 25 |
Feb 09 05:58:30 AM UTC 25 |
727070400 ps |
| T662 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.232137085 |
|
|
Feb 09 05:54:49 AM UTC 25 |
Feb 09 05:58:31 AM UTC 25 |
68505500 ps |
| T663 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2226906500 |
|
|
Feb 09 05:58:26 AM UTC 25 |
Feb 09 05:58:45 AM UTC 25 |
36440200 ps |
| T664 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3935472608 |
|
|
Feb 09 05:55:48 AM UTC 25 |
Feb 09 05:59:07 AM UTC 25 |
6137629300 ps |
| T665 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1767594745 |
|
|
Feb 09 05:58:46 AM UTC 25 |
Feb 09 05:59:12 AM UTC 25 |
10989600 ps |
| T277 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1892381725 |
|
|
Feb 09 05:57:31 AM UTC 25 |
Feb 09 05:59:13 AM UTC 25 |
10033580400 ps |
| T444 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.3102102262 |
|
|
Feb 09 05:58:44 AM UTC 25 |
Feb 09 05:59:23 AM UTC 25 |
130199600 ps |
| T666 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.188417311 |
|
|
Feb 09 05:58:32 AM UTC 25 |
Feb 09 05:59:25 AM UTC 25 |
37320000 ps |
| T667 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3472514715 |
|
|
Feb 09 05:58:31 AM UTC 25 |
Feb 09 05:59:28 AM UTC 25 |
47530200 ps |
| T145 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.4031398031 |
|
|
Feb 09 05:42:57 AM UTC 25 |
Feb 09 05:59:33 AM UTC 25 |
56297779400 ps |
| T668 |
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2216163507 |
|
|
Feb 09 05:59:14 AM UTC 25 |
Feb 09 05:59:35 AM UTC 25 |
26978000 ps |